if_sn.c revision 155280
1/*- 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/dev/sn/if_sn.c 155280 2006-02-04 08:15:29Z imp $"); 34 35/* 36 * This is a driver for SMC's 9000 series of Ethernet adapters. 37 * 38 * This FreeBSD driver is derived from the smc9194 Linux driver by 39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 40 * This driver also shamelessly borrows from the FreeBSD ep driver 41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 42 * All rights reserved. 43 * 44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 45 * PC. It is adapted from Erik Stahlman's Linux driver which worked 46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 47 * it will work for the entire SMC 9xxx series. (Ha Ha) 48 * 49 * "Features" of the SMC chip: 50 * 4608 byte packet memory. (for the 91C92. Others have more) 51 * EEPROM for configuration 52 * AUI/TP selection 53 * 54 * Authors: 55 * Erik Stahlman erik@vt.edu 56 * Herb Peyerl hpeyerl@novatel.ca 57 * Andres Vega Garcia avega@sophia.inria.fr 58 * Serge Babkin babkin@hq.icb.chel.su 59 * Gardner Buchanan gbuchanan@shl.com 60 * 61 * Sources: 62 * o SMC databook 63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 65 * 66 * Known Bugs: 67 * o Setting of the hardware address isn't supported. 68 * o Hardware padding isn't used. 69 */ 70 71/* 72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 73 * 74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 75 * BSD-nomads, Tokyo, Japan. 76 */ 77/* 78 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 79 * Special thanks to itojun@itojun.org 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/errno.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/socket.h> 88#include <sys/syslog.h> 89 90#include <sys/module.h> 91#include <sys/bus.h> 92 93#include <machine/bus.h> 94#include <machine/resource.h> 95#include <sys/rman.h> 96 97#include <net/ethernet.h> 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/if_dl.h> 101#include <net/if_types.h> 102#include <net/if_mib.h> 103 104#ifdef INET 105#include <netinet/in.h> 106#include <netinet/in_systm.h> 107#include <netinet/in_var.h> 108#include <netinet/ip.h> 109#endif 110 111#include <net/bpf.h> 112#include <net/bpfdesc.h> 113 114#include <dev/sn/if_snreg.h> 115#include <dev/sn/if_snvar.h> 116 117/* Exported variables */ 118devclass_t sn_devclass; 119 120static int snioctl(struct ifnet * ifp, u_long, caddr_t); 121 122static void snresume(struct ifnet *); 123 124static void sninit_locked(void *); 125static void snstart_locked(struct ifnet *); 126 127static void sninit(void *); 128static void snread(struct ifnet *); 129static void snstart(struct ifnet *); 130static void snstop(struct sn_softc *); 131static void snwatchdog(struct ifnet *); 132 133static void sn_setmcast(struct sn_softc *); 134static int sn_getmcf(struct ifnet *ifp, u_char *mcf); 135 136/* I (GB) have been unlucky getting the hardware padding 137 * to work properly. 138 */ 139#define SW_PAD 140 141static const char *chip_ids[15] = { 142 NULL, NULL, NULL, 143 /* 3 */ "SMC91C90/91C92", 144 /* 4 */ "SMC91C94/91C96", 145 /* 5 */ "SMC91C95", 146 NULL, 147 /* 7 */ "SMC91C100", 148 /* 8 */ "SMC91C100FD", 149 /* 9 */ "SMC91C110", 150 NULL, NULL, 151 NULL, NULL, NULL 152}; 153 154int 155sn_attach(device_t dev) 156{ 157 struct sn_softc *sc = device_get_softc(dev); 158 struct ifnet *ifp; 159 uint16_t i; 160 uint8_t *p; 161 int rev; 162 uint16_t address; 163 int err; 164 u_char eaddr[6]; 165 166 ifp = sc->ifp = if_alloc(IFT_ETHER); 167 if (ifp == NULL) { 168 device_printf(dev, "can not if_alloc()\n"); 169 return (ENOSPC); 170 } 171 172 SN_LOCK_INIT(sc); 173 snstop(sc); 174 sc->pages_wanted = -1; 175 176 if (bootverbose || 1) { 177 SMC_SELECT_BANK(sc, 3); 178 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; 179 if (chip_ids[rev]) 180 device_printf(dev, " %s ", chip_ids[rev]); 181 else 182 device_printf(dev, " unsupported chip: rev %d ", rev); 183 SMC_SELECT_BANK(sc, 1); 184 i = CSR_READ_2(sc, CONFIG_REG_W); 185 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP"); 186 } 187 188 /* 189 * Read the station address from the chip. The MAC address is bank 1, 190 * regs 4 - 9 191 */ 192 SMC_SELECT_BANK(sc, 1); 193 p = (uint8_t *) eaddr; 194 for (i = 0; i < 6; i += 2) { 195 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); 196 p[i + 1] = address >> 8; 197 p[i] = address & 0xFF; 198 } 199 ifp->if_softc = sc; 200 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 201 ifp->if_mtu = ETHERMTU; 202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 203 ifp->if_start = snstart; 204 ifp->if_ioctl = snioctl; 205 ifp->if_watchdog = snwatchdog; 206 ifp->if_init = sninit; 207 ifp->if_baudrate = 10000000; 208 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 209 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 210 IFQ_SET_READY(&ifp->if_snd); 211 ifp->if_timer = 0; 212 213 ether_ifattach(ifp, eaddr); 214 215 /* 216 * Activate the interrupt so we can get card interrupts. This 217 * needs to be done last so that we don't have/hold the lock 218 * during startup to avoid LORs in the network layer. 219 */ 220 if ((err = bus_setup_intr(dev, sc->irq_res, 221 INTR_TYPE_NET | INTR_MPSAFE, sn_intr, sc, &sc->intrhand)) != 0) { 222 sn_detach(dev); 223 return err; 224 } 225 return 0; 226} 227 228 229int 230sn_detach(device_t dev) 231{ 232 struct sn_softc *sc = device_get_softc(dev); 233 struct ifnet *ifp = sc->ifp; 234 235 snstop(sc); 236 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 237 ether_ifdetach(ifp); 238 sn_deactivate(dev); 239 if_free(ifp); 240 SN_LOCK_DESTROY(sc); 241 return 0; 242} 243 244static void 245sninit(void *xsc) 246{ 247 struct sn_softc *sc = xsc; 248 SN_LOCK(sc); 249 sninit_locked(sc); 250 SN_UNLOCK(sc); 251} 252 253/* 254 * Reset and initialize the chip 255 */ 256static void 257sninit_locked(void *xsc) 258{ 259 struct sn_softc *sc = xsc; 260 struct ifnet *ifp = sc->ifp; 261 int flags; 262 int mask; 263 264 SN_ASSERT_LOCKED(sc); 265 266 /* 267 * This resets the registers mostly to defaults, but doesn't affect 268 * EEPROM. After the reset cycle, we pause briefly for the chip to 269 * be happy. 270 */ 271 SMC_SELECT_BANK(sc, 0); 272 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); 273 SMC_DELAY(sc); 274 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 275 SMC_DELAY(sc); 276 SMC_DELAY(sc); 277 278 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 279 280 /* 281 * Set the control register to automatically release succesfully 282 * transmitted packets (making the best use out of our limited 283 * memory) and to enable the EPH interrupt on certain TX errors. 284 */ 285 SMC_SELECT_BANK(sc, 1); 286 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 287 CTR_CR_ENABLE | CTR_LE_ENABLE)); 288 289 /* Set squelch level to 240mV (default 480mV) */ 290 flags = CSR_READ_2(sc, CONFIG_REG_W); 291 flags |= CR_SET_SQLCH; 292 CSR_WRITE_2(sc, CONFIG_REG_W, flags); 293 294 /* 295 * Reset the MMU and wait for it to be un-busy. 296 */ 297 SMC_SELECT_BANK(sc, 2); 298 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); 299 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 300 ; 301 302 /* 303 * Disable all interrupts 304 */ 305 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 306 307 sn_setmcast(sc); 308 309 /* 310 * Set the transmitter control. We want it enabled. 311 */ 312 flags = TCR_ENABLE; 313 314#ifndef SW_PAD 315 /* 316 * I (GB) have been unlucky getting this to work. 317 */ 318 flags |= TCR_PAD_ENABLE; 319#endif /* SW_PAD */ 320 321 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); 322 323 324 /* 325 * Now, enable interrupts 326 */ 327 SMC_SELECT_BANK(sc, 2); 328 329 mask = IM_EPH_INT | 330 IM_RX_OVRN_INT | 331 IM_RCV_INT | 332 IM_TX_INT; 333 334 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 335 sc->intr_mask = mask; 336 sc->pages_wanted = -1; 337 338 339 /* 340 * Mark the interface running but not active. 341 */ 342 ifp->if_drv_flags |= IFF_DRV_RUNNING; 343 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 344 345 /* 346 * Attempt to push out any waiting packets. 347 */ 348 snstart_locked(ifp); 349} 350 351static void 352snstart(struct ifnet *ifp) 353{ 354 struct sn_softc *sc = ifp->if_softc; 355 SN_LOCK(sc); 356 snstart_locked(ifp); 357 SN_UNLOCK(sc); 358} 359 360 361static void 362snstart_locked(struct ifnet *ifp) 363{ 364 struct sn_softc *sc = ifp->if_softc; 365 u_int len; 366 struct mbuf *m; 367 struct mbuf *top; 368 int pad; 369 int mask; 370 uint16_t length; 371 uint16_t numPages; 372 uint8_t packet_no; 373 int time_out; 374 int junk = 0; 375 376 SN_ASSERT_LOCKED(sc); 377 378 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 379 return; 380 if (sc->pages_wanted != -1) { 381 if_printf(ifp, "snstart() while memory allocation pending\n"); 382 return; 383 } 384startagain: 385 386 /* 387 * Sneak a peek at the next packet 388 */ 389 m = ifp->if_snd.ifq_head; 390 if (m == 0) 391 return; 392 /* 393 * Compute the frame length and set pad to give an overall even 394 * number of bytes. Below we assume that the packet length is even. 395 */ 396 for (len = 0, top = m; m; m = m->m_next) 397 len += m->m_len; 398 399 pad = (len & 1); 400 401 /* 402 * We drop packets that are too large. Perhaps we should truncate 403 * them instead? 404 */ 405 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 406 if_printf(ifp, "large packet discarded (A)\n"); 407 ++ifp->if_oerrors; 408 IF_DRV_DEQUEUE(&ifp->if_snd, m); 409 m_freem(m); 410 goto readcheck; 411 } 412#ifdef SW_PAD 413 414 /* 415 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 416 */ 417 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 418 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 419 420#endif /* SW_PAD */ 421 422 length = pad + len; 423 424 /* 425 * The MMU wants the number of pages to be the number of 256 byte 426 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 427 * include space for the status word, byte count and control bytes in 428 * the allocation request. 429 */ 430 numPages = (length + 6) >> 8; 431 432 433 /* 434 * Now, try to allocate the memory 435 */ 436 SMC_SELECT_BANK(sc, 2); 437 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 438 439 /* 440 * Wait a short amount of time to see if the allocation request 441 * completes. Otherwise, I enable the interrupt and wait for 442 * completion asyncronously. 443 */ 444 445 time_out = MEMORY_WAIT_TIME; 446 do { 447 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) 448 break; 449 } while (--time_out); 450 451 if (!time_out || junk > 10) { 452 453 /* 454 * No memory now. Oh well, wait until the chip finds memory 455 * later. Remember how many pages we were asking for and 456 * enable the allocation completion interrupt. Also set a 457 * watchdog in case we miss the interrupt. We mark the 458 * interface active since there is no point in attempting an 459 * snstart() until after the memory is available. 460 */ 461 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; 462 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 463 sc->intr_mask = mask; 464 465 ifp->if_timer = 1; 466 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 467 sc->pages_wanted = numPages; 468 return; 469 } 470 /* 471 * The memory allocation completed. Check the results. 472 */ 473 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 474 if (packet_no & ARR_FAILED) { 475 if (junk++ > 10) 476 if_printf(ifp, "Memory allocation failed\n"); 477 goto startagain; 478 } 479 /* 480 * We have a packet number, so tell the card to use it. 481 */ 482 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 483 484 /* 485 * Point to the beginning of the packet 486 */ 487 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 488 489 /* 490 * Send the packet length (+6 for status, length and control byte) 491 * and the status word (set to zeros) 492 */ 493 CSR_WRITE_2(sc, DATA_REG_W, 0); 494 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 495 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 496 497 /* 498 * Get the packet from the kernel. This will include the Ethernet 499 * frame header, MAC Addresses etc. 500 */ 501 IF_DRV_DEQUEUE(&ifp->if_snd, m); 502 503 /* 504 * Push out the data to the card. 505 */ 506 for (top = m; m != 0; m = m->m_next) { 507 508 /* 509 * Push out words. 510 */ 511 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 512 m->m_len / 2); 513 514 /* 515 * Push out remaining byte. 516 */ 517 if (m->m_len & 1) 518 CSR_WRITE_1(sc, DATA_REG_B, 519 *(mtod(m, caddr_t) + m->m_len - 1)); 520 } 521 522 /* 523 * Push out padding. 524 */ 525 while (pad > 1) { 526 CSR_WRITE_2(sc, DATA_REG_W, 0); 527 pad -= 2; 528 } 529 if (pad) 530 CSR_WRITE_1(sc, DATA_REG_B, 0); 531 532 /* 533 * Push out control byte and unused packet byte The control byte is 0 534 * meaning the packet is even lengthed and no special CRC handling is 535 * desired. 536 */ 537 CSR_WRITE_2(sc, DATA_REG_W, 0); 538 539 /* 540 * Enable the interrupts and let the chipset deal with it Also set a 541 * watchdog in case we miss the interrupt. 542 */ 543 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 544 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 545 sc->intr_mask = mask; 546 547 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 548 549 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 550 ifp->if_timer = 1; 551 552 BPF_MTAP(ifp, top); 553 554 ifp->if_opackets++; 555 m_freem(top); 556 557 558readcheck: 559 560 /* 561 * Is another packet coming in? We don't want to overflow the tiny 562 * RX FIFO. If nothing has arrived then attempt to queue another 563 * transmit packet. 564 */ 565 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY) 566 goto startagain; 567 return; 568} 569 570 571 572/* Resume a packet transmit operation after a memory allocation 573 * has completed. 574 * 575 * This is basically a hacked up copy of snstart() which handles 576 * a completed memory allocation the same way snstart() does. 577 * It then passes control to snstart to handle any other queued 578 * packets. 579 */ 580static void 581snresume(struct ifnet *ifp) 582{ 583 struct sn_softc *sc = ifp->if_softc; 584 u_int len; 585 struct mbuf *m; 586 struct mbuf *top; 587 int pad; 588 int mask; 589 uint16_t length; 590 uint16_t numPages; 591 uint16_t pages_wanted; 592 uint8_t packet_no; 593 594 if (sc->pages_wanted < 0) 595 return; 596 597 pages_wanted = sc->pages_wanted; 598 sc->pages_wanted = -1; 599 600 /* 601 * Sneak a peek at the next packet 602 */ 603 m = ifp->if_snd.ifq_head; 604 if (m == 0) { 605 if_printf(ifp, "snresume() with nothing to send\n"); 606 return; 607 } 608 /* 609 * Compute the frame length and set pad to give an overall even 610 * number of bytes. Below we assume that the packet length is even. 611 */ 612 for (len = 0, top = m; m; m = m->m_next) 613 len += m->m_len; 614 615 pad = (len & 1); 616 617 /* 618 * We drop packets that are too large. Perhaps we should truncate 619 * them instead? 620 */ 621 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 622 if_printf(ifp, "large packet discarded (B)\n"); 623 ++ifp->if_oerrors; 624 IF_DRV_DEQUEUE(&ifp->if_snd, m); 625 m_freem(m); 626 return; 627 } 628#ifdef SW_PAD 629 630 /* 631 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 632 */ 633 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 634 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 635 636#endif /* SW_PAD */ 637 638 length = pad + len; 639 640 641 /* 642 * The MMU wants the number of pages to be the number of 256 byte 643 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 644 * include space for the status word, byte count and control bytes in 645 * the allocation request. 646 */ 647 numPages = (length + 6) >> 8; 648 649 650 SMC_SELECT_BANK(sc, 2); 651 652 /* 653 * The memory allocation completed. Check the results. If it failed, 654 * we simply set a watchdog timer and hope for the best. 655 */ 656 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 657 if (packet_no & ARR_FAILED) { 658 if_printf(ifp, "Memory allocation failed. Weird.\n"); 659 ifp->if_timer = 1; 660 goto try_start; 661 } 662 /* 663 * We have a packet number, so tell the card to use it. 664 */ 665 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 666 667 /* 668 * Now, numPages should match the pages_wanted recorded when the 669 * memory allocation was initiated. 670 */ 671 if (pages_wanted != numPages) { 672 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 673 /* 674 * If the allocation was the wrong size we simply release the 675 * memory once it is granted. Wait for the MMU to be un-busy. 676 */ 677 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 678 ; 679 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 680 681 return; 682 } 683 /* 684 * Point to the beginning of the packet 685 */ 686 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 687 688 /* 689 * Send the packet length (+6 for status, length and control byte) 690 * and the status word (set to zeros) 691 */ 692 CSR_WRITE_2(sc, DATA_REG_W, 0); 693 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 694 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 695 696 /* 697 * Get the packet from the kernel. This will include the Ethernet 698 * frame header, MAC Addresses etc. 699 */ 700 IF_DRV_DEQUEUE(&ifp->if_snd, m); 701 702 /* 703 * Push out the data to the card. 704 */ 705 for (top = m; m != 0; m = m->m_next) { 706 707 /* 708 * Push out words. 709 */ 710 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 711 m->m_len / 2); 712 /* 713 * Push out remaining byte. 714 */ 715 if (m->m_len & 1) 716 CSR_WRITE_1(sc, DATA_REG_B, 717 *(mtod(m, caddr_t) + m->m_len - 1)); 718 } 719 720 /* 721 * Push out padding. 722 */ 723 while (pad > 1) { 724 CSR_WRITE_2(sc, DATA_REG_W, 0); 725 pad -= 2; 726 } 727 if (pad) 728 CSR_WRITE_1(sc, DATA_REG_B, 0); 729 730 /* 731 * Push out control byte and unused packet byte The control byte is 0 732 * meaning the packet is even lengthed and no special CRC handling is 733 * desired. 734 */ 735 CSR_WRITE_2(sc, DATA_REG_W, 0); 736 737 /* 738 * Enable the interrupts and let the chipset deal with it Also set a 739 * watchdog in case we miss the interrupt. 740 */ 741 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 742 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 743 sc->intr_mask = mask; 744 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 745 746 BPF_MTAP(ifp, top); 747 748 ifp->if_opackets++; 749 m_freem(top); 750 751try_start: 752 753 /* 754 * Now pass control to snstart() to queue any additional packets 755 */ 756 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 757 snstart(ifp); 758 759 /* 760 * We've sent something, so we're active. Set a watchdog in case the 761 * TX_EMPTY interrupt is lost. 762 */ 763 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 764 ifp->if_timer = 1; 765 766 return; 767} 768 769 770void 771sn_intr(void *arg) 772{ 773 int status, interrupts; 774 struct sn_softc *sc = (struct sn_softc *) arg; 775 struct ifnet *ifp = sc->ifp; 776 777 /* 778 * Chip state registers 779 */ 780 uint8_t mask; 781 uint8_t packet_no; 782 uint16_t tx_status; 783 uint16_t card_stats; 784 785 SN_LOCK(sc); 786 787 /* 788 * Clear the watchdog. 789 */ 790 ifp->if_timer = 0; 791 792 SMC_SELECT_BANK(sc, 2); 793 794 /* 795 * Obtain the current interrupt mask and clear the hardware mask 796 * while servicing interrupts. 797 */ 798 mask = CSR_READ_1(sc, INTR_MASK_REG_B); 799 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 800 801 /* 802 * Get the set of interrupts which occurred and eliminate any which 803 * are masked. 804 */ 805 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); 806 status = interrupts & mask; 807 808 /* 809 * Now, process each of the interrupt types. 810 */ 811 812 /* 813 * Receive Overrun. 814 */ 815 if (status & IM_RX_OVRN_INT) { 816 /* 817 * Acknowlege Interrupt 818 */ 819 SMC_SELECT_BANK(sc, 2); 820 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT); 821 822 ++ifp->if_ierrors; 823 } 824 /* 825 * Got a packet. 826 */ 827 if (status & IM_RCV_INT) { 828 int packet_number; 829 830 SMC_SELECT_BANK(sc, 2); 831 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 832 833 if (packet_number & FIFO_REMPTY) { 834 /* 835 * we got called , but nothing was on the FIFO 836 */ 837 printf("sn: Receive interrupt with nothing on FIFO\n"); 838 goto out; 839 } 840 snread(ifp); 841 } 842 /* 843 * An on-card memory allocation came through. 844 */ 845 if (status & IM_ALLOC_INT) { 846 /* 847 * Disable this interrupt. 848 */ 849 mask &= ~IM_ALLOC_INT; 850 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 851 snresume(ifp); 852 } 853 /* 854 * TX Completion. Handle a transmit error message. This will only be 855 * called when there is an error, because of the AUTO_RELEASE mode. 856 */ 857 if (status & IM_TX_INT) { 858 /* 859 * Acknowlege Interrupt 860 */ 861 SMC_SELECT_BANK(sc, 2); 862 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT); 863 864 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); 865 packet_no &= FIFO_TX_MASK; 866 867 /* 868 * select this as the packet to read from 869 */ 870 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 871 872 /* 873 * Position the pointer to the first word from this packet 874 */ 875 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 876 877 /* 878 * Fetch the TX status word. The value found here will be a 879 * copy of the EPH_STATUS_REG_W at the time the transmit 880 * failed. 881 */ 882 tx_status = CSR_READ_2(sc, DATA_REG_W); 883 884 if (tx_status & EPHSR_TX_SUC) { 885 device_printf(sc->dev, 886 "Successful packet caused interrupt\n"); 887 } else { 888 ++ifp->if_oerrors; 889 } 890 891 if (tx_status & EPHSR_LATCOL) 892 ++ifp->if_collisions; 893 894 /* 895 * Some of these errors will have disabled transmit. 896 * Re-enable transmit now. 897 */ 898 SMC_SELECT_BANK(sc, 0); 899 900#ifdef SW_PAD 901 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE); 902#else 903 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 904#endif /* SW_PAD */ 905 906 /* 907 * kill the failed packet. Wait for the MMU to be un-busy. 908 */ 909 SMC_SELECT_BANK(sc, 2); 910 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 911 ; 912 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 913 914 /* 915 * Attempt to queue more transmits. 916 */ 917 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 918 snstart_locked(ifp); 919 } 920 /* 921 * Transmit underrun. We use this opportunity to update transmit 922 * statistics from the card. 923 */ 924 if (status & IM_TX_EMPTY_INT) { 925 926 /* 927 * Acknowlege Interrupt 928 */ 929 SMC_SELECT_BANK(sc, 2); 930 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 931 932 /* 933 * Disable this interrupt. 934 */ 935 mask &= ~IM_TX_EMPTY_INT; 936 937 SMC_SELECT_BANK(sc, 0); 938 card_stats = CSR_READ_2(sc, COUNTER_REG_W); 939 940 /* 941 * Single collisions 942 */ 943 ifp->if_collisions += card_stats & ECR_COLN_MASK; 944 945 /* 946 * Multiple collisions 947 */ 948 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 949 950 SMC_SELECT_BANK(sc, 2); 951 952 /* 953 * Attempt to enqueue some more stuff. 954 */ 955 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 956 snstart_locked(ifp); 957 } 958 /* 959 * Some other error. Try to fix it by resetting the adapter. 960 */ 961 if (status & IM_EPH_INT) { 962 snstop(sc); 963 sninit_locked(sc); 964 } 965 966out: 967 /* 968 * Handled all interrupt sources. 969 */ 970 971 SMC_SELECT_BANK(sc, 2); 972 973 /* 974 * Reestablish interrupts from mask which have not been deselected 975 * during this interrupt. Note that the hardware mask, which was set 976 * to 0x00 at the start of this service routine, may have been 977 * updated by one or more of the interrupt handers and we must let 978 * those new interrupts stay enabled here. 979 */ 980 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); 981 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 982 sc->intr_mask = mask; 983 SN_UNLOCK(sc); 984} 985 986static void 987snread(struct ifnet *ifp) 988{ 989 struct sn_softc *sc = ifp->if_softc; 990 struct ether_header *eh; 991 struct mbuf *m; 992 short status; 993 int packet_number; 994 uint16_t packet_length; 995 uint8_t *data; 996 997 SMC_SELECT_BANK(sc, 2); 998#if 0 999 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1000 1001 if (packet_number & FIFO_REMPTY) { 1002 1003 /* 1004 * we got called , but nothing was on the FIFO 1005 */ 1006 printf("sn: Receive interrupt with nothing on FIFO\n"); 1007 return; 1008 } 1009#endif 1010read_another: 1011 1012 /* 1013 * Start reading from the start of the packet. Since PTR_RCV is set, 1014 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1015 */ 1016 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1017 1018 /* 1019 * First two words are status and packet_length 1020 */ 1021 status = CSR_READ_2(sc, DATA_REG_W); 1022 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK; 1023 1024 /* 1025 * The packet length contains 3 extra words: status, length, and a 1026 * extra word with the control byte. 1027 */ 1028 packet_length -= 6; 1029 1030 /* 1031 * Account for receive errors and discard. 1032 */ 1033 if (status & RS_ERRORS) { 1034 ++ifp->if_ierrors; 1035 goto out; 1036 } 1037 /* 1038 * A packet is received. 1039 */ 1040 1041 /* 1042 * Adjust for odd-length packet. 1043 */ 1044 if (status & RS_ODDFRAME) 1045 packet_length++; 1046 1047 /* 1048 * Allocate a header mbuf from the kernel. 1049 */ 1050 MGETHDR(m, M_DONTWAIT, MT_DATA); 1051 if (m == NULL) 1052 goto out; 1053 1054 m->m_pkthdr.rcvif = ifp; 1055 m->m_pkthdr.len = m->m_len = packet_length; 1056 1057 /* 1058 * Attach an mbuf cluster 1059 */ 1060 MCLGET(m, M_DONTWAIT); 1061 1062 /* 1063 * Insist on getting a cluster 1064 */ 1065 if ((m->m_flags & M_EXT) == 0) { 1066 m_freem(m); 1067 ++ifp->if_ierrors; 1068 printf("sn: snread() kernel memory allocation problem\n"); 1069 goto out; 1070 } 1071 eh = mtod(m, struct ether_header *); 1072 1073 /* 1074 * Get packet, including link layer address, from interface. 1075 */ 1076 data = (uint8_t *) eh; 1077 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1); 1078 if (packet_length & 1) { 1079 data += packet_length & ~1; 1080 *data = CSR_READ_1(sc, DATA_REG_B); 1081 } 1082 ++ifp->if_ipackets; 1083 1084 /* 1085 * Remove link layer addresses and whatnot. 1086 */ 1087 m->m_pkthdr.len = m->m_len = packet_length; 1088 1089 /* 1090 * Drop locks before calling if_input() since it may re-enter 1091 * snstart() in the netisr case. This would result in a 1092 * lock reversal. Better performance might be obtained by 1093 * chaining all packets received, dropping the lock, and then 1094 * calling if_input() on each one. 1095 */ 1096 SN_UNLOCK(sc); 1097 (*ifp->if_input)(ifp, m); 1098 SN_LOCK(sc); 1099 1100out: 1101 1102 /* 1103 * Error or good, tell the card to get rid of this packet Wait for 1104 * the MMU to be un-busy. 1105 */ 1106 SMC_SELECT_BANK(sc, 2); 1107 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1108 ; 1109 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE); 1110 1111 /* 1112 * Check whether another packet is ready 1113 */ 1114 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1115 if (packet_number & FIFO_REMPTY) { 1116 return; 1117 } 1118 goto read_another; 1119} 1120 1121 1122/* 1123 * Handle IOCTLS. This function is completely stolen from if_ep.c 1124 * As with its progenitor, it does not handle hardware address 1125 * changes. 1126 */ 1127static int 1128snioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1129{ 1130 struct sn_softc *sc = ifp->if_softc; 1131 int error = 0; 1132 1133 switch (cmd) { 1134 case SIOCSIFFLAGS: 1135 SN_LOCK(sc); 1136 if ((ifp->if_flags & IFF_UP) == 0 && 1137 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1138 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1139 snstop(sc); 1140 } else { 1141 /* reinitialize card on any parameter change */ 1142 sninit_locked(sc); 1143 } 1144 SN_UNLOCK(sc); 1145 break; 1146 1147 case SIOCADDMULTI: 1148 case SIOCDELMULTI: 1149 /* update multicast filter list. */ 1150 SN_LOCK(sc); 1151 sn_setmcast(sc); 1152 error = 0; 1153 SN_UNLOCK(sc); 1154 break; 1155 default: 1156 error = ether_ioctl(ifp, cmd, data); 1157 break; 1158 } 1159 return (error); 1160} 1161 1162static void 1163snwatchdog(struct ifnet *ifp) 1164{ 1165 sn_intr(ifp->if_softc); 1166} 1167 1168 1169/* 1. zero the interrupt mask 1170 * 2. clear the enable receive flag 1171 * 3. clear the enable xmit flags 1172 */ 1173static void 1174snstop(struct sn_softc *sc) 1175{ 1176 1177 struct ifnet *ifp = sc->ifp; 1178 1179 /* 1180 * Clear interrupt mask; disable all interrupts. 1181 */ 1182 SMC_SELECT_BANK(sc, 2); 1183 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 1184 1185 /* 1186 * Disable transmitter and Receiver 1187 */ 1188 SMC_SELECT_BANK(sc, 0); 1189 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 1190 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 1191 1192 /* 1193 * Cancel watchdog. 1194 */ 1195 ifp->if_timer = 0; 1196} 1197 1198 1199int 1200sn_activate(device_t dev) 1201{ 1202 struct sn_softc *sc = device_get_softc(dev); 1203 1204 sc->port_rid = 0; 1205 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1206 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1207 if (!sc->port_res) { 1208 if (bootverbose) 1209 device_printf(dev, "Cannot allocate ioport\n"); 1210 return ENOMEM; 1211 } 1212 1213 sc->irq_rid = 0; 1214 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 1215 RF_ACTIVE); 1216 if (!sc->irq_res) { 1217 if (bootverbose) 1218 device_printf(dev, "Cannot allocate irq\n"); 1219 sn_deactivate(dev); 1220 return ENOMEM; 1221 } 1222 sc->bst = rman_get_bustag(sc->port_res); 1223 sc->bsh = rman_get_bushandle(sc->port_res); 1224 return (0); 1225} 1226 1227void 1228sn_deactivate(device_t dev) 1229{ 1230 struct sn_softc *sc = device_get_softc(dev); 1231 1232 if (sc->intrhand) 1233 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1234 sc->intrhand = 0; 1235 if (sc->port_res) 1236 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1237 sc->port_res); 1238 sc->port_res = 0; 1239 if (sc->modem_res) 1240 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid, 1241 sc->modem_res); 1242 sc->modem_res = 0; 1243 if (sc->irq_res) 1244 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1245 sc->irq_res); 1246 sc->irq_res = 0; 1247 return; 1248} 1249 1250/* 1251 * Function: sn_probe(device_t dev) 1252 * 1253 * Purpose: 1254 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1255 * Tries to cause as little damage as possible if it's not a SMC chip. 1256 * Returns a 0 on success 1257 * 1258 * Algorithm: 1259 * (1) see if the high byte of BANK_SELECT is 0x33 1260 * (2) compare the ioaddr with the base register's address 1261 * (3) see if I recognize the chip ID in the appropriate register 1262 * 1263 * 1264 */ 1265int 1266sn_probe(device_t dev) 1267{ 1268 struct sn_softc *sc = device_get_softc(dev); 1269 uint16_t bank; 1270 uint16_t revision_register; 1271 uint16_t base_address_register; 1272 int err; 1273 1274 if ((err = sn_activate(dev)) != 0) 1275 return err; 1276 1277 /* 1278 * First, see if the high byte is 0x33 1279 */ 1280 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1281 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1282#ifdef SN_DEBUG 1283 device_printf(dev, "test1 failed\n"); 1284#endif 1285 goto error; 1286 } 1287 /* 1288 * The above MIGHT indicate a device, but I need to write to further 1289 * test this. Go to bank 0, then test that the register still 1290 * reports the high byte is 0x33. 1291 */ 1292 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000); 1293 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1294 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1295#ifdef SN_DEBUG 1296 device_printf(dev, "test2 failed\n"); 1297#endif 1298 goto error; 1299 } 1300 /* 1301 * well, we've already written once, so hopefully another time won't 1302 * hurt. This time, I need to switch the bank register to bank 1, so 1303 * I can access the base address register. The contents of the 1304 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1305 * to match the I/O port address where the adapter is being probed. 1306 */ 1307 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001); 1308 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0; 1309 1310 if (rman_get_start(sc->port_res) != base_address_register) { 1311 1312 /* 1313 * Well, the base address register didn't match. Must not 1314 * have been a SMC chip after all. 1315 */ 1316#ifdef SN_DEBUG 1317 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1318 "base_address_register = 0x%x\n", 1319 rman_get_start(sc->port_res), base_address_register); 1320#endif 1321 goto error; 1322 } 1323 1324 /* 1325 * Check if the revision register is something that I recognize. 1326 * These might need to be added to later, as future revisions could 1327 * be added. 1328 */ 1329 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3); 1330 revision_register = CSR_READ_2(sc, REVISION_REG_W); 1331 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1332 1333 /* 1334 * I don't regonize this chip, so... 1335 */ 1336#ifdef SN_DEBUG 1337 device_printf(dev, "test4 failed\n"); 1338#endif 1339 goto error; 1340 } 1341 1342 /* 1343 * at this point I'll assume that the chip is an SMC9xxx. It might be 1344 * prudent to check a listing of MAC addresses against the hardware 1345 * address, or do some other tests. 1346 */ 1347 sn_deactivate(dev); 1348 return 0; 1349 error: 1350 sn_deactivate(dev); 1351 return ENXIO; 1352} 1353 1354#define MCFSZ 8 1355 1356static void 1357sn_setmcast(struct sn_softc *sc) 1358{ 1359 struct ifnet *ifp = sc->ifp; 1360 int flags; 1361 uint8_t mcf[MCFSZ]; 1362 1363 SN_ASSERT_LOCKED(sc); 1364 1365 /* 1366 * Set the receiver filter. We want receive enabled and auto strip 1367 * of CRC from received packet. If we are promiscuous then set that 1368 * bit too. 1369 */ 1370 flags = RCR_ENABLE | RCR_STRIP_CRC; 1371 1372 if (ifp->if_flags & IFF_PROMISC) { 1373 flags |= RCR_PROMISC | RCR_ALMUL; 1374 } else if (ifp->if_flags & IFF_ALLMULTI) { 1375 flags |= RCR_ALMUL; 1376 } else { 1377 if (sn_getmcf(ifp, mcf)) { 1378 /* set filter */ 1379 SMC_SELECT_BANK(sc, 3); 1380 CSR_WRITE_2(sc, MULTICAST1_REG_W, 1381 ((uint16_t)mcf[1] << 8) | mcf[0]); 1382 CSR_WRITE_2(sc, MULTICAST2_REG_W, 1383 ((uint16_t)mcf[3] << 8) | mcf[2]); 1384 CSR_WRITE_2(sc, MULTICAST3_REG_W, 1385 ((uint16_t)mcf[5] << 8) | mcf[4]); 1386 CSR_WRITE_2(sc, MULTICAST4_REG_W, 1387 ((uint16_t)mcf[7] << 8) | mcf[6]); 1388 } else { 1389 flags |= RCR_ALMUL; 1390 } 1391 } 1392 SMC_SELECT_BANK(sc, 0); 1393 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags); 1394} 1395 1396static int 1397sn_getmcf(struct ifnet *ifp, uint8_t *mcf) 1398{ 1399 int i; 1400 uint32_t index, index2; 1401 uint8_t *af = mcf; 1402 struct ifmultiaddr *ifma; 1403 1404 bzero(mcf, MCFSZ); 1405 1406 IF_ADDR_LOCK(ifp); 1407 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1408 if (ifma->ifma_addr->sa_family != AF_LINK) { 1409 IF_ADDR_UNLOCK(ifp); 1410 return 0; 1411 } 1412 index = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1413 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f; 1414 index2 = 0; 1415 for (i = 0; i < 6; i++) { 1416 index2 <<= 1; 1417 index2 |= (index & 0x01); 1418 index >>= 1; 1419 } 1420 af[index2 >> 3] |= 1 << (index2 & 7); 1421 } 1422 IF_ADDR_UNLOCK(ifp); 1423 return 1; /* use multicast filter */ 1424} 1425