if_sn.c revision 122678
1/* 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/dev/sn/if_sn.c 122678 2003-11-14 17:16:58Z obrien $"); 34 35/* 36 * This is a driver for SMC's 9000 series of Ethernet adapters. 37 * 38 * This FreeBSD driver is derived from the smc9194 Linux driver by 39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 40 * This driver also shamelessly borrows from the FreeBSD ep driver 41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 42 * All rights reserved. 43 * 44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 45 * PC. It is adapted from Erik Stahlman's Linux driver which worked 46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 47 * it will work for the entire SMC 9xxx series. (Ha Ha) 48 * 49 * "Features" of the SMC chip: 50 * 4608 byte packet memory. (for the 91C92. Others have more) 51 * EEPROM for configuration 52 * AUI/TP selection 53 * 54 * Authors: 55 * Erik Stahlman erik@vt.edu 56 * Herb Peyerl hpeyerl@novatel.ca 57 * Andres Vega Garcia avega@sophia.inria.fr 58 * Serge Babkin babkin@hq.icb.chel.su 59 * Gardner Buchanan gbuchanan@shl.com 60 * 61 * Sources: 62 * o SMC databook 63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 65 * 66 * Known Bugs: 67 * o Setting of the hardware address isn't supported. 68 * o Hardware padding isn't used. 69 */ 70 71/* 72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 73 * 74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 75 * BSD-nomads, Tokyo, Japan. 76 */ 77/* 78 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 79 * Special thanks to itojun@itojun.org 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/errno.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/socket.h> 88#include <sys/syslog.h> 89 90#include <sys/module.h> 91#include <sys/bus.h> 92 93#include <machine/bus.h> 94#include <machine/resource.h> 95#include <sys/rman.h> 96 97#include <net/ethernet.h> 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/if_dl.h> 101#include <net/if_types.h> 102#include <net/if_mib.h> 103 104#ifdef INET 105#include <netinet/in.h> 106#include <netinet/in_systm.h> 107#include <netinet/in_var.h> 108#include <netinet/ip.h> 109#endif 110 111#include <net/bpf.h> 112#include <net/bpfdesc.h> 113 114 115#include <dev/sn/if_snreg.h> 116#include <dev/sn/if_snvar.h> 117 118/* Exported variables */ 119devclass_t sn_devclass; 120 121static int snioctl(struct ifnet * ifp, u_long, caddr_t); 122 123static void snresume(struct ifnet *); 124 125static void sninit_locked(void *); 126static void snstart_locked(struct ifnet *); 127 128static void sninit(void *); 129static void snread(struct ifnet *); 130static void snstart(struct ifnet *); 131static void snstop(struct sn_softc *); 132static void snwatchdog(struct ifnet *); 133 134static void sn_setmcast(struct sn_softc *); 135static int sn_getmcf(struct arpcom *ac, u_char *mcf); 136static uint32_t sn_mchash(const uint8_t *addr); 137 138/* I (GB) have been unlucky getting the hardware padding 139 * to work properly. 140 */ 141#define SW_PAD 142 143static const char *chip_ids[15] = { 144 NULL, NULL, NULL, 145 /* 3 */ "SMC91C90/91C92", 146 /* 4 */ "SMC91C94", 147 /* 5 */ "SMC91C95", 148 NULL, 149 /* 7 */ "SMC91C100", 150 /* 8 */ "SMC91C100FD", 151 NULL, NULL, NULL, 152 NULL, NULL, NULL 153}; 154 155int 156sn_attach(device_t dev) 157{ 158 struct sn_softc *sc = device_get_softc(dev); 159 struct ifnet *ifp = &sc->arpcom.ac_if; 160 uint16_t i, w; 161 uint8_t *p; 162 struct ifaddr *ifa; 163 struct sockaddr_dl *sdl; 164 int rev; 165 uint16_t address; 166 int j; 167 int err; 168 169 sc->dev = dev; 170 sn_activate(dev); 171 SN_LOCK_INIT(sc); 172 snstop(sc); 173 sc->pages_wanted = -1; 174 175 SMC_SELECT_BANK(sc, 3); 176 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; 177 if (chip_ids[rev]) 178 device_printf(dev, " %s ", chip_ids[rev]); 179 else 180 device_printf(dev, " unsupported chip"); 181 182 SMC_SELECT_BANK(sc, 1); 183 i = CSR_READ_2(sc, CONFIG_REG_W); 184 printf(i & CR_AUI_SELECT ? "AUI" : "UTP"); 185 186 if (sc->pccard_enaddr) 187 for (j = 0; j < 3; j++) { 188 w = (uint16_t)sc->arpcom.ac_enaddr[j * 2] | 189 (((uint16_t)sc->arpcom.ac_enaddr[j * 2 + 1]) << 8); 190 CSR_WRITE_2(sc, IAR_ADDR0_REG_W + j * 2, w); 191 } 192 193 /* 194 * Read the station address from the chip. The MAC address is bank 1, 195 * regs 4 - 9 196 */ 197 SMC_SELECT_BANK(sc, 1); 198 p = (uint8_t *) &sc->arpcom.ac_enaddr; 199 for (i = 0; i < 6; i += 2) { 200 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); 201 p[i + 1] = address >> 8; 202 p[i] = address & 0xFF; 203 } 204 printf(" MAC address %6D\n", sc->arpcom.ac_enaddr, ":"); 205 ifp->if_softc = sc; 206 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 207 ifp->if_mtu = ETHERMTU; 208 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 209 ifp->if_output = ether_output; 210 ifp->if_start = snstart; 211 ifp->if_ioctl = snioctl; 212 ifp->if_watchdog = snwatchdog; 213 ifp->if_init = sninit; 214 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 215 ifp->if_timer = 0; 216 217 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 218 219 /* 220 * Fill the hardware address into ifa_addr if we find an AF_LINK 221 * entry. We need to do this so bpf's can get the hardware addr of 222 * this card. netstat likes this too! 223 */ 224 ifa = TAILQ_FIRST(&ifp->if_addrhead); 225 while ((ifa != 0) && (ifa->ifa_addr != 0) && 226 (ifa->ifa_addr->sa_family != AF_LINK)) 227 ifa = TAILQ_NEXT(ifa, ifa_link); 228 229 if ((ifa != 0) && (ifa->ifa_addr != 0)) { 230 sdl = (struct sockaddr_dl *) ifa->ifa_addr; 231 sdl->sdl_type = IFT_ETHER; 232 sdl->sdl_alen = ETHER_ADDR_LEN; 233 sdl->sdl_slen = 0; 234 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN); 235 } 236 237 /* 238 * Activate the interrupt so we can get card interrupts. This 239 * needs to be done last so that we don't have/hold the lock 240 * during startup to avoid LORs in the network layer. 241 */ 242 if ((err = bus_setup_intr(dev, sc->irq_res, 243 INTR_TYPE_NET | INTR_MPSAFE, sn_intr, sc, &sc->intrhand)) != 0) { 244 sn_detach(dev); 245 return err; 246 } 247 return 0; 248} 249 250 251int 252sn_detach(device_t dev) 253{ 254 struct sn_softc *sc = device_get_softc(dev); 255 256 snstop(sc); 257 sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING; 258 ether_ifdetach(&sc->arpcom.ac_if); 259 sn_deactivate(dev); 260 SN_LOCK_DESTORY(sc); 261 return 0; 262} 263 264static void 265sninit(void *xsc) 266{ 267 struct sn_softc *sc = xsc; 268 SN_LOCK(sc); 269 sninit_locked(sc); 270 SN_UNLOCK(sc); 271} 272 273/* 274 * Reset and initialize the chip 275 */ 276static void 277sninit_locked(void *xsc) 278{ 279 struct sn_softc *sc = xsc; 280 struct ifnet *ifp = &sc->arpcom.ac_if; 281 int flags; 282 int mask; 283 284 SN_ASSERT_LOCKED(sc); 285 286 /* 287 * This resets the registers mostly to defaults, but doesn't affect 288 * EEPROM. After the reset cycle, we pause briefly for the chip to 289 * be happy. 290 */ 291 SMC_SELECT_BANK(sc, 0); 292 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); 293 SMC_DELAY(sc); 294 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 295 SMC_DELAY(sc); 296 SMC_DELAY(sc); 297 298 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 299 300 /* 301 * Set the control register to automatically release succesfully 302 * transmitted packets (making the best use out of our limited 303 * memory) and to enable the EPH interrupt on certain TX errors. 304 */ 305 SMC_SELECT_BANK(sc, 1); 306 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 307 CTR_CR_ENABLE | CTR_LE_ENABLE)); 308 309 /* Set squelch level to 240mV (default 480mV) */ 310 flags = CSR_READ_2(sc, CONFIG_REG_W); 311 flags |= CR_SET_SQLCH; 312 CSR_WRITE_2(sc, CONFIG_REG_W, flags); 313 314 /* 315 * Reset the MMU and wait for it to be un-busy. 316 */ 317 SMC_SELECT_BANK(sc, 2); 318 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); 319 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 320 ; 321 322 /* 323 * Disable all interrupts 324 */ 325 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 326 327 sn_setmcast(sc); 328 329 /* 330 * Set the transmitter control. We want it enabled. 331 */ 332 flags = TCR_ENABLE; 333 334#ifndef SW_PAD 335 /* 336 * I (GB) have been unlucky getting this to work. 337 */ 338 flags |= TCR_PAD_ENABLE; 339#endif /* SW_PAD */ 340 341 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); 342 343 344 /* 345 * Now, enable interrupts 346 */ 347 SMC_SELECT_BANK(sc, 2); 348 349 mask = IM_EPH_INT | 350 IM_RX_OVRN_INT | 351 IM_RCV_INT | 352 IM_TX_INT; 353 354 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 355 sc->intr_mask = mask; 356 sc->pages_wanted = -1; 357 358 359 /* 360 * Mark the interface running but not active. 361 */ 362 ifp->if_flags |= IFF_RUNNING; 363 ifp->if_flags &= ~IFF_OACTIVE; 364 365 /* 366 * Attempt to push out any waiting packets. 367 */ 368 snstart_locked(ifp); 369} 370 371static void 372snstart(struct ifnet *ifp) 373{ 374 struct sn_softc *sc = ifp->if_softc; 375 SN_LOCK(sc); 376 snstart_locked(ifp); 377 SN_UNLOCK(sc); 378} 379 380 381static void 382snstart_locked(struct ifnet *ifp) 383{ 384 struct sn_softc *sc = ifp->if_softc; 385 u_int len; 386 struct mbuf *m; 387 struct mbuf *top; 388 int pad; 389 int mask; 390 uint16_t length; 391 uint16_t numPages; 392 uint8_t packet_no; 393 int time_out; 394 int junk = 0; 395 396 SN_ASSERT_LOCKED(sc); 397 398 if (sc->arpcom.ac_if.if_flags & IFF_OACTIVE) 399 return; 400 if (sc->pages_wanted != -1) { 401 if_printf(ifp, "snstart() while memory allocation pending\n"); 402 return; 403 } 404startagain: 405 406 /* 407 * Sneak a peek at the next packet 408 */ 409 m = sc->arpcom.ac_if.if_snd.ifq_head; 410 if (m == 0) 411 return; 412 /* 413 * Compute the frame length and set pad to give an overall even 414 * number of bytes. Below we assume that the packet length is even. 415 */ 416 for (len = 0, top = m; m; m = m->m_next) 417 len += m->m_len; 418 419 pad = (len & 1); 420 421 /* 422 * We drop packets that are too large. Perhaps we should truncate 423 * them instead? 424 */ 425 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 426 if_printf(ifp, "large packet discarded (A)\n"); 427 ++sc->arpcom.ac_if.if_oerrors; 428 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 429 m_freem(m); 430 goto readcheck; 431 } 432#ifdef SW_PAD 433 434 /* 435 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 436 */ 437 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 438 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 439 440#endif /* SW_PAD */ 441 442 length = pad + len; 443 444 /* 445 * The MMU wants the number of pages to be the number of 256 byte 446 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 447 * include space for the status word, byte count and control bytes in 448 * the allocation request. 449 */ 450 numPages = (length + 6) >> 8; 451 452 453 /* 454 * Now, try to allocate the memory 455 */ 456 SMC_SELECT_BANK(sc, 2); 457 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 458 459 /* 460 * Wait a short amount of time to see if the allocation request 461 * completes. Otherwise, I enable the interrupt and wait for 462 * completion asyncronously. 463 */ 464 465 time_out = MEMORY_WAIT_TIME; 466 do { 467 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) 468 break; 469 } while (--time_out); 470 471 if (!time_out || junk > 10) { 472 473 /* 474 * No memory now. Oh well, wait until the chip finds memory 475 * later. Remember how many pages we were asking for and 476 * enable the allocation completion interrupt. Also set a 477 * watchdog in case we miss the interrupt. We mark the 478 * interface active since there is no point in attempting an 479 * snstart() until after the memory is available. 480 */ 481 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; 482 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 483 sc->intr_mask = mask; 484 485 sc->arpcom.ac_if.if_timer = 1; 486 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 487 sc->pages_wanted = numPages; 488 return; 489 } 490 /* 491 * The memory allocation completed. Check the results. 492 */ 493 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 494 if (packet_no & ARR_FAILED) { 495 if (junk++ > 10) 496 if_printf(ifp, "Memory allocation failed\n"); 497 goto startagain; 498 } 499 /* 500 * We have a packet number, so tell the card to use it. 501 */ 502 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 503 504 /* 505 * Point to the beginning of the packet 506 */ 507 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 508 509 /* 510 * Send the packet length (+6 for status, length and control byte) 511 * and the status word (set to zeros) 512 */ 513 CSR_WRITE_2(sc, DATA_REG_W, 0); 514 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 515 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 516 517 /* 518 * Get the packet from the kernel. This will include the Ethernet 519 * frame header, MAC Addresses etc. 520 */ 521 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 522 523 /* 524 * Push out the data to the card. 525 */ 526 for (top = m; m != 0; m = m->m_next) { 527 528 /* 529 * Push out words. 530 */ 531 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 532 m->m_len / 2); 533 534 /* 535 * Push out remaining byte. 536 */ 537 if (m->m_len & 1) 538 CSR_WRITE_1(sc, DATA_REG_B, 539 *(mtod(m, caddr_t) + m->m_len - 1)); 540 } 541 542 /* 543 * Push out padding. 544 */ 545 while (pad > 1) { 546 CSR_WRITE_2(sc, DATA_REG_W, 0); 547 pad -= 2; 548 } 549 if (pad) 550 CSR_WRITE_1(sc, DATA_REG_B, 0); 551 552 /* 553 * Push out control byte and unused packet byte The control byte is 0 554 * meaning the packet is even lengthed and no special CRC handling is 555 * desired. 556 */ 557 CSR_WRITE_2(sc, DATA_REG_W, 0); 558 559 /* 560 * Enable the interrupts and let the chipset deal with it Also set a 561 * watchdog in case we miss the interrupt. 562 */ 563 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 564 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 565 sc->intr_mask = mask; 566 567 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 568 569 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 570 sc->arpcom.ac_if.if_timer = 1; 571 572 BPF_MTAP(ifp, top); 573 574 sc->arpcom.ac_if.if_opackets++; 575 m_freem(top); 576 577 578readcheck: 579 580 /* 581 * Is another packet coming in? We don't want to overflow the tiny 582 * RX FIFO. If nothing has arrived then attempt to queue another 583 * transmit packet. 584 */ 585 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY) 586 goto startagain; 587 return; 588} 589 590 591 592/* Resume a packet transmit operation after a memory allocation 593 * has completed. 594 * 595 * This is basically a hacked up copy of snstart() which handles 596 * a completed memory allocation the same way snstart() does. 597 * It then passes control to snstart to handle any other queued 598 * packets. 599 */ 600static void 601snresume(struct ifnet *ifp) 602{ 603 struct sn_softc *sc = ifp->if_softc; 604 u_int len; 605 struct mbuf *m; 606 struct mbuf *top; 607 int pad; 608 int mask; 609 uint16_t length; 610 uint16_t numPages; 611 uint16_t pages_wanted; 612 uint8_t packet_no; 613 614 if (sc->pages_wanted < 0) 615 return; 616 617 pages_wanted = sc->pages_wanted; 618 sc->pages_wanted = -1; 619 620 /* 621 * Sneak a peek at the next packet 622 */ 623 m = sc->arpcom.ac_if.if_snd.ifq_head; 624 if (m == 0) { 625 if_printf(ifp, "snresume() with nothing to send\n"); 626 return; 627 } 628 /* 629 * Compute the frame length and set pad to give an overall even 630 * number of bytes. Below we assume that the packet length is even. 631 */ 632 for (len = 0, top = m; m; m = m->m_next) 633 len += m->m_len; 634 635 pad = (len & 1); 636 637 /* 638 * We drop packets that are too large. Perhaps we should truncate 639 * them instead? 640 */ 641 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 642 if_printf(ifp, "large packet discarded (B)\n"); 643 ++sc->arpcom.ac_if.if_oerrors; 644 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 645 m_freem(m); 646 return; 647 } 648#ifdef SW_PAD 649 650 /* 651 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 652 */ 653 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 654 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 655 656#endif /* SW_PAD */ 657 658 length = pad + len; 659 660 661 /* 662 * The MMU wants the number of pages to be the number of 256 byte 663 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 664 * include space for the status word, byte count and control bytes in 665 * the allocation request. 666 */ 667 numPages = (length + 6) >> 8; 668 669 670 SMC_SELECT_BANK(sc, 2); 671 672 /* 673 * The memory allocation completed. Check the results. If it failed, 674 * we simply set a watchdog timer and hope for the best. 675 */ 676 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 677 if (packet_no & ARR_FAILED) { 678 if_printf(ifp, "Memory allocation failed. Weird.\n"); 679 sc->arpcom.ac_if.if_timer = 1; 680 goto try_start; 681 } 682 /* 683 * We have a packet number, so tell the card to use it. 684 */ 685 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 686 687 /* 688 * Now, numPages should match the pages_wanted recorded when the 689 * memory allocation was initiated. 690 */ 691 if (pages_wanted != numPages) { 692 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 693 /* 694 * If the allocation was the wrong size we simply release the 695 * memory once it is granted. Wait for the MMU to be un-busy. 696 */ 697 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 698 ; 699 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 700 701 return; 702 } 703 /* 704 * Point to the beginning of the packet 705 */ 706 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 707 708 /* 709 * Send the packet length (+6 for status, length and control byte) 710 * and the status word (set to zeros) 711 */ 712 CSR_WRITE_2(sc, DATA_REG_W, 0); 713 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 714 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 715 716 /* 717 * Get the packet from the kernel. This will include the Ethernet 718 * frame header, MAC Addresses etc. 719 */ 720 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 721 722 /* 723 * Push out the data to the card. 724 */ 725 for (top = m; m != 0; m = m->m_next) { 726 727 /* 728 * Push out words. 729 */ 730 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 731 m->m_len / 2); 732 /* 733 * Push out remaining byte. 734 */ 735 if (m->m_len & 1) 736 CSR_WRITE_1(sc, DATA_REG_B, 737 *(mtod(m, caddr_t) + m->m_len - 1)); 738 } 739 740 /* 741 * Push out padding. 742 */ 743 while (pad > 1) { 744 CSR_WRITE_2(sc, DATA_REG_W, 0); 745 pad -= 2; 746 } 747 if (pad) 748 CSR_WRITE_1(sc, DATA_REG_B, 0); 749 750 /* 751 * Push out control byte and unused packet byte The control byte is 0 752 * meaning the packet is even lengthed and no special CRC handling is 753 * desired. 754 */ 755 CSR_WRITE_2(sc, DATA_REG_W, 0); 756 757 /* 758 * Enable the interrupts and let the chipset deal with it Also set a 759 * watchdog in case we miss the interrupt. 760 */ 761 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 762 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 763 sc->intr_mask = mask; 764 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 765 766 BPF_MTAP(ifp, top); 767 768 sc->arpcom.ac_if.if_opackets++; 769 m_freem(top); 770 771try_start: 772 773 /* 774 * Now pass control to snstart() to queue any additional packets 775 */ 776 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 777 snstart(ifp); 778 779 /* 780 * We've sent something, so we're active. Set a watchdog in case the 781 * TX_EMPTY interrupt is lost. 782 */ 783 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 784 sc->arpcom.ac_if.if_timer = 1; 785 786 return; 787} 788 789 790void 791sn_intr(void *arg) 792{ 793 int status, interrupts; 794 struct sn_softc *sc = (struct sn_softc *) arg; 795 struct ifnet *ifp = &sc->arpcom.ac_if; 796 797 /* 798 * Chip state registers 799 */ 800 uint8_t mask; 801 uint8_t packet_no; 802 uint16_t tx_status; 803 uint16_t card_stats; 804 805 SN_LOCK(sc); 806 807 /* 808 * Clear the watchdog. 809 */ 810 ifp->if_timer = 0; 811 812 SMC_SELECT_BANK(sc, 2); 813 814 /* 815 * Obtain the current interrupt mask and clear the hardware mask 816 * while servicing interrupts. 817 */ 818 mask = CSR_READ_1(sc, INTR_MASK_REG_B); 819 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 820 821 /* 822 * Get the set of interrupts which occurred and eliminate any which 823 * are masked. 824 */ 825 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); 826 status = interrupts & mask; 827 828 /* 829 * Now, process each of the interrupt types. 830 */ 831 832 /* 833 * Receive Overrun. 834 */ 835 if (status & IM_RX_OVRN_INT) { 836 /* 837 * Acknowlege Interrupt 838 */ 839 SMC_SELECT_BANK(sc, 2); 840 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT); 841 842 ++sc->arpcom.ac_if.if_ierrors; 843 } 844 /* 845 * Got a packet. 846 */ 847 if (status & IM_RCV_INT) { 848 int packet_number; 849 850 SMC_SELECT_BANK(sc, 2); 851 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 852 853 if (packet_number & FIFO_REMPTY) { 854 /* 855 * we got called , but nothing was on the FIFO 856 */ 857 printf("sn: Receive interrupt with nothing on FIFO\n"); 858 goto out; 859 } 860 snread(ifp); 861 } 862 /* 863 * An on-card memory allocation came through. 864 */ 865 if (status & IM_ALLOC_INT) { 866 /* 867 * Disable this interrupt. 868 */ 869 mask &= ~IM_ALLOC_INT; 870 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 871 snresume(&sc->arpcom.ac_if); 872 } 873 /* 874 * TX Completion. Handle a transmit error message. This will only be 875 * called when there is an error, because of the AUTO_RELEASE mode. 876 */ 877 if (status & IM_TX_INT) { 878 /* 879 * Acknowlege Interrupt 880 */ 881 SMC_SELECT_BANK(sc, 2); 882 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT); 883 884 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); 885 packet_no &= FIFO_TX_MASK; 886 887 /* 888 * select this as the packet to read from 889 */ 890 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 891 892 /* 893 * Position the pointer to the first word from this packet 894 */ 895 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 896 897 /* 898 * Fetch the TX status word. The value found here will be a 899 * copy of the EPH_STATUS_REG_W at the time the transmit 900 * failed. 901 */ 902 tx_status = CSR_READ_2(sc, DATA_REG_W); 903 904 if (tx_status & EPHSR_TX_SUC) { 905 device_printf(sc->dev, 906 "Successful packet caused interrupt\n"); 907 } else { 908 ++sc->arpcom.ac_if.if_oerrors; 909 } 910 911 if (tx_status & EPHSR_LATCOL) 912 ++sc->arpcom.ac_if.if_collisions; 913 914 /* 915 * Some of these errors will have disabled transmit. 916 * Re-enable transmit now. 917 */ 918 SMC_SELECT_BANK(sc, 0); 919 920#ifdef SW_PAD 921 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE); 922#else 923 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 924#endif /* SW_PAD */ 925 926 /* 927 * kill the failed packet. Wait for the MMU to be un-busy. 928 */ 929 SMC_SELECT_BANK(sc, 2); 930 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 931 ; 932 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 933 934 /* 935 * Attempt to queue more transmits. 936 */ 937 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 938 snstart_locked(&sc->arpcom.ac_if); 939 } 940 /* 941 * Transmit underrun. We use this opportunity to update transmit 942 * statistics from the card. 943 */ 944 if (status & IM_TX_EMPTY_INT) { 945 946 /* 947 * Acknowlege Interrupt 948 */ 949 SMC_SELECT_BANK(sc, 2); 950 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 951 952 /* 953 * Disable this interrupt. 954 */ 955 mask &= ~IM_TX_EMPTY_INT; 956 957 SMC_SELECT_BANK(sc, 0); 958 card_stats = CSR_READ_2(sc, COUNTER_REG_W); 959 960 /* 961 * Single collisions 962 */ 963 sc->arpcom.ac_if.if_collisions += card_stats & ECR_COLN_MASK; 964 965 /* 966 * Multiple collisions 967 */ 968 sc->arpcom.ac_if.if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 969 970 SMC_SELECT_BANK(sc, 2); 971 972 /* 973 * Attempt to enqueue some more stuff. 974 */ 975 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 976 snstart_locked(&sc->arpcom.ac_if); 977 } 978 /* 979 * Some other error. Try to fix it by resetting the adapter. 980 */ 981 if (status & IM_EPH_INT) { 982 snstop(sc); 983 sninit_locked(sc); 984 } 985 986out: 987 /* 988 * Handled all interrupt sources. 989 */ 990 991 SMC_SELECT_BANK(sc, 2); 992 993 /* 994 * Reestablish interrupts from mask which have not been deselected 995 * during this interrupt. Note that the hardware mask, which was set 996 * to 0x00 at the start of this service routine, may have been 997 * updated by one or more of the interrupt handers and we must let 998 * those new interrupts stay enabled here. 999 */ 1000 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); 1001 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 1002 sc->intr_mask = mask; 1003 SN_UNLOCK(sc); 1004} 1005 1006static void 1007snread(struct ifnet *ifp) 1008{ 1009 struct sn_softc *sc = ifp->if_softc; 1010 struct ether_header *eh; 1011 struct mbuf *m; 1012 short status; 1013 int packet_number; 1014 uint16_t packet_length; 1015 uint8_t *data; 1016 1017 SMC_SELECT_BANK(sc, 2); 1018#if 0 1019 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1020 1021 if (packet_number & FIFO_REMPTY) { 1022 1023 /* 1024 * we got called , but nothing was on the FIFO 1025 */ 1026 printf("sn: Receive interrupt with nothing on FIFO\n"); 1027 return; 1028 } 1029#endif 1030read_another: 1031 1032 /* 1033 * Start reading from the start of the packet. Since PTR_RCV is set, 1034 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1035 */ 1036 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1037 1038 /* 1039 * First two words are status and packet_length 1040 */ 1041 status = CSR_READ_2(sc, DATA_REG_W); 1042 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK; 1043 1044 /* 1045 * The packet length contains 3 extra words: status, length, and a 1046 * extra word with the control byte. 1047 */ 1048 packet_length -= 6; 1049 1050 /* 1051 * Account for receive errors and discard. 1052 */ 1053 if (status & RS_ERRORS) { 1054 ++sc->arpcom.ac_if.if_ierrors; 1055 goto out; 1056 } 1057 /* 1058 * A packet is received. 1059 */ 1060 1061 /* 1062 * Adjust for odd-length packet. 1063 */ 1064 if (status & RS_ODDFRAME) 1065 packet_length++; 1066 1067 /* 1068 * Allocate a header mbuf from the kernel. 1069 */ 1070 MGETHDR(m, M_DONTWAIT, MT_DATA); 1071 if (m == NULL) 1072 goto out; 1073 1074 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 1075 m->m_pkthdr.len = m->m_len = packet_length; 1076 1077 /* 1078 * Attach an mbuf cluster 1079 */ 1080 MCLGET(m, M_DONTWAIT); 1081 1082 /* 1083 * Insist on getting a cluster 1084 */ 1085 if ((m->m_flags & M_EXT) == 0) { 1086 m_freem(m); 1087 ++sc->arpcom.ac_if.if_ierrors; 1088 printf("sn: snread() kernel memory allocation problem\n"); 1089 goto out; 1090 } 1091 eh = mtod(m, struct ether_header *); 1092 1093 /* 1094 * Get packet, including link layer address, from interface. 1095 */ 1096 data = (uint8_t *) eh; 1097 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1); 1098 if (packet_length & 1) { 1099 data += packet_length & ~1; 1100 *data = CSR_READ_1(sc, DATA_REG_B); 1101 } 1102 ++sc->arpcom.ac_if.if_ipackets; 1103 1104 /* 1105 * Remove link layer addresses and whatnot. 1106 */ 1107 m->m_pkthdr.len = m->m_len = packet_length; 1108 1109 /* 1110 * Drop locks before calling if_input() since it may re-enter 1111 * snstart() in the netisr case. This would result in a 1112 * lock reversal. Better performance might be obtained by 1113 * chaining all packets received, dropping the lock, and then 1114 * calling if_input() on each one. 1115 */ 1116 SN_UNLOCK(sc); 1117 (*ifp->if_input)(ifp, m); 1118 SN_LOCK(sc); 1119 1120out: 1121 1122 /* 1123 * Error or good, tell the card to get rid of this packet Wait for 1124 * the MMU to be un-busy. 1125 */ 1126 SMC_SELECT_BANK(sc, 2); 1127 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1128 ; 1129 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE); 1130 1131 /* 1132 * Check whether another packet is ready 1133 */ 1134 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1135 if (packet_number & FIFO_REMPTY) { 1136 return; 1137 } 1138 goto read_another; 1139} 1140 1141 1142/* 1143 * Handle IOCTLS. This function is completely stolen from if_ep.c 1144 * As with its progenitor, it does not handle hardware address 1145 * changes. 1146 */ 1147static int 1148snioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1149{ 1150 struct sn_softc *sc = ifp->if_softc; 1151 int error = 0; 1152 1153 switch (cmd) { 1154 case SIOCSIFFLAGS: 1155 SN_LOCK(sc); 1156 if ((ifp->if_flags & IFF_UP) == 0 && ifp->if_flags & IFF_RUNNING) { 1157 ifp->if_flags &= ~IFF_RUNNING; 1158 snstop(sc); 1159 } else { 1160 /* reinitialize card on any parameter change */ 1161 sninit_locked(sc); 1162 } 1163 SN_UNLOCK(sc); 1164 break; 1165 1166#ifdef notdef 1167 case SIOCGHWADDR: 1168 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data, 1169 sizeof(sc->sc_addr)); 1170 break; 1171#endif 1172 1173 case SIOCADDMULTI: 1174 /* update multicast filter list. */ 1175 SN_LOCK(sc); 1176 sn_setmcast(sc); 1177 error = 0; 1178 SN_UNLOCK(sc); 1179 break; 1180 case SIOCDELMULTI: 1181 /* update multicast filter list. */ 1182 SN_LOCK(sc); 1183 sn_setmcast(sc); 1184 error = 0; 1185 SN_UNLOCK(sc); 1186 break; 1187 default: 1188 error = EINVAL; 1189 error = ether_ioctl(ifp, cmd, data); 1190 break; 1191 } 1192 return (error); 1193} 1194 1195static void 1196snwatchdog(struct ifnet *ifp) 1197{ 1198 sn_intr(ifp->if_softc); 1199} 1200 1201 1202/* 1. zero the interrupt mask 1203 * 2. clear the enable receive flag 1204 * 3. clear the enable xmit flags 1205 */ 1206static void 1207snstop(struct sn_softc *sc) 1208{ 1209 1210 struct ifnet *ifp = &sc->arpcom.ac_if; 1211 1212 /* 1213 * Clear interrupt mask; disable all interrupts. 1214 */ 1215 SMC_SELECT_BANK(sc, 2); 1216 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 1217 1218 /* 1219 * Disable transmitter and Receiver 1220 */ 1221 SMC_SELECT_BANK(sc, 0); 1222 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 1223 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 1224 1225 /* 1226 * Cancel watchdog. 1227 */ 1228 ifp->if_timer = 0; 1229} 1230 1231 1232int 1233sn_activate(device_t dev) 1234{ 1235 struct sn_softc *sc = device_get_softc(dev); 1236 1237 sc->port_rid = 0; 1238 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1239 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1240 if (!sc->port_res) { 1241 if (bootverbose) 1242 device_printf(dev, "Cannot allocate ioport\n"); 1243 return ENOMEM; 1244 } 1245 1246 sc->irq_rid = 0; 1247 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 1248 0, ~0, 1, RF_ACTIVE); 1249 if (!sc->irq_res) { 1250 if (bootverbose) 1251 device_printf(dev, "Cannot allocate irq\n"); 1252 sn_deactivate(dev); 1253 return ENOMEM; 1254 } 1255 sc->bst = rman_get_bustag(sc->port_res); 1256 sc->bsh = rman_get_bushandle(sc->port_res); 1257 return (0); 1258} 1259 1260void 1261sn_deactivate(device_t dev) 1262{ 1263 struct sn_softc *sc = device_get_softc(dev); 1264 1265 if (sc->intrhand) 1266 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1267 sc->intrhand = 0; 1268 if (sc->port_res) 1269 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1270 sc->port_res); 1271 sc->port_res = 0; 1272 if (sc->irq_res) 1273 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1274 sc->irq_res); 1275 sc->irq_res = 0; 1276 return; 1277} 1278 1279/* 1280 * Function: sn_probe( device_t dev, int pccard ) 1281 * 1282 * Purpose: 1283 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1284 * Tries to cause as little damage as possible if it's not a SMC chip. 1285 * Returns a 0 on success 1286 * 1287 * Algorithm: 1288 * (1) see if the high byte of BANK_SELECT is 0x33 1289 * (2) compare the ioaddr with the base register's address 1290 * (3) see if I recognize the chip ID in the appropriate register 1291 * 1292 * 1293 */ 1294int 1295sn_probe(device_t dev, int pccard) 1296{ 1297 struct sn_softc *sc = device_get_softc(dev); 1298 uint16_t bank; 1299 uint16_t revision_register; 1300 uint16_t base_address_register; 1301 int err; 1302 1303 if ((err = sn_activate(dev)) != 0) 1304 return err; 1305 1306 /* 1307 * First, see if the high byte is 0x33 1308 */ 1309 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1310 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1311#ifdef SN_DEBUG 1312 device_printf(dev, "test1 failed\n"); 1313#endif 1314 goto error; 1315 } 1316 /* 1317 * The above MIGHT indicate a device, but I need to write to further 1318 * test this. Go to bank 0, then test that the register still 1319 * reports the high byte is 0x33. 1320 */ 1321 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000); 1322 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1323 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1324#ifdef SN_DEBUG 1325 device_printf(dev, "test2 failed\n"); 1326#endif 1327 goto error; 1328 } 1329 /* 1330 * well, we've already written once, so hopefully another time won't 1331 * hurt. This time, I need to switch the bank register to bank 1, so 1332 * I can access the base address register. The contents of the 1333 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1334 * to match the I/O port address where the adapter is being probed. 1335 */ 1336 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001); 1337 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0; 1338 1339 /* 1340 * This test is nonsence on PC-card architecture, so if 1341 * pccard == 1, skip this test. (hosokawa) 1342 */ 1343 if (!pccard && rman_get_start(sc->port_res) != base_address_register) { 1344 1345 /* 1346 * Well, the base address register didn't match. Must not 1347 * have been a SMC chip after all. 1348 */ 1349#ifdef SN_DEBUG 1350 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1351 "base_address_register = 0x%x\n", 1352 rman_get_start(sc->port_res), base_address_register); 1353#endif 1354 goto error; 1355 } 1356 1357 /* 1358 * Check if the revision register is something that I recognize. 1359 * These might need to be added to later, as future revisions could 1360 * be added. 1361 */ 1362 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3); 1363 revision_register = CSR_READ_2(sc, REVISION_REG_W); 1364 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1365 1366 /* 1367 * I don't regonize this chip, so... 1368 */ 1369#ifdef SN_DEBUG 1370 device_printf(dev, "test4 failed\n"); 1371#endif 1372 goto error; 1373 } 1374 1375 /* 1376 * at this point I'll assume that the chip is an SMC9xxx. It might be 1377 * prudent to check a listing of MAC addresses against the hardware 1378 * address, or do some other tests. 1379 */ 1380 sn_deactivate(dev); 1381 return 0; 1382 error: 1383 sn_deactivate(dev); 1384 return ENXIO; 1385} 1386 1387#define MCFSZ 8 1388 1389static void 1390sn_setmcast(struct sn_softc *sc) 1391{ 1392 struct ifnet *ifp = (struct ifnet *)sc; 1393 int flags; 1394 uint8_t mcf[MCFSZ]; 1395 1396 SN_ASSERT_LOCKED(sc); 1397 1398 /* 1399 * Set the receiver filter. We want receive enabled and auto strip 1400 * of CRC from received packet. If we are promiscuous then set that 1401 * bit too. 1402 */ 1403 flags = RCR_ENABLE | RCR_STRIP_CRC; 1404 1405 if (ifp->if_flags & IFF_PROMISC) { 1406 flags |= RCR_PROMISC | RCR_ALMUL; 1407 } else if (ifp->if_flags & IFF_ALLMULTI) { 1408 flags |= RCR_ALMUL; 1409 } else { 1410 if (sn_getmcf(&sc->arpcom, mcf)) { 1411 /* set filter */ 1412 SMC_SELECT_BANK(sc, 3); 1413 CSR_WRITE_2(sc, MULTICAST1_REG_W, 1414 ((uint16_t)mcf[1] << 8) | mcf[0]); 1415 CSR_WRITE_2(sc, MULTICAST2_REG_W, 1416 ((uint16_t)mcf[3] << 8) | mcf[2]); 1417 CSR_WRITE_2(sc, MULTICAST3_REG_W, 1418 ((uint16_t)mcf[5] << 8) | mcf[4]); 1419 CSR_WRITE_2(sc, MULTICAST4_REG_W, 1420 ((uint16_t)mcf[7] << 8) | mcf[6]); 1421 } else { 1422 flags |= RCR_ALMUL; 1423 } 1424 } 1425 SMC_SELECT_BANK(sc, 0); 1426 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags); 1427} 1428 1429static int 1430sn_getmcf(struct arpcom *ac, uint8_t *mcf) 1431{ 1432 int i; 1433 uint32_t index, index2; 1434 uint8_t *af = mcf; 1435 struct ifmultiaddr *ifma; 1436 1437 bzero(mcf, MCFSZ); 1438 1439 TAILQ_FOREACH(ifma, &ac->ac_if.if_multiaddrs, ifma_link) { 1440 if (ifma->ifma_addr->sa_family != AF_LINK) 1441 return 0; 1442 index = sn_mchash( 1443 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) & 0x3f; 1444 index2 = 0; 1445 for (i = 0; i < 6; i++) { 1446 index2 <<= 1; 1447 index2 |= (index & 0x01); 1448 index >>= 1; 1449 } 1450 af[index2 >> 3] |= 1 << (index2 & 7); 1451 } 1452 return 1; /* use multicast filter */ 1453} 1454 1455static uint32_t 1456sn_mchash(const uint8_t *addr) 1457{ 1458 const uint32_t poly = 0xedb88320; 1459 uint32_t crc; 1460 int idx, bit; 1461 uint8_t data; 1462 1463 /* Compute CRC for the address value. */ 1464 crc = 0xFFFFFFFF; /* initial value */ 1465 1466 for (idx = 0; idx < ETHER_ADDR_LEN; idx++) { 1467 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1468 crc = (crc >> 1)^(((crc ^ data) & 0x01) ? poly : 0); 1469 } 1470 } 1471 return crc; 1472} 1473