if_smc.c revision 179719
1169689Skan/*- 2169689Skan * Copyright (c) 2008 Benno Rice. All rights reserved. 3169689Skan * 4169689Skan * Redistribution and use in source and binary forms, with or without 5169689Skan * modification, are permitted provided that the following conditions 6169689Skan * are met: 7169689Skan * 1. Redistributions of source code must retain the above copyright 8169689Skan * notice, this list of conditions and the following disclaimer. 9169689Skan * 2. Redistributions in binary form must reproduce the above copyright 10169689Skan * notice, this list of conditions and the following disclaimer in the 11169689Skan * documentation and/or other materials provided with the distribution. 12169689Skan * 13169689Skan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14169689Skan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15169689Skan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16169689Skan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17169689Skan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18169689Skan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19169689Skan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20169689Skan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21169689Skan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22169689Skan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23169689Skan */ 24169689Skan 25169689Skan#include <sys/cdefs.h> 26169689Skan__FBSDID("$FreeBSD: head/sys/dev/smc/if_smc.c 179719 2008-06-11 07:26:02Z benno $"); 27169689Skan 28169689Skan/* 29169689Skan * Driver for SMSC LAN91C111, may work for older variants. 30169689Skan */ 31169689Skan 32169689Skan#ifdef HAVE_KERNEL_OPTION_HEADERS 33169689Skan#include "opt_device_polling.h" 34169689Skan#endif 35169689Skan 36169689Skan#include <sys/param.h> 37169689Skan#include <sys/systm.h> 38169689Skan#include <sys/errno.h> 39169689Skan#include <sys/kernel.h> 40169689Skan#include <sys/sockio.h> 41169689Skan#include <sys/malloc.h> 42169689Skan#include <sys/mbuf.h> 43169689Skan#include <sys/queue.h> 44169689Skan#include <sys/socket.h> 45169689Skan#include <sys/syslog.h> 46169689Skan#include <sys/taskqueue.h> 47169689Skan 48169689Skan#include <sys/module.h> 49169689Skan#include <sys/bus.h> 50169689Skan 51169689Skan#include <machine/bus.h> 52169689Skan#include <machine/resource.h> 53169689Skan#include <sys/rman.h> 54169689Skan 55169689Skan#include <net/ethernet.h> 56169689Skan#include <net/if.h> 57169689Skan#include <net/if_arp.h> 58169689Skan#include <net/if_dl.h> 59169689Skan#include <net/if_types.h> 60169689Skan#include <net/if_mib.h> 61169689Skan#include <net/if_media.h> 62169689Skan 63169689Skan#ifdef INET 64169689Skan#include <netinet/in.h> 65169689Skan#include <netinet/in_systm.h> 66169689Skan#include <netinet/in_var.h> 67169689Skan#include <netinet/ip.h> 68169689Skan#endif 69169689Skan 70169689Skan#include <net/bpf.h> 71169689Skan#include <net/bpfdesc.h> 72169689Skan 73169689Skan#include <dev/smc/if_smcreg.h> 74169689Skan#include <dev/smc/if_smcvar.h> 75169689Skan 76169689Skan#include <dev/mii/mii.h> 77169689Skan#include <dev/mii/miivar.h> 78169689Skan 79169689Skan#define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 80169689Skan#define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 81169689Skan#define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 82169689Skan 83169689Skan#define SMC_INTR_PRIORITY 0 84169689Skan#define SMC_RX_PRIORITY 5 85169689Skan#define SMC_TX_PRIORITY 10 86169689Skan 87169689Skandevclass_t smc_devclass; 88169689Skan 89169689Skanstatic const char *smc_chip_ids[16] = { 90169689Skan NULL, NULL, NULL, 91169689Skan /* 3 */ "SMSC LAN91C90 or LAN91C92", 92169689Skan /* 4 */ "SMSC LAN91C94", 93169689Skan /* 5 */ "SMSC LAN91C95", 94169689Skan /* 6 */ "SMSC LAN91C96", 95169689Skan /* 7 */ "SMSC LAN91C100", 96169689Skan /* 8 */ "SMSC LAN91C100FD", 97169689Skan /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 98169689Skan NULL, NULL, NULL, 99169689Skan NULL, NULL, NULL 100169689Skan}; 101169689Skan 102169689Skanstatic void smc_init(void *); 103169689Skanstatic void smc_start(struct ifnet *); 104169689Skanstatic int smc_ioctl(struct ifnet *, u_long, caddr_t); 105169689Skan 106169689Skanstatic void smc_init_locked(struct smc_softc *); 107169689Skanstatic void smc_start_locked(struct ifnet *); 108169689Skanstatic void smc_reset(struct smc_softc *); 109169689Skanstatic int smc_mii_ifmedia_upd(struct ifnet *); 110169689Skanstatic void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 111169689Skanstatic void smc_mii_tick(void *); 112169689Skanstatic void smc_mii_mediachg(struct smc_softc *); 113169689Skanstatic int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 114169689Skan 115169689Skanstatic void smc_task_intr(void *, int); 116169689Skanstatic void smc_task_rx(void *, int); 117169689Skanstatic void smc_task_tx(void *, int); 118169689Skan 119169689Skanstatic driver_filter_t smc_intr; 120169689Skanstatic timeout_t smc_watchdog; 121169689Skan#ifdef DEVICE_POLLING 122169689Skanstatic poll_handler_t smc_poll; 123169689Skan#endif 124169689Skan 125169689Skanstatic __inline void 126169689Skansmc_select_bank(struct smc_softc *sc, uint16_t bank) 127169689Skan{ 128169689Skan 129169689Skan bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 130169689Skan} 131169689Skan 132169689Skan/* Never call this when not in bank 2. */ 133169689Skanstatic __inline void 134169689Skansmc_mmu_wait(struct smc_softc *sc) 135169689Skan{ 136169689Skan 137169689Skan KASSERT((bus_read_2(sc->smc_reg, BSR) & 138169689Skan BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 139169689Skan device_get_nameunit(sc->smc_dev))); 140169689Skan while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 141169689Skan ; 142169689Skan} 143169689Skan 144169689Skanstatic __inline uint8_t 145169689Skansmc_read_1(struct smc_softc *sc, bus_addr_t offset) 146169689Skan{ 147169689Skan 148169689Skan return (bus_read_1(sc->smc_reg, offset)); 149169689Skan} 150169689Skan 151169689Skanstatic __inline void 152169689Skansmc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val) 153169689Skan{ 154169689Skan 155169689Skan bus_write_1(sc->smc_reg, offset, val); 156169689Skan} 157169689Skan 158169689Skanstatic __inline uint16_t 159169689Skansmc_read_2(struct smc_softc *sc, bus_addr_t offset) 160169689Skan{ 161169689Skan 162169689Skan return (bus_read_2(sc->smc_reg, offset)); 163169689Skan} 164169689Skan 165169689Skanstatic __inline void 166169689Skansmc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val) 167169689Skan{ 168169689Skan 169169689Skan bus_write_2(sc->smc_reg, offset, val); 170169689Skan} 171169689Skan 172169689Skanstatic __inline void 173169689Skansmc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, 174169689Skan bus_size_t count) 175169689Skan{ 176169689Skan 177169689Skan bus_read_multi_2(sc->smc_reg, offset, datap, count); 178169689Skan} 179169689Skan 180169689Skanstatic __inline void 181169689Skansmc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, 182169689Skan bus_size_t count) 183169689Skan{ 184169689Skan 185169689Skan bus_write_multi_2(sc->smc_reg, offset, datap, count); 186169689Skan} 187169689Skan 188169689Skanint 189169689Skansmc_probe(device_t dev) 190169689Skan{ 191169689Skan int rid, type, error; 192169689Skan uint16_t val; 193169689Skan struct smc_softc *sc; 194169689Skan struct resource *reg; 195169689Skan 196169689Skan sc = device_get_softc(dev); 197169689Skan rid = 0; 198169689Skan type = SYS_RES_IOPORT; 199169689Skan error = 0; 200169689Skan 201169689Skan if (sc->smc_usemem) 202169689Skan type = SYS_RES_MEMORY; 203169689Skan 204169689Skan reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); 205169689Skan if (reg == NULL) { 206169689Skan if (bootverbose) 207169689Skan device_printf(dev, 208169689Skan "could not allocate I/O resource for probe\n"); 209169689Skan return (ENXIO); 210169689Skan } 211169689Skan 212169689Skan /* Check for the identification value in the BSR. */ 213169689Skan val = bus_read_2(reg, BSR); 214169689Skan if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 215169689Skan if (bootverbose) 216169689Skan device_printf(dev, "identification value not in BSR\n"); 217169689Skan error = ENXIO; 218169689Skan goto done; 219169689Skan } 220169689Skan 221169689Skan /* 222169689Skan * Try switching banks and make sure we still get the identification 223169689Skan * value. 224169689Skan */ 225169689Skan bus_write_2(reg, BSR, 0); 226169689Skan val = bus_read_2(reg, BSR); 227169689Skan if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 228169689Skan if (bootverbose) 229169689Skan device_printf(dev, 230169689Skan "identification value not in BSR after write\n"); 231169689Skan error = ENXIO; 232169689Skan goto done; 233169689Skan } 234169689Skan 235169689Skan#if 0 236169689Skan /* Check the BAR. */ 237169689Skan bus_write_2(reg, BSR, 1); 238169689Skan val = bus_read_2(reg, BAR); 239169689Skan val = BAR_ADDRESS(val); 240169689Skan if (rman_get_start(reg) != val) { 241169689Skan if (bootverbose) 242169689Skan device_printf(dev, "BAR address %x does not match " 243169689Skan "I/O resource address %lx\n", val, 244169689Skan rman_get_start(reg)); 245169689Skan error = ENXIO; 246169689Skan goto done; 247169689Skan } 248169689Skan#endif 249169689Skan 250169689Skan /* Compare REV against known chip revisions. */ 251169689Skan bus_write_2(reg, BSR, 3); 252169689Skan val = bus_read_2(reg, REV); 253169689Skan val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 254169689Skan if (smc_chip_ids[val] == NULL) { 255169689Skan if (bootverbose) 256169689Skan device_printf(dev, "Unknown chip revision: %d\n", val); 257169689Skan error = ENXIO; 258169689Skan goto done; 259169689Skan } 260169689Skan 261169689Skan device_set_desc(dev, smc_chip_ids[val]); 262169689Skan 263169689Skandone: 264169689Skan bus_release_resource(dev, type, rid, reg); 265169689Skan return (error); 266169689Skan} 267169689Skan 268169689Skanint 269169689Skansmc_attach(device_t dev) 270169689Skan{ 271169689Skan int type, error; 272169689Skan uint16_t val; 273169689Skan u_char eaddr[ETHER_ADDR_LEN]; 274169689Skan struct smc_softc *sc; 275169689Skan struct ifnet *ifp; 276169689Skan 277169689Skan sc = device_get_softc(dev); 278169689Skan error = 0; 279169689Skan 280169689Skan sc->smc_dev = dev; 281169689Skan 282169689Skan /* Set up watchdog callout. */ 283169689Skan callout_init(&sc->smc_watchdog, 1); 284169689Skan 285169689Skan ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 286169689Skan if (ifp == NULL) { 287169689Skan error = ENOSPC; 288169689Skan goto done; 289169689Skan } 290169689Skan 291169689Skan mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 292169689Skan 293169689Skan type = SYS_RES_IOPORT; 294169689Skan if (sc->smc_usemem) 295169689Skan type = SYS_RES_MEMORY; 296169689Skan 297169689Skan sc->smc_reg_rid = 0; 298169689Skan sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, 299169689Skan 16, RF_ACTIVE); 300169689Skan if (sc->smc_reg == NULL) { 301169689Skan error = ENXIO; 302169689Skan goto done; 303169689Skan } 304169689Skan 305169689Skan sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, 306169689Skan ~0, 1, RF_ACTIVE | RF_SHAREABLE); 307169689Skan if (sc->smc_irq == NULL) { 308169689Skan error = ENXIO; 309169689Skan goto done; 310169689Skan } 311169689Skan 312169689Skan SMC_LOCK(sc); 313169689Skan smc_reset(sc); 314169689Skan SMC_UNLOCK(sc); 315169689Skan 316169689Skan smc_select_bank(sc, 3); 317169689Skan val = smc_read_2(sc, REV); 318169689Skan sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 319169689Skan sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 320169689Skan if (bootverbose) 321169689Skan device_printf(dev, "revision %x\n", sc->smc_rev); 322169689Skan 323169689Skan callout_init(&sc->smc_mii_tick_ch, 1); 324169689Skan if (sc->smc_chip >= REV_CHIP_91110FD) { 325169689Skan mii_phy_probe(dev, &sc->smc_miibus, smc_mii_ifmedia_upd, 326169689Skan smc_mii_ifmedia_sts); 327169689Skan if (sc->smc_miibus != NULL) { 328169689Skan sc->smc_mii_tick = smc_mii_tick; 329169689Skan sc->smc_mii_mediachg = smc_mii_mediachg; 330169689Skan sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 331169689Skan } 332169689Skan } 333169689Skan 334169689Skan smc_select_bank(sc, 1); 335169689Skan eaddr[0] = smc_read_1(sc, IAR0); 336169689Skan eaddr[1] = smc_read_1(sc, IAR1); 337169689Skan eaddr[2] = smc_read_1(sc, IAR2); 338169689Skan eaddr[3] = smc_read_1(sc, IAR3); 339169689Skan eaddr[4] = smc_read_1(sc, IAR4); 340169689Skan eaddr[5] = smc_read_1(sc, IAR5); 341169689Skan 342169689Skan if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 343169689Skan ifp->if_softc = sc; 344169689Skan ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 345169689Skan ifp->if_init = smc_init; 346169689Skan ifp->if_ioctl = smc_ioctl; 347169689Skan ifp->if_start = smc_start; 348169689Skan IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 349169689Skan IFQ_SET_READY(&ifp->if_snd); 350169689Skan 351169689Skan ifp->if_capabilities = ifp->if_capenable = 0; 352169689Skan 353169689Skan#ifdef DEVICE_POLLING 354169689Skan ifp->if_capabilities |= IFCAP_POLLING; 355169689Skan#endif 356169689Skan 357169689Skan ether_ifattach(ifp, eaddr); 358169689Skan 359169689Skan /* Set up taskqueue */ 360169689Skan TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 361169689Skan TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 362169689Skan TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 363169689Skan sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 364169689Skan taskqueue_thread_enqueue, &sc->smc_tq); 365169689Skan taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 366169689Skan device_get_nameunit(sc->smc_dev)); 367169689Skan 368169689Skan /* Mask all interrupts. */ 369169689Skan sc->smc_mask = 0; 370169689Skan smc_write_1(sc, MSK, 0); 371169689Skan 372169689Skan /* Wire up interrupt */ 373169689Skan error = bus_setup_intr(dev, sc->smc_irq, 374169689Skan INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 375169689Skan if (error != 0) 376169689Skan goto done; 377169689Skan 378169689Skandone: 379169689Skan if (error != 0) 380169689Skan smc_detach(dev); 381169689Skan return (error); 382169689Skan} 383169689Skan 384169689Skanint 385169689Skansmc_detach(device_t dev) 386169689Skan{ 387169689Skan int type; 388169689Skan struct smc_softc *sc; 389169689Skan 390169689Skan sc = device_get_softc(dev); 391169689Skan 392169689Skan callout_stop(&sc->smc_watchdog); 393169689Skan 394169689Skan#ifdef DEVICE_POLLING 395169689Skan if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 396169689Skan ether_poll_deregister(sc->smc_ifp); 397169689Skan#endif 398169689Skan 399169689Skan if (sc->smc_ih != NULL) 400169689Skan bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 401169689Skan 402169689Skan if (sc->smc_ifp != NULL) { 403169689Skan ether_ifdetach(sc->smc_ifp); 404169689Skan if_free(sc->smc_ifp); 405169689Skan } 406169689Skan 407169689Skan if (sc->smc_miibus != NULL) { 408169689Skan device_delete_child(sc->smc_dev, sc->smc_miibus); 409169689Skan bus_generic_detach(sc->smc_dev); 410169689Skan } 411169689Skan 412169689Skan if (sc->smc_reg != NULL) { 413169689Skan type = SYS_RES_IOPORT; 414169689Skan if (sc->smc_usemem) 415169689Skan type = SYS_RES_MEMORY; 416169689Skan 417169689Skan bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 418169689Skan sc->smc_reg); 419169689Skan } 420169689Skan 421169689Skan if (sc->smc_irq != NULL) 422169689Skan bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 423169689Skan sc->smc_irq); 424169689Skan 425169689Skan if (sc->smc_tq != NULL) 426169689Skan taskqueue_free(sc->smc_tq); 427169689Skan 428169689Skan if (mtx_initialized(&sc->smc_mtx)) 429169689Skan mtx_destroy(&sc->smc_mtx); 430169689Skan 431169689Skan return (0); 432169689Skan} 433169689Skan 434169689Skanstatic void 435169689Skansmc_start(struct ifnet *ifp) 436169689Skan{ 437169689Skan struct smc_softc *sc; 438169689Skan 439169689Skan sc = ifp->if_softc; 440169689Skan SMC_LOCK(sc); 441169689Skan smc_start_locked(ifp); 442169689Skan SMC_UNLOCK(sc); 443169689Skan} 444169689Skan 445169689Skanstatic void 446169689Skansmc_start_locked(struct ifnet *ifp) 447169689Skan{ 448169689Skan struct smc_softc *sc; 449169689Skan struct mbuf *m; 450169689Skan u_int len, npages, spin_count; 451169689Skan 452169689Skan sc = ifp->if_softc; 453169689Skan SMC_ASSERT_LOCKED(sc); 454169689Skan 455169689Skan if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 456169689Skan return; 457169689Skan if (IFQ_IS_EMPTY(&ifp->if_snd)) 458169689Skan return; 459169689Skan 460169689Skan /* 461169689Skan * Grab the next packet. If it's too big, drop it. 462169689Skan */ 463169689Skan IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 464169689Skan len = m_length(m, NULL); 465169689Skan len += (len & 1); 466169689Skan if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 467169689Skan if_printf(ifp, "large packet discarded\n"); 468169689Skan ++ifp->if_oerrors; 469169689Skan m_freem(m); 470169689Skan return; /* XXX readcheck? */ 471169689Skan } 472 473 /* 474 * Flag that we're busy. 475 */ 476 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 477 sc->smc_pending = m; 478 479 /* 480 * Work out how many 256 byte "pages" we need. We have to include the 481 * control data for the packet in this calculation. 482 */ 483 npages = (len * PKT_CTRL_DATA_LEN) >> 8; 484 if (npages == 0) 485 npages = 1; 486 487 /* 488 * Request memory. 489 */ 490 smc_select_bank(sc, 2); 491 smc_mmu_wait(sc); 492 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 493 494 /* 495 * Spin briefly to see if the allocation succeeds. 496 */ 497 spin_count = TX_ALLOC_WAIT_TIME; 498 do { 499 if (smc_read_1(sc, IST) & ALLOC_INT) { 500 smc_write_1(sc, ACK, ALLOC_INT); 501 break; 502 } 503 } while (--spin_count); 504 505 /* 506 * If the allocation is taking too long, unmask the alloc interrupt 507 * and wait. 508 */ 509 if (spin_count == 0) { 510 sc->smc_mask |= ALLOC_INT; 511 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 512 smc_write_1(sc, MSK, sc->smc_mask); 513 return; 514 } 515 516 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 517} 518 519static void 520smc_task_tx(void *context, int pending) 521{ 522 struct ifnet *ifp; 523 struct smc_softc *sc; 524 struct mbuf *m, *m0; 525 u_int packet, len; 526 uint8_t *data; 527 528 (void)pending; 529 ifp = (struct ifnet *)context; 530 sc = ifp->if_softc; 531 532 SMC_LOCK(sc); 533 534 if (sc->smc_pending == NULL) { 535 SMC_UNLOCK(sc); 536 goto next_packet; 537 } 538 539 m = m0 = sc->smc_pending; 540 sc->smc_pending = NULL; 541 smc_select_bank(sc, 2); 542 543 /* 544 * Check the allocation result. 545 */ 546 packet = smc_read_1(sc, ARR); 547 548 /* 549 * If the allocation failed, requeue the packet and retry. 550 */ 551 if (packet & ARR_FAILED) { 552 IFQ_DRV_PREPEND(&ifp->if_snd, m); 553 ++ifp->if_oerrors; 554 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 555 smc_start_locked(ifp); 556 SMC_UNLOCK(sc); 557 return; 558 } 559 560 /* 561 * Tell the device to write to our packet number. 562 */ 563 smc_write_1(sc, PNR, packet); 564 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 565 566 /* 567 * Tell the device how long the packet is (including control data). 568 */ 569 len = m_length(m, 0); 570 len += PKT_CTRL_DATA_LEN; 571 smc_write_2(sc, DATA0, 0); 572 smc_write_2(sc, DATA0, len); 573 574 /* 575 * Push the data out to the device. 576 */ 577 data = NULL; 578 for (; m != NULL; m = m->m_next) { 579 data = mtod(m, uint8_t *); 580 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 581 } 582 583 /* 584 * Push out the control byte and and the odd byte if needed. 585 */ 586 if ((len & 1) != 0 && data != NULL) 587 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]); 588 else 589 smc_write_2(sc, DATA0, 0); 590 591 /* 592 * Unmask the TX empty interrupt. 593 */ 594 sc->smc_mask |= TX_EMPTY_INT; 595 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 596 smc_write_1(sc, MSK, sc->smc_mask); 597 598 /* 599 * Enqueue the packet. 600 */ 601 smc_mmu_wait(sc); 602 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 603 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 604 605 /* 606 * Finish up. 607 */ 608 ifp->if_opackets++; 609 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 610 SMC_UNLOCK(sc); 611 BPF_MTAP(ifp, m0); 612 m_freem(m0); 613 614next_packet: 615 /* 616 * See if there's anything else to do. 617 */ 618 smc_start(ifp); 619} 620 621static void 622smc_task_rx(void *context, int pending) 623{ 624 u_int packet, status, len; 625 uint8_t *data; 626 struct ifnet *ifp; 627 struct smc_softc *sc; 628 struct mbuf *m, *mhead, *mtail; 629 630 (void)pending; 631 ifp = (struct ifnet *)context; 632 sc = ifp->if_softc; 633 mhead = mtail = NULL; 634 635 SMC_LOCK(sc); 636 637 packet = smc_read_1(sc, FIFO_RX); 638 while ((packet & FIFO_EMPTY) == 0) { 639 /* 640 * Grab an mbuf and attach a cluster. 641 */ 642 MGETHDR(m, M_DONTWAIT, MT_DATA); 643 if (m == NULL) { 644 break; 645 } 646 MCLGET(m, M_DONTWAIT); 647 if ((m->m_flags & M_EXT) == 0) { 648 m_freem(m); 649 break; 650 } 651 652 /* 653 * Point to the start of the packet. 654 */ 655 smc_select_bank(sc, 2); 656 smc_write_1(sc, PNR, packet); 657 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 658 659 /* 660 * Grab status and packet length. 661 */ 662 status = smc_read_2(sc, DATA0); 663 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 664 len -= 6; 665 if (status & RX_ODDFRM) 666 len += 1; 667 668 /* 669 * Check for errors. 670 */ 671 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 672 smc_mmu_wait(sc); 673 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 674 ifp->if_ierrors++; 675 m_freem(m); 676 break; 677 } 678 679 /* 680 * Set the mbuf up the way we want it. 681 */ 682 m->m_pkthdr.rcvif = ifp; 683 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 684 m_adj(m, ETHER_ALIGN); 685 686 /* 687 * Pull the packet out of the device. Make sure we're in the 688 * right bank first as things may have changed while we were 689 * allocating our mbuf. 690 */ 691 smc_select_bank(sc, 2); 692 smc_write_1(sc, PNR, packet); 693 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 694 data = mtod(m, uint8_t *); 695 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 696 if (len & 1) { 697 data += len & ~1; 698 *data = smc_read_1(sc, DATA0); 699 } 700 701 /* 702 * Tell the device we're done. 703 */ 704 smc_mmu_wait(sc); 705 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 706 if (m == NULL) { 707 break; 708 } 709 710 if (mhead == NULL) { 711 mhead = mtail = m; 712 m->m_next = NULL; 713 } else { 714 mtail->m_next = m; 715 mtail = m; 716 } 717 packet = smc_read_1(sc, FIFO_RX); 718 } 719 720 sc->smc_mask |= RCV_INT; 721 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 722 smc_write_1(sc, MSK, sc->smc_mask); 723 724 SMC_UNLOCK(sc); 725 726 while (mhead != NULL) { 727 m = mhead; 728 mhead = mhead->m_next; 729 m->m_next = NULL; 730 ifp->if_ipackets++; 731 (*ifp->if_input)(ifp, m); 732 } 733} 734 735#ifdef DEVICE_POLLING 736static void 737smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 738{ 739 struct smc_softc *sc; 740 741 sc = ifp->if_softc; 742 743 SMC_LOCK(sc); 744 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 745 SMC_UNLOCK(sc); 746 return; 747 } 748 SMC_UNLOCK(sc); 749 750 if (cmd == POLL_AND_CHECK_STATUS) 751 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 752} 753#endif 754 755static int 756smc_intr(void *context) 757{ 758 struct smc_softc *sc; 759 760 sc = (struct smc_softc *)context; 761 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 762 return (FILTER_HANDLED); 763} 764 765static void 766smc_task_intr(void *context, int pending) 767{ 768 struct smc_softc *sc; 769 struct ifnet *ifp; 770 u_int status, packet, counter, tcr; 771 772 (void)pending; 773 ifp = (struct ifnet *)context; 774 sc = ifp->if_softc; 775 776 SMC_LOCK(sc); 777 smc_select_bank(sc, 2); 778 779 /* 780 * Get the current mask, and then block all interrupts while we're 781 * working. 782 */ 783 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 784 smc_write_1(sc, MSK, 0); 785 786 /* 787 * Find out what interrupts are flagged. 788 */ 789 status = smc_read_1(sc, IST) & sc->smc_mask; 790 791 /* 792 * Transmit error 793 */ 794 if (status & TX_INT) { 795 /* 796 * Kill off the packet if there is one and re-enable transmit. 797 */ 798 packet = smc_read_1(sc, FIFO_TX); 799 if ((packet & FIFO_EMPTY) == 0) { 800 smc_write_1(sc, PNR, packet); 801 smc_write_2(sc, PTR, 0 | PTR_READ | 802 PTR_AUTO_INCR); 803 tcr = smc_read_2(sc, DATA0); 804 if ((tcr & EPHSR_TX_SUC) == 0) 805 device_printf(sc->smc_dev, 806 "bad packet\n"); 807 smc_mmu_wait(sc); 808 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 809 810 smc_select_bank(sc, 0); 811 tcr = smc_read_2(sc, TCR); 812 tcr |= TCR_TXENA | TCR_PAD_EN; 813 smc_write_2(sc, TCR, tcr); 814 smc_select_bank(sc, 2); 815 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 816 } 817 818 /* 819 * Ack the interrupt. 820 */ 821 smc_write_1(sc, ACK, TX_INT); 822 } 823 824 /* 825 * Receive 826 */ 827 if (status & RCV_INT) { 828 smc_write_1(sc, ACK, RCV_INT); 829 sc->smc_mask &= ~RCV_INT; 830 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); 831 } 832 833 /* 834 * Allocation 835 */ 836 if (status & ALLOC_INT) { 837 smc_write_1(sc, ACK, ALLOC_INT); 838 sc->smc_mask &= ~ALLOC_INT; 839 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 840 } 841 842 /* 843 * Receive overrun 844 */ 845 if (status & RX_OVRN_INT) { 846 smc_write_1(sc, ACK, RX_OVRN_INT); 847 ifp->if_ierrors++; 848 } 849 850 /* 851 * Transmit empty 852 */ 853 if (status & TX_EMPTY_INT) { 854 smc_write_1(sc, ACK, TX_EMPTY_INT); 855 sc->smc_mask &= ~TX_EMPTY_INT; 856 callout_stop(&sc->smc_watchdog); 857 858 /* 859 * Update collision stats. 860 */ 861 smc_select_bank(sc, 0); 862 counter = smc_read_2(sc, ECR); 863 smc_select_bank(sc, 2); 864 ifp->if_collisions += 865 (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT; 866 ifp->if_collisions += 867 (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT; 868 869 /* 870 * See if there are any packets to transmit. 871 */ 872 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 873 } 874 875 /* 876 * Update the interrupt mask. 877 */ 878 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 879 smc_write_1(sc, MSK, sc->smc_mask); 880 881 SMC_UNLOCK(sc); 882} 883 884static u_int 885smc_mii_readbits(struct smc_softc *sc, int nbits) 886{ 887 u_int mgmt, mask, val; 888 889 SMC_ASSERT_LOCKED(sc); 890 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 891 ("%s: smc_mii_readbits called with bank %d (!= 3)", 892 device_get_nameunit(sc->smc_dev), 893 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 894 895 /* 896 * Set up the MGMT (aka MII) register. 897 */ 898 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); 899 smc_write_2(sc, MGMT, mgmt); 900 901 /* 902 * Read the bits in. 903 */ 904 for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) { 905 if (smc_read_2(sc, MGMT) & MGMT_MDI) 906 val |= mask; 907 908 smc_write_2(sc, MGMT, mgmt); 909 DELAY(1); 910 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); 911 DELAY(1); 912 } 913 914 return (val); 915} 916 917static void 918smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits) 919{ 920 u_int mgmt, mask; 921 922 SMC_ASSERT_LOCKED(sc); 923 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 924 ("%s: smc_mii_writebits called with bank %d (!= 3)", 925 device_get_nameunit(sc->smc_dev), 926 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 927 928 /* 929 * Set up the MGMT (aka MII) register). 930 */ 931 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); 932 mgmt |= MGMT_MDOE; 933 934 /* 935 * Push the bits out. 936 */ 937 for (mask = 1 << (nbits - 1); mask; mask >>= 1) { 938 if (val & mask) 939 mgmt |= MGMT_MDO; 940 else 941 mgmt &= ~MGMT_MDO; 942 943 smc_write_2(sc, MGMT, mgmt); 944 DELAY(1); 945 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); 946 DELAY(1); 947 } 948} 949 950int 951smc_miibus_readreg(device_t dev, int phy, int reg) 952{ 953 struct smc_softc *sc; 954 int val; 955 956 sc = device_get_softc(dev); 957 958 SMC_LOCK(sc); 959 960 smc_select_bank(sc, 3); 961 962 /* 963 * Send out the idle pattern. 964 */ 965 smc_mii_writebits(sc, 0xffffffff, 32); 966 967 /* 968 * Start code + read opcode + phy address + phy register 969 */ 970 smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14); 971 972 /* 973 * Turnaround + data 974 */ 975 val = smc_mii_readbits(sc, 18); 976 977 /* 978 * Reset the MDIO interface. 979 */ 980 smc_write_2(sc, MGMT, 981 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); 982 983 SMC_UNLOCK(sc); 984 return (val); 985} 986 987void 988smc_miibus_writereg(device_t dev, int phy, int reg, int data) 989{ 990 struct smc_softc *sc; 991 992 sc = device_get_softc(dev); 993 994 SMC_LOCK(sc); 995 996 smc_select_bank(sc, 3); 997 998 /* 999 * Send idle pattern. 1000 */ 1001 smc_mii_writebits(sc, 0xffffffff, 32); 1002 1003 /* 1004 * Start code + write opcode + phy address + phy register + turnaround 1005 * + data. 1006 */ 1007 smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data, 1008 32); 1009 1010 /* 1011 * Reset MDIO interface. 1012 */ 1013 smc_write_2(sc, MGMT, 1014 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); 1015 1016 SMC_UNLOCK(sc); 1017} 1018 1019void 1020smc_miibus_statchg(device_t dev) 1021{ 1022 struct smc_softc *sc; 1023 struct mii_data *mii; 1024 uint16_t tcr; 1025 1026 sc = device_get_softc(dev); 1027 mii = device_get_softc(sc->smc_miibus); 1028 1029 SMC_LOCK(sc); 1030 1031 smc_select_bank(sc, 0); 1032 tcr = smc_read_2(sc, TCR); 1033 1034 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1035 tcr |= TCR_SWFDUP; 1036 else 1037 tcr &= ~TCR_SWFDUP; 1038 1039 smc_write_2(sc, TCR, tcr); 1040 1041 SMC_UNLOCK(sc); 1042} 1043 1044static int 1045smc_mii_ifmedia_upd(struct ifnet *ifp) 1046{ 1047 struct smc_softc *sc; 1048 struct mii_data *mii; 1049 1050 sc = ifp->if_softc; 1051 if (sc->smc_miibus == NULL) 1052 return (ENXIO); 1053 1054 mii = device_get_softc(sc->smc_miibus); 1055 return (mii_mediachg(mii)); 1056} 1057 1058static void 1059smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1060{ 1061 struct smc_softc *sc; 1062 struct mii_data *mii; 1063 1064 sc = ifp->if_softc; 1065 if (sc->smc_miibus == NULL) 1066 return; 1067 1068 mii = device_get_softc(sc->smc_miibus); 1069 mii_pollstat(mii); 1070 ifmr->ifm_active = mii->mii_media_active; 1071 ifmr->ifm_status = mii->mii_media_status; 1072} 1073 1074static void 1075smc_mii_tick(void *context) 1076{ 1077 struct smc_softc *sc; 1078 1079 sc = (struct smc_softc *)context; 1080 1081 if (sc->smc_miibus == NULL) 1082 return; 1083 1084 mii_tick(device_get_softc(sc->smc_miibus)); 1085 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1086} 1087 1088static void 1089smc_mii_mediachg(struct smc_softc *sc) 1090{ 1091 1092 if (sc->smc_miibus == NULL) 1093 return; 1094 mii_mediachg(device_get_softc(sc->smc_miibus)); 1095} 1096 1097static int 1098smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1099{ 1100 struct mii_data *mii; 1101 1102 if (sc->smc_miibus == NULL) 1103 return (EINVAL); 1104 1105 mii = device_get_softc(sc->smc_miibus); 1106 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1107} 1108 1109static void 1110smc_reset(struct smc_softc *sc) 1111{ 1112 u_int ctr; 1113 1114 SMC_ASSERT_LOCKED(sc); 1115 1116 smc_select_bank(sc, 2); 1117 1118 /* 1119 * Mask all interrupts. 1120 */ 1121 smc_write_1(sc, MSK, 0); 1122 1123 /* 1124 * Tell the device to reset. 1125 */ 1126 smc_select_bank(sc, 0); 1127 smc_write_2(sc, RCR, RCR_SOFT_RST); 1128 1129 /* 1130 * Set up the configuration register. 1131 */ 1132 smc_select_bank(sc, 1); 1133 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1134 DELAY(1); 1135 1136 /* 1137 * Turn off transmit and receive. 1138 */ 1139 smc_select_bank(sc, 0); 1140 smc_write_2(sc, TCR, 0); 1141 smc_write_2(sc, RCR, 0); 1142 1143 /* 1144 * Set up the control register. 1145 */ 1146 smc_select_bank(sc, 1); 1147 ctr = smc_read_2(sc, CTR); 1148 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1149 smc_write_2(sc, CTR, ctr); 1150 1151 /* 1152 * Reset the MMU. 1153 */ 1154 smc_select_bank(sc, 2); 1155 smc_mmu_wait(sc); 1156 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1157} 1158 1159static void 1160smc_enable(struct smc_softc *sc) 1161{ 1162 struct ifnet *ifp; 1163 1164 SMC_ASSERT_LOCKED(sc); 1165 ifp = sc->smc_ifp; 1166 1167 /* 1168 * Set up the receive/PHY control register. 1169 */ 1170 smc_select_bank(sc, 0); 1171 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1172 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1173 1174 /* 1175 * Set up the transmit and receive control registers. 1176 */ 1177 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1178 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1179 1180 /* 1181 * Set up the interrupt mask. 1182 */ 1183 smc_select_bank(sc, 2); 1184 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1185 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1186 smc_write_1(sc, MSK, sc->smc_mask); 1187} 1188 1189static void 1190smc_stop(struct smc_softc *sc) 1191{ 1192 1193 SMC_ASSERT_LOCKED(sc); 1194 1195 /* 1196 * Turn off watchdog. 1197 */ 1198 callout_stop(&sc->smc_watchdog); 1199 1200 /* 1201 * Mask all interrupts. 1202 */ 1203 smc_select_bank(sc, 2); 1204 sc->smc_mask = 0; 1205 smc_write_1(sc, MSK, 0); 1206#ifdef DEVICE_POLLING 1207 ether_poll_deregister(sc->smc_ifp); 1208 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1209#endif 1210 1211 /* 1212 * Disable transmit and receive. 1213 */ 1214 smc_select_bank(sc, 0); 1215 smc_write_2(sc, TCR, 0); 1216 smc_write_2(sc, RCR, 0); 1217 1218 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1219} 1220 1221static void 1222smc_watchdog(void *arg) 1223{ 1224 struct smc_softc *sc; 1225 1226 sc = (struct smc_softc *)arg; 1227 device_printf(sc->smc_dev, "watchdog timeout\n"); 1228 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 1229} 1230 1231static void 1232smc_init(void *context) 1233{ 1234 struct smc_softc *sc; 1235 1236 sc = (struct smc_softc *)context; 1237 SMC_LOCK(sc); 1238 smc_init_locked(sc); 1239 SMC_UNLOCK(sc); 1240} 1241 1242static void 1243smc_init_locked(struct smc_softc *sc) 1244{ 1245 struct ifnet *ifp; 1246 1247 ifp = sc->smc_ifp; 1248 1249 SMC_ASSERT_LOCKED(sc); 1250 1251 smc_reset(sc); 1252 smc_enable(sc); 1253 1254 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1255 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1256 1257 smc_start_locked(ifp); 1258 1259 if (sc->smc_mii_tick != NULL) 1260 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1261 1262#ifdef DEVICE_POLLING 1263 SMC_UNLOCK(sc); 1264 ether_poll_register(smc_poll, ifp); 1265 SMC_LOCK(sc); 1266 ifp->if_capenable |= IFCAP_POLLING; 1267#endif 1268} 1269 1270static int 1271smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1272{ 1273 struct smc_softc *sc; 1274 int error; 1275 1276 sc = ifp->if_softc; 1277 error = 0; 1278 1279 switch (cmd) { 1280 case SIOCSIFFLAGS: 1281 if ((ifp->if_flags & IFF_UP) == 0 && 1282 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1283 SMC_LOCK(sc); 1284 smc_stop(sc); 1285 SMC_UNLOCK(sc); 1286 } else { 1287 smc_init(sc); 1288 if (sc->smc_mii_mediachg != NULL) 1289 sc->smc_mii_mediachg(sc); 1290 } 1291 break; 1292 1293 case SIOCADDMULTI: 1294 case SIOCDELMULTI: 1295 /* XXX 1296 SMC_LOCK(sc); 1297 smc_setmcast(sc); 1298 SMC_UNLOCK(sc); 1299 */ 1300 error = EINVAL; 1301 break; 1302 1303 case SIOCGIFMEDIA: 1304 case SIOCSIFMEDIA: 1305 if (sc->smc_mii_mediaioctl == NULL) { 1306 error = EINVAL; 1307 break; 1308 } 1309 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1310 break; 1311 1312 default: 1313 error = ether_ioctl(ifp, cmd, data); 1314 break; 1315 } 1316 1317 return (error); 1318} 1319