if_smc.c revision 179592
1/*- 2 * Copyright (c) 2006 Benno Rice. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: head/sys/dev/smc/if_smc.c 179592 2008-06-06 05:00:49Z benno $"); 27 28/* 29 * Driver for SMSC LAN91C111, may work for older variants. 30 */ 31 32#ifdef HAVE_KERNEL_OPTION_HEADERS 33#include "opt_device_polling.h" 34#endif 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/errno.h> 39#include <sys/kernel.h> 40#include <sys/sockio.h> 41#include <sys/malloc.h> 42#include <sys/mbuf.h> 43#include <sys/queue.h> 44#include <sys/socket.h> 45#include <sys/syslog.h> 46#include <sys/taskqueue.h> 47 48#include <sys/module.h> 49#include <sys/bus.h> 50 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <sys/rman.h> 54 55#include <net/ethernet.h> 56#include <net/if.h> 57#include <net/if_arp.h> 58#include <net/if_dl.h> 59#include <net/if_types.h> 60#include <net/if_mib.h> 61#include <net/if_media.h> 62 63#ifdef INET 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/in_var.h> 67#include <netinet/ip.h> 68#endif 69 70#include <net/bpf.h> 71#include <net/bpfdesc.h> 72 73#include <dev/smc/if_smcreg.h> 74#include <dev/smc/if_smcvar.h> 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79devclass_t smc_devclass; 80 81static const char *smc_chip_ids[16] = { 82 NULL, NULL, NULL, 83 /* 3 */ "SMSC LAN91C90 or LAN91C92", 84 /* 4 */ "SMSC LAN91C94", 85 /* 5 */ "SMSC LAN91C95", 86 /* 6 */ "SMSC LAN91C96", 87 /* 7 */ "SMSC LAN91C100", 88 /* 8 */ "SMSC LAN91C100FD", 89 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 90 NULL, NULL, NULL, 91 NULL, NULL, NULL 92}; 93 94static void smc_init(void *); 95static void smc_start(struct ifnet *); 96static int smc_ioctl(struct ifnet *, u_long, caddr_t); 97 98static void smc_init_locked(struct smc_softc *); 99static void smc_start_locked(struct ifnet *); 100static void smc_reset(struct smc_softc *); 101static int smc_mii_ifmedia_upd(struct ifnet *); 102static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 103static void smc_mii_tick(void *); 104static void smc_mii_mediachg(struct smc_softc *); 105static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 106 107static void smc_task_rx(void *, int); 108static void smc_task_tx(void *, int); 109 110static driver_filter_t smc_intr; 111static timeout_t smc_watchdog; 112#ifdef DEVICE_POLLING 113static poll_handler_t smc_poll; 114#endif 115 116static __inline void 117smc_select_bank(struct smc_softc *sc, uint16_t bank) 118{ 119 120 bus_space_write_2(sc->smc_bst, sc->smc_bsh, BSR, bank & BSR_BANK_MASK); 121} 122 123/* Never call this when not in bank 2. */ 124static __inline void 125smc_mmu_wait(struct smc_softc *sc) 126{ 127 128 KASSERT((bus_space_read_2(sc->smc_bst, sc->smc_bsh, BSR) & 129 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 130 device_get_nameunit(sc->smc_dev))); 131 while (bus_space_read_2(sc->smc_bst, sc->smc_bsh, MMUCR) & MMUCR_BUSY) 132 ; 133} 134 135static __inline uint8_t 136smc_read_1(struct smc_softc *sc, bus_addr_t offset) 137{ 138 139 return (bus_space_read_1(sc->smc_bst, sc->smc_bsh, offset)); 140} 141 142static __inline void 143smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val) 144{ 145 146 bus_space_write_1(sc->smc_bst, sc->smc_bsh, offset, val); 147} 148 149static __inline uint16_t 150smc_read_2(struct smc_softc *sc, bus_addr_t offset) 151{ 152 153 return (bus_space_read_2(sc->smc_bst, sc->smc_bsh, offset)); 154} 155 156static __inline void 157smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val) 158{ 159 160 bus_space_write_2(sc->smc_bst, sc->smc_bsh, offset, val); 161} 162 163static __inline void 164smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, 165 bus_size_t count) 166{ 167 168 bus_space_read_multi_2(sc->smc_bst, sc->smc_bsh, offset, datap, count); 169} 170 171static __inline void 172smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, 173 bus_size_t count) 174{ 175 176 bus_space_write_multi_2(sc->smc_bst, sc->smc_bsh, offset, datap, count); 177} 178 179int 180smc_probe(device_t dev) 181{ 182 int rid, type, error; 183 uint16_t val; 184 struct smc_softc *sc; 185 struct resource *reg; 186 bus_space_tag_t bst; 187 bus_space_handle_t bsh; 188 189 sc = device_get_softc(dev); 190 rid = 0; 191 type = SYS_RES_IOPORT; 192 error = 0; 193 194 if (sc->smc_usemem) 195 type = SYS_RES_MEMORY; 196 197 reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); 198 if (reg == NULL) { 199 if (bootverbose) 200 device_printf(dev, 201 "could not allocate I/O resource for probe\n"); 202 return (ENXIO); 203 } 204 205 bst = rman_get_bustag(reg); 206 bsh = rman_get_bushandle(reg); 207 208 /* Check for the identification value in the BSR. */ 209 val = bus_space_read_2(bst, bsh, BSR); 210 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 211 if (bootverbose) 212 device_printf(dev, "identification value not in BSR\n"); 213 error = ENXIO; 214 goto done; 215 } 216 217 /* 218 * Try switching banks and make sure we still get the identification 219 * value. 220 */ 221 bus_space_write_2(bst, bsh, BSR, 0); 222 val = bus_space_read_2(bst, bsh, BSR); 223 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 224 if (bootverbose) 225 device_printf(dev, 226 "identification value not in BSR after write\n"); 227 error = ENXIO; 228 goto done; 229 } 230 231#if 0 232 /* Check the BAR. */ 233 bus_space_write_2(bst, bsh, BSR, 1); 234 val = bus_space_read_2(bst, bsh, BAR); 235 val = BAR_ADDRESS(val); 236 if (rman_get_start(reg) != val) { 237 if (bootverbose) 238 device_printf(dev, "BAR address %x does not match " 239 "I/O resource address %lx\n", val, 240 rman_get_start(reg)); 241 error = ENXIO; 242 goto done; 243 } 244#endif 245 246 /* Compare REV against known chip revisions. */ 247 bus_space_write_2(bst, bsh, BSR, 3); 248 val = bus_space_read_2(bst, bsh, REV); 249 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 250 if (smc_chip_ids[val] == NULL) { 251 if (bootverbose) 252 device_printf(dev, "Unknown chip revision: %d\n", val); 253 error = ENXIO; 254 goto done; 255 } 256 257 device_set_desc(dev, smc_chip_ids[val]); 258 259done: 260 bus_release_resource(dev, type, rid, reg); 261 return (error); 262} 263 264int 265smc_attach(device_t dev) 266{ 267 int type, error; 268 uint16_t val; 269 u_char eaddr[ETHER_ADDR_LEN]; 270 struct smc_softc *sc; 271 struct ifnet *ifp; 272 273 sc = device_get_softc(dev); 274 error = 0; 275 276 sc->smc_dev = dev; 277 278 /* Set up watchdog callout. */ 279 callout_init(&sc->smc_watchdog, 1); 280 281 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 282 if (ifp == NULL) { 283 error = ENOSPC; 284 goto done; 285 } 286 287 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_SPIN); 288 289 type = SYS_RES_IOPORT; 290 if (sc->smc_usemem) 291 type = SYS_RES_MEMORY; 292 293 sc->smc_reg_rid = 0; 294 sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, 295 16, RF_ACTIVE); 296 if (sc->smc_reg == NULL) { 297 error = ENXIO; 298 goto done; 299 } 300 301 sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, 302 ~0, 1, RF_ACTIVE | RF_SHAREABLE); 303 if (sc->smc_irq == NULL) { 304 error = ENXIO; 305 goto done; 306 } 307 308 sc->smc_bst = rman_get_bustag(sc->smc_reg); 309 sc->smc_bsh = rman_get_bushandle(sc->smc_reg); 310 311 SMC_LOCK(sc); 312 smc_reset(sc); 313 SMC_UNLOCK(sc); 314 315 smc_select_bank(sc, 3); 316 val = smc_read_2(sc, REV); 317 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 318 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 319 if (bootverbose) 320 device_printf(dev, "revision %x\n", sc->smc_rev); 321 322 callout_init(&sc->smc_mii_tick_ch, 1); 323 if (sc->smc_chip >= REV_CHIP_91110FD) { 324 mii_phy_probe(dev, &sc->smc_miibus, smc_mii_ifmedia_upd, 325 smc_mii_ifmedia_sts); 326 if (sc->smc_miibus != NULL) { 327 sc->smc_mii_tick = smc_mii_tick; 328 sc->smc_mii_mediachg = smc_mii_mediachg; 329 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 330 } 331 } 332 333 smc_select_bank(sc, 1); 334 eaddr[0] = smc_read_1(sc, IAR0); 335 eaddr[1] = smc_read_1(sc, IAR1); 336 eaddr[2] = smc_read_1(sc, IAR2); 337 eaddr[3] = smc_read_1(sc, IAR3); 338 eaddr[4] = smc_read_1(sc, IAR4); 339 eaddr[5] = smc_read_1(sc, IAR5); 340 341 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 342 ifp->if_softc = sc; 343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 344 ifp->if_init = smc_init; 345 ifp->if_ioctl = smc_ioctl; 346 ifp->if_start = smc_start; 347 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 348 IFQ_SET_READY(&ifp->if_snd); 349 350 ifp->if_capabilities = ifp->if_capenable = 0; 351 352#ifdef DEVICE_POLLING 353 ifp->if_capabilities |= IFCAP_POLLING; 354#endif 355 356 ether_ifattach(ifp, eaddr); 357 358 /* Set up taskqueue */ 359 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 360 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 361 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 362 taskqueue_thread_enqueue, &sc->smc_tq); 363 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 364 device_get_nameunit(sc->smc_dev)); 365 366 /* Mask all interrupts. */ 367 sc->smc_mask = 0; 368 smc_write_1(sc, MSK, 0); 369 370 /* Wire up interrupt */ 371 error = bus_setup_intr(dev, sc->smc_irq, 372 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, ifp, &sc->smc_ih); 373 if (error != 0) 374 goto done; 375 376done: 377 if (error != 0) 378 smc_detach(dev); 379 return (error); 380} 381 382int 383smc_detach(device_t dev) 384{ 385 int type; 386 struct smc_softc *sc; 387 388 sc = device_get_softc(dev); 389 390 callout_stop(&sc->smc_watchdog); 391 392 if (mtx_initialized(&sc->smc_mtx)) 393 SMC_LOCK(sc); 394 395#ifdef DEVICE_POLLING 396 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 397 ether_poll_deregister(sc->smc_ifp); 398#endif 399 400 if (sc->smc_ih != NULL) 401 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 402 403 if (sc->smc_ifp != NULL) { 404 ether_ifdetach(sc->smc_ifp); 405 if_free(sc->smc_ifp); 406 } 407 408 if (sc->smc_miibus != NULL) { 409 device_delete_child(sc->smc_dev, sc->smc_miibus); 410 bus_generic_detach(sc->smc_dev); 411 } 412 413 if (sc->smc_reg != NULL) { 414 type = SYS_RES_IOPORT; 415 if (sc->smc_usemem) 416 type = SYS_RES_MEMORY; 417 418 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 419 sc->smc_reg); 420 } 421 422 if (sc->smc_irq != NULL) 423 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 424 sc->smc_irq); 425 426 if (sc->smc_tq != NULL) 427 taskqueue_free(sc->smc_tq); 428 429 if (mtx_initialized(&sc->smc_mtx)) 430 mtx_destroy(&sc->smc_mtx); 431 432 return (0); 433} 434 435static void 436smc_start(struct ifnet *ifp) 437{ 438 struct smc_softc *sc; 439 440 sc = ifp->if_softc; 441 SMC_LOCK(sc); 442 smc_start_locked(ifp); 443 SMC_UNLOCK(sc); 444} 445 446static void 447smc_start_locked(struct ifnet *ifp) 448{ 449 struct smc_softc *sc; 450 struct mbuf *m; 451 u_int len, npages, spin_count; 452 453 sc = ifp->if_softc; 454 SMC_ASSERT_LOCKED(sc); 455 456 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 457 return; 458 if (IFQ_IS_EMPTY(&ifp->if_snd)) 459 return; 460 461 /* 462 * Grab the next packet. If it's too big, drop it. 463 */ 464 SMC_UNLOCK(sc); 465 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 466 SMC_LOCK(sc); 467 len = m_length(m, NULL); 468 len += (len & 1); 469 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 470 if_printf(ifp, "large packet discarded\n"); 471 ++ifp->if_oerrors; 472 m_freem(m); 473 return; /* XXX readcheck? */ 474 } 475 476 /* 477 * Flag that we're busy. 478 */ 479 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 480 sc->smc_pending = m; 481 482 /* 483 * Work out how many 256 byte "pages" we need. We have to include the 484 * control data for the packet in this calculation. 485 */ 486 npages = (len * PKT_CTRL_DATA_LEN) >> 8; 487 if (npages == 0) 488 npages = 1; 489 490 /* 491 * Request memory. 492 */ 493 smc_select_bank(sc, 2); 494 smc_mmu_wait(sc); 495 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 496 497 /* 498 * Spin briefly to see if the allocation succeeds. 499 */ 500 spin_count = TX_ALLOC_WAIT_TIME; 501 do { 502 if (smc_read_1(sc, IST) & ALLOC_INT) { 503 smc_write_1(sc, ACK, ALLOC_INT); 504 break; 505 } 506 } while (--spin_count); 507 508 /* 509 * If the allocation is taking too long, unmask the alloc interrupt 510 * and wait. 511 */ 512 if (spin_count == 0) { 513 sc->smc_mask |= ALLOC_INT; 514 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 515 smc_write_1(sc, MSK, sc->smc_mask); 516 return; 517 } 518 519 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 520} 521 522static void 523smc_task_tx(void *context, int pending) 524{ 525 struct ifnet *ifp; 526 struct smc_softc *sc; 527 struct mbuf *m, *m0; 528 u_int packet, len; 529 uint8_t *data; 530 531 (void)pending; 532 ifp = (struct ifnet *)context; 533 sc = ifp->if_softc; 534 535 SMC_LOCK(sc); 536 537 if (sc->smc_pending == NULL) { 538 SMC_UNLOCK(sc); 539 goto next_packet; 540 } 541 542 m = m0 = sc->smc_pending; 543 sc->smc_pending = NULL; 544 smc_select_bank(sc, 2); 545 546 /* 547 * Check the allocation result. 548 */ 549 packet = smc_read_1(sc, ARR); 550 551 /* 552 * If the allocation failed, requeue the packet and retry. 553 */ 554 if (packet & ARR_FAILED) { 555 IFQ_DRV_PREPEND(&ifp->if_snd, m); 556 ++ifp->if_oerrors; 557 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 558 smc_start_locked(ifp); 559 SMC_UNLOCK(sc); 560 return; 561 } 562 563 /* 564 * Tell the device to write to our packet number. 565 */ 566 smc_write_1(sc, PNR, packet); 567 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 568 569 /* 570 * Tell the device how long the packet is (including control data). 571 */ 572 len = m_length(m, 0); 573 len += PKT_CTRL_DATA_LEN; 574 smc_write_2(sc, DATA0, 0); 575 smc_write_2(sc, DATA0, len); 576 577 /* 578 * Push the data out to the device. 579 */ 580 data = NULL; 581 for (; m != NULL; m = m->m_next) { 582 data = mtod(m, uint8_t *); 583 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 584 } 585 586 /* 587 * Push out the control byte and and the odd byte if needed. 588 */ 589 if ((len & 1) != 0 && data != NULL) 590 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]); 591 else 592 smc_write_2(sc, DATA0, 0); 593 594 /* 595 * Unmask the TX empty interrupt. 596 */ 597 sc->smc_mask |= TX_EMPTY_INT; 598 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 599 smc_write_1(sc, MSK, sc->smc_mask); 600 601 /* 602 * Enqueue the packet. 603 */ 604 smc_mmu_wait(sc); 605 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 606 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, ifp); 607 608 /* 609 * Finish up. 610 */ 611 ifp->if_opackets++; 612 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 613 SMC_UNLOCK(sc); 614 BPF_MTAP(ifp, m0); 615 m_freem(m0); 616 617next_packet: 618 /* 619 * See if there's anything else to do. 620 */ 621 smc_start(ifp); 622} 623 624static void 625smc_task_rx(void *context, int pending) 626{ 627 u_int packet, status, len; 628 uint8_t *data; 629 struct ifnet *ifp; 630 struct smc_softc *sc; 631 struct mbuf *m, *mhead, *mtail; 632 633 (void)pending; 634 ifp = (struct ifnet *)context; 635 sc = ifp->if_softc; 636 mhead = mtail = NULL; 637 638 SMC_LOCK(sc); 639 640 packet = smc_read_1(sc, FIFO_RX); 641 while ((packet & FIFO_EMPTY) == 0) { 642 /* 643 * Grab an mbuf and attach a cluster. 644 */ 645 MGETHDR(m, M_DONTWAIT, MT_DATA); 646 if (m == NULL) { 647 break; 648 } 649 MCLGET(m, M_DONTWAIT); 650 if ((m->m_flags & M_EXT) == 0) { 651 m_freem(m); 652 break; 653 } 654 655 /* 656 * Point to the start of the packet. 657 */ 658 smc_select_bank(sc, 2); 659 smc_write_1(sc, PNR, packet); 660 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 661 662 /* 663 * Grab status and packet length. 664 */ 665 status = smc_read_2(sc, DATA0); 666 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 667 len -= 6; 668 if (status & RX_ODDFRM) 669 len += 1; 670 671 /* 672 * Check for errors. 673 */ 674 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 675 smc_mmu_wait(sc); 676 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 677 ifp->if_ierrors++; 678 m_freem(m); 679 break; 680 } 681 682 /* 683 * Set the mbuf up the way we want it. 684 */ 685 m->m_pkthdr.rcvif = ifp; 686 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 687 m_adj(m, ETHER_ALIGN); 688 689 /* 690 * Pull the packet out of the device. Make sure we're in the 691 * right bank first as things may have changed while we were 692 * allocating our mbuf. 693 */ 694 smc_select_bank(sc, 2); 695 smc_write_1(sc, PNR, packet); 696 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 697 data = mtod(m, uint8_t *); 698 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 699 if (len & 1) { 700 data += len & ~1; 701 *data = smc_read_1(sc, DATA0); 702 } 703 704 /* 705 * Tell the device we're done. 706 */ 707 smc_mmu_wait(sc); 708 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 709 if (m == NULL) { 710 break; 711 } 712 713 if (mhead == NULL) { 714 mhead = mtail = m; 715 m->m_next = NULL; 716 } else { 717 mtail->m_next = m; 718 mtail = m; 719 } 720 packet = smc_read_1(sc, FIFO_RX); 721 } 722 723 sc->smc_mask |= RCV_INT; 724 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 725 smc_write_1(sc, MSK, sc->smc_mask); 726 727 SMC_UNLOCK(sc); 728 729 while (mhead != NULL) { 730 m = mhead; 731 mhead = mhead->m_next; 732 m->m_next = NULL; 733 ifp->if_ipackets++; 734 (*ifp->if_input)(ifp, m); 735 } 736} 737 738#ifdef DEVICE_POLLING 739static void 740smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 741{ 742 struct smc_softc *sc; 743 744 sc = ifp->if_softc; 745 746 SMC_LOCK(sc); 747 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 748 SMC_UNLOCK(sc); 749 return; 750 } 751 SMC_UNLOCK(sc); 752 753 if (cmd == POLL_AND_CHECK_STATUS) 754 smc_intr(ifp); 755} 756#endif 757 758static int 759smc_intr(void *context) 760{ 761 struct smc_softc *sc; 762 struct ifnet *ifp; 763 u_int status, packet, counter, tcr; 764 765 ifp = (struct ifnet *)context; 766 sc = ifp->if_softc; 767 768 SMC_LOCK(sc); 769 smc_select_bank(sc, 2); 770 771 /* 772 * Get the current mask, and then block all interrupts while we're 773 * working. 774 */ 775 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 776 smc_write_1(sc, MSK, 0); 777 778 /* 779 * Find out what interrupts are flagged. 780 */ 781 status = smc_read_1(sc, IST) & sc->smc_mask; 782 783 /* 784 * Transmit error 785 */ 786 if (status & TX_INT) { 787 /* 788 * Kill off the packet if there is one and re-enable transmit. 789 */ 790 packet = smc_read_1(sc, FIFO_TX); 791 if ((packet & FIFO_EMPTY) == 0) { 792 smc_write_1(sc, PNR, packet); 793 smc_write_2(sc, PTR, 0 | PTR_READ | 794 PTR_AUTO_INCR); 795 tcr = smc_read_2(sc, DATA0); 796 if ((tcr & EPHSR_TX_SUC) == 0) 797 device_printf(sc->smc_dev, 798 "bad packet\n"); 799 smc_mmu_wait(sc); 800 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 801 802 smc_select_bank(sc, 0); 803 tcr = smc_read_2(sc, TCR); 804 tcr |= TCR_TXENA | TCR_PAD_EN; 805 smc_write_2(sc, TCR, tcr); 806 smc_select_bank(sc, 2); 807 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 808 } 809 810 /* 811 * Ack the interrupt. 812 */ 813 smc_write_1(sc, ACK, TX_INT); 814 } 815 816 /* 817 * Receive 818 */ 819 if (status & RCV_INT) { 820 smc_write_1(sc, ACK, RCV_INT); 821 sc->smc_mask &= ~RCV_INT; 822 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); 823 } 824 825 /* 826 * Allocation 827 */ 828 if (status & ALLOC_INT) { 829 smc_write_1(sc, ACK, ALLOC_INT); 830 sc->smc_mask &= ~ALLOC_INT; 831 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 832 } 833 834 /* 835 * Receive overrun 836 */ 837 if (status & RX_OVRN_INT) { 838 smc_write_1(sc, ACK, RX_OVRN_INT); 839 ifp->if_ierrors++; 840 } 841 842 /* 843 * Transmit empty 844 */ 845 if (status & TX_EMPTY_INT) { 846 smc_write_1(sc, ACK, TX_EMPTY_INT); 847 sc->smc_mask &= ~TX_EMPTY_INT; 848 callout_stop(&sc->smc_watchdog); 849 850 /* 851 * Update collision stats. 852 */ 853 smc_select_bank(sc, 0); 854 counter = smc_read_2(sc, ECR); 855 smc_select_bank(sc, 2); 856 ifp->if_collisions += 857 (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT; 858 ifp->if_collisions += 859 (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT; 860 861 /* 862 * See if there are any packets to transmit. 863 */ 864 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 865 } 866 867 /* 868 * Update the interrupt mask. 869 */ 870 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 871 smc_write_1(sc, MSK, sc->smc_mask); 872 873 SMC_UNLOCK(sc); 874 875 return (FILTER_HANDLED); 876} 877 878static u_int 879smc_mii_readbits(struct smc_softc *sc, int nbits) 880{ 881 u_int mgmt, mask, val; 882 883 SMC_ASSERT_LOCKED(sc); 884 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 885 ("%s: smc_mii_readbits called with bank %d (!= 3)", 886 device_get_nameunit(sc->smc_dev), 887 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 888 889 /* 890 * Set up the MGMT (aka MII) register. 891 */ 892 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); 893 smc_write_2(sc, MGMT, mgmt); 894 895 /* 896 * Read the bits in. 897 */ 898 for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) { 899 if (smc_read_2(sc, MGMT) & MGMT_MDI) 900 val |= mask; 901 902 smc_write_2(sc, MGMT, mgmt); 903 DELAY(1); 904 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); 905 DELAY(1); 906 } 907 908 return (val); 909} 910 911static void 912smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits) 913{ 914 u_int mgmt, mask; 915 916 SMC_ASSERT_LOCKED(sc); 917 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 918 ("%s: smc_mii_writebits called with bank %d (!= 3)", 919 device_get_nameunit(sc->smc_dev), 920 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 921 922 /* 923 * Set up the MGMT (aka MII) register). 924 */ 925 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); 926 mgmt |= MGMT_MDOE; 927 928 /* 929 * Push the bits out. 930 */ 931 for (mask = 1 << (nbits - 1); mask; mask >>= 1) { 932 if (val & mask) 933 mgmt |= MGMT_MDO; 934 else 935 mgmt &= ~MGMT_MDO; 936 937 smc_write_2(sc, MGMT, mgmt); 938 DELAY(1); 939 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); 940 DELAY(1); 941 } 942} 943 944int 945smc_miibus_readreg(device_t dev, int phy, int reg) 946{ 947 struct smc_softc *sc; 948 int val; 949 950 sc = device_get_softc(dev); 951 952 SMC_LOCK(sc); 953 954 smc_select_bank(sc, 3); 955 956 /* 957 * Send out the idle pattern. 958 */ 959 smc_mii_writebits(sc, 0xffffffff, 32); 960 961 /* 962 * Start code + read opcode + phy address + phy register 963 */ 964 smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14); 965 966 /* 967 * Turnaround + data 968 */ 969 val = smc_mii_readbits(sc, 18); 970 971 /* 972 * Reset the MDIO interface. 973 */ 974 smc_write_2(sc, MGMT, 975 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); 976 977 SMC_UNLOCK(sc); 978 return (val); 979} 980 981void 982smc_miibus_writereg(device_t dev, int phy, int reg, int data) 983{ 984 struct smc_softc *sc; 985 986 sc = device_get_softc(dev); 987 988 SMC_LOCK(sc); 989 990 smc_select_bank(sc, 3); 991 992 /* 993 * Send idle pattern. 994 */ 995 smc_mii_writebits(sc, 0xffffffff, 32); 996 997 /* 998 * Start code + write opcode + phy address + phy register + turnaround 999 * + data. 1000 */ 1001 smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data, 1002 32); 1003 1004 /* 1005 * Reset MDIO interface. 1006 */ 1007 smc_write_2(sc, MGMT, 1008 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); 1009 1010 SMC_UNLOCK(sc); 1011} 1012 1013void 1014smc_miibus_statchg(device_t dev) 1015{ 1016 struct smc_softc *sc; 1017 struct mii_data *mii; 1018 uint16_t tcr; 1019 1020 sc = device_get_softc(dev); 1021 mii = device_get_softc(sc->smc_miibus); 1022 1023 SMC_LOCK(sc); 1024 1025 smc_select_bank(sc, 0); 1026 tcr = smc_read_2(sc, TCR); 1027 1028 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1029 tcr |= TCR_SWFDUP; 1030 else 1031 tcr &= ~TCR_SWFDUP; 1032 1033 smc_write_2(sc, TCR, tcr); 1034 1035 SMC_UNLOCK(sc); 1036} 1037 1038static int 1039smc_mii_ifmedia_upd(struct ifnet *ifp) 1040{ 1041 struct smc_softc *sc; 1042 struct mii_data *mii; 1043 1044 sc = ifp->if_softc; 1045 if (sc->smc_miibus == NULL) 1046 return (ENXIO); 1047 1048 mii = device_get_softc(sc->smc_miibus); 1049 return (mii_mediachg(mii)); 1050} 1051 1052static void 1053smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1054{ 1055 struct smc_softc *sc; 1056 struct mii_data *mii; 1057 1058 sc = ifp->if_softc; 1059 if (sc->smc_miibus == NULL) 1060 return; 1061 1062 mii = device_get_softc(sc->smc_miibus); 1063 mii_pollstat(mii); 1064 ifmr->ifm_active = mii->mii_media_active; 1065 ifmr->ifm_status = mii->mii_media_status; 1066} 1067 1068static void 1069smc_mii_tick(void *context) 1070{ 1071 struct smc_softc *sc; 1072 1073 sc = (struct smc_softc *)context; 1074 1075 if (sc->smc_miibus == NULL) 1076 return; 1077 1078 mii_tick(device_get_softc(sc->smc_miibus)); 1079 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1080} 1081 1082static void 1083smc_mii_mediachg(struct smc_softc *sc) 1084{ 1085 1086 if (sc->smc_miibus == NULL) 1087 return; 1088 mii_mediachg(device_get_softc(sc->smc_miibus)); 1089} 1090 1091static int 1092smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1093{ 1094 struct mii_data *mii; 1095 1096 if (sc->smc_miibus == NULL) 1097 return (EINVAL); 1098 1099 mii = device_get_softc(sc->smc_miibus); 1100 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1101} 1102 1103static void 1104smc_reset(struct smc_softc *sc) 1105{ 1106 u_int ctr; 1107 1108 SMC_ASSERT_LOCKED(sc); 1109 1110 smc_select_bank(sc, 2); 1111 1112 /* 1113 * Mask all interrupts. 1114 */ 1115 smc_write_1(sc, MSK, 0); 1116 1117 /* 1118 * Tell the device to reset. 1119 */ 1120 smc_select_bank(sc, 0); 1121 smc_write_2(sc, RCR, RCR_SOFT_RST); 1122 1123 /* 1124 * Set up the configuration register. 1125 */ 1126 smc_select_bank(sc, 1); 1127 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1128 DELAY(1); 1129 1130 /* 1131 * Turn off transmit and receive. 1132 */ 1133 smc_select_bank(sc, 0); 1134 smc_write_2(sc, TCR, 0); 1135 smc_write_2(sc, RCR, 0); 1136 1137 /* 1138 * Set up the control register. 1139 */ 1140 smc_select_bank(sc, 1); 1141 ctr = smc_read_2(sc, CTR); 1142 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1143 smc_write_2(sc, CTR, ctr); 1144 1145 /* 1146 * Reset the MMU. 1147 */ 1148 smc_select_bank(sc, 2); 1149 smc_mmu_wait(sc); 1150 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1151} 1152 1153static void 1154smc_enable(struct smc_softc *sc) 1155{ 1156 struct ifnet *ifp; 1157 1158 SMC_ASSERT_LOCKED(sc); 1159 ifp = sc->smc_ifp; 1160 1161 /* 1162 * Set up the receive/PHY control register. 1163 */ 1164 smc_select_bank(sc, 0); 1165 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1166 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1167 1168 /* 1169 * Set up the transmit and receive control registers. 1170 */ 1171 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1172 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1173 1174 /* 1175 * Set up the interrupt mask. 1176 */ 1177 smc_select_bank(sc, 2); 1178 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1179 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1180 smc_write_1(sc, MSK, sc->smc_mask); 1181} 1182 1183static void 1184smc_stop(struct smc_softc *sc) 1185{ 1186 1187 SMC_ASSERT_LOCKED(sc); 1188 1189 /* 1190 * Turn off watchdog. 1191 */ 1192 callout_stop(&sc->smc_watchdog); 1193 1194 /* 1195 * Mask all interrupts. 1196 */ 1197 smc_select_bank(sc, 2); 1198 sc->smc_mask = 0; 1199 smc_write_1(sc, MSK, 0); 1200#ifdef DEVICE_POLLING 1201 ether_poll_deregister(sc->smc_ifp); 1202 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1203#endif 1204 1205 /* 1206 * Disable transmit and receive. 1207 */ 1208 smc_select_bank(sc, 0); 1209 smc_write_2(sc, TCR, 0); 1210 smc_write_2(sc, RCR, 0); 1211 1212 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1213} 1214 1215static void 1216smc_watchdog(void *arg) 1217{ 1218 struct ifnet *ifp; 1219 1220 ifp = (struct ifnet *)arg; 1221 if_printf(ifp, "watchdog timeout\n"); 1222 smc_intr(ifp); 1223} 1224 1225static void 1226smc_init(void *context) 1227{ 1228 struct smc_softc *sc; 1229 1230 sc = (struct smc_softc *)context; 1231 SMC_LOCK(sc); 1232 smc_init_locked(sc); 1233 SMC_UNLOCK(sc); 1234} 1235 1236static void 1237smc_init_locked(struct smc_softc *sc) 1238{ 1239 struct ifnet *ifp; 1240 1241 ifp = sc->smc_ifp; 1242 1243 SMC_ASSERT_LOCKED(sc); 1244 1245 smc_reset(sc); 1246 smc_enable(sc); 1247 1248 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1249 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1250 1251 smc_start_locked(ifp); 1252 1253 if (sc->smc_mii_tick != NULL) 1254 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1255 1256#ifdef DEVICE_POLLING 1257 SMC_UNLOCK(sc); 1258 ether_poll_register(smc_poll, ifp); 1259 SMC_LOCK(sc); 1260 ifp->if_capenable |= IFCAP_POLLING; 1261#endif 1262} 1263 1264static int 1265smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1266{ 1267 struct smc_softc *sc; 1268 int error; 1269 1270 sc = ifp->if_softc; 1271 error = 0; 1272 1273 switch (cmd) { 1274 case SIOCSIFFLAGS: 1275 if ((ifp->if_flags & IFF_UP) == 0 && 1276 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1277 SMC_LOCK(sc); 1278 smc_stop(sc); 1279 SMC_UNLOCK(sc); 1280 } else { 1281 smc_init(sc); 1282 if (sc->smc_mii_mediachg != NULL) 1283 sc->smc_mii_mediachg(sc); 1284 } 1285 break; 1286 1287 case SIOCADDMULTI: 1288 case SIOCDELMULTI: 1289 /* XXX 1290 SMC_LOCK(sc); 1291 smc_setmcast(sc); 1292 SMC_UNLOCK(sc); 1293 */ 1294 error = EINVAL; 1295 break; 1296 1297 case SIOCGIFMEDIA: 1298 case SIOCSIFMEDIA: 1299 if (sc->smc_mii_mediaioctl == NULL) { 1300 error = EINVAL; 1301 break; 1302 } 1303 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1304 break; 1305 1306 default: 1307 error = ether_ioctl(ifp, cmd, data); 1308 break; 1309 } 1310 1311 return (error); 1312} 1313