sdhci.c revision 185661
133965Sjdp/*- 260484Sobrien * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 333965Sjdp * All rights reserved. 433965Sjdp * 560484Sobrien * Redistribution and use in source and binary forms, with or without 660484Sobrien * modification, are permitted provided that the following conditions 733965Sjdp * are met: 860484Sobrien * 1. Redistributions of source code must retain the above copyright 960484Sobrien * notice, this list of conditions and the following disclaimer. 1060484Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1160484Sobrien * notice, this list of conditions and the following disclaimer in the 1233965Sjdp * documentation and/or other materials provided with the distribution. 1360484Sobrien * 1460484Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1560484Sobrien * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1660484Sobrien * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1760484Sobrien * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1860484Sobrien * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 1960484Sobrien * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2060484Sobrien * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2160484Sobrien * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2260484Sobrien * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2360484Sobrien * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2460484Sobrien */ 2560484Sobrien 2660484Sobrien#include <sys/cdefs.h> 2733965Sjdp__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci.c 185661 2008-12-06 01:31:07Z mav $"); 2833965Sjdp 2933965Sjdp#include <sys/param.h> 3033965Sjdp#include <sys/systm.h> 3133965Sjdp#include <sys/bus.h> 3233965Sjdp#include <sys/conf.h> 3333965Sjdp#include <sys/kernel.h> 3433965Sjdp#include <sys/lock.h> 3533965Sjdp#include <sys/module.h> 3633965Sjdp#include <sys/mutex.h> 3733965Sjdp#include <sys/resource.h> 3833965Sjdp#include <sys/rman.h> 3933965Sjdp#include <sys/taskqueue.h> 4033965Sjdp 4133965Sjdp#include <dev/pci/pcireg.h> 4233965Sjdp#include <dev/pci/pcivar.h> 4333965Sjdp 4433965Sjdp#include <machine/bus.h> 4533965Sjdp#include <machine/resource.h> 4633965Sjdp#include <machine/stdarg.h> 4733965Sjdp 4833965Sjdp#include <dev/mmc/bridge.h> 4933965Sjdp#include <dev/mmc/mmcreg.h> 5033965Sjdp#include <dev/mmc/mmcbrvar.h> 5133965Sjdp 5233965Sjdp#include "mmcbr_if.h" 5333965Sjdp#include "sdhci.h" 5433965Sjdp 5533965Sjdp#define DMA_BLOCK_SIZE 4096 5633965Sjdp#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 5733965Sjdp 5833965Sjdp/* Controller doesn't honor resets unless we touch the clock register */ 5933965Sjdp#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 6033965Sjdp/* Controller really supports DMA */ 6133965Sjdp#define SDHCI_QUIRK_FORCE_DMA (1<<1) 6233965Sjdp/* Controller has unusable DMA engine */ 6333965Sjdp#define SDHCI_QUIRK_BROKEN_DMA (1<<2) 6433965Sjdp/* Controller doesn't like to be reset when there is no card inserted. */ 6533965Sjdp#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 6633965Sjdp/* Controller has flaky internal state so reset it on each ios change */ 6733965Sjdp#define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 6833965Sjdp/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 6933965Sjdp#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 7033965Sjdp/* Controller needs to be reset after each request to stay stable */ 7133965Sjdp#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 7233965Sjdp/* Controller has an off-by-one issue with timeout value */ 7333965Sjdp#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 7433965Sjdp/* Controller has broken read timings */ 7533965Sjdp#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 7633965Sjdp 7733965Sjdpstatic const struct sdhci_device { 7833965Sjdp uint32_t model; 7960484Sobrien uint16_t subvendor; 8060484Sobrien char *desc; 8160484Sobrien u_int quirks; 8260484Sobrien} sdhci_devices[] = { 8360484Sobrien { 0x08221180, 0xffff, "RICOH R5C822 SD", 8460484Sobrien SDHCI_QUIRK_FORCE_DMA }, 8560484Sobrien { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 8660484Sobrien SDHCI_QUIRK_FORCE_DMA }, 8760484Sobrien { 0x05501524, 0xffff, "ENE CB712 SD", 8860484Sobrien SDHCI_QUIRK_BROKEN_TIMINGS }, 8960484Sobrien { 0x05511524, 0xffff, "ENE CB712 SD 2", 9060484Sobrien SDHCI_QUIRK_BROKEN_TIMINGS }, 9160484Sobrien { 0x07501524, 0xffff, "ENE CB714 SD", 9260484Sobrien SDHCI_QUIRK_RESET_ON_IOS | 9360484Sobrien SDHCI_QUIRK_BROKEN_TIMINGS }, 9460484Sobrien { 0x07511524, 0xffff, "ENE CB714 SD 2", 9560484Sobrien SDHCI_QUIRK_RESET_ON_IOS | 9660484Sobrien SDHCI_QUIRK_BROKEN_TIMINGS }, 9760484Sobrien { 0x410111ab, 0xffff, "Marvell CaFe SD", 9860484Sobrien SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 9960484Sobrien { 0x2381197B, 0xffff, "JMicron JMB38X SD", 10060484Sobrien SDHCI_QUIRK_32BIT_DMA_SIZE | 10133965Sjdp SDHCI_QUIRK_RESET_AFTER_REQUEST }, 10233965Sjdp { 0, 0xffff, NULL, 10333965Sjdp 0 } 10433965Sjdp}; 10533965Sjdp 10633965Sjdpstruct sdhci_softc; 10733965Sjdp 10833965Sjdpstruct sdhci_slot { 10933965Sjdp struct sdhci_softc *sc; 11033965Sjdp device_t dev; /* Slot device */ 11133965Sjdp u_char num; /* Slot number */ 11260484Sobrien u_char opt; /* Slot options */ 11333965Sjdp#define SDHCI_HAVE_DMA 1 11433965Sjdp uint32_t max_clk; /* Max possible freq */ 11533965Sjdp uint32_t timeout_clk; /* Timeout freq */ 11660484Sobrien struct resource *mem_res; /* Memory resource */ 11760484Sobrien int mem_rid; 11860484Sobrien bus_dma_tag_t dmatag; 11960484Sobrien bus_dmamap_t dmamap; 12060484Sobrien u_char *dmamem; 12160484Sobrien bus_addr_t paddr; /* DMA buffer address */ 12260484Sobrien struct task card_task; /* Card presence check task */ 12360484Sobrien struct callout card_callout; /* Card insert delay callout */ 12460484Sobrien struct mmc_host host; /* Host parameters */ 12560484Sobrien struct mmc_request *req; /* Current request */ 12660484Sobrien struct mmc_command *curcmd; /* Current command of current request */ 12760484Sobrien 12860484Sobrien uint32_t intmask; /* Current interrupt mask */ 12933965Sjdp uint32_t clock; /* Current clock freq. */ 13033965Sjdp size_t offset; /* Data buffer offset */ 13133965Sjdp uint8_t hostctrl; /* Current host control register */ 13233965Sjdp u_char power; /* Current power */ 13333965Sjdp u_char bus_busy; /* Bus busy status */ 13433965Sjdp u_char cmd_done; /* CMD command part done flag */ 13533965Sjdp u_char data_done; /* DAT command part done flag */ 13633965Sjdp u_char flags; /* Request execution flags */ 13733965Sjdp#define CMD_STARTED 1 13860484Sobrien#define STOP_STARTED 2 13933965Sjdp#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 14033965Sjdp struct mtx mtx; /* Slot mutex */ 14133965Sjdp}; 14233965Sjdp 14333965Sjdpstruct sdhci_softc { 14433965Sjdp device_t dev; /* Controller device */ 14533965Sjdp u_int quirks; /* Chip specific quirks */ 14633965Sjdp struct resource *irq_res; /* IRQ resource */ 14733965Sjdp int irq_rid; 14833965Sjdp void *intrhand; /* Interrupt handle */ 14933965Sjdp 15033965Sjdp int num_slots; /* Number of slots on this controller */ 15133965Sjdp struct sdhci_slot slots[6]; 15233965Sjdp}; 15333965Sjdp 15433965Sjdpstatic inline uint8_t 15560484SobrienRD1(struct sdhci_slot *slot, bus_size_t off) 15660484Sobrien{ 15760484Sobrien bus_barrier(slot->mem_res, 0, 0xFF, 15860484Sobrien BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 15933965Sjdp return bus_read_1(slot->mem_res, off); 16033965Sjdp} 16160484Sobrien 16233965Sjdpstatic inline void 16333965SjdpWR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) 16433965Sjdp{ 16533965Sjdp bus_barrier(slot->mem_res, 0, 0xFF, 16660484Sobrien BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 16733965Sjdp bus_write_1(slot->mem_res, off, val); 16833965Sjdp} 16933965Sjdp 17033965Sjdpstatic inline uint16_t 17133965SjdpRD2(struct sdhci_slot *slot, bus_size_t off) 17233965Sjdp{ 17333965Sjdp bus_barrier(slot->mem_res, 0, 0xFF, 17433965Sjdp BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 17533965Sjdp return bus_read_2(slot->mem_res, off); 17633965Sjdp} 17733965Sjdp 17833965Sjdpstatic inline void 17933965SjdpWR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) 18033965Sjdp{ 18133965Sjdp bus_barrier(slot->mem_res, 0, 0xFF, 18233965Sjdp BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 18333965Sjdp bus_write_2(slot->mem_res, off, val); 18460484Sobrien} 18560484Sobrien 18660484Sobrienstatic inline uint32_t 18760484SobrienRD4(struct sdhci_slot *slot, bus_size_t off) 18833965Sjdp{ 18933965Sjdp bus_barrier(slot->mem_res, 0, 0xFF, 19060484Sobrien BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 19133965Sjdp return bus_read_4(slot->mem_res, off); 19233965Sjdp} 19333965Sjdp 19433965Sjdpstatic inline void 19533965SjdpWR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) 19633965Sjdp{ 19760484Sobrien bus_barrier(slot->mem_res, 0, 0xFF, 19833965Sjdp BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 19933965Sjdp bus_write_4(slot->mem_res, off, val); 20033965Sjdp} 20133965Sjdp 20233965Sjdp/* bus entry points */ 20333965Sjdpstatic int sdhci_probe(device_t dev); 20460484Sobrienstatic int sdhci_attach(device_t dev); 20533965Sjdpstatic int sdhci_detach(device_t dev); 20633965Sjdpstatic void sdhci_intr(void *); 20733965Sjdp 20833965Sjdpstatic void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 20933965Sjdpstatic void sdhci_start(struct sdhci_slot *slot); 21033965Sjdpstatic void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 21133965Sjdp 21233965Sjdpstatic void sdhci_card_task(void *, int); 21360484Sobrien 21460484Sobrien/* helper routines */ 21560484Sobrien#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 21660484Sobrien#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 21733965Sjdp#define SDHCI_LOCK_INIT(_slot) \ 21833965Sjdp mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 21960484Sobrien#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 22033965Sjdp#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 22133965Sjdp#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 22233965Sjdp 22333965Sjdpstatic int 22433965Sjdpslot_printf(struct sdhci_slot *slot, const char * fmt, ...) 22560484Sobrien{ 22633965Sjdp va_list ap; 22733965Sjdp int retval; 22833965Sjdp 22933965Sjdp retval = printf("%s-slot%d: ", 23033965Sjdp device_get_nameunit(slot->sc->dev), slot->num); 23133965Sjdp 23233965Sjdp va_start(ap, fmt); 23333965Sjdp retval += vprintf(fmt, ap); 23433965Sjdp va_end(ap); 23533965Sjdp return (retval); 23633965Sjdp} 23733965Sjdp 23833965Sjdpstatic void 23933965Sjdpsdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 24033965Sjdp{ 24133965Sjdp if (error != 0) { 24233965Sjdp printf("getaddr: error %d\n", error); 24360484Sobrien return; 24460484Sobrien } 24560484Sobrien *(bus_addr_t *)arg = segs[0].ds_addr; 24660484Sobrien} 24733965Sjdp 24833965Sjdpstatic void 24960484Sobriensdhci_dumpregs(struct sdhci_slot *slot) 25033965Sjdp{ 25133965Sjdp slot_printf(slot, 25233965Sjdp "============== REGISTER DUMP ==============\n"); 25333965Sjdp 25433965Sjdp slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 25533965Sjdp RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 25633965Sjdp slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 25760484Sobrien RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 25833965Sjdp slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 25933965Sjdp RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 26033965Sjdp slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 26133965Sjdp RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 26233965Sjdp slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 26333965Sjdp RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 26460484Sobrien slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 26533965Sjdp RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 26633965Sjdp slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 26733965Sjdp RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 26833965Sjdp slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 26933965Sjdp RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 27033965Sjdp slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 27133965Sjdp RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 27233965Sjdp slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 27333965Sjdp RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 27433965Sjdp 27533965Sjdp slot_printf(slot, 27633965Sjdp "===========================================\n"); 27733965Sjdp} 27833965Sjdp 27933965Sjdpstatic void 28033965Sjdpsdhci_reset(struct sdhci_slot *slot, uint8_t mask) 28133965Sjdp{ 28260484Sobrien int timeout; 28360484Sobrien uint8_t res; 28460484Sobrien 28533965Sjdp if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 28633965Sjdp if (!(RD4(slot, SDHCI_PRESENT_STATE) & 28733965Sjdp SDHCI_CARD_PRESENT)) 28833965Sjdp return; 28933965Sjdp } 29033965Sjdp 29133965Sjdp /* Some controllers need this kick or reset won't work. */ 29233965Sjdp if ((mask & SDHCI_RESET_ALL) == 0 && 29333965Sjdp (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 29460484Sobrien uint32_t clock; 29533965Sjdp 29633965Sjdp /* This is to force an update */ 29733965Sjdp clock = slot->clock; 29833965Sjdp slot->clock = 0; 29933965Sjdp sdhci_set_clock(slot, clock); 30033965Sjdp } 30133965Sjdp 30233965Sjdp WR1(slot, SDHCI_SOFTWARE_RESET, mask); 30333965Sjdp 30433965Sjdp if (mask & SDHCI_RESET_ALL) { 30533965Sjdp slot->clock = 0; 30633965Sjdp slot->power = 0; 30733965Sjdp } 30833965Sjdp 30933965Sjdp /* Wait max 100 ms */ 31033965Sjdp timeout = 100; 31133965Sjdp /* Controller clears the bits when it's done */ 31233965Sjdp while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 31333965Sjdp if (timeout == 0) { 31433965Sjdp slot_printf(slot, 31533965Sjdp "Reset 0x%x never completed - 0x%x.\n", 31633965Sjdp (int)mask, (int)res); 31733965Sjdp sdhci_dumpregs(slot); 31833965Sjdp return; 31933965Sjdp } 32033965Sjdp timeout--; 32133965Sjdp DELAY(1000); 32233965Sjdp } 32333965Sjdp} 32433965Sjdp 32533965Sjdpstatic void 32633965Sjdpsdhci_init(struct sdhci_slot *slot) 32733965Sjdp{ 32833965Sjdp 32933965Sjdp sdhci_reset(slot, SDHCI_RESET_ALL); 33033965Sjdp 33133965Sjdp /* Enable interrupts. */ 33233965Sjdp slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 33333965Sjdp SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 33433965Sjdp SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 33533965Sjdp SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 33633965Sjdp SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 33733965Sjdp SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 33833965Sjdp SDHCI_INT_ACMD12ERR; 33933965Sjdp WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 34033965Sjdp WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 34133965Sjdp} 34233965Sjdp 34333965Sjdpstatic void 34433965Sjdpsdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 34533965Sjdp{ 34633965Sjdp uint32_t res; 34733965Sjdp uint16_t clk; 34833965Sjdp int timeout; 34933965Sjdp 35033965Sjdp if (clock == slot->clock) 35133965Sjdp return; 35233965Sjdp slot->clock = clock; 35333965Sjdp 35433965Sjdp /* Turn off the clock. */ 35533965Sjdp WR2(slot, SDHCI_CLOCK_CONTROL, 0); 35633965Sjdp /* If no clock requested - left it so. */ 35733965Sjdp if (clock == 0) 35833965Sjdp return; 35933965Sjdp /* Looking for highest freq <= clock. */ 36033965Sjdp res = slot->max_clk; 36133965Sjdp for (clk = 1; clk < 256; clk <<= 1) { 36233965Sjdp if (res <= clock) 36333965Sjdp break; 36433965Sjdp res >>= 1; 36533965Sjdp } 36633965Sjdp /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 36733965Sjdp clk >>= 1; 36833965Sjdp /* Now we have got divider, set it. */ 36933965Sjdp clk <<= SDHCI_DIVIDER_SHIFT; 37033965Sjdp WR2(slot, SDHCI_CLOCK_CONTROL, clk); 37133965Sjdp /* Enable clock. */ 37233965Sjdp clk |= SDHCI_CLOCK_INT_EN; 37333965Sjdp WR2(slot, SDHCI_CLOCK_CONTROL, clk); 37433965Sjdp /* Wait up to 10 ms until it stabilize. */ 37533965Sjdp timeout = 10; 37633965Sjdp while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 37733965Sjdp & SDHCI_CLOCK_INT_STABLE)) { 37833965Sjdp if (timeout == 0) { 37933965Sjdp slot_printf(slot, 38033965Sjdp "Internal clock never stabilised.\n"); 38133965Sjdp sdhci_dumpregs(slot); 38233965Sjdp return; 38333965Sjdp } 38433965Sjdp timeout--; 38533965Sjdp DELAY(1000); 38633965Sjdp } 38733965Sjdp /* Pass clock signal to the bus. */ 38833965Sjdp clk |= SDHCI_CLOCK_CARD_EN; 38933965Sjdp WR2(slot, SDHCI_CLOCK_CONTROL, clk); 39033965Sjdp} 39133965Sjdp 39233965Sjdpstatic void 39333965Sjdpsdhci_set_power(struct sdhci_slot *slot, u_char power) 39433965Sjdp{ 39533965Sjdp uint8_t pwr; 39633965Sjdp 39733965Sjdp if (slot->power == power) 39833965Sjdp return; 39933965Sjdp slot->power = power; 40033965Sjdp 40133965Sjdp /* Turn off the power. */ 40233965Sjdp pwr = 0; 40333965Sjdp WR1(slot, SDHCI_POWER_CONTROL, pwr); 40433965Sjdp /* If power down requested - left it so. */ 40533965Sjdp if (power == 0) 40633965Sjdp return; 40733965Sjdp /* Set voltage. */ 40833965Sjdp switch (1 << power) { 40933965Sjdp case MMC_OCR_LOW_VOLTAGE: 41033965Sjdp pwr |= SDHCI_POWER_180; 41133965Sjdp break; 41233965Sjdp case MMC_OCR_290_300: 41333965Sjdp case MMC_OCR_300_310: 41433965Sjdp pwr |= SDHCI_POWER_300; 41533965Sjdp break; 41633965Sjdp case MMC_OCR_320_330: 41733965Sjdp case MMC_OCR_330_340: 41833965Sjdp pwr |= SDHCI_POWER_330; 41933965Sjdp break; 42033965Sjdp } 42133965Sjdp WR1(slot, SDHCI_POWER_CONTROL, pwr); 42233965Sjdp /* Turn on the power. */ 42333965Sjdp pwr |= SDHCI_POWER_ON; 42433965Sjdp WR1(slot, SDHCI_POWER_CONTROL, pwr); 42533965Sjdp} 42633965Sjdp 42733965Sjdpstatic void 42833965Sjdpsdhci_read_block_pio(struct sdhci_slot *slot) 42933965Sjdp{ 43033965Sjdp uint32_t data; 43133965Sjdp char *buffer; 43233965Sjdp size_t left; 43333965Sjdp 43433965Sjdp buffer = slot->curcmd->data->data; 43533965Sjdp buffer += slot->offset; 43633965Sjdp /* Transfer one block at a time. */ 43733965Sjdp left = min(512, slot->curcmd->data->len - slot->offset); 43860484Sobrien slot->offset += left; 43960484Sobrien 44060484Sobrien /* If we are too fast, broken controllers return zeroes. */ 44160484Sobrien if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 44260484Sobrien DELAY(10); 44360484Sobrien /* Handle unalligned and alligned buffer cases. */ 44460484Sobrien if ((intptr_t)buffer & 3) { 44560484Sobrien while (left > 3) { 44660484Sobrien data = RD4(slot, SDHCI_BUFFER); 44760484Sobrien buffer[0] = data; 44860484Sobrien buffer[1] = (data >> 8); 44960484Sobrien buffer[2] = (data >> 16); 45060484Sobrien buffer[3] = (data >> 24); 45160484Sobrien buffer += 4; 45260484Sobrien left -= 4; 45360484Sobrien } 45460484Sobrien } else { 45560484Sobrien bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 45660484Sobrien (uint32_t *)buffer, left >> 2); 45760484Sobrien left &= 3; 45860484Sobrien } 45960484Sobrien /* Handle uneven size case. */ 46060484Sobrien if (left > 0) { 46160484Sobrien data = RD4(slot, SDHCI_BUFFER); 46260484Sobrien while (left > 0) { 46360484Sobrien *(buffer++) = data; 46460484Sobrien data >>= 8; 46560484Sobrien left--; 46660484Sobrien } 46760484Sobrien } 46860484Sobrien} 46960484Sobrien 47060484Sobrienstatic void 47133965Sjdpsdhci_write_block_pio(struct sdhci_slot *slot) 47233965Sjdp{ 47333965Sjdp uint32_t data = 0; 47433965Sjdp char *buffer; 47533965Sjdp size_t left; 47633965Sjdp 47733965Sjdp buffer = slot->curcmd->data->data; 47833965Sjdp buffer += slot->offset; 47933965Sjdp /* Transfer one block at a time. */ 48033965Sjdp left = min(512, slot->curcmd->data->len - slot->offset); 48133965Sjdp slot->offset += left; 48233965Sjdp 48333965Sjdp /* Handle unalligned and alligned buffer cases. */ 48433965Sjdp if ((intptr_t)buffer & 3) { 48533965Sjdp while (left > 3) { 48633965Sjdp data = buffer[0] + 48733965Sjdp (buffer[1] << 8) + 48833965Sjdp (buffer[2] << 16) + 48933965Sjdp (buffer[3] << 24); 49033965Sjdp left -= 4; 49133965Sjdp buffer += 4; 49233965Sjdp WR4(slot, SDHCI_BUFFER, data); 49333965Sjdp } 49433965Sjdp } else { 49533965Sjdp bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 49633965Sjdp (uint32_t *)buffer, left >> 2); 49733965Sjdp left &= 3; 49833965Sjdp } 49933965Sjdp /* Handle uneven size case. */ 50033965Sjdp if (left > 0) { 50133965Sjdp while (left > 0) { 50233965Sjdp data <<= 8; 50333965Sjdp data += *(buffer++); 50433965Sjdp left--; 50533965Sjdp } 50633965Sjdp WR4(slot, SDHCI_BUFFER, data); 50733965Sjdp } 50833965Sjdp} 50960484Sobrien 51060484Sobrienstatic void 51160484Sobriensdhci_transfer_pio(struct sdhci_slot *slot) 51260484Sobrien{ 51360484Sobrien 51460484Sobrien /* Read as many blocks as possible. */ 51560484Sobrien if (slot->curcmd->data->flags & MMC_DATA_READ) { 51633965Sjdp while (RD4(slot, SDHCI_PRESENT_STATE) & 51733965Sjdp SDHCI_DATA_AVAILABLE) { 51833965Sjdp sdhci_read_block_pio(slot); 51933965Sjdp if (slot->offset >= slot->curcmd->data->len) 52033965Sjdp break; 52133965Sjdp } 52233965Sjdp } else { 52333965Sjdp while (RD4(slot, SDHCI_PRESENT_STATE) & 52433965Sjdp SDHCI_SPACE_AVAILABLE) { 52533965Sjdp sdhci_write_block_pio(slot); 52633965Sjdp if (slot->offset >= slot->curcmd->data->len) 52733965Sjdp break; 52833965Sjdp } 52933965Sjdp } 53033965Sjdp} 53133965Sjdp 53233965Sjdpstatic void 53333965Sjdpsdhci_card_delay(void *arg) 53433965Sjdp{ 53533965Sjdp struct sdhci_slot *slot = arg; 53633965Sjdp 53733965Sjdp taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 53833965Sjdp} 53933965Sjdp 54033965Sjdpstatic void 54133965Sjdpsdhci_card_task(void *arg, int pending) 54233965Sjdp{ 54333965Sjdp struct sdhci_slot *slot = arg; 54433965Sjdp 54533965Sjdp SDHCI_LOCK(slot); 54633965Sjdp if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 54733965Sjdp if (slot->dev == NULL) { 54833965Sjdp /* If card is present - attach mmc bus. */ 54933965Sjdp slot->dev = device_add_child(slot->sc->dev, "mmc", -1); 55033965Sjdp device_set_ivars(slot->dev, slot); 55133965Sjdp SDHCI_UNLOCK(slot); 55233965Sjdp device_probe_and_attach(slot->dev); 55333965Sjdp } else 55433965Sjdp SDHCI_UNLOCK(slot); 55533965Sjdp } else { 55633965Sjdp if (slot->dev != NULL) { 55733965Sjdp /* If no card present - detach mmc bus. */ 55833965Sjdp device_t d = slot->dev; 55933965Sjdp slot->dev = NULL; 56033965Sjdp SDHCI_UNLOCK(slot); 56133965Sjdp device_delete_child(slot->sc->dev, d); 56233965Sjdp } else 56333965Sjdp SDHCI_UNLOCK(slot); 56433965Sjdp } 56533965Sjdp} 56633965Sjdp 56733965Sjdpstatic int 56833965Sjdpsdhci_probe(device_t dev) 56933965Sjdp{ 57033965Sjdp uint32_t model; 57133965Sjdp uint16_t subvendor; 57233965Sjdp uint8_t class, subclass; 57333965Sjdp int i, result; 57433965Sjdp 57533965Sjdp model = (uint32_t)pci_get_device(dev) << 16; 57633965Sjdp model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 57733965Sjdp subvendor = pci_get_subvendor(dev); 57833965Sjdp class = pci_get_class(dev); 57933965Sjdp subclass = pci_get_subclass(dev); 58033965Sjdp 58133965Sjdp result = ENXIO; 58233965Sjdp for (i = 0; sdhci_devices[i].model != 0; i++) { 58333965Sjdp if (sdhci_devices[i].model == model && 58433965Sjdp (sdhci_devices[i].subvendor == 0xffff || 58533965Sjdp sdhci_devices[i].subvendor == subvendor)) { 58633965Sjdp device_set_desc(dev, sdhci_devices[i].desc); 58733965Sjdp result = BUS_PROBE_DEFAULT; 58833965Sjdp break; 58933965Sjdp } 59033965Sjdp } 59133965Sjdp if (result == ENXIO && class == PCIC_BASEPERIPH && 59233965Sjdp subclass == PCIS_BASEPERIPH_SDHC) { 59333965Sjdp device_set_desc(dev, "Generic SD HCI"); 594 result = BUS_PROBE_GENERIC; 595 } 596 597 return (result); 598} 599 600static int 601sdhci_attach(device_t dev) 602{ 603 struct sdhci_softc *sc = device_get_softc(dev); 604 uint32_t model; 605 uint16_t subvendor; 606 uint8_t class, subclass, progif; 607 int err, slots, bar, i; 608 609 sc->dev = dev; 610 model = (uint32_t)pci_get_device(dev) << 16; 611 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 612 subvendor = pci_get_subvendor(dev); 613 class = pci_get_class(dev); 614 subclass = pci_get_subclass(dev); 615 progif = pci_get_progif(dev); 616 /* Apply chip specific quirks. */ 617 for (i = 0; sdhci_devices[i].model != 0; i++) { 618 if (sdhci_devices[i].model == model && 619 (sdhci_devices[i].subvendor == 0xffff || 620 sdhci_devices[i].subvendor == subvendor)) { 621 sc->quirks = sdhci_devices[i].quirks; 622 break; 623 } 624 } 625 /* Read slots info from PCI registers. */ 626 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 627 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 628 slots = PCI_SLOT_INFO_SLOTS(slots); 629 if (slots > 6 || bar > 5) { 630 device_printf(dev, "Incorrect slots information (%d, %d).\n", 631 slots, bar); 632 return (EINVAL); 633 } 634 /* Allocate IRQ. */ 635 sc->irq_rid = 0; 636 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 637 RF_SHAREABLE | RF_ACTIVE); 638 if (sc->irq_res == NULL) { 639 device_printf(dev, "Can't allocate IRQ\n"); 640 return (ENOMEM); 641 } 642 /* Scan all slots. */ 643 for (i = 0; i < slots; i++) { 644 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 645 uint32_t caps; 646 647 SDHCI_LOCK_INIT(slot); 648 slot->sc = sc; 649 slot->num = sc->num_slots; 650 /* Allocate memory. */ 651 slot->mem_rid = PCIR_BAR(bar + i); 652 slot->mem_res = bus_alloc_resource(dev, 653 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 654 if (slot->mem_res == NULL) { 655 device_printf(dev, "Can't allocate memory\n"); 656 SDHCI_LOCK_DESTROY(slot); 657 continue; 658 } 659 /* Allocate DMA tag. */ 660 err = bus_dma_tag_create(bus_get_dma_tag(dev), 661 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 662 BUS_SPACE_MAXADDR, NULL, NULL, 663 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 664 BUS_DMA_ALLOCNOW, NULL, NULL, 665 &slot->dmatag); 666 if (err != 0) { 667 device_printf(dev, "Can't create DMA tag\n"); 668 SDHCI_LOCK_DESTROY(slot); 669 continue; 670 } 671 /* Allocate DMA memory. */ 672 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 673 BUS_DMA_NOWAIT, &slot->dmamap); 674 if (err != 0) { 675 device_printf(dev, "Can't alloc DMA memory\n"); 676 SDHCI_LOCK_DESTROY(slot); 677 continue; 678 } 679 /* Map the memory. */ 680 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 681 (void *)slot->dmamem, DMA_BLOCK_SIZE, 682 sdhci_getaddr, &slot->paddr, 0); 683 if (err != 0 || slot->paddr == 0) { 684 device_printf(dev, "Can't load DMA memory\n"); 685 SDHCI_LOCK_DESTROY(slot); 686 continue; 687 } 688 /* Initialize slot. */ 689 sdhci_init(slot); 690 caps = RD4(slot, SDHCI_CAPABILITIES); 691 /* Calculate base clock frequency. */ 692 slot->max_clk = 693 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 694 if (slot->max_clk == 0) { 695 device_printf(dev, "Hardware doesn't specify base clock " 696 "frequency.\n"); 697 } 698 slot->max_clk *= 1000000; 699 /* Calculate timeout clock frequency. */ 700 slot->timeout_clk = 701 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 702 if (slot->timeout_clk == 0) { 703 device_printf(dev, "Hardware doesn't specify timeout clock " 704 "frequency.\n"); 705 } 706 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 707 slot->timeout_clk *= 1000; 708 709 slot->host.f_min = slot->max_clk / 256; 710 slot->host.f_max = slot->max_clk; 711 slot->host.host_ocr = 0; 712 if (caps & SDHCI_CAN_VDD_330) 713 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 714 if (caps & SDHCI_CAN_VDD_300) 715 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 716 if (caps & SDHCI_CAN_VDD_180) 717 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 718 if (slot->host.host_ocr == 0) { 719 device_printf(dev, "Hardware doesn't report any " 720 "support voltages.\n"); 721 } 722 slot->host.caps = MMC_CAP_4_BIT_DATA; 723 if (caps & SDHCI_CAN_DO_HISPD) 724 slot->host.caps |= MMC_CAP_HSPEED; 725 /* Decide if we have usable DMA. */ 726 if (caps & SDHCI_CAN_DO_DMA) 727 slot->opt |= SDHCI_HAVE_DMA; 728 if (class == PCIC_BASEPERIPH && 729 subclass == PCIS_BASEPERIPH_SDHC && 730 progif != PCI_SDHCI_IFDMA) 731 slot->opt &= ~SDHCI_HAVE_DMA; 732 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) 733 slot->opt &= ~SDHCI_HAVE_DMA; 734 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) 735 slot->opt |= SDHCI_HAVE_DMA; 736 737 if (bootverbose) { 738 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 739 slot->max_clk / 1000000, 740 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 741 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 742 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 743 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 744 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 745 sdhci_dumpregs(slot); 746 } 747 748 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 749 callout_init(&slot->card_callout, 1); 750 sc->num_slots++; 751 } 752 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 753 /* Activate the interrupt */ 754 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 755 NULL, sdhci_intr, sc, &sc->intrhand); 756 if (err) 757 device_printf(dev, "Can't setup IRQ\n"); 758 pci_enable_busmaster(dev); 759 /* Process cards detection. */ 760 for (i = 0; i < sc->num_slots; i++) { 761 struct sdhci_slot *slot = &sc->slots[i]; 762 763 sdhci_card_task(slot, 0); 764 } 765 766 return (0); 767} 768 769static int 770sdhci_detach(device_t dev) 771{ 772 struct sdhci_softc *sc = device_get_softc(dev); 773 int i; 774 775 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 776 bus_release_resource(dev, SYS_RES_IRQ, 777 sc->irq_rid, sc->irq_res); 778 779 for (i = 0; i < sc->num_slots; i++) { 780 struct sdhci_slot *slot = &sc->slots[i]; 781 device_t d; 782 783 callout_drain(&slot->card_callout); 784 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 785 786 SDHCI_LOCK(slot); 787 d = slot->dev; 788 slot->dev = NULL; 789 SDHCI_UNLOCK(slot); 790 if (d != NULL) 791 device_delete_child(dev, d); 792 793 SDHCI_LOCK(slot); 794 sdhci_reset(slot, SDHCI_RESET_ALL); 795 SDHCI_UNLOCK(slot); 796 bus_dmamap_unload(slot->dmatag, slot->dmamap); 797 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 798 bus_dma_tag_destroy(slot->dmatag); 799 bus_release_resource(dev, SYS_RES_MEMORY, 800 slot->mem_rid, slot->mem_res); 801 SDHCI_LOCK_DESTROY(slot); 802 } 803 return (0); 804} 805 806static int 807sdhci_suspend(device_t dev) 808{ 809 struct sdhci_softc *sc = device_get_softc(dev); 810 int i, err; 811 812 err = bus_generic_suspend(dev); 813 if (err) 814 return (err); 815 for (i = 0; i < sc->num_slots; i++) 816 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); 817 return (0); 818} 819 820static int 821sdhci_resume(device_t dev) 822{ 823 struct sdhci_softc *sc = device_get_softc(dev); 824 int i; 825 826 for (i = 0; i < sc->num_slots; i++) 827 sdhci_init(&sc->slots[i]); 828 return (bus_generic_resume(dev)); 829} 830 831static int 832sdhci_update_ios(device_t brdev, device_t reqdev) 833{ 834 struct sdhci_slot *slot = device_get_ivars(reqdev); 835 struct mmc_ios *ios = &slot->host.ios; 836 837 SDHCI_LOCK(slot); 838 /* Do full reset on bus power down to clear from any state. */ 839 if (ios->power_mode == power_off) { 840 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 841 sdhci_init(slot); 842 } 843 /* Configure the bus. */ 844 sdhci_set_clock(slot, ios->clock); 845 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 846 if (ios->bus_width == bus_width_4) 847 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 848 else 849 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 850 if (ios->timing == bus_timing_hs) 851 slot->hostctrl |= SDHCI_CTRL_HISPD; 852 else 853 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 854 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 855 /* Some controllers like reset after bus changes. */ 856 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) 857 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 858 859 SDHCI_UNLOCK(slot); 860 return (0); 861} 862 863static void 864sdhci_set_transfer_mode(struct sdhci_slot *slot, 865 struct mmc_data *data) 866{ 867 uint16_t mode; 868 869 if (data == NULL) 870 return; 871 872 mode = SDHCI_TRNS_BLK_CNT_EN; 873 if (data->len > 512) 874 mode |= SDHCI_TRNS_MULTI; 875 if (data->flags & MMC_DATA_READ) 876 mode |= SDHCI_TRNS_READ; 877 if (slot->req->stop) 878 mode |= SDHCI_TRNS_ACMD12; 879 if (slot->flags & SDHCI_USE_DMA) 880 mode |= SDHCI_TRNS_DMA; 881 882 WR2(slot, SDHCI_TRANSFER_MODE, mode); 883} 884 885static void 886sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 887{ 888 struct mmc_request *req = slot->req; 889 int flags, timeout; 890 uint32_t mask, state; 891 892 slot->curcmd = cmd; 893 slot->cmd_done = 0; 894 895 cmd->error = MMC_ERR_NONE; 896 897 /* This flags combination is not supported by controller. */ 898 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 899 slot_printf(slot, "Unsupported response type!\n"); 900 cmd->error = MMC_ERR_FAILED; 901 slot->req = NULL; 902 slot->curcmd = NULL; 903 req->done(req); 904 return; 905 } 906 907 /* Read controller present state. */ 908 state = RD4(slot, SDHCI_PRESENT_STATE); 909 /* Do not issue command if there is no card, clock or power. 910 * Controller will not detect timeout without clock active. */ 911 if ((state & SDHCI_CARD_PRESENT) == 0 || 912 slot->power == 0 || 913 slot->clock == 0) { 914 cmd->error = MMC_ERR_FAILED; 915 slot->req = NULL; 916 slot->curcmd = NULL; 917 req->done(req); 918 return; 919 } 920 /* Always wait for free CMD bus. */ 921 mask = SDHCI_CMD_INHIBIT; 922 /* Wait for free DAT if we have data or busy signal. */ 923 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 924 mask |= SDHCI_DAT_INHIBIT; 925 /* We shouldn't wait for DAT for stop commands. */ 926 if (cmd == slot->req->stop) 927 mask &= ~SDHCI_DAT_INHIBIT; 928 /* Wait for bus no more then 10 ms. */ 929 timeout = 10; 930 while (state & mask) { 931 if (timeout == 0) { 932 slot_printf(slot, "Controller never released " 933 "inhibit bit(s).\n"); 934 sdhci_dumpregs(slot); 935 cmd->error = MMC_ERR_FAILED; 936 slot->req = NULL; 937 slot->curcmd = NULL; 938 req->done(req); 939 return; 940 } 941 timeout--; 942 DELAY(1000); 943 state = RD4(slot, SDHCI_PRESENT_STATE); 944 } 945 946 /* Prepare command flags. */ 947 if (!(cmd->flags & MMC_RSP_PRESENT)) 948 flags = SDHCI_CMD_RESP_NONE; 949 else if (cmd->flags & MMC_RSP_136) 950 flags = SDHCI_CMD_RESP_LONG; 951 else if (cmd->flags & MMC_RSP_BUSY) 952 flags = SDHCI_CMD_RESP_SHORT_BUSY; 953 else 954 flags = SDHCI_CMD_RESP_SHORT; 955 if (cmd->flags & MMC_RSP_CRC) 956 flags |= SDHCI_CMD_CRC; 957 if (cmd->flags & MMC_RSP_OPCODE) 958 flags |= SDHCI_CMD_INDEX; 959 if (cmd->data) 960 flags |= SDHCI_CMD_DATA; 961 if (cmd->opcode == MMC_STOP_TRANSMISSION) 962 flags |= SDHCI_CMD_TYPE_ABORT; 963 /* Prepare data. */ 964 sdhci_start_data(slot, cmd->data); 965 /* 966 * Interrupt aggregation: To reduce total number of interrupts 967 * group response interrupt with data interrupt when possible. 968 * If there going to be data interrupt, mask response one. 969 */ 970 if (slot->data_done == 0) { 971 WR4(slot, SDHCI_SIGNAL_ENABLE, 972 slot->intmask &= ~SDHCI_INT_RESPONSE); 973 } 974 /* Set command argument. */ 975 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 976 /* Set data transfer mode. */ 977 sdhci_set_transfer_mode(slot, cmd->data); 978 /* Set command flags. */ 979 WR1(slot, SDHCI_COMMAND_FLAGS, flags); 980 /* Start command. */ 981 WR1(slot, SDHCI_COMMAND, cmd->opcode); 982} 983 984static void 985sdhci_finish_command(struct sdhci_slot *slot) 986{ 987 int i; 988 989 slot->cmd_done = 1; 990 /* Interrupt aggregation: Restore command interrupt. 991 * Main restore point for the case when command interrupt 992 * happened first. */ 993 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 994 /* In case of error - reset host and return. */ 995 if (slot->curcmd->error) { 996 sdhci_reset(slot, SDHCI_RESET_CMD); 997 sdhci_reset(slot, SDHCI_RESET_DATA); 998 sdhci_start(slot); 999 return; 1000 } 1001 /* If command has response - fetch it. */ 1002 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1003 if (slot->curcmd->flags & MMC_RSP_136) { 1004 /* CRC is stripped so we need one byte shift. */ 1005 uint8_t extra = 0; 1006 for (i = 0; i < 4; i++) { 1007 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1008 slot->curcmd->resp[3 - i] = (val << 8) + extra; 1009 extra = val >> 24; 1010 } 1011 } else 1012 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1013 } 1014 /* If data ready - finish. */ 1015 if (slot->data_done) 1016 sdhci_start(slot); 1017} 1018 1019static void 1020sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1021{ 1022 uint32_t target_timeout, current_timeout; 1023 uint8_t div; 1024 1025 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1026 slot->data_done = 1; 1027 return; 1028 } 1029 1030 slot->data_done = 0; 1031 1032 /* Calculate and set data timeout.*/ 1033 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1034 target_timeout = 1000000; 1035 div = 0; 1036 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1037 while (current_timeout < target_timeout) { 1038 div++; 1039 current_timeout <<= 1; 1040 if (div >= 0xF) 1041 break; 1042 } 1043 /* Compensate for an off-by-one error in the CaFe chip.*/ 1044 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 1045 div++; 1046 if (div >= 0xF) { 1047 slot_printf(slot, "Timeout too large!\n"); 1048 div = 0xE; 1049 } 1050 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1051 1052 if (data == NULL) 1053 return; 1054 1055 /* Use DMA if possible. */ 1056 if ((slot->opt & SDHCI_HAVE_DMA)) 1057 slot->flags |= SDHCI_USE_DMA; 1058 /* If data is small, broken DMA may return zeroes instead of data, */ 1059 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1060 (data->len <= 512)) 1061 slot->flags &= ~SDHCI_USE_DMA; 1062 /* Some controllers require even block sizes. */ 1063 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1064 ((data->len) & 0x3)) 1065 slot->flags &= ~SDHCI_USE_DMA; 1066 /* Load DMA buffer. */ 1067 if (slot->flags & SDHCI_USE_DMA) { 1068 if (data->flags & MMC_DATA_READ) 1069 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 1070 else { 1071 memcpy(slot->dmamem, data->data, 1072 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 1073 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 1074 } 1075 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1076 /* Interrupt aggregation: Mask border interrupt 1077 * for the last page and unmask else. */ 1078 if (data->len == DMA_BLOCK_SIZE) 1079 slot->intmask &= ~SDHCI_INT_DMA_END; 1080 else 1081 slot->intmask |= SDHCI_INT_DMA_END; 1082 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1083 } 1084 /* Current data offset for both PIO and DMA. */ 1085 slot->offset = 0; 1086 /* Set block size and request IRQ on 4K border. */ 1087 WR2(slot, SDHCI_BLOCK_SIZE, 1088 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1089 /* Set block count. */ 1090 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1091} 1092 1093static void 1094sdhci_finish_data(struct sdhci_slot *slot) 1095{ 1096 struct mmc_data *data = slot->curcmd->data; 1097 1098 slot->data_done = 1; 1099 /* Interrupt aggregation: Restore command interrupt. 1100 * Auxillary restore point for the case when data interrupt 1101 * happened first. */ 1102 if (!slot->cmd_done) { 1103 WR4(slot, SDHCI_SIGNAL_ENABLE, 1104 slot->intmask |= SDHCI_INT_RESPONSE); 1105 } 1106 /* Unload rest of data from DMA buffer. */ 1107 if (slot->flags & SDHCI_USE_DMA) { 1108 if (data->flags & MMC_DATA_READ) { 1109 size_t left = data->len - slot->offset; 1110 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1111 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1112 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1113 } else 1114 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1115 } 1116 /* If there was error - reset the host. */ 1117 if (slot->curcmd->error) { 1118 sdhci_reset(slot, SDHCI_RESET_CMD); 1119 sdhci_reset(slot, SDHCI_RESET_DATA); 1120 sdhci_start(slot); 1121 return; 1122 } 1123 /* If we already have command response - finish. */ 1124 if (slot->cmd_done) 1125 sdhci_start(slot); 1126} 1127 1128static void 1129sdhci_start(struct sdhci_slot *slot) 1130{ 1131 struct mmc_request *req; 1132 1133 req = slot->req; 1134 if (req == NULL) 1135 return; 1136 1137 if (!(slot->flags & CMD_STARTED)) { 1138 slot->flags |= CMD_STARTED; 1139 sdhci_start_command(slot, req->cmd); 1140 return; 1141 } 1142/* We don't need this until using Auto-CMD12 feature 1143 if (!(slot->flags & STOP_STARTED) && req->stop) { 1144 slot->flags |= STOP_STARTED; 1145 sdhci_start_command(slot, req->stop); 1146 return; 1147 } 1148*/ 1149 if (req->cmd->error) { 1150 if (bootverbose) { 1151 slot_printf(slot, 1152 "Command error %d (opcode %u arg %u flags %u " 1153 "dlen %u dflags %u)\n", 1154 req->cmd->error, req->cmd->opcode, req->cmd->arg, 1155 req->cmd->flags, 1156 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1157 (req->cmd->data)?(u_int)req->cmd->data->flags:0); 1158 } 1159 } else if (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST) { 1160 sdhci_reset(slot, SDHCI_RESET_CMD); 1161 sdhci_reset(slot, SDHCI_RESET_DATA); 1162 } 1163 1164 /* We must be done -- bad idea to do this while locked? */ 1165 slot->req = NULL; 1166 slot->curcmd = NULL; 1167 req->done(req); 1168} 1169 1170static int 1171sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1172{ 1173 struct sdhci_slot *slot = device_get_ivars(reqdev); 1174 1175 SDHCI_LOCK(slot); 1176 if (slot->req != NULL) { 1177 SDHCI_UNLOCK(slot); 1178 return (EBUSY); 1179 } 1180/* printf("%s cmd op %u arg %u flags %u data %ju\n", __func__, 1181 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1182 (req->cmd->data)?req->cmd->data->len:0); */ 1183 slot->req = req; 1184 slot->flags = 0; 1185 sdhci_start(slot); 1186 SDHCI_UNLOCK(slot); 1187 return (0); 1188} 1189 1190static int 1191sdhci_get_ro(device_t brdev, device_t reqdev) 1192{ 1193 struct sdhci_slot *slot = device_get_ivars(reqdev); 1194 uint32_t val; 1195 1196 SDHCI_LOCK(slot); 1197 val = RD4(slot, SDHCI_PRESENT_STATE); 1198 SDHCI_UNLOCK(slot); 1199 return (!(val & SDHCI_WRITE_PROTECT)); 1200} 1201 1202static int 1203sdhci_acquire_host(device_t brdev, device_t reqdev) 1204{ 1205 struct sdhci_slot *slot = device_get_ivars(reqdev); 1206 int err = 0; 1207 1208 SDHCI_LOCK(slot); 1209 while (slot->bus_busy) 1210 msleep(slot, &slot->mtx, PZERO, "sdhciah", hz / 5); 1211 slot->bus_busy++; 1212 /* Activate led. */ 1213 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1214 SDHCI_UNLOCK(slot); 1215 return (err); 1216} 1217 1218static int 1219sdhci_release_host(device_t brdev, device_t reqdev) 1220{ 1221 struct sdhci_slot *slot = device_get_ivars(reqdev); 1222 1223 SDHCI_LOCK(slot); 1224 /* Deactivate led. */ 1225 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1226 slot->bus_busy--; 1227 wakeup(slot); 1228 SDHCI_UNLOCK(slot); 1229 return (0); 1230} 1231 1232static void 1233sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1234{ 1235 1236 if (!slot->curcmd) { 1237 slot_printf(slot, "Got command interrupt 0x%08x, but " 1238 "there is no active command.\n", intmask); 1239 sdhci_dumpregs(slot); 1240 return; 1241 } 1242 if (intmask & SDHCI_INT_TIMEOUT) 1243 slot->curcmd->error = MMC_ERR_TIMEOUT; 1244 else if (intmask & SDHCI_INT_CRC) 1245 slot->curcmd->error = MMC_ERR_BADCRC; 1246 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1247 slot->curcmd->error = MMC_ERR_FIFO; 1248 1249 sdhci_finish_command(slot); 1250} 1251 1252static void 1253sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1254{ 1255 1256 if (!slot->curcmd) { 1257 slot_printf(slot, "Got data interrupt 0x%08x, but " 1258 "there is no active command.\n", intmask); 1259 sdhci_dumpregs(slot); 1260 return; 1261 } 1262 if (slot->curcmd->data == NULL && 1263 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1264 slot_printf(slot, "Got data interrupt 0x%08x, but " 1265 "there is no active data operation.\n", 1266 intmask); 1267 sdhci_dumpregs(slot); 1268 return; 1269 } 1270 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1271 slot->curcmd->error = MMC_ERR_TIMEOUT; 1272 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1273 slot->curcmd->error = MMC_ERR_BADCRC; 1274 if (slot->curcmd->data == NULL && 1275 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1276 SDHCI_INT_DMA_END))) { 1277 slot_printf(slot, "Got data interrupt 0x%08x, but " 1278 "there is busy-only command.\n", intmask); 1279 sdhci_dumpregs(slot); 1280 slot->curcmd->error = MMC_ERR_INVALID; 1281 } 1282 if (slot->curcmd->error) { 1283 /* No need to continue after any error. */ 1284 sdhci_finish_data(slot); 1285 return; 1286 } 1287 1288 /* Handle PIO interrupt. */ 1289 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1290 sdhci_transfer_pio(slot); 1291 /* Handle DMA border. */ 1292 if (intmask & SDHCI_INT_DMA_END) { 1293 struct mmc_data *data = slot->curcmd->data; 1294 size_t left; 1295 1296 /* Unload DMA buffer... */ 1297 left = data->len - slot->offset; 1298 if (data->flags & MMC_DATA_READ) { 1299 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1300 BUS_DMASYNC_POSTREAD); 1301 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1302 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1303 } else { 1304 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1305 BUS_DMASYNC_POSTWRITE); 1306 } 1307 /* ... and reload it again. */ 1308 slot->offset += DMA_BLOCK_SIZE; 1309 left = data->len - slot->offset; 1310 if (data->flags & MMC_DATA_READ) { 1311 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1312 BUS_DMASYNC_PREREAD); 1313 } else { 1314 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1315 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1316 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1317 BUS_DMASYNC_PREWRITE); 1318 } 1319 /* Interrupt aggregation: Mask border interrupt 1320 * for the last page. */ 1321 if (left == DMA_BLOCK_SIZE) { 1322 slot->intmask &= ~SDHCI_INT_DMA_END; 1323 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1324 } 1325 /* Restart DMA. */ 1326 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1327 } 1328 /* We have got all data. */ 1329 if (intmask & SDHCI_INT_DATA_END) 1330 sdhci_finish_data(slot); 1331} 1332 1333static void 1334sdhci_acmd_irq(struct sdhci_slot *slot) 1335{ 1336 uint16_t err; 1337 1338 err = RD4(slot, SDHCI_ACMD12_ERR); 1339 if (!slot->curcmd) { 1340 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1341 "there is no active command.\n", err); 1342 sdhci_dumpregs(slot); 1343 return; 1344 } 1345 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1346 sdhci_reset(slot, SDHCI_RESET_CMD); 1347} 1348 1349static void 1350sdhci_intr(void *arg) 1351{ 1352 struct sdhci_softc *sc = (struct sdhci_softc *)arg; 1353 int i; 1354 1355 for (i = 0; i < sc->num_slots; i++) { 1356 struct sdhci_slot *slot = &sc->slots[i]; 1357 uint32_t intmask; 1358 1359 SDHCI_LOCK(slot); 1360 /* Read slot interrupt status. */ 1361 intmask = RD4(slot, SDHCI_INT_STATUS); 1362 if (intmask == 0 || intmask == 0xffffffff) { 1363 SDHCI_UNLOCK(slot); 1364 continue; 1365 } 1366/* 1367 slot_printf(slot, "got interrupt %x\n", intmask); 1368*/ 1369 /* Handle card presence interrupts. */ 1370 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1371 WR4(slot, SDHCI_INT_STATUS, intmask & 1372 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1373 1374 if (intmask & SDHCI_INT_CARD_REMOVE) { 1375 if (bootverbose) 1376 slot_printf(slot, "Card removed\n"); 1377 callout_stop(&slot->card_callout); 1378 taskqueue_enqueue(taskqueue_swi_giant, 1379 &slot->card_task); 1380 } 1381 if (intmask & SDHCI_INT_CARD_INSERT) { 1382 if (bootverbose) 1383 slot_printf(slot, "Card inserted\n"); 1384 callout_reset(&slot->card_callout, hz / 2, 1385 sdhci_card_delay, slot); 1386 } 1387 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1388 } 1389 /* Handle command interrupts. */ 1390 if (intmask & SDHCI_INT_CMD_MASK) { 1391 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1392 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1393 } 1394 /* Handle data interrupts. */ 1395 if (intmask & SDHCI_INT_DATA_MASK) { 1396 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1397 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1398 } 1399 /* Handle AutoCMD12 error interrupt. */ 1400 if (intmask & SDHCI_INT_ACMD12ERR) { 1401 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1402 sdhci_acmd_irq(slot); 1403 } 1404 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1405 intmask &= ~SDHCI_INT_ACMD12ERR; 1406 intmask &= ~SDHCI_INT_ERROR; 1407 /* Handle bus power interrupt. */ 1408 if (intmask & SDHCI_INT_BUS_POWER) { 1409 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1410 slot_printf(slot, 1411 "Card is consuming too much power!\n"); 1412 intmask &= ~SDHCI_INT_BUS_POWER; 1413 } 1414 /* The rest is unknown. */ 1415 if (intmask) { 1416 WR4(slot, SDHCI_INT_STATUS, intmask); 1417 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1418 intmask); 1419 sdhci_dumpregs(slot); 1420 } 1421 1422 SDHCI_UNLOCK(slot); 1423 } 1424} 1425 1426static int 1427sdhci_read_ivar(device_t bus, device_t child, int which, u_char *result) 1428{ 1429 struct sdhci_slot *slot = device_get_ivars(child); 1430 1431 switch (which) { 1432 default: 1433 return (EINVAL); 1434 case MMCBR_IVAR_BUS_MODE: 1435 *(int *)result = slot->host.ios.bus_mode; 1436 break; 1437 case MMCBR_IVAR_BUS_WIDTH: 1438 *(int *)result = slot->host.ios.bus_width; 1439 break; 1440 case MMCBR_IVAR_CHIP_SELECT: 1441 *(int *)result = slot->host.ios.chip_select; 1442 break; 1443 case MMCBR_IVAR_CLOCK: 1444 *(int *)result = slot->host.ios.clock; 1445 break; 1446 case MMCBR_IVAR_F_MIN: 1447 *(int *)result = slot->host.f_min; 1448 break; 1449 case MMCBR_IVAR_F_MAX: 1450 *(int *)result = slot->host.f_max; 1451 break; 1452 case MMCBR_IVAR_HOST_OCR: 1453 *(int *)result = slot->host.host_ocr; 1454 break; 1455 case MMCBR_IVAR_MODE: 1456 *(int *)result = slot->host.mode; 1457 break; 1458 case MMCBR_IVAR_OCR: 1459 *(int *)result = slot->host.ocr; 1460 break; 1461 case MMCBR_IVAR_POWER_MODE: 1462 *(int *)result = slot->host.ios.power_mode; 1463 break; 1464 case MMCBR_IVAR_VDD: 1465 *(int *)result = slot->host.ios.vdd; 1466 break; 1467 case MMCBR_IVAR_CAPS: 1468 *(int *)result = slot->host.caps; 1469 break; 1470 case MMCBR_IVAR_TIMING: 1471 *(int *)result = slot->host.ios.timing; 1472 break; 1473 case MMCBR_IVAR_MAX_DATA: 1474 *(int *)result = 65535; 1475 break; 1476 } 1477 return (0); 1478} 1479 1480static int 1481sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1482{ 1483 struct sdhci_slot *slot = device_get_ivars(child); 1484 1485 switch (which) { 1486 default: 1487 return (EINVAL); 1488 case MMCBR_IVAR_BUS_MODE: 1489 slot->host.ios.bus_mode = value; 1490 break; 1491 case MMCBR_IVAR_BUS_WIDTH: 1492 slot->host.ios.bus_width = value; 1493 break; 1494 case MMCBR_IVAR_CHIP_SELECT: 1495 slot->host.ios.chip_select = value; 1496 break; 1497 case MMCBR_IVAR_CLOCK: 1498 if (value > 0) { 1499 uint32_t clock = slot->max_clk; 1500 int i; 1501 1502 for (i = 0; i < 8; i++) { 1503 if (clock <= value) 1504 break; 1505 clock >>= 1; 1506 } 1507 slot->host.ios.clock = clock; 1508 } else 1509 slot->host.ios.clock = 0; 1510 break; 1511 case MMCBR_IVAR_MODE: 1512 slot->host.mode = value; 1513 break; 1514 case MMCBR_IVAR_OCR: 1515 slot->host.ocr = value; 1516 break; 1517 case MMCBR_IVAR_POWER_MODE: 1518 slot->host.ios.power_mode = value; 1519 break; 1520 case MMCBR_IVAR_VDD: 1521 slot->host.ios.vdd = value; 1522 break; 1523 case MMCBR_IVAR_TIMING: 1524 slot->host.ios.timing = value; 1525 break; 1526 case MMCBR_IVAR_CAPS: 1527 case MMCBR_IVAR_HOST_OCR: 1528 case MMCBR_IVAR_F_MIN: 1529 case MMCBR_IVAR_F_MAX: 1530 case MMCBR_IVAR_MAX_DATA: 1531 return (EINVAL); 1532 } 1533 return (0); 1534} 1535 1536static device_method_t sdhci_methods[] = { 1537 /* device_if */ 1538 DEVMETHOD(device_probe, sdhci_probe), 1539 DEVMETHOD(device_attach, sdhci_attach), 1540 DEVMETHOD(device_detach, sdhci_detach), 1541 DEVMETHOD(device_suspend, sdhci_suspend), 1542 DEVMETHOD(device_resume, sdhci_resume), 1543 1544 /* Bus interface */ 1545 DEVMETHOD(bus_read_ivar, sdhci_read_ivar), 1546 DEVMETHOD(bus_write_ivar, sdhci_write_ivar), 1547 1548 /* mmcbr_if */ 1549 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), 1550 DEVMETHOD(mmcbr_request, sdhci_request), 1551 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), 1552 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), 1553 DEVMETHOD(mmcbr_release_host, sdhci_release_host), 1554 1555 {0, 0}, 1556}; 1557 1558static driver_t sdhci_driver = { 1559 "sdhci", 1560 sdhci_methods, 1561 sizeof(struct sdhci_softc), 1562}; 1563static devclass_t sdhci_devclass; 1564 1565 1566DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); 1567