sdhci.c revision 278703
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci.c 278703 2015-02-13 20:38:39Z ian $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/callout.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/lock.h> 36#include <sys/module.h> 37#include <sys/mutex.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/stdarg.h> 46 47#include <dev/mmc/bridge.h> 48#include <dev/mmc/mmcreg.h> 49#include <dev/mmc/mmcbrvar.h> 50 51#include "mmcbr_if.h" 52#include "sdhci.h" 53#include "sdhci_if.h" 54 55SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57static int sdhci_debug; 58TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 59SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level"); 60 61#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 62#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 63#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 64#define RD_MULTI_4(slot, off, ptr, count) \ 65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 66 67#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 68#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 69#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 70#define WR_MULTI_4(slot, off, ptr, count) \ 71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 72 73static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 74static void sdhci_start(struct sdhci_slot *slot); 75static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 76 77static void sdhci_card_task(void *, int); 78 79/* helper routines */ 80#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 81#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 82#define SDHCI_LOCK_INIT(_slot) \ 83 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 84#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 85#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 86#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 87 88#define SDHCI_DEFAULT_MAX_FREQ 50 89 90#define SDHCI_200_MAX_DIVIDER 256 91#define SDHCI_300_MAX_DIVIDER 2046 92 93static void 94sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 95{ 96 if (error != 0) { 97 printf("getaddr: error %d\n", error); 98 return; 99 } 100 *(bus_addr_t *)arg = segs[0].ds_addr; 101} 102 103static int 104slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 105{ 106 va_list ap; 107 int retval; 108 109 retval = printf("%s-slot%d: ", 110 device_get_nameunit(slot->bus), slot->num); 111 112 va_start(ap, fmt); 113 retval += vprintf(fmt, ap); 114 va_end(ap); 115 return (retval); 116} 117 118static void 119sdhci_dumpregs(struct sdhci_slot *slot) 120{ 121 slot_printf(slot, 122 "============== REGISTER DUMP ==============\n"); 123 124 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 125 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 126 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 127 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 128 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 129 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 130 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 131 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 132 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 133 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 134 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 135 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 136 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 137 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 138 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 139 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 140 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 141 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 142 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 143 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 144 145 slot_printf(slot, 146 "===========================================\n"); 147} 148 149static void 150sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 151{ 152 int timeout; 153 154 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 155 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 156 SDHCI_CARD_PRESENT)) 157 return; 158 } 159 160 /* Some controllers need this kick or reset won't work. */ 161 if ((mask & SDHCI_RESET_ALL) == 0 && 162 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 163 uint32_t clock; 164 165 /* This is to force an update */ 166 clock = slot->clock; 167 slot->clock = 0; 168 sdhci_set_clock(slot, clock); 169 } 170 171 if (mask & SDHCI_RESET_ALL) { 172 slot->clock = 0; 173 slot->power = 0; 174 } 175 176 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 177 178 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 179 /* 180 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 181 * specification. The reset bit has internal propagation delay, 182 * so a fast read after write returns 0 even if reset process is 183 * in progress. The workaround is to poll for 1 before polling 184 * for 0. In the worst case, if we miss seeing it asserted the 185 * time we spent waiting is enough to ensure the reset finishes. 186 */ 187 timeout = 10000; 188 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 189 if (timeout <= 0) 190 break; 191 timeout--; 192 DELAY(1); 193 } 194 } 195 196 /* Wait max 100 ms */ 197 timeout = 10000; 198 /* Controller clears the bits when it's done */ 199 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 200 if (timeout <= 0) { 201 slot_printf(slot, "Reset 0x%x never completed.\n", 202 mask); 203 sdhci_dumpregs(slot); 204 return; 205 } 206 timeout--; 207 DELAY(10); 208 } 209} 210 211static void 212sdhci_init(struct sdhci_slot *slot) 213{ 214 215 sdhci_reset(slot, SDHCI_RESET_ALL); 216 217 /* Enable interrupts. */ 218 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 219 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 220 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 221 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 222 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 223 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 224 SDHCI_INT_ACMD12ERR; 225 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 226 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 227} 228 229static void 230sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 231{ 232 uint32_t res; 233 uint16_t clk; 234 uint16_t div; 235 int timeout; 236 237 if (clock == slot->clock) 238 return; 239 slot->clock = clock; 240 241 /* Turn off the clock. */ 242 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 243 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 244 /* If no clock requested - left it so. */ 245 if (clock == 0) 246 return; 247 248 /* Recalculate timeout clock frequency based on the new sd clock. */ 249 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 250 slot->timeout_clk = slot->clock / 1000; 251 252 if (slot->version < SDHCI_SPEC_300) { 253 /* Looking for highest freq <= clock. */ 254 res = slot->max_clk; 255 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 256 if (res <= clock) 257 break; 258 res >>= 1; 259 } 260 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 261 div >>= 1; 262 } 263 else { 264 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 265 if (clock >= slot->max_clk) 266 div = 0; 267 else { 268 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 269 if ((slot->max_clk / div) <= clock) 270 break; 271 } 272 } 273 div >>= 1; 274 } 275 276 if (bootverbose || sdhci_debug) 277 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 278 div, clock, slot->max_clk); 279 280 /* Now we have got divider, set it. */ 281 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 282 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 283 << SDHCI_DIVIDER_HI_SHIFT; 284 285 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 286 /* Enable clock. */ 287 clk |= SDHCI_CLOCK_INT_EN; 288 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 289 /* Wait up to 10 ms until it stabilize. */ 290 timeout = 10; 291 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 292 & SDHCI_CLOCK_INT_STABLE)) { 293 if (timeout == 0) { 294 slot_printf(slot, 295 "Internal clock never stabilised.\n"); 296 sdhci_dumpregs(slot); 297 return; 298 } 299 timeout--; 300 DELAY(1000); 301 } 302 /* Pass clock signal to the bus. */ 303 clk |= SDHCI_CLOCK_CARD_EN; 304 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 305} 306 307static void 308sdhci_set_power(struct sdhci_slot *slot, u_char power) 309{ 310 uint8_t pwr; 311 312 if (slot->power == power) 313 return; 314 315 slot->power = power; 316 317 /* Turn off the power. */ 318 pwr = 0; 319 WR1(slot, SDHCI_POWER_CONTROL, pwr); 320 /* If power down requested - left it so. */ 321 if (power == 0) 322 return; 323 /* Set voltage. */ 324 switch (1 << power) { 325 case MMC_OCR_LOW_VOLTAGE: 326 pwr |= SDHCI_POWER_180; 327 break; 328 case MMC_OCR_290_300: 329 case MMC_OCR_300_310: 330 pwr |= SDHCI_POWER_300; 331 break; 332 case MMC_OCR_320_330: 333 case MMC_OCR_330_340: 334 pwr |= SDHCI_POWER_330; 335 break; 336 } 337 WR1(slot, SDHCI_POWER_CONTROL, pwr); 338 /* Turn on the power. */ 339 pwr |= SDHCI_POWER_ON; 340 WR1(slot, SDHCI_POWER_CONTROL, pwr); 341} 342 343static void 344sdhci_read_block_pio(struct sdhci_slot *slot) 345{ 346 uint32_t data; 347 char *buffer; 348 size_t left; 349 350 buffer = slot->curcmd->data->data; 351 buffer += slot->offset; 352 /* Transfer one block at a time. */ 353 left = min(512, slot->curcmd->data->len - slot->offset); 354 slot->offset += left; 355 356 /* If we are too fast, broken controllers return zeroes. */ 357 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 358 DELAY(10); 359 /* Handle unaligned and aligned buffer cases. */ 360 if ((intptr_t)buffer & 3) { 361 while (left > 3) { 362 data = RD4(slot, SDHCI_BUFFER); 363 buffer[0] = data; 364 buffer[1] = (data >> 8); 365 buffer[2] = (data >> 16); 366 buffer[3] = (data >> 24); 367 buffer += 4; 368 left -= 4; 369 } 370 } else { 371 RD_MULTI_4(slot, SDHCI_BUFFER, 372 (uint32_t *)buffer, left >> 2); 373 left &= 3; 374 } 375 /* Handle uneven size case. */ 376 if (left > 0) { 377 data = RD4(slot, SDHCI_BUFFER); 378 while (left > 0) { 379 *(buffer++) = data; 380 data >>= 8; 381 left--; 382 } 383 } 384} 385 386static void 387sdhci_write_block_pio(struct sdhci_slot *slot) 388{ 389 uint32_t data = 0; 390 char *buffer; 391 size_t left; 392 393 buffer = slot->curcmd->data->data; 394 buffer += slot->offset; 395 /* Transfer one block at a time. */ 396 left = min(512, slot->curcmd->data->len - slot->offset); 397 slot->offset += left; 398 399 /* Handle unaligned and aligned buffer cases. */ 400 if ((intptr_t)buffer & 3) { 401 while (left > 3) { 402 data = buffer[0] + 403 (buffer[1] << 8) + 404 (buffer[2] << 16) + 405 (buffer[3] << 24); 406 left -= 4; 407 buffer += 4; 408 WR4(slot, SDHCI_BUFFER, data); 409 } 410 } else { 411 WR_MULTI_4(slot, SDHCI_BUFFER, 412 (uint32_t *)buffer, left >> 2); 413 left &= 3; 414 } 415 /* Handle uneven size case. */ 416 if (left > 0) { 417 while (left > 0) { 418 data <<= 8; 419 data += *(buffer++); 420 left--; 421 } 422 WR4(slot, SDHCI_BUFFER, data); 423 } 424} 425 426static void 427sdhci_transfer_pio(struct sdhci_slot *slot) 428{ 429 430 /* Read as many blocks as possible. */ 431 if (slot->curcmd->data->flags & MMC_DATA_READ) { 432 while (RD4(slot, SDHCI_PRESENT_STATE) & 433 SDHCI_DATA_AVAILABLE) { 434 sdhci_read_block_pio(slot); 435 if (slot->offset >= slot->curcmd->data->len) 436 break; 437 } 438 } else { 439 while (RD4(slot, SDHCI_PRESENT_STATE) & 440 SDHCI_SPACE_AVAILABLE) { 441 sdhci_write_block_pio(slot); 442 if (slot->offset >= slot->curcmd->data->len) 443 break; 444 } 445 } 446} 447 448static void 449sdhci_card_delay(void *arg) 450{ 451 struct sdhci_slot *slot = arg; 452 453 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 454} 455 456static void 457sdhci_card_task(void *arg, int pending) 458{ 459 struct sdhci_slot *slot = arg; 460 461 SDHCI_LOCK(slot); 462 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 463 if (slot->dev == NULL) { 464 /* If card is present - attach mmc bus. */ 465 slot->dev = device_add_child(slot->bus, "mmc", -1); 466 device_set_ivars(slot->dev, slot); 467 SDHCI_UNLOCK(slot); 468 device_probe_and_attach(slot->dev); 469 } else 470 SDHCI_UNLOCK(slot); 471 } else { 472 if (slot->dev != NULL) { 473 /* If no card present - detach mmc bus. */ 474 device_t d = slot->dev; 475 slot->dev = NULL; 476 SDHCI_UNLOCK(slot); 477 device_delete_child(slot->bus, d); 478 } else 479 SDHCI_UNLOCK(slot); 480 } 481} 482 483int 484sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 485{ 486 uint32_t caps, freq; 487 int err; 488 489 SDHCI_LOCK_INIT(slot); 490 slot->num = num; 491 slot->bus = dev; 492 493 /* Allocate DMA tag. */ 494 err = bus_dma_tag_create(bus_get_dma_tag(dev), 495 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 496 BUS_SPACE_MAXADDR, NULL, NULL, 497 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 498 BUS_DMA_ALLOCNOW, NULL, NULL, 499 &slot->dmatag); 500 if (err != 0) { 501 device_printf(dev, "Can't create DMA tag\n"); 502 SDHCI_LOCK_DESTROY(slot); 503 return (err); 504 } 505 /* Allocate DMA memory. */ 506 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 507 BUS_DMA_NOWAIT, &slot->dmamap); 508 if (err != 0) { 509 device_printf(dev, "Can't alloc DMA memory\n"); 510 SDHCI_LOCK_DESTROY(slot); 511 return (err); 512 } 513 /* Map the memory. */ 514 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 515 (void *)slot->dmamem, DMA_BLOCK_SIZE, 516 sdhci_getaddr, &slot->paddr, 0); 517 if (err != 0 || slot->paddr == 0) { 518 device_printf(dev, "Can't load DMA memory\n"); 519 SDHCI_LOCK_DESTROY(slot); 520 if(err) 521 return (err); 522 else 523 return (EFAULT); 524 } 525 526 /* Initialize slot. */ 527 sdhci_init(slot); 528 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 529 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 530 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 531 caps = slot->caps; 532 else 533 caps = RD4(slot, SDHCI_CAPABILITIES); 534 /* Calculate base clock frequency. */ 535 if (slot->version >= SDHCI_SPEC_300) 536 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 537 SDHCI_CLOCK_BASE_SHIFT; 538 else 539 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 540 SDHCI_CLOCK_BASE_SHIFT; 541 if (freq != 0) 542 slot->max_clk = freq * 1000000; 543 /* 544 * If the frequency wasn't in the capabilities and the hardware driver 545 * hasn't already set max_clk we're probably not going to work right 546 * with an assumption, so complain about it. 547 */ 548 if (slot->max_clk == 0) { 549 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 550 device_printf(dev, "Hardware doesn't specify base clock " 551 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 552 } 553 /* Calculate timeout clock frequency. */ 554 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 555 slot->timeout_clk = slot->max_clk / 1000; 556 } else { 557 slot->timeout_clk = 558 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 559 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 560 slot->timeout_clk *= 1000; 561 } 562 /* 563 * If the frequency wasn't in the capabilities and the hardware driver 564 * hasn't already set timeout_clk we'll probably work okay using the 565 * max timeout, but still mention it. 566 */ 567 if (slot->timeout_clk == 0) { 568 device_printf(dev, "Hardware doesn't specify timeout clock " 569 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 570 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 571 } 572 573 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 574 slot->host.f_max = slot->max_clk; 575 slot->host.host_ocr = 0; 576 if (caps & SDHCI_CAN_VDD_330) 577 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 578 if (caps & SDHCI_CAN_VDD_300) 579 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 580 if (caps & SDHCI_CAN_VDD_180) 581 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 582 if (slot->host.host_ocr == 0) { 583 device_printf(dev, "Hardware doesn't report any " 584 "support voltages.\n"); 585 } 586 slot->host.caps = MMC_CAP_4_BIT_DATA; 587 if (caps & SDHCI_CAN_DO_HISPD) 588 slot->host.caps |= MMC_CAP_HSPEED; 589 /* Decide if we have usable DMA. */ 590 if (caps & SDHCI_CAN_DO_DMA) 591 slot->opt |= SDHCI_HAVE_DMA; 592 593 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 594 slot->opt &= ~SDHCI_HAVE_DMA; 595 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 596 slot->opt |= SDHCI_HAVE_DMA; 597 598 /* 599 * Use platform-provided transfer backend 600 * with PIO as a fallback mechanism 601 */ 602 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 603 slot->opt &= ~SDHCI_HAVE_DMA; 604 605 if (bootverbose || sdhci_debug) { 606 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 607 slot->max_clk / 1000000, 608 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 609 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 610 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 611 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 612 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 613 sdhci_dumpregs(slot); 614 } 615 616 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 617 callout_init(&slot->card_callout, 1); 618 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 619 return (0); 620} 621 622void 623sdhci_start_slot(struct sdhci_slot *slot) 624{ 625 sdhci_card_task(slot, 0); 626} 627 628int 629sdhci_cleanup_slot(struct sdhci_slot *slot) 630{ 631 device_t d; 632 633 callout_drain(&slot->timeout_callout); 634 callout_drain(&slot->card_callout); 635 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 636 637 SDHCI_LOCK(slot); 638 d = slot->dev; 639 slot->dev = NULL; 640 SDHCI_UNLOCK(slot); 641 if (d != NULL) 642 device_delete_child(slot->bus, d); 643 644 SDHCI_LOCK(slot); 645 sdhci_reset(slot, SDHCI_RESET_ALL); 646 SDHCI_UNLOCK(slot); 647 bus_dmamap_unload(slot->dmatag, slot->dmamap); 648 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 649 bus_dma_tag_destroy(slot->dmatag); 650 651 SDHCI_LOCK_DESTROY(slot); 652 653 return (0); 654} 655 656int 657sdhci_generic_suspend(struct sdhci_slot *slot) 658{ 659 sdhci_reset(slot, SDHCI_RESET_ALL); 660 661 return (0); 662} 663 664int 665sdhci_generic_resume(struct sdhci_slot *slot) 666{ 667 sdhci_init(slot); 668 669 return (0); 670} 671 672uint32_t 673sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 674{ 675 if (slot->version >= SDHCI_SPEC_300) 676 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 677 else 678 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 679} 680 681int 682sdhci_generic_update_ios(device_t brdev, device_t reqdev) 683{ 684 struct sdhci_slot *slot = device_get_ivars(reqdev); 685 struct mmc_ios *ios = &slot->host.ios; 686 687 SDHCI_LOCK(slot); 688 /* Do full reset on bus power down to clear from any state. */ 689 if (ios->power_mode == power_off) { 690 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 691 sdhci_init(slot); 692 } 693 /* Configure the bus. */ 694 sdhci_set_clock(slot, ios->clock); 695 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 696 if (ios->bus_width == bus_width_4) 697 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 698 else 699 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 700 if (ios->timing == bus_timing_hs && 701 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 702 slot->hostctrl |= SDHCI_CTRL_HISPD; 703 else 704 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 705 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 706 /* Some controllers like reset after bus changes. */ 707 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 708 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 709 710 SDHCI_UNLOCK(slot); 711 return (0); 712} 713 714static void 715sdhci_req_done(struct sdhci_slot *slot) 716{ 717 struct mmc_request *req; 718 719 if (slot->req != NULL && slot->curcmd != NULL) { 720 callout_stop(&slot->timeout_callout); 721 req = slot->req; 722 slot->req = NULL; 723 slot->curcmd = NULL; 724 req->done(req); 725 } 726} 727 728static void 729sdhci_timeout(void *arg) 730{ 731 struct sdhci_slot *slot = arg; 732 733 if (slot->curcmd != NULL) { 734 slot_printf(slot, " Controller timeout\n"); 735 sdhci_dumpregs(slot); 736 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 737 slot->curcmd->error = MMC_ERR_TIMEOUT; 738 sdhci_req_done(slot); 739 } else { 740 slot_printf(slot, " Spurious timeout - no active command\n"); 741 } 742} 743 744static void 745sdhci_set_transfer_mode(struct sdhci_slot *slot, 746 struct mmc_data *data) 747{ 748 uint16_t mode; 749 750 if (data == NULL) 751 return; 752 753 mode = SDHCI_TRNS_BLK_CNT_EN; 754 if (data->len > 512) 755 mode |= SDHCI_TRNS_MULTI; 756 if (data->flags & MMC_DATA_READ) 757 mode |= SDHCI_TRNS_READ; 758 if (slot->req->stop) 759 mode |= SDHCI_TRNS_ACMD12; 760 if (slot->flags & SDHCI_USE_DMA) 761 mode |= SDHCI_TRNS_DMA; 762 763 WR2(slot, SDHCI_TRANSFER_MODE, mode); 764} 765 766static void 767sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 768{ 769 int flags, timeout; 770 uint32_t mask, state; 771 772 slot->curcmd = cmd; 773 slot->cmd_done = 0; 774 775 cmd->error = MMC_ERR_NONE; 776 777 /* This flags combination is not supported by controller. */ 778 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 779 slot_printf(slot, "Unsupported response type!\n"); 780 cmd->error = MMC_ERR_FAILED; 781 sdhci_req_done(slot); 782 return; 783 } 784 785 /* Read controller present state. */ 786 state = RD4(slot, SDHCI_PRESENT_STATE); 787 /* Do not issue command if there is no card, clock or power. 788 * Controller will not detect timeout without clock active. */ 789 if ((state & SDHCI_CARD_PRESENT) == 0 || 790 slot->power == 0 || 791 slot->clock == 0) { 792 cmd->error = MMC_ERR_FAILED; 793 sdhci_req_done(slot); 794 return; 795 } 796 /* Always wait for free CMD bus. */ 797 mask = SDHCI_CMD_INHIBIT; 798 /* Wait for free DAT if we have data or busy signal. */ 799 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 800 mask |= SDHCI_DAT_INHIBIT; 801 /* We shouldn't wait for DAT for stop commands. */ 802 if (cmd == slot->req->stop) 803 mask &= ~SDHCI_DAT_INHIBIT; 804 /* 805 * Wait for bus no more then 250 ms. Typically there will be no wait 806 * here at all, but when writing a crash dump we may be bypassing the 807 * host platform's interrupt handler, and in some cases that handler 808 * may be working around hardware quirks such as not respecting r1b 809 * busy indications. In those cases, this wait-loop serves the purpose 810 * of waiting for the prior command and data transfers to be done, and 811 * SD cards are allowed to take up to 250ms for write and erase ops. 812 * (It's usually more like 20-30ms in the real world.) 813 */ 814 timeout = 250; 815 while (state & mask) { 816 if (timeout == 0) { 817 slot_printf(slot, "Controller never released " 818 "inhibit bit(s).\n"); 819 sdhci_dumpregs(slot); 820 cmd->error = MMC_ERR_FAILED; 821 sdhci_req_done(slot); 822 return; 823 } 824 timeout--; 825 DELAY(1000); 826 state = RD4(slot, SDHCI_PRESENT_STATE); 827 } 828 829 /* Prepare command flags. */ 830 if (!(cmd->flags & MMC_RSP_PRESENT)) 831 flags = SDHCI_CMD_RESP_NONE; 832 else if (cmd->flags & MMC_RSP_136) 833 flags = SDHCI_CMD_RESP_LONG; 834 else if (cmd->flags & MMC_RSP_BUSY) 835 flags = SDHCI_CMD_RESP_SHORT_BUSY; 836 else 837 flags = SDHCI_CMD_RESP_SHORT; 838 if (cmd->flags & MMC_RSP_CRC) 839 flags |= SDHCI_CMD_CRC; 840 if (cmd->flags & MMC_RSP_OPCODE) 841 flags |= SDHCI_CMD_INDEX; 842 if (cmd->data) 843 flags |= SDHCI_CMD_DATA; 844 if (cmd->opcode == MMC_STOP_TRANSMISSION) 845 flags |= SDHCI_CMD_TYPE_ABORT; 846 /* Prepare data. */ 847 sdhci_start_data(slot, cmd->data); 848 /* 849 * Interrupt aggregation: To reduce total number of interrupts 850 * group response interrupt with data interrupt when possible. 851 * If there going to be data interrupt, mask response one. 852 */ 853 if (slot->data_done == 0) { 854 WR4(slot, SDHCI_SIGNAL_ENABLE, 855 slot->intmask &= ~SDHCI_INT_RESPONSE); 856 } 857 /* Set command argument. */ 858 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 859 /* Set data transfer mode. */ 860 sdhci_set_transfer_mode(slot, cmd->data); 861 /* Start command. */ 862 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 863 /* Start timeout callout. */ 864 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot); 865} 866 867static void 868sdhci_finish_command(struct sdhci_slot *slot) 869{ 870 int i; 871 872 slot->cmd_done = 1; 873 /* Interrupt aggregation: Restore command interrupt. 874 * Main restore point for the case when command interrupt 875 * happened first. */ 876 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 877 /* In case of error - reset host and return. */ 878 if (slot->curcmd->error) { 879 sdhci_reset(slot, SDHCI_RESET_CMD); 880 sdhci_reset(slot, SDHCI_RESET_DATA); 881 sdhci_start(slot); 882 return; 883 } 884 /* If command has response - fetch it. */ 885 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 886 if (slot->curcmd->flags & MMC_RSP_136) { 887 /* CRC is stripped so we need one byte shift. */ 888 uint8_t extra = 0; 889 for (i = 0; i < 4; i++) { 890 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 891 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 892 slot->curcmd->resp[3 - i] = val; 893 else { 894 slot->curcmd->resp[3 - i] = 895 (val << 8) | extra; 896 extra = val >> 24; 897 } 898 } 899 } else 900 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 901 } 902 /* If data ready - finish. */ 903 if (slot->data_done) 904 sdhci_start(slot); 905} 906 907static void 908sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 909{ 910 uint32_t target_timeout, current_timeout; 911 uint8_t div; 912 913 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 914 slot->data_done = 1; 915 return; 916 } 917 918 slot->data_done = 0; 919 920 /* Calculate and set data timeout.*/ 921 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 922 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 923 div = 0xE; 924 } else { 925 target_timeout = 1000000; 926 div = 0; 927 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 928 while (current_timeout < target_timeout && div < 0xE) { 929 ++div; 930 current_timeout <<= 1; 931 } 932 /* Compensate for an off-by-one error in the CaFe chip.*/ 933 if (div < 0xE && 934 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 935 ++div; 936 } 937 } 938 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 939 940 if (data == NULL) 941 return; 942 943 /* Use DMA if possible. */ 944 if ((slot->opt & SDHCI_HAVE_DMA)) 945 slot->flags |= SDHCI_USE_DMA; 946 /* If data is small, broken DMA may return zeroes instead of data, */ 947 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 948 (data->len <= 512)) 949 slot->flags &= ~SDHCI_USE_DMA; 950 /* Some controllers require even block sizes. */ 951 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 952 ((data->len) & 0x3)) 953 slot->flags &= ~SDHCI_USE_DMA; 954 /* Load DMA buffer. */ 955 if (slot->flags & SDHCI_USE_DMA) { 956 if (data->flags & MMC_DATA_READ) 957 bus_dmamap_sync(slot->dmatag, slot->dmamap, 958 BUS_DMASYNC_PREREAD); 959 else { 960 memcpy(slot->dmamem, data->data, 961 (data->len < DMA_BLOCK_SIZE) ? 962 data->len : DMA_BLOCK_SIZE); 963 bus_dmamap_sync(slot->dmatag, slot->dmamap, 964 BUS_DMASYNC_PREWRITE); 965 } 966 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 967 /* Interrupt aggregation: Mask border interrupt 968 * for the last page and unmask else. */ 969 if (data->len == DMA_BLOCK_SIZE) 970 slot->intmask &= ~SDHCI_INT_DMA_END; 971 else 972 slot->intmask |= SDHCI_INT_DMA_END; 973 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 974 } 975 /* Current data offset for both PIO and DMA. */ 976 slot->offset = 0; 977 /* Set block size and request IRQ on 4K border. */ 978 WR2(slot, SDHCI_BLOCK_SIZE, 979 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 980 /* Set block count. */ 981 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 982} 983 984void 985sdhci_finish_data(struct sdhci_slot *slot) 986{ 987 struct mmc_data *data = slot->curcmd->data; 988 989 /* Interrupt aggregation: Restore command interrupt. 990 * Auxiliary restore point for the case when data interrupt 991 * happened first. */ 992 if (!slot->cmd_done) { 993 WR4(slot, SDHCI_SIGNAL_ENABLE, 994 slot->intmask |= SDHCI_INT_RESPONSE); 995 } 996 /* Unload rest of data from DMA buffer. */ 997 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 998 if (data->flags & MMC_DATA_READ) { 999 size_t left = data->len - slot->offset; 1000 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1001 BUS_DMASYNC_POSTREAD); 1002 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1003 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1004 } else 1005 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1006 BUS_DMASYNC_POSTWRITE); 1007 } 1008 slot->data_done = 1; 1009 /* If there was error - reset the host. */ 1010 if (slot->curcmd->error) { 1011 sdhci_reset(slot, SDHCI_RESET_CMD); 1012 sdhci_reset(slot, SDHCI_RESET_DATA); 1013 sdhci_start(slot); 1014 return; 1015 } 1016 /* If we already have command response - finish. */ 1017 if (slot->cmd_done) 1018 sdhci_start(slot); 1019} 1020 1021static void 1022sdhci_start(struct sdhci_slot *slot) 1023{ 1024 struct mmc_request *req; 1025 1026 req = slot->req; 1027 if (req == NULL) 1028 return; 1029 1030 if (!(slot->flags & CMD_STARTED)) { 1031 slot->flags |= CMD_STARTED; 1032 sdhci_start_command(slot, req->cmd); 1033 return; 1034 } 1035/* We don't need this until using Auto-CMD12 feature 1036 if (!(slot->flags & STOP_STARTED) && req->stop) { 1037 slot->flags |= STOP_STARTED; 1038 sdhci_start_command(slot, req->stop); 1039 return; 1040 } 1041*/ 1042 if (sdhci_debug > 1) 1043 slot_printf(slot, "result: %d\n", req->cmd->error); 1044 if (!req->cmd->error && 1045 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1046 sdhci_reset(slot, SDHCI_RESET_CMD); 1047 sdhci_reset(slot, SDHCI_RESET_DATA); 1048 } 1049 1050 sdhci_req_done(slot); 1051} 1052 1053int 1054sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1055{ 1056 struct sdhci_slot *slot = device_get_ivars(reqdev); 1057 1058 SDHCI_LOCK(slot); 1059 if (slot->req != NULL) { 1060 SDHCI_UNLOCK(slot); 1061 return (EBUSY); 1062 } 1063 if (sdhci_debug > 1) { 1064 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1065 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1066 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1067 (req->cmd->data)?req->cmd->data->flags:0); 1068 } 1069 slot->req = req; 1070 slot->flags = 0; 1071 sdhci_start(slot); 1072 SDHCI_UNLOCK(slot); 1073 if (dumping) { 1074 while (slot->req != NULL) { 1075 sdhci_generic_intr(slot); 1076 DELAY(10); 1077 } 1078 } 1079 return (0); 1080} 1081 1082int 1083sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1084{ 1085 struct sdhci_slot *slot = device_get_ivars(reqdev); 1086 uint32_t val; 1087 1088 SDHCI_LOCK(slot); 1089 val = RD4(slot, SDHCI_PRESENT_STATE); 1090 SDHCI_UNLOCK(slot); 1091 return (!(val & SDHCI_WRITE_PROTECT)); 1092} 1093 1094int 1095sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1096{ 1097 struct sdhci_slot *slot = device_get_ivars(reqdev); 1098 int err = 0; 1099 1100 SDHCI_LOCK(slot); 1101 while (slot->bus_busy) 1102 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1103 slot->bus_busy++; 1104 /* Activate led. */ 1105 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1106 SDHCI_UNLOCK(slot); 1107 return (err); 1108} 1109 1110int 1111sdhci_generic_release_host(device_t brdev, device_t reqdev) 1112{ 1113 struct sdhci_slot *slot = device_get_ivars(reqdev); 1114 1115 SDHCI_LOCK(slot); 1116 /* Deactivate led. */ 1117 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1118 slot->bus_busy--; 1119 SDHCI_UNLOCK(slot); 1120 wakeup(slot); 1121 return (0); 1122} 1123 1124static void 1125sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1126{ 1127 1128 if (!slot->curcmd) { 1129 slot_printf(slot, "Got command interrupt 0x%08x, but " 1130 "there is no active command.\n", intmask); 1131 sdhci_dumpregs(slot); 1132 return; 1133 } 1134 if (intmask & SDHCI_INT_TIMEOUT) 1135 slot->curcmd->error = MMC_ERR_TIMEOUT; 1136 else if (intmask & SDHCI_INT_CRC) 1137 slot->curcmd->error = MMC_ERR_BADCRC; 1138 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1139 slot->curcmd->error = MMC_ERR_FIFO; 1140 1141 sdhci_finish_command(slot); 1142} 1143 1144static void 1145sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1146{ 1147 1148 if (!slot->curcmd) { 1149 slot_printf(slot, "Got data interrupt 0x%08x, but " 1150 "there is no active command.\n", intmask); 1151 sdhci_dumpregs(slot); 1152 return; 1153 } 1154 if (slot->curcmd->data == NULL && 1155 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1156 slot_printf(slot, "Got data interrupt 0x%08x, but " 1157 "there is no active data operation.\n", 1158 intmask); 1159 sdhci_dumpregs(slot); 1160 return; 1161 } 1162 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1163 slot->curcmd->error = MMC_ERR_TIMEOUT; 1164 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1165 slot->curcmd->error = MMC_ERR_BADCRC; 1166 if (slot->curcmd->data == NULL && 1167 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1168 SDHCI_INT_DMA_END))) { 1169 slot_printf(slot, "Got data interrupt 0x%08x, but " 1170 "there is busy-only command.\n", intmask); 1171 sdhci_dumpregs(slot); 1172 slot->curcmd->error = MMC_ERR_INVALID; 1173 } 1174 if (slot->curcmd->error) { 1175 /* No need to continue after any error. */ 1176 goto done; 1177 } 1178 1179 /* Handle PIO interrupt. */ 1180 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1181 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1182 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1183 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1184 slot->flags |= PLATFORM_DATA_STARTED; 1185 } else 1186 sdhci_transfer_pio(slot); 1187 } 1188 /* Handle DMA border. */ 1189 if (intmask & SDHCI_INT_DMA_END) { 1190 struct mmc_data *data = slot->curcmd->data; 1191 size_t left; 1192 1193 /* Unload DMA buffer... */ 1194 left = data->len - slot->offset; 1195 if (data->flags & MMC_DATA_READ) { 1196 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1197 BUS_DMASYNC_POSTREAD); 1198 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1199 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1200 } else { 1201 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1202 BUS_DMASYNC_POSTWRITE); 1203 } 1204 /* ... and reload it again. */ 1205 slot->offset += DMA_BLOCK_SIZE; 1206 left = data->len - slot->offset; 1207 if (data->flags & MMC_DATA_READ) { 1208 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1209 BUS_DMASYNC_PREREAD); 1210 } else { 1211 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1212 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1213 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1214 BUS_DMASYNC_PREWRITE); 1215 } 1216 /* Interrupt aggregation: Mask border interrupt 1217 * for the last page. */ 1218 if (left == DMA_BLOCK_SIZE) { 1219 slot->intmask &= ~SDHCI_INT_DMA_END; 1220 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1221 } 1222 /* Restart DMA. */ 1223 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1224 } 1225 /* We have got all data. */ 1226 if (intmask & SDHCI_INT_DATA_END) { 1227 if (slot->flags & PLATFORM_DATA_STARTED) { 1228 slot->flags &= ~PLATFORM_DATA_STARTED; 1229 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1230 } else 1231 sdhci_finish_data(slot); 1232 } 1233done: 1234 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1235 if (slot->flags & PLATFORM_DATA_STARTED) { 1236 slot->flags &= ~PLATFORM_DATA_STARTED; 1237 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1238 } else 1239 sdhci_finish_data(slot); 1240 return; 1241 } 1242} 1243 1244static void 1245sdhci_acmd_irq(struct sdhci_slot *slot) 1246{ 1247 uint16_t err; 1248 1249 err = RD4(slot, SDHCI_ACMD12_ERR); 1250 if (!slot->curcmd) { 1251 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1252 "there is no active command.\n", err); 1253 sdhci_dumpregs(slot); 1254 return; 1255 } 1256 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1257 sdhci_reset(slot, SDHCI_RESET_CMD); 1258} 1259 1260void 1261sdhci_generic_intr(struct sdhci_slot *slot) 1262{ 1263 uint32_t intmask; 1264 1265 SDHCI_LOCK(slot); 1266 /* Read slot interrupt status. */ 1267 intmask = RD4(slot, SDHCI_INT_STATUS); 1268 if (intmask == 0 || intmask == 0xffffffff) { 1269 SDHCI_UNLOCK(slot); 1270 return; 1271 } 1272 if (sdhci_debug > 2) 1273 slot_printf(slot, "Interrupt %#x\n", intmask); 1274 1275 /* Handle card presence interrupts. */ 1276 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1277 WR4(slot, SDHCI_INT_STATUS, intmask & 1278 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1279 1280 if (intmask & SDHCI_INT_CARD_REMOVE) { 1281 if (bootverbose || sdhci_debug) 1282 slot_printf(slot, "Card removed\n"); 1283 callout_stop(&slot->card_callout); 1284 taskqueue_enqueue(taskqueue_swi_giant, 1285 &slot->card_task); 1286 } 1287 if (intmask & SDHCI_INT_CARD_INSERT) { 1288 if (bootverbose || sdhci_debug) 1289 slot_printf(slot, "Card inserted\n"); 1290 callout_reset(&slot->card_callout, hz / 2, 1291 sdhci_card_delay, slot); 1292 } 1293 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1294 } 1295 /* Handle command interrupts. */ 1296 if (intmask & SDHCI_INT_CMD_MASK) { 1297 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1298 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1299 } 1300 /* Handle data interrupts. */ 1301 if (intmask & SDHCI_INT_DATA_MASK) { 1302 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1303 /* Dont call data_irq in case of errored command */ 1304 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1305 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1306 } 1307 /* Handle AutoCMD12 error interrupt. */ 1308 if (intmask & SDHCI_INT_ACMD12ERR) { 1309 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1310 sdhci_acmd_irq(slot); 1311 } 1312 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1313 intmask &= ~SDHCI_INT_ACMD12ERR; 1314 intmask &= ~SDHCI_INT_ERROR; 1315 /* Handle bus power interrupt. */ 1316 if (intmask & SDHCI_INT_BUS_POWER) { 1317 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1318 slot_printf(slot, 1319 "Card is consuming too much power!\n"); 1320 intmask &= ~SDHCI_INT_BUS_POWER; 1321 } 1322 /* The rest is unknown. */ 1323 if (intmask) { 1324 WR4(slot, SDHCI_INT_STATUS, intmask); 1325 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1326 intmask); 1327 sdhci_dumpregs(slot); 1328 } 1329 1330 SDHCI_UNLOCK(slot); 1331} 1332 1333int 1334sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1335{ 1336 struct sdhci_slot *slot = device_get_ivars(child); 1337 1338 switch (which) { 1339 default: 1340 return (EINVAL); 1341 case MMCBR_IVAR_BUS_MODE: 1342 *result = slot->host.ios.bus_mode; 1343 break; 1344 case MMCBR_IVAR_BUS_WIDTH: 1345 *result = slot->host.ios.bus_width; 1346 break; 1347 case MMCBR_IVAR_CHIP_SELECT: 1348 *result = slot->host.ios.chip_select; 1349 break; 1350 case MMCBR_IVAR_CLOCK: 1351 *result = slot->host.ios.clock; 1352 break; 1353 case MMCBR_IVAR_F_MIN: 1354 *result = slot->host.f_min; 1355 break; 1356 case MMCBR_IVAR_F_MAX: 1357 *result = slot->host.f_max; 1358 break; 1359 case MMCBR_IVAR_HOST_OCR: 1360 *result = slot->host.host_ocr; 1361 break; 1362 case MMCBR_IVAR_MODE: 1363 *result = slot->host.mode; 1364 break; 1365 case MMCBR_IVAR_OCR: 1366 *result = slot->host.ocr; 1367 break; 1368 case MMCBR_IVAR_POWER_MODE: 1369 *result = slot->host.ios.power_mode; 1370 break; 1371 case MMCBR_IVAR_VDD: 1372 *result = slot->host.ios.vdd; 1373 break; 1374 case MMCBR_IVAR_CAPS: 1375 *result = slot->host.caps; 1376 break; 1377 case MMCBR_IVAR_TIMING: 1378 *result = slot->host.ios.timing; 1379 break; 1380 case MMCBR_IVAR_MAX_DATA: 1381 *result = 65535; 1382 break; 1383 } 1384 return (0); 1385} 1386 1387int 1388sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1389{ 1390 struct sdhci_slot *slot = device_get_ivars(child); 1391 1392 switch (which) { 1393 default: 1394 return (EINVAL); 1395 case MMCBR_IVAR_BUS_MODE: 1396 slot->host.ios.bus_mode = value; 1397 break; 1398 case MMCBR_IVAR_BUS_WIDTH: 1399 slot->host.ios.bus_width = value; 1400 break; 1401 case MMCBR_IVAR_CHIP_SELECT: 1402 slot->host.ios.chip_select = value; 1403 break; 1404 case MMCBR_IVAR_CLOCK: 1405 if (value > 0) { 1406 uint32_t max_clock; 1407 uint32_t clock; 1408 int i; 1409 1410 max_clock = slot->max_clk; 1411 clock = max_clock; 1412 1413 if (slot->version < SDHCI_SPEC_300) { 1414 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1415 i <<= 1) { 1416 if (clock <= value) 1417 break; 1418 clock >>= 1; 1419 } 1420 } 1421 else { 1422 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1423 i += 2) { 1424 if (clock <= value) 1425 break; 1426 clock = max_clock / (i + 2); 1427 } 1428 } 1429 1430 slot->host.ios.clock = clock; 1431 } else 1432 slot->host.ios.clock = 0; 1433 break; 1434 case MMCBR_IVAR_MODE: 1435 slot->host.mode = value; 1436 break; 1437 case MMCBR_IVAR_OCR: 1438 slot->host.ocr = value; 1439 break; 1440 case MMCBR_IVAR_POWER_MODE: 1441 slot->host.ios.power_mode = value; 1442 break; 1443 case MMCBR_IVAR_VDD: 1444 slot->host.ios.vdd = value; 1445 break; 1446 case MMCBR_IVAR_TIMING: 1447 slot->host.ios.timing = value; 1448 break; 1449 case MMCBR_IVAR_CAPS: 1450 case MMCBR_IVAR_HOST_OCR: 1451 case MMCBR_IVAR_F_MIN: 1452 case MMCBR_IVAR_F_MAX: 1453 case MMCBR_IVAR_MAX_DATA: 1454 return (EINVAL); 1455 } 1456 return (0); 1457} 1458 1459MODULE_VERSION(sdhci, 1); 1460