sdhci.c revision 241600
1271493Sdelphij/*- 2271493Sdelphij * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3271493Sdelphij * All rights reserved. 4271493Sdelphij * 5291348Sbdrewery * Redistribution and use in source and binary forms, with or without 6271493Sdelphij * modification, are permitted provided that the following conditions 7271493Sdelphij * are met: 8271493Sdelphij * 1. Redistributions of source code must retain the above copyright 9271493Sdelphij * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci.c 241600 2012-10-16 01:10:43Z gonzo $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <machine/stdarg.h> 45 46#include <dev/mmc/bridge.h> 47#include <dev/mmc/mmcreg.h> 48#include <dev/mmc/mmcbrvar.h> 49 50#include "mmcbr_if.h" 51#include "sdhci.h" 52#include "sdhci_if.h" 53 54struct sdhci_softc; 55 56struct sdhci_softc { 57 device_t dev; /* Controller device */ 58 struct resource *irq_res; /* IRQ resource */ 59 int irq_rid; 60 void *intrhand; /* Interrupt handle */ 61 62 int num_slots; /* Number of slots on this controller */ 63 struct sdhci_slot slots[6]; 64}; 65 66static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 67 68int sdhci_debug = 0; 69TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 70SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 71 72#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 73#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 74#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 75#define RD_MULTI_4(slot, off, ptr, count) \ 76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 77 78#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 79#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 80#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 81#define WR_MULTI_4(slot, off, ptr, count) \ 82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 83 84static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 85static void sdhci_start(struct sdhci_slot *slot); 86static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 87 88static void sdhci_card_task(void *, int); 89 90/* helper routines */ 91#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93#define SDHCI_LOCK_INIT(_slot) \ 94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98 99static void 100sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 101{ 102 if (error != 0) { 103 printf("getaddr: error %d\n", error); 104 return; 105 } 106 *(bus_addr_t *)arg = segs[0].ds_addr; 107} 108 109static int 110slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 111{ 112 va_list ap; 113 int retval; 114 115 retval = printf("%s-slot%d: ", 116 device_get_nameunit(slot->bus), slot->num); 117 118 va_start(ap, fmt); 119 retval += vprintf(fmt, ap); 120 va_end(ap); 121 return (retval); 122} 123 124static void 125sdhci_dumpregs(struct sdhci_slot *slot) 126{ 127 slot_printf(slot, 128 "============== REGISTER DUMP ==============\n"); 129 130 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 131 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 132 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 133 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 134 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 135 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 136 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 137 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 138 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 139 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 140 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 141 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 142 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 143 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 144 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 145 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 146 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 147 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 148 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 149 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 150 151 slot_printf(slot, 152 "===========================================\n"); 153} 154 155static void 156sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 157{ 158 int timeout; 159 uint8_t res; 160 161 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 162 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 163 SDHCI_CARD_PRESENT)) 164 return; 165 } 166 167 /* Some controllers need this kick or reset won't work. */ 168 if ((mask & SDHCI_RESET_ALL) == 0 && 169 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 170 uint32_t clock; 171 172 /* This is to force an update */ 173 clock = slot->clock; 174 slot->clock = 0; 175 sdhci_set_clock(slot, clock); 176 } 177 178 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 179 180 if (mask & SDHCI_RESET_ALL) { 181 slot->clock = 0; 182 slot->power = 0; 183 } 184 185 /* Wait max 100 ms */ 186 timeout = 100; 187 /* Controller clears the bits when it's done */ 188 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 189 if (timeout == 0) { 190 slot_printf(slot, 191 "Reset 0x%x never completed - 0x%x.\n", 192 (int)mask, (int)res); 193 sdhci_dumpregs(slot); 194 return; 195 } 196 timeout--; 197 DELAY(1000); 198 } 199} 200 201static void 202sdhci_init(struct sdhci_slot *slot) 203{ 204 205 sdhci_reset(slot, SDHCI_RESET_ALL); 206 207 /* Enable interrupts. */ 208 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 209 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 210 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 211 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 212 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 213 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 214 SDHCI_INT_ACMD12ERR; 215 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 216 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 217} 218 219static void 220sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 221{ 222 uint32_t res; 223 uint16_t clk; 224 int timeout; 225 226 if (clock == slot->clock) 227 return; 228 slot->clock = clock; 229 230 /* Turn off the clock. */ 231 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 232 /* If no clock requested - left it so. */ 233 if (clock == 0) 234 return; 235 /* Looking for highest freq <= clock. */ 236 res = slot->max_clk; 237 for (clk = 1; clk < 256; clk <<= 1) { 238 if (res <= clock) 239 break; 240 res >>= 1; 241 } 242 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 243 clk >>= 1; 244 /* Now we have got divider, set it. */ 245 clk <<= SDHCI_DIVIDER_SHIFT; 246 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 247 /* Enable clock. */ 248 clk |= SDHCI_CLOCK_INT_EN; 249 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 250 /* Wait up to 10 ms until it stabilize. */ 251 timeout = 10; 252 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 253 & SDHCI_CLOCK_INT_STABLE)) { 254 if (timeout == 0) { 255 slot_printf(slot, 256 "Internal clock never stabilised.\n"); 257 sdhci_dumpregs(slot); 258 return; 259 } 260 timeout--; 261 DELAY(1000); 262 } 263 /* Pass clock signal to the bus. */ 264 clk |= SDHCI_CLOCK_CARD_EN; 265 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 266} 267 268static void 269sdhci_set_power(struct sdhci_slot *slot, u_char power) 270{ 271 uint8_t pwr; 272 273 if (slot->power == power) 274 return; 275 276 slot->power = power; 277 278 /* Turn off the power. */ 279 pwr = 0; 280 WR1(slot, SDHCI_POWER_CONTROL, pwr); 281 /* If power down requested - left it so. */ 282 if (power == 0) 283 return; 284 /* Set voltage. */ 285 switch (1 << power) { 286 case MMC_OCR_LOW_VOLTAGE: 287 pwr |= SDHCI_POWER_180; 288 break; 289 case MMC_OCR_290_300: 290 case MMC_OCR_300_310: 291 pwr |= SDHCI_POWER_300; 292 break; 293 case MMC_OCR_320_330: 294 case MMC_OCR_330_340: 295 pwr |= SDHCI_POWER_330; 296 break; 297 } 298 WR1(slot, SDHCI_POWER_CONTROL, pwr); 299 /* Turn on the power. */ 300 pwr |= SDHCI_POWER_ON; 301 WR1(slot, SDHCI_POWER_CONTROL, pwr); 302} 303 304static void 305sdhci_read_block_pio(struct sdhci_slot *slot) 306{ 307 uint32_t data; 308 char *buffer; 309 size_t left; 310 311 buffer = slot->curcmd->data->data; 312 buffer += slot->offset; 313 /* Transfer one block at a time. */ 314 left = min(512, slot->curcmd->data->len - slot->offset); 315 slot->offset += left; 316 317 /* If we are too fast, broken controllers return zeroes. */ 318 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 319 DELAY(10); 320 /* Handle unalligned and alligned buffer cases. */ 321 if ((intptr_t)buffer & 3) { 322 while (left > 3) { 323 data = RD4(slot, SDHCI_BUFFER); 324 buffer[0] = data; 325 buffer[1] = (data >> 8); 326 buffer[2] = (data >> 16); 327 buffer[3] = (data >> 24); 328 buffer += 4; 329 left -= 4; 330 } 331 } else { 332 RD_MULTI_4(slot, SDHCI_BUFFER, 333 (uint32_t *)buffer, left >> 2); 334 left &= 3; 335 } 336 /* Handle uneven size case. */ 337 if (left > 0) { 338 data = RD4(slot, SDHCI_BUFFER); 339 while (left > 0) { 340 *(buffer++) = data; 341 data >>= 8; 342 left--; 343 } 344 } 345} 346 347static void 348sdhci_write_block_pio(struct sdhci_slot *slot) 349{ 350 uint32_t data = 0; 351 char *buffer; 352 size_t left; 353 354 buffer = slot->curcmd->data->data; 355 buffer += slot->offset; 356 /* Transfer one block at a time. */ 357 left = min(512, slot->curcmd->data->len - slot->offset); 358 slot->offset += left; 359 360 /* Handle unalligned and alligned buffer cases. */ 361 if ((intptr_t)buffer & 3) { 362 while (left > 3) { 363 data = buffer[0] + 364 (buffer[1] << 8) + 365 (buffer[2] << 16) + 366 (buffer[3] << 24); 367 left -= 4; 368 buffer += 4; 369 WR4(slot, SDHCI_BUFFER, data); 370 } 371 } else { 372 WR_MULTI_4(slot, SDHCI_BUFFER, 373 (uint32_t *)buffer, left >> 2); 374 left &= 3; 375 } 376 /* Handle uneven size case. */ 377 if (left > 0) { 378 while (left > 0) { 379 data <<= 8; 380 data += *(buffer++); 381 left--; 382 } 383 WR4(slot, SDHCI_BUFFER, data); 384 } 385} 386 387static void 388sdhci_transfer_pio(struct sdhci_slot *slot) 389{ 390 391 /* Read as many blocks as possible. */ 392 if (slot->curcmd->data->flags & MMC_DATA_READ) { 393 while (RD4(slot, SDHCI_PRESENT_STATE) & 394 SDHCI_DATA_AVAILABLE) { 395 sdhci_read_block_pio(slot); 396 if (slot->offset >= slot->curcmd->data->len) 397 break; 398 } 399 } else { 400 while (RD4(slot, SDHCI_PRESENT_STATE) & 401 SDHCI_SPACE_AVAILABLE) { 402 sdhci_write_block_pio(slot); 403 if (slot->offset >= slot->curcmd->data->len) 404 break; 405 } 406 } 407} 408 409static void 410sdhci_card_delay(void *arg) 411{ 412 struct sdhci_slot *slot = arg; 413 414 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 415} 416 417static void 418sdhci_card_task(void *arg, int pending) 419{ 420 struct sdhci_slot *slot = arg; 421 422 SDHCI_LOCK(slot); 423 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 424 if (slot->dev == NULL) { 425 /* If card is present - attach mmc bus. */ 426 slot->dev = device_add_child(slot->bus, "mmc", -1); 427 device_set_ivars(slot->dev, slot); 428 SDHCI_UNLOCK(slot); 429 device_probe_and_attach(slot->dev); 430 } else 431 SDHCI_UNLOCK(slot); 432 } else { 433 if (slot->dev != NULL) { 434 /* If no card present - detach mmc bus. */ 435 device_t d = slot->dev; 436 slot->dev = NULL; 437 SDHCI_UNLOCK(slot); 438 device_delete_child(slot->bus, d); 439 } else 440 SDHCI_UNLOCK(slot); 441 } 442} 443 444int 445sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 446{ 447 uint32_t caps; 448 int err; 449 450 SDHCI_LOCK_INIT(slot); 451 slot->num = num; 452 slot->bus = dev; 453 454 /* Allocate DMA tag. */ 455 err = bus_dma_tag_create(bus_get_dma_tag(dev), 456 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 457 BUS_SPACE_MAXADDR, NULL, NULL, 458 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 459 BUS_DMA_ALLOCNOW, NULL, NULL, 460 &slot->dmatag); 461 if (err != 0) { 462 device_printf(dev, "Can't create DMA tag\n"); 463 SDHCI_LOCK_DESTROY(slot); 464 return (err); 465 } 466 /* Allocate DMA memory. */ 467 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 468 BUS_DMA_NOWAIT, &slot->dmamap); 469 if (err != 0) { 470 device_printf(dev, "Can't alloc DMA memory\n"); 471 SDHCI_LOCK_DESTROY(slot); 472 return (err); 473 } 474 /* Map the memory. */ 475 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 476 (void *)slot->dmamem, DMA_BLOCK_SIZE, 477 sdhci_getaddr, &slot->paddr, 0); 478 if (err != 0 || slot->paddr == 0) { 479 device_printf(dev, "Can't load DMA memory\n"); 480 SDHCI_LOCK_DESTROY(slot); 481 if(err) 482 return (err); 483 else 484 return (EFAULT); 485 } 486 487 /* Initialize slot. */ 488 sdhci_init(slot); 489 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 490 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 491 caps = RD4(slot, SDHCI_CAPABILITIES); 492 /* Calculate base clock frequency. */ 493 slot->max_clk = 494 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 495 if (slot->max_clk == 0) { 496 slot->max_clk = 50; 497 device_printf(dev, "Hardware doesn't specify base clock " 498 "frequency.\n"); 499 } 500 slot->max_clk *= 1000000; 501 /* Calculate timeout clock frequency. */ 502 slot->timeout_clk = 503 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 504 if (slot->timeout_clk == 0) { 505 device_printf(dev, "Hardware doesn't specify timeout clock " 506 "frequency.\n"); 507 } 508 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 509 slot->timeout_clk *= 1000; 510 511 slot->host.f_min = slot->max_clk / 256; 512 slot->host.f_max = slot->max_clk; 513 slot->host.host_ocr = 0; 514 if (caps & SDHCI_CAN_VDD_330) 515 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 516 if (caps & SDHCI_CAN_VDD_300) 517 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 518 if (caps & SDHCI_CAN_VDD_180) 519 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 520 if (slot->host.host_ocr == 0) { 521 device_printf(dev, "Hardware doesn't report any " 522 "support voltages.\n"); 523 } 524 slot->host.caps = MMC_CAP_4_BIT_DATA; 525 if (caps & SDHCI_CAN_DO_HISPD) 526 slot->host.caps |= MMC_CAP_HSPEED; 527 /* Decide if we have usable DMA. */ 528 if (caps & SDHCI_CAN_DO_DMA) 529 slot->opt |= SDHCI_HAVE_DMA; 530 531 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 532 slot->opt &= ~SDHCI_HAVE_DMA; 533 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 534 slot->opt |= SDHCI_HAVE_DMA; 535 536 if (bootverbose || sdhci_debug) { 537 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 538 slot->max_clk / 1000000, 539 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 540 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 541 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 542 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 543 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 544 sdhci_dumpregs(slot); 545 } 546 547 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 548 callout_init(&slot->card_callout, 1); 549 return (0); 550} 551 552void 553sdhci_start_slot(struct sdhci_slot *slot) 554{ 555 sdhci_card_task(slot, 0); 556} 557 558int 559sdhci_cleanup_slot(struct sdhci_slot *slot) 560{ 561 device_t d; 562 563 callout_drain(&slot->card_callout); 564 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 565 566 SDHCI_LOCK(slot); 567 d = slot->dev; 568 slot->dev = NULL; 569 SDHCI_UNLOCK(slot); 570 if (d != NULL) 571 device_delete_child(slot->bus, d); 572 573 SDHCI_LOCK(slot); 574 sdhci_reset(slot, SDHCI_RESET_ALL); 575 SDHCI_UNLOCK(slot); 576 bus_dmamap_unload(slot->dmatag, slot->dmamap); 577 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 578 bus_dma_tag_destroy(slot->dmatag); 579 580 SDHCI_LOCK_DESTROY(slot); 581 582 return (0); 583} 584 585int 586sdhci_generic_suspend(struct sdhci_slot *slot) 587{ 588 sdhci_reset(slot, SDHCI_RESET_ALL); 589 590 return (0); 591} 592 593int 594sdhci_generic_resume(struct sdhci_slot *slot) 595{ 596 sdhci_init(slot); 597 598 return (0); 599} 600 601int 602sdhci_generic_update_ios(device_t brdev, device_t reqdev) 603{ 604 struct sdhci_slot *slot = device_get_ivars(reqdev); 605 struct mmc_ios *ios = &slot->host.ios; 606 607 SDHCI_LOCK(slot); 608 /* Do full reset on bus power down to clear from any state. */ 609 if (ios->power_mode == power_off) { 610 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 611 sdhci_init(slot); 612 } 613 /* Configure the bus. */ 614 sdhci_set_clock(slot, ios->clock); 615 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 616 if (ios->bus_width == bus_width_4) 617 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 618 else 619 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 620 if (ios->timing == bus_timing_hs) 621 slot->hostctrl |= SDHCI_CTRL_HISPD; 622 else 623 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 624 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 625 /* Some controllers like reset after bus changes. */ 626 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 627 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 628 629 SDHCI_UNLOCK(slot); 630 return (0); 631} 632 633static void 634sdhci_set_transfer_mode(struct sdhci_slot *slot, 635 struct mmc_data *data) 636{ 637 uint16_t mode; 638 639 if (data == NULL) 640 return; 641 642 mode = SDHCI_TRNS_BLK_CNT_EN; 643 if (data->len > 512) 644 mode |= SDHCI_TRNS_MULTI; 645 if (data->flags & MMC_DATA_READ) 646 mode |= SDHCI_TRNS_READ; 647 if (slot->req->stop) 648 mode |= SDHCI_TRNS_ACMD12; 649 if (slot->flags & SDHCI_USE_DMA) 650 mode |= SDHCI_TRNS_DMA; 651 652 WR2(slot, SDHCI_TRANSFER_MODE, mode); 653} 654 655static void 656sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 657{ 658 struct mmc_request *req = slot->req; 659 int flags, timeout; 660 uint32_t mask, state; 661 662 slot->curcmd = cmd; 663 slot->cmd_done = 0; 664 665 cmd->error = MMC_ERR_NONE; 666 667 /* This flags combination is not supported by controller. */ 668 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 669 slot_printf(slot, "Unsupported response type!\n"); 670 cmd->error = MMC_ERR_FAILED; 671 slot->req = NULL; 672 slot->curcmd = NULL; 673 req->done(req); 674 return; 675 } 676 677 /* Read controller present state. */ 678 state = RD4(slot, SDHCI_PRESENT_STATE); 679 /* Do not issue command if there is no card, clock or power. 680 * Controller will not detect timeout without clock active. */ 681 if ((state & SDHCI_CARD_PRESENT) == 0 || 682 slot->power == 0 || 683 slot->clock == 0) { 684 cmd->error = MMC_ERR_FAILED; 685 slot->req = NULL; 686 slot->curcmd = NULL; 687 req->done(req); 688 return; 689 } 690 /* Always wait for free CMD bus. */ 691 mask = SDHCI_CMD_INHIBIT; 692 /* Wait for free DAT if we have data or busy signal. */ 693 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 694 mask |= SDHCI_DAT_INHIBIT; 695 /* We shouldn't wait for DAT for stop commands. */ 696 if (cmd == slot->req->stop) 697 mask &= ~SDHCI_DAT_INHIBIT; 698 /* Wait for bus no more then 10 ms. */ 699 timeout = 10; 700 while (state & mask) { 701 if (timeout == 0) { 702 slot_printf(slot, "Controller never released " 703 "inhibit bit(s).\n"); 704 sdhci_dumpregs(slot); 705 cmd->error = MMC_ERR_FAILED; 706 slot->req = NULL; 707 slot->curcmd = NULL; 708 req->done(req); 709 return; 710 } 711 timeout--; 712 DELAY(1000); 713 state = RD4(slot, SDHCI_PRESENT_STATE); 714 } 715 716 /* Prepare command flags. */ 717 if (!(cmd->flags & MMC_RSP_PRESENT)) 718 flags = SDHCI_CMD_RESP_NONE; 719 else if (cmd->flags & MMC_RSP_136) 720 flags = SDHCI_CMD_RESP_LONG; 721 else if (cmd->flags & MMC_RSP_BUSY) 722 flags = SDHCI_CMD_RESP_SHORT_BUSY; 723 else 724 flags = SDHCI_CMD_RESP_SHORT; 725 if (cmd->flags & MMC_RSP_CRC) 726 flags |= SDHCI_CMD_CRC; 727 if (cmd->flags & MMC_RSP_OPCODE) 728 flags |= SDHCI_CMD_INDEX; 729 if (cmd->data) 730 flags |= SDHCI_CMD_DATA; 731 if (cmd->opcode == MMC_STOP_TRANSMISSION) 732 flags |= SDHCI_CMD_TYPE_ABORT; 733 /* Prepare data. */ 734 sdhci_start_data(slot, cmd->data); 735 /* 736 * Interrupt aggregation: To reduce total number of interrupts 737 * group response interrupt with data interrupt when possible. 738 * If there going to be data interrupt, mask response one. 739 */ 740 if (slot->data_done == 0) { 741 WR4(slot, SDHCI_SIGNAL_ENABLE, 742 slot->intmask &= ~SDHCI_INT_RESPONSE); 743 } 744 /* Set command argument. */ 745 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 746 /* Set data transfer mode. */ 747 sdhci_set_transfer_mode(slot, cmd->data); 748 /* Start command. */ 749 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 750} 751 752static void 753sdhci_finish_command(struct sdhci_slot *slot) 754{ 755 int i; 756 757 slot->cmd_done = 1; 758 /* Interrupt aggregation: Restore command interrupt. 759 * Main restore point for the case when command interrupt 760 * happened first. */ 761 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 762 /* In case of error - reset host and return. */ 763 if (slot->curcmd->error) { 764 sdhci_reset(slot, SDHCI_RESET_CMD); 765 sdhci_reset(slot, SDHCI_RESET_DATA); 766 sdhci_start(slot); 767 return; 768 } 769 /* If command has response - fetch it. */ 770 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 771 if (slot->curcmd->flags & MMC_RSP_136) { 772 /* CRC is stripped so we need one byte shift. */ 773 uint8_t extra = 0; 774 for (i = 0; i < 4; i++) { 775 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 776 slot->curcmd->resp[3 - i] = (val << 8) + extra; 777 extra = val >> 24; 778 } 779 } else 780 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 781 } 782 /* If data ready - finish. */ 783 if (slot->data_done) 784 sdhci_start(slot); 785} 786 787static void 788sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 789{ 790 uint32_t target_timeout, current_timeout; 791 uint8_t div; 792 793 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 794 slot->data_done = 1; 795 return; 796 } 797 798 slot->data_done = 0; 799 800 /* Calculate and set data timeout.*/ 801 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 802 target_timeout = 1000000; 803 div = 0; 804 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 805 while (current_timeout < target_timeout) { 806 div++; 807 current_timeout <<= 1; 808 if (div >= 0xF) 809 break; 810 } 811 /* Compensate for an off-by-one error in the CaFe chip.*/ 812 if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 813 div++; 814 if (div >= 0xF) { 815 slot_printf(slot, "Timeout too large!\n"); 816 div = 0xE; 817 } 818 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 819 820 if (data == NULL) 821 return; 822 823 /* Use DMA if possible. */ 824 if ((slot->opt & SDHCI_HAVE_DMA)) 825 slot->flags |= SDHCI_USE_DMA; 826 /* If data is small, broken DMA may return zeroes instead of data, */ 827 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 828 (data->len <= 512)) 829 slot->flags &= ~SDHCI_USE_DMA; 830 /* Some controllers require even block sizes. */ 831 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 832 ((data->len) & 0x3)) 833 slot->flags &= ~SDHCI_USE_DMA; 834 /* Load DMA buffer. */ 835 if (slot->flags & SDHCI_USE_DMA) { 836 if (data->flags & MMC_DATA_READ) 837 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 838 else { 839 memcpy(slot->dmamem, data->data, 840 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 841 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 842 } 843 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 844 /* Interrupt aggregation: Mask border interrupt 845 * for the last page and unmask else. */ 846 if (data->len == DMA_BLOCK_SIZE) 847 slot->intmask &= ~SDHCI_INT_DMA_END; 848 else 849 slot->intmask |= SDHCI_INT_DMA_END; 850 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 851 } 852 /* Current data offset for both PIO and DMA. */ 853 slot->offset = 0; 854 /* Set block size and request IRQ on 4K border. */ 855 WR2(slot, SDHCI_BLOCK_SIZE, 856 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 857 /* Set block count. */ 858 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 859} 860 861static void 862sdhci_finish_data(struct sdhci_slot *slot) 863{ 864 struct mmc_data *data = slot->curcmd->data; 865 866 slot->data_done = 1; 867 /* Interrupt aggregation: Restore command interrupt. 868 * Auxillary restore point for the case when data interrupt 869 * happened first. */ 870 if (!slot->cmd_done) { 871 WR4(slot, SDHCI_SIGNAL_ENABLE, 872 slot->intmask |= SDHCI_INT_RESPONSE); 873 } 874 /* Unload rest of data from DMA buffer. */ 875 if (slot->flags & SDHCI_USE_DMA) { 876 if (data->flags & MMC_DATA_READ) { 877 size_t left = data->len - slot->offset; 878 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 879 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 880 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 881 } else 882 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 883 } 884 /* If there was error - reset the host. */ 885 if (slot->curcmd->error) { 886 sdhci_reset(slot, SDHCI_RESET_CMD); 887 sdhci_reset(slot, SDHCI_RESET_DATA); 888 sdhci_start(slot); 889 return; 890 } 891 /* If we already have command response - finish. */ 892 if (slot->cmd_done) 893 sdhci_start(slot); 894} 895 896static void 897sdhci_start(struct sdhci_slot *slot) 898{ 899 struct mmc_request *req; 900 901 req = slot->req; 902 if (req == NULL) 903 return; 904 905 if (!(slot->flags & CMD_STARTED)) { 906 slot->flags |= CMD_STARTED; 907 sdhci_start_command(slot, req->cmd); 908 return; 909 } 910/* We don't need this until using Auto-CMD12 feature 911 if (!(slot->flags & STOP_STARTED) && req->stop) { 912 slot->flags |= STOP_STARTED; 913 sdhci_start_command(slot, req->stop); 914 return; 915 } 916*/ 917 if (sdhci_debug > 1) 918 slot_printf(slot, "result: %d\n", req->cmd->error); 919 if (!req->cmd->error && 920 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 921 sdhci_reset(slot, SDHCI_RESET_CMD); 922 sdhci_reset(slot, SDHCI_RESET_DATA); 923 } 924 925 /* We must be done -- bad idea to do this while locked? */ 926 slot->req = NULL; 927 slot->curcmd = NULL; 928 req->done(req); 929} 930 931int 932sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 933{ 934 struct sdhci_slot *slot = device_get_ivars(reqdev); 935 936 SDHCI_LOCK(slot); 937 if (slot->req != NULL) { 938 SDHCI_UNLOCK(slot); 939 return (EBUSY); 940 } 941 if (sdhci_debug > 1) { 942 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 943 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 944 (req->cmd->data)?(u_int)req->cmd->data->len:0, 945 (req->cmd->data)?req->cmd->data->flags:0); 946 } 947 slot->req = req; 948 slot->flags = 0; 949 sdhci_start(slot); 950 SDHCI_UNLOCK(slot); 951 if (dumping) { 952 while (slot->req != NULL) { 953 sdhci_generic_intr(slot); 954 DELAY(10); 955 } 956 } 957 return (0); 958} 959 960int 961sdhci_generic_get_ro(device_t brdev, device_t reqdev) 962{ 963 struct sdhci_slot *slot = device_get_ivars(reqdev); 964 uint32_t val; 965 966 SDHCI_LOCK(slot); 967 val = RD4(slot, SDHCI_PRESENT_STATE); 968 SDHCI_UNLOCK(slot); 969 return (!(val & SDHCI_WRITE_PROTECT)); 970} 971 972int 973sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 974{ 975 struct sdhci_slot *slot = device_get_ivars(reqdev); 976 int err = 0; 977 978 SDHCI_LOCK(slot); 979 while (slot->bus_busy) 980 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 981 slot->bus_busy++; 982 /* Activate led. */ 983 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 984 SDHCI_UNLOCK(slot); 985 return (err); 986} 987 988int 989sdhci_generic_release_host(device_t brdev, device_t reqdev) 990{ 991 struct sdhci_slot *slot = device_get_ivars(reqdev); 992 993 SDHCI_LOCK(slot); 994 /* Deactivate led. */ 995 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 996 slot->bus_busy--; 997 SDHCI_UNLOCK(slot); 998 wakeup(slot); 999 return (0); 1000} 1001 1002static void 1003sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1004{ 1005 1006 if (!slot->curcmd) { 1007 slot_printf(slot, "Got command interrupt 0x%08x, but " 1008 "there is no active command.\n", intmask); 1009 sdhci_dumpregs(slot); 1010 return; 1011 } 1012 if (intmask & SDHCI_INT_TIMEOUT) 1013 slot->curcmd->error = MMC_ERR_TIMEOUT; 1014 else if (intmask & SDHCI_INT_CRC) 1015 slot->curcmd->error = MMC_ERR_BADCRC; 1016 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1017 slot->curcmd->error = MMC_ERR_FIFO; 1018 1019 sdhci_finish_command(slot); 1020} 1021 1022static void 1023sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1024{ 1025 1026 if (!slot->curcmd) { 1027 slot_printf(slot, "Got data interrupt 0x%08x, but " 1028 "there is no active command.\n", intmask); 1029 sdhci_dumpregs(slot); 1030 return; 1031 } 1032 if (slot->curcmd->data == NULL && 1033 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1034 slot_printf(slot, "Got data interrupt 0x%08x, but " 1035 "there is no active data operation.\n", 1036 intmask); 1037 sdhci_dumpregs(slot); 1038 return; 1039 } 1040 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1041 slot->curcmd->error = MMC_ERR_TIMEOUT; 1042 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1043 slot->curcmd->error = MMC_ERR_BADCRC; 1044 if (slot->curcmd->data == NULL && 1045 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1046 SDHCI_INT_DMA_END))) { 1047 slot_printf(slot, "Got data interrupt 0x%08x, but " 1048 "there is busy-only command.\n", intmask); 1049 sdhci_dumpregs(slot); 1050 slot->curcmd->error = MMC_ERR_INVALID; 1051 } 1052 if (slot->curcmd->error) { 1053 /* No need to continue after any error. */ 1054 sdhci_finish_data(slot); 1055 return; 1056 } 1057 1058 /* Handle PIO interrupt. */ 1059 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1060 sdhci_transfer_pio(slot); 1061 /* Handle DMA border. */ 1062 if (intmask & SDHCI_INT_DMA_END) { 1063 struct mmc_data *data = slot->curcmd->data; 1064 size_t left; 1065 1066 /* Unload DMA buffer... */ 1067 left = data->len - slot->offset; 1068 if (data->flags & MMC_DATA_READ) { 1069 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1070 BUS_DMASYNC_POSTREAD); 1071 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1072 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1073 } else { 1074 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1075 BUS_DMASYNC_POSTWRITE); 1076 } 1077 /* ... and reload it again. */ 1078 slot->offset += DMA_BLOCK_SIZE; 1079 left = data->len - slot->offset; 1080 if (data->flags & MMC_DATA_READ) { 1081 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1082 BUS_DMASYNC_PREREAD); 1083 } else { 1084 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1085 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1086 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1087 BUS_DMASYNC_PREWRITE); 1088 } 1089 /* Interrupt aggregation: Mask border interrupt 1090 * for the last page. */ 1091 if (left == DMA_BLOCK_SIZE) { 1092 slot->intmask &= ~SDHCI_INT_DMA_END; 1093 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1094 } 1095 /* Restart DMA. */ 1096 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1097 } 1098 /* We have got all data. */ 1099 if (intmask & SDHCI_INT_DATA_END) 1100 sdhci_finish_data(slot); 1101} 1102 1103static void 1104sdhci_acmd_irq(struct sdhci_slot *slot) 1105{ 1106 uint16_t err; 1107 1108 err = RD4(slot, SDHCI_ACMD12_ERR); 1109 if (!slot->curcmd) { 1110 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1111 "there is no active command.\n", err); 1112 sdhci_dumpregs(slot); 1113 return; 1114 } 1115 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1116 sdhci_reset(slot, SDHCI_RESET_CMD); 1117} 1118 1119void 1120sdhci_generic_intr(struct sdhci_slot *slot) 1121{ 1122 uint32_t intmask; 1123 1124 SDHCI_LOCK(slot); 1125 /* Read slot interrupt status. */ 1126 intmask = RD4(slot, SDHCI_INT_STATUS); 1127 if (intmask == 0 || intmask == 0xffffffff) { 1128 SDHCI_UNLOCK(slot); 1129 return; 1130 } 1131 if (sdhci_debug > 2) 1132 slot_printf(slot, "Interrupt %#x\n", intmask); 1133 1134 /* Handle card presence interrupts. */ 1135 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1136 WR4(slot, SDHCI_INT_STATUS, intmask & 1137 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1138 1139 if (intmask & SDHCI_INT_CARD_REMOVE) { 1140 if (bootverbose || sdhci_debug) 1141 slot_printf(slot, "Card removed\n"); 1142 callout_stop(&slot->card_callout); 1143 taskqueue_enqueue(taskqueue_swi_giant, 1144 &slot->card_task); 1145 } 1146 if (intmask & SDHCI_INT_CARD_INSERT) { 1147 if (bootverbose || sdhci_debug) 1148 slot_printf(slot, "Card inserted\n"); 1149 callout_reset(&slot->card_callout, hz / 2, 1150 sdhci_card_delay, slot); 1151 } 1152 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1153 } 1154 /* Handle command interrupts. */ 1155 if (intmask & SDHCI_INT_CMD_MASK) { 1156 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1157 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1158 } 1159 /* Handle data interrupts. */ 1160 if (intmask & SDHCI_INT_DATA_MASK) { 1161 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1162 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1163 } 1164 /* Handle AutoCMD12 error interrupt. */ 1165 if (intmask & SDHCI_INT_ACMD12ERR) { 1166 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1167 sdhci_acmd_irq(slot); 1168 } 1169 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1170 intmask &= ~SDHCI_INT_ACMD12ERR; 1171 intmask &= ~SDHCI_INT_ERROR; 1172 /* Handle bus power interrupt. */ 1173 if (intmask & SDHCI_INT_BUS_POWER) { 1174 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1175 slot_printf(slot, 1176 "Card is consuming too much power!\n"); 1177 intmask &= ~SDHCI_INT_BUS_POWER; 1178 } 1179 /* The rest is unknown. */ 1180 if (intmask) { 1181 WR4(slot, SDHCI_INT_STATUS, intmask); 1182 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1183 intmask); 1184 sdhci_dumpregs(slot); 1185 } 1186 1187 SDHCI_UNLOCK(slot); 1188} 1189 1190int 1191sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1192{ 1193 struct sdhci_slot *slot = device_get_ivars(child); 1194 1195 switch (which) { 1196 default: 1197 return (EINVAL); 1198 case MMCBR_IVAR_BUS_MODE: 1199 *result = slot->host.ios.bus_mode; 1200 break; 1201 case MMCBR_IVAR_BUS_WIDTH: 1202 *result = slot->host.ios.bus_width; 1203 break; 1204 case MMCBR_IVAR_CHIP_SELECT: 1205 *result = slot->host.ios.chip_select; 1206 break; 1207 case MMCBR_IVAR_CLOCK: 1208 *result = slot->host.ios.clock; 1209 break; 1210 case MMCBR_IVAR_F_MIN: 1211 *result = slot->host.f_min; 1212 break; 1213 case MMCBR_IVAR_F_MAX: 1214 *result = slot->host.f_max; 1215 break; 1216 case MMCBR_IVAR_HOST_OCR: 1217 *result = slot->host.host_ocr; 1218 break; 1219 case MMCBR_IVAR_MODE: 1220 *result = slot->host.mode; 1221 break; 1222 case MMCBR_IVAR_OCR: 1223 *result = slot->host.ocr; 1224 break; 1225 case MMCBR_IVAR_POWER_MODE: 1226 *result = slot->host.ios.power_mode; 1227 break; 1228 case MMCBR_IVAR_VDD: 1229 *result = slot->host.ios.vdd; 1230 break; 1231 case MMCBR_IVAR_CAPS: 1232 *result = slot->host.caps; 1233 break; 1234 case MMCBR_IVAR_TIMING: 1235 *result = slot->host.ios.timing; 1236 break; 1237 case MMCBR_IVAR_MAX_DATA: 1238 *result = 65535; 1239 break; 1240 } 1241 return (0); 1242} 1243 1244int 1245sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1246{ 1247 struct sdhci_slot *slot = device_get_ivars(child); 1248 1249 switch (which) { 1250 default: 1251 return (EINVAL); 1252 case MMCBR_IVAR_BUS_MODE: 1253 slot->host.ios.bus_mode = value; 1254 break; 1255 case MMCBR_IVAR_BUS_WIDTH: 1256 slot->host.ios.bus_width = value; 1257 break; 1258 case MMCBR_IVAR_CHIP_SELECT: 1259 slot->host.ios.chip_select = value; 1260 break; 1261 case MMCBR_IVAR_CLOCK: 1262 if (value > 0) { 1263 uint32_t clock = slot->max_clk; 1264 int i; 1265 1266 for (i = 0; i < 8; i++) { 1267 if (clock <= value) 1268 break; 1269 clock >>= 1; 1270 } 1271 slot->host.ios.clock = clock; 1272 } else 1273 slot->host.ios.clock = 0; 1274 break; 1275 case MMCBR_IVAR_MODE: 1276 slot->host.mode = value; 1277 break; 1278 case MMCBR_IVAR_OCR: 1279 slot->host.ocr = value; 1280 break; 1281 case MMCBR_IVAR_POWER_MODE: 1282 slot->host.ios.power_mode = value; 1283 break; 1284 case MMCBR_IVAR_VDD: 1285 slot->host.ios.vdd = value; 1286 break; 1287 case MMCBR_IVAR_TIMING: 1288 slot->host.ios.timing = value; 1289 break; 1290 case MMCBR_IVAR_CAPS: 1291 case MMCBR_IVAR_HOST_OCR: 1292 case MMCBR_IVAR_F_MIN: 1293 case MMCBR_IVAR_F_MAX: 1294 case MMCBR_IVAR_MAX_DATA: 1295 return (EINVAL); 1296 } 1297 return (0); 1298} 1299 1300MODULE_VERSION(sdhci, 1); 1301