sahw.c revision 285809
1285809Sscottl/******************************************************************************* 2285809Sscottl*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3285809Sscottl* 4285809Sscottl*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5285809Sscottl*that the following conditions are met: 6285809Sscottl*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7285809Sscottl*following disclaimer. 8285809Sscottl*2. Redistributions in binary form must reproduce the above copyright notice, 9285809Sscottl*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10285809Sscottl*with the distribution. 11285809Sscottl* 12285809Sscottl*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13285809Sscottl*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14285809Sscottl*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15285809Sscottl*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16285809Sscottl*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17285809Sscottl*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18285809Sscottl*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19285809Sscottl*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20285809Sscottl 21285809Sscottl********************************************************************************/ 22285809Sscottl/*******************************************************************************/ 23285809Sscottl/*! \file sahw.c 24285809Sscottl * \brief The file implements the functions for reset and shutdown 25285809Sscottl */ 26285809Sscottl/******************************************************************************/ 27285809Sscottl#include <sys/cdefs.h> 28285809Sscottl__FBSDID("$FreeBSD$"); 29285809Sscottl#include <dev/pms/config.h> 30285809Sscottl 31285809Sscottl#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 32285809Sscottl#ifdef SA_ENABLE_HDA_FUNCTIONS 33285809Sscottl#ifndef SA_EXCLUDE_FW_IMG 34285809Sscottl/* 35285809Sscottl#include "istrimg.h" 36285809Sscottl#include "ilaimg.h" 37285809Sscottl#include "aap1img.h" 38285809Sscottl#include "iopimg.h" 39285809Sscottl*/ 40285809Sscottl#endif 41285809Sscottl#endif 42285809Sscottl#if defined(SALLSDK_DEBUG) 43285809Sscottlextern bit32 gLLSoftResetCounter; 44285809Sscottl#endif 45285809Sscottl 46285809Sscottl#ifdef SA_ENABLE_TRACE_FUNCTIONS 47285809Sscottl#ifdef siTraceFileID 48285809Sscottl#undef siTraceFileID 49285809Sscottl#endif 50285809Sscottl#define siTraceFileID 'E' 51285809Sscottl#endif 52285809Sscottl 53285809Sscottl 54285809Sscottlbit32 gWait_3 = 3; 55285809Sscottlbit32 gWait_2 = 2; 56285809Sscottl 57285809Sscottlbit32 gWaitmSec = 0; 58285809Sscottl 59285809Sscottl 60285809Sscottl 61285809SscottlLOCAL bit32 si_V_SoftReset(agsaRoot_t *agRoot, bit32 signature); 62285809Sscottl 63285809Sscottl 64285809SscottlLOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot); 65285809Sscottl 66285809Sscottl#ifdef SA_ENABLE_HDA_FUNCTIONS 67285809SscottlLOCAL void siPciMemCpy(agsaRoot_t *agRoot, bit32 dstoffset, void *src, 68285809Sscottl bit32 DWcount, bit32 busBaseNumber); 69285809Sscottl 70285809SscottlLOCAL bit32 siBar4Cpy(agsaRoot_t *agRoot, bit32 offset, bit8 *parray, bit32 array_size); 71285809Sscottl#endif 72285809Sscottl 73285809Sscottl/******************************************************************************/ 74285809Sscottl/*! \brief Function to reset the Hardware 75285809Sscottl * 76285809Sscottl * The saHwReset() function is called to reset the SAS/SATA HW controller 77285809Sscottl * All outstanding I/Os are explicitly aborted. 78285809Sscottl * This API need to access before saInitialize() so checking saRoot is needed 79285809Sscottl * 80285809Sscottl * \param agRoot Handles for this instance of SAS/SATA hardware 81285809Sscottl * \param resetType The reset type 82285809Sscottl * \param resetParm The paramter passed for reset operation 83285809Sscottl * 84285809Sscottl * \return -void- 85285809Sscottl */ 86285809Sscottl/*******************************************************************************/ 87285809SscottlGLOBAL void saHwReset( 88285809Sscottl agsaRoot_t *agRoot, 89285809Sscottl bit32 resetType, 90285809Sscottl bit32 resetParm 91285809Sscottl ) 92285809Sscottl{ 93285809Sscottl agsaLLRoot_t *saRoot = agNULL; 94285809Sscottl bit32 ret = AGSA_RC_SUCCESS; 95285809Sscottl bit32 value; 96285809Sscottl bit32 sysIntsActive = agFALSE; 97285809Sscottl#if defined(SALLSDK_DEBUG) 98285809Sscottl bit32 value1; 99285809Sscottl agsaControllerStatus_t controllerStatus; 100285809Sscottl agsaFatalErrorInfo_t fatal_error; 101285809Sscottl#endif 102285809Sscottl 103285809Sscottl#ifdef SOFT_RESET_TEST 104285809Sscottl DbgPrint("Reset Start\n"); 105285809Sscottl#endif 106285809Sscottl 107285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD, "5a"); 108285809Sscottl 109285809Sscottl /* sanity check */ 110285809Sscottl SA_ASSERT( (agNULL != agRoot), ""); 111285809Sscottl if (agNULL != agRoot) 112285809Sscottl { 113285809Sscottl if (agNULL != agRoot->sdkData) 114285809Sscottl { 115285809Sscottl saRoot = (agsaLLRoot_t*) agRoot->sdkData; 116285809Sscottl sysIntsActive = saRoot->sysIntsActive; 117285809Sscottl if(sysIntsActive) 118285809Sscottl { 119285809Sscottl saSystemInterruptsActive(agRoot,agFALSE); 120285809Sscottl } 121285809Sscottl } 122285809Sscottl } 123285809Sscottl else 124285809Sscottl { 125285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5a"); 126285809Sscottl return; 127285809Sscottl } 128285809Sscottl 129285809Sscottl 130285809Sscottl#if defined(SALLSDK_DEBUG) 131285809Sscottl { 132285809Sscottl if (agNULL != agRoot->sdkData) 133285809Sscottl { 134285809Sscottl /* check fatal errors */ 135285809Sscottl value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 136285809Sscottl value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 137285809Sscottl /* check AAP error */ 138285809Sscottl if( smIS_SPC(agRoot) ) 139285809Sscottl { 140285809Sscottl value &= SCRATCH_PAD_STATE_MASK; 141285809Sscottl value1 &= SCRATCH_PAD_STATE_MASK; 142285809Sscottl 143285809Sscottl if ((SCRATCH_PAD1_ERR == value) || (SCRATCH_PAD2_ERR == value1)) 144285809Sscottl { 145285809Sscottl 146285809Sscottl si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 147285809Sscottl /* read detail fatal errors */ 148285809Sscottl value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 149285809Sscottl fatal_error.errorInfo0 = value; 150285809Sscottl SA_DBG1(("saHwReset: ScratchPad0 AAP error code 0x%x\n", value)); 151285809Sscottl value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 152285809Sscottl fatal_error.errorInfo1 = value; 153285809Sscottl /* AAP error state */ 154285809Sscottl SA_DBG1(("saHwReset: AAP error state and error code 0x%x\n", value)); 155285809Sscottl value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 156285809Sscottl fatal_error.errorInfo2 = value; 157285809Sscottl /* IOP error state */ 158285809Sscottl SA_DBG1(("saHwReset: IOP error state and error code 0x%x\n", value)); 159285809Sscottl value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 160285809Sscottl SA_DBG1(("saHwReset: ScratchPad3 IOP error code 0x%x\n", value)); 161285809Sscottl fatal_error.errorInfo3 = value; 162285809Sscottl if (agNULL != saRoot) 163285809Sscottl { 164285809Sscottl fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 165285809Sscottl fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 166285809Sscottl fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 167285809Sscottl fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 168285809Sscottl fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 169285809Sscottl fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 170285809Sscottl } 171285809Sscottl 172285809Sscottl /* Call Back with error */ 173285809Sscottl SA_DBG1(("saHwReset: OSSA_HW_EVENT_MALFUNCTION SPC SP1 0x%x\n", value1)); 174285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); 175285809Sscottl } 176285809Sscottl } 177285809Sscottl else 178285809Sscottl { 179285809Sscottl if( ( (value & SCRATCH_PAD1_V_BOOTLDR_ERROR) == SCRATCH_PAD1_V_BOOTLDR_ERROR)) 180285809Sscottl { 181285809Sscottl SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_BOOTLDR_ERROR 0x%x\n", value)); 182285809Sscottl } 183285809Sscottl if(SCRATCH_PAD1_V_ERROR_STATE(value)) 184285809Sscottl { 185285809Sscottl SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_ERROR_STATE 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE(value) )); 186285809Sscottl } 187285809Sscottl if( (value & SCRATCH_PAD1_V_READY) == SCRATCH_PAD1_V_READY ) 188285809Sscottl { 189285809Sscottl SA_DBG1(("saHwReset: ScratchPad1 SCRATCH_PAD1_V_READY 0x%x\n", value)); 190285809Sscottl } 191285809Sscottl } 192285809Sscottl saGetControllerStatus(agRoot, &controllerStatus); 193285809Sscottl if (agNULL != saRoot) 194285809Sscottl { 195285809Sscottl /* display all pending Ios */ 196285809Sscottl siDumpActiveIORequests(agRoot, saRoot->swConfig.maxActiveIOs); 197285809Sscottl } 198285809Sscottl } 199285809Sscottl } 200285809Sscottl#endif /* SALLSDK_DEBUG */ 201285809Sscottl 202285809Sscottl /* Check the resetType */ 203285809Sscottl switch (resetType) 204285809Sscottl { 205285809Sscottl /* Reset the whole chip */ 206285809Sscottl case AGSA_CHIP_RESET: 207285809Sscottl { 208285809Sscottl /* callback with RESET_START */ 209285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 210285809Sscottl 211285809Sscottl if (agNULL != agRoot->sdkData && agNULL != saRoot) 212285809Sscottl { 213285809Sscottl /* Set chip status */ 214285809Sscottl saRoot->chipStatus |= CHIP_RESETTING; 215285809Sscottl 216285809Sscottl /* Disable all interrupt */ 217285809Sscottl saSystemInterruptsActive(agRoot,agFALSE); 218285809Sscottl } 219285809Sscottl 220285809Sscottl /* do chip reset */ 221285809Sscottl siChipReset(agRoot); 222285809Sscottl 223285809Sscottl if (agNULL != saRoot) 224285809Sscottl { 225285809Sscottl /* clear up the internal resource */ 226285809Sscottl siInitResources(agRoot, 227285809Sscottl &saRoot->memoryAllocated, 228285809Sscottl &saRoot->hwConfig, 229285809Sscottl &saRoot->swConfig, 230285809Sscottl saRoot->usecsPerTick); 231285809Sscottl } 232285809Sscottl 233285809Sscottl /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ 234285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 235285809Sscottl 236285809Sscottl if (agNULL != saRoot) 237285809Sscottl { 238285809Sscottl /* mask off reset FW status */ 239285809Sscottl saRoot->chipStatus &= ~CHIP_RESETTING; 240285809Sscottl } 241285809Sscottl break; 242285809Sscottl } 243285809Sscottl case AGSA_SOFT_RESET: 244285809Sscottl { 245285809Sscottl 246285809Sscottl if( smIS_SPCV(agRoot) ) 247285809Sscottl { 248285809Sscottl SA_DBG1(("saHwReset: AGSA_SOFT_RESET chip type V %d\n",smIS_SPCV(agRoot) )); 249285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 250285809Sscottl if (agNULL != saRoot) 251285809Sscottl { 252285809Sscottl saRoot->ResetStartTick = saRoot->timeTick; 253285809Sscottl saCountActiveIORequests( agRoot); 254285809Sscottl } //delray end 255285809Sscottl 256285809Sscottl ret = siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE ); 257285809Sscottl 258285809Sscottl if(agNULL !=saRoot) 259285809Sscottl { 260285809Sscottl /* clear up the internal resource */ 261285809Sscottl siInitResources(agRoot, 262285809Sscottl &saRoot->memoryAllocated, 263285809Sscottl &saRoot->hwConfig, 264285809Sscottl &saRoot->swConfig, 265285809Sscottl saRoot->usecsPerTick); 266285809Sscottl } 267285809Sscottl 268285809Sscottl if (AGSA_RC_SUCCESS == ret) 269285809Sscottl { 270285809Sscottl /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ 271285809Sscottl SA_DBG1(("saHwReset: siChipResetV AGSA_RC_SUCCESS\n" )); 272285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 273285809Sscottl } 274285809Sscottl else 275285809Sscottl { 276285809Sscottl /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */ 277285809Sscottl SA_DBG1(("saHwReset: siChipResetV not AGSA_RC_SUCCESS (0x%x)\n" ,ret)); 278285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_FAILURE << SHIFT8, agNULL, agNULL); 279285809Sscottl if (agNULL != saRoot) 280285809Sscottl { 281285809Sscottl saRoot->ResetFailed = agTRUE; 282285809Sscottl SA_DBG1(("saHwReset: siChipResetV saRoot->ResetFailed ret (0x%x)\n" ,ret)); 283285809Sscottl } 284285809Sscottl 285285809Sscottl } 286285809Sscottl break; 287285809Sscottl } 288285809Sscottl else 289285809Sscottl { 290285809Sscottl if (agNULL != saRoot) 291285809Sscottl { 292285809Sscottl /* get register dump from GSM and save it to LL local memory */ 293285809Sscottl siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump0[0], 294285809Sscottl REG_DUMP_NUM0, 0, saRoot->mainConfigTable.FatalErrorDumpLength0); 295285809Sscottl siGetRegisterDumpGSM(agRoot, (void *)&saRoot->registerDump1[0], 296285809Sscottl REG_DUMP_NUM1, 0, saRoot->mainConfigTable.FatalErrorDumpLength1); 297285809Sscottl } 298285809Sscottl 299285809Sscottl /* callback with RESET_START */ 300285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_START, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 301285809Sscottl 302285809Sscottl if (agNULL != agRoot->sdkData && agNULL != saRoot) 303285809Sscottl { 304285809Sscottl /* Set chip status */ 305285809Sscottl saRoot->chipStatus |= CHIP_RESET_FW; 306285809Sscottl 307285809Sscottl /* Disable all interrupt */ 308285809Sscottl saSystemInterruptsActive(agRoot,agFALSE); 309285809Sscottl saCountActiveIORequests( agRoot); //delray start 310285809Sscottl 311285809Sscottl } 312285809Sscottl 313285809Sscottl /* check HDA mode */ 314285809Sscottl value = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 315285809Sscottl 316285809Sscottl if (value == BOOTTLOADERHDA_IDLE) 317285809Sscottl { 318285809Sscottl /* HDA mode */ 319285809Sscottl SA_DBG1(("saHwReset: HDA mode, value = 0x%x\n", value)); 320285809Sscottl ret = AGSA_RC_HDA_NO_FW_RUNNING; 321285809Sscottl } 322285809Sscottl else 323285809Sscottl { 324285809Sscottl /* do Soft Reset */ 325285809Sscottl ret = siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 326285809Sscottl } 327285809Sscottl if(agNULL !=saRoot) 328285809Sscottl { 329285809Sscottl /* clear up the internal resource */ 330285809Sscottl siInitResources(agRoot, 331285809Sscottl &saRoot->memoryAllocated, 332285809Sscottl &saRoot->hwConfig, 333285809Sscottl &saRoot->swConfig, 334285809Sscottl saRoot->usecsPerTick); 335285809Sscottl } 336285809Sscottl if (AGSA_RC_SUCCESS == ret) 337285809Sscottl { 338285809Sscottl /* callback with CHIP_RESET_COMPLETE with OSSA_SUCCESS */ 339285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 340285809Sscottl } 341285809Sscottl else if (AGSA_RC_HDA_NO_FW_RUNNING == ret) 342285809Sscottl { 343285809Sscottl /* callback with CHIP_RESET_COMPLETE with OSSA_CHIP_FAILED */ 344285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, OSSA_SUCCESS << SHIFT8, agNULL, agNULL); 345285809Sscottl } 346285809Sscottl else 347285809Sscottl { 348285809Sscottl /* callback with CHIP_RESET_COMPLETE with OSSA_FAILURE */ 349285809Sscottl ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_RESET_COMPLETE, (OSSA_FAILURE << SHIFT8), agNULL, agNULL); 350285809Sscottl } 351285809Sscottl 352285809Sscottl if (agNULL != saRoot) 353285809Sscottl { 354285809Sscottl /* mask off reset FW status */ 355285809Sscottl saRoot->chipStatus &= ~CHIP_RESET_FW; 356285809Sscottl } 357285809Sscottl break; 358285809Sscottl } 359285809Sscottl } 360285809Sscottl /* Unsupported type */ 361285809Sscottl default: 362285809Sscottl { 363285809Sscottl SA_DBG1(("saHwReset: Unsupported reset type %X\n",resetType)); 364285809Sscottl break; 365285809Sscottl } 366285809Sscottl } 367285809Sscottl 368285809Sscottl if (agNULL != saRoot) 369285809Sscottl { 370285809Sscottl if(sysIntsActive && ret == AGSA_RC_SUCCESS) 371285809Sscottl { 372285809Sscottl saSystemInterruptsActive(agRoot,agTRUE); 373285809Sscottl } 374285809Sscottl 375285809Sscottl saCountActiveIORequests( agRoot); 376285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5a"); 377285809Sscottl } 378285809Sscottl 379285809Sscottl return; 380285809Sscottl} 381285809Sscottl 382285809Sscottl/******************************************************************************/ 383285809Sscottl/*! \brief Function to shutdown the Hardware 384285809Sscottl * 385285809Sscottl * The saHwShutdown() function is called to discontinue the use of the SAS/SATA 386285809Sscottl * hardware. Upon return, the SASA/SAT hardware instance does not generate any 387285809Sscottl * interrupts or any other bus accesses. All LL Layer hardware host resources 388285809Sscottl * (i.e. both cached and noncached memory) are no longer owned by the LL Layer. 389285809Sscottl * 390285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 391285809Sscottl * 392285809Sscottl * \return -void- 393285809Sscottl */ 394285809Sscottl/*******************************************************************************/ 395285809SscottlGLOBAL void saHwShutdown( 396285809Sscottl agsaRoot_t *agRoot 397285809Sscottl ) 398285809Sscottl{ 399285809Sscottl agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 400285809Sscottl bit32 spad0 = 0; 401285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"5b"); 402285809Sscottl 403285809Sscottl /* sanity check */ 404285809Sscottl SA_ASSERT( (agNULL != agRoot), ""); 405285809Sscottl SA_DBG1(("saHwShutdown: Shutting down .....\n")); 406285809Sscottl 407285809Sscottl if (agRoot->sdkData) 408285809Sscottl { 409285809Sscottl 410285809Sscottl spad0 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 411285809Sscottl 412285809Sscottl if(0xFFFFFFFF == spad0) 413285809Sscottl { 414285809Sscottl SA_ASSERT(0xFFFFFFFF == spad0, "saHwShutdown Chip PCI dead"); 415285809Sscottl 416285809Sscottl SA_DBG1(("saHwShutdown: Chip PCI dead SCRATCH_PAD0 0x%x\n", spad0)); 417285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5b"); 418285809Sscottl return; 419285809Sscottl } 420285809Sscottl 421285809Sscottl 422285809Sscottl#if defined(SALLSDK_DEBUG) 423285809Sscottl SA_DBG1(("saHwShutdown: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0))); 424285809Sscottl SA_DBG1(("saHwShutdown: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1))); 425285809Sscottl SA_DBG1(("saHwShutdown: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2))); 426285809Sscottl SA_DBG1(("saHwShutdown: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3))); 427285809Sscottl 428285809Sscottl if(1) 429285809Sscottl { 430285809Sscottl mpiOCQueue_t *circularQ; 431285809Sscottl int i; 432285809Sscottl SA_DBG4(("saHwShutdown:\n")); 433285809Sscottl for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 434285809Sscottl { 435285809Sscottl circularQ = &saRoot->outboundQueue[i]; 436285809Sscottl OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 437285809Sscottl if(circularQ->producerIdx != circularQ->consumerIdx) 438285809Sscottl { 439285809Sscottl SA_DBG1(("saHwShutdown: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx )); 440285809Sscottl } 441285809Sscottl } 442285809Sscottl } 443285809Sscottl#endif /* SALLSDK_DBG */ 444285809Sscottl 445285809Sscottl if(smIS_SPCV(agRoot)) 446285809Sscottl { 447285809Sscottl 448285809Sscottl siScratchDump(agRoot); 449285809Sscottl 450285809Sscottl SA_DBG1(("saHwShutdown: SPC_V\n" )); 451285809Sscottl } 452285809Sscottl /* Set chip status */ 453285809Sscottl saRoot->chipStatus |= CHIP_SHUTDOWN; 454285809Sscottl 455285809Sscottl /* Un-Initialization Configuration Table */ 456285809Sscottl mpiUnInitConfigTable(agRoot); 457285809Sscottl if (saRoot->swConfig.hostDirectAccessSupport && !saRoot->swConfig.hostDirectAccessMode) 458285809Sscottl { 459285809Sscottl /* HDA mode - do HDAsoftReset */ 460285809Sscottl if(smIS_SPC(agRoot)) 461285809Sscottl { 462285809Sscottl /* HDA soft reset */ 463285809Sscottl siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 464285809Sscottl } 465285809Sscottl if(smIS_SPCV(agRoot)) 466285809Sscottl { 467285809Sscottl siChipResetV(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 468285809Sscottl SA_DBG1(("saHwShutdown: HDA saRoot->ChipId == VEN_DEV_SPCV\n")); 469285809Sscottl } 470285809Sscottl } 471285809Sscottl else 472285809Sscottl { 473285809Sscottl /* do Normal softReset */ 474285809Sscottl if(smIS_SPC(agRoot)) 475285809Sscottl { 476285809Sscottl /* Soft Reset the SPC */ 477285809Sscottl siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 478285809Sscottl } 479285809Sscottl if(smIS_SPCV(agRoot)) 480285809Sscottl { 481285809Sscottl SA_DBG1(("saHwShutdown: saRoot->ChipId == VEN_DEV_SPCV\n")); 482285809Sscottl siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); 483285809Sscottl } 484285809Sscottl 485285809Sscottl } 486285809Sscottl 487285809Sscottl /* clean the LL resources */ 488285809Sscottl siInitResources(agRoot, 489285809Sscottl &saRoot->memoryAllocated, 490285809Sscottl &saRoot->hwConfig, 491285809Sscottl &saRoot->swConfig, 492285809Sscottl saRoot->usecsPerTick); 493285809Sscottl SA_DBG1(("saHwShutdown: Shutting down Complete\n")); 494285809Sscottl } 495285809Sscottl else 496285809Sscottl { 497285809Sscottl SA_DBG1(("saHwShutdown: No saRoot\n")); 498285809Sscottl if( smIS_SPCV(agRoot) ) 499285809Sscottl { 500285809Sscottl siChipResetV(agRoot, SPC_SOFT_RESET_SIGNATURE); 501285809Sscottl } 502285809Sscottl else 503285809Sscottl { 504285809Sscottl siSpcSoftReset(agRoot, SPC_SOFT_RESET_SIGNATURE); 505285809Sscottl } 506285809Sscottl } 507285809Sscottl /* agroot/saroot null do not access -trace OK */ 508285809Sscottl 509285809Sscottl SA_ASSERT( (agNULL != agRoot), "10"); 510285809Sscottl /* return */ 511285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5b"); 512285809Sscottl return; 513285809Sscottl} 514285809Sscottl 515285809Sscottl 516285809Sscottl/******************************************************************************/ 517285809Sscottl/*! \brief Generic Reset 518285809Sscottl * 519285809Sscottl * The siChipReset() function is called to reset the SPC chip. Upon return, 520285809Sscottl * the SPC chip got reset. The PCIe bus got reset. 521285809Sscottl * 522285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 523285809Sscottl * 524285809Sscottl * \return -void- 525285809Sscottl */ 526285809Sscottl/*******************************************************************************/ 527285809Sscottl 528285809SscottlGLOBAL void siChipReset( 529285809Sscottl agsaRoot_t *agRoot 530285809Sscottl ) 531285809Sscottl{ 532285809Sscottl agsaLLRoot_t *saRoot; 533285809Sscottl 534285809Sscottl /* sanity check */ 535285809Sscottl SA_ASSERT( (agNULL != agRoot), ""); 536285809Sscottl 537285809Sscottl saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 538285809Sscottl if(agNULL != saRoot) 539285809Sscottl { 540285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"2C"); 541285809Sscottl 542285809Sscottl SA_DBG1(("siChipReset: saRoot->ChipId == VEN_DEV_SPCV\n")); 543285809Sscottl if(smIS_SPC(agRoot) ) 544285809Sscottl { 545285809Sscottl /* Soft Reset the SPC */ 546285809Sscottl siChipResetSpc( agRoot); 547285809Sscottl }else /* saRoot->ChipId == VEN_DEV_SPCV */ 548285809Sscottl { 549285809Sscottl siChipResetV( agRoot, SPC_SOFT_RESET_SIGNATURE); 550285809Sscottl } 551285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2C"); 552285809Sscottl } 553285809Sscottl 554285809Sscottl} 555285809Sscottl 556285809Sscottl 557285809Sscottl/******************************************************************************/ 558285809Sscottl/*! \brief Function to Reset the SPC V Hardware 559285809Sscottl * 560285809Sscottl * The siChipResetV() function is called to reset the SPC chip. Upon return, 561285809Sscottl * the SPC chip got reset. The PCIe bus got reset. 562285809Sscottl * 563285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 564285809Sscottl * 565285809Sscottl * \return -void- 566285809Sscottl */ 567285809Sscottl/*******************************************************************************/ 568285809Sscottl 569285809SscottlGLOBAL bit32 siChipResetV( 570285809Sscottl agsaRoot_t *agRoot, 571285809Sscottl bit32 signature 572285809Sscottl ) 573285809Sscottl{ 574285809Sscottl bit32 regVal; 575285809Sscottl bit32 returnVal = AGSA_RC_SUCCESS; 576285809Sscottl 577285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"3A"); 578285809Sscottl smTrace(hpDBG_LOUD,"Lr",ossaTimeStamp64(agRoot)); 579285809Sscottl regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); 580285809Sscottl 581285809Sscottl SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal)); 582285809Sscottl 583285809Sscottl if (signature == SPC_SOFT_RESET_SIGNATURE) 584285809Sscottl { 585285809Sscottl SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); 586285809Sscottl regVal = SPCv_Reset_Write_NormalReset; 587285809Sscottl } 588285809Sscottl else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 589285809Sscottl { 590285809Sscottl SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal)); 591285809Sscottl regVal = SPCv_Reset_Write_SoftResetHDA; 592285809Sscottl } 593285809Sscottl else 594285809Sscottl { 595285809Sscottl SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X regVal 0x%X a\n",signature ,regVal)); 596285809Sscottl regVal = 1; 597285809Sscottl } 598285809Sscottl 599285809Sscottl smTrace(hpDBG_LOUD,"Ls",ossaTimeStamp64(agRoot)); 600285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */ 601285809Sscottl smTrace(hpDBG_LOUD,"Lt",ossaTimeStamp64(agRoot)); 602285809Sscottl ossaStallThread(agRoot, (500 * 1000)); /* wait 500 milliseconds or PCIe will hang */ 603285809Sscottl /* Soft reset sequence (Normal mode) */ 604285809Sscottl smTrace(hpDBG_LOUD,"Lv",ossaTimeStamp64(agRoot)); 605285809Sscottl 606285809Sscottl if (signature == SPC_HDASOFT_RESET_SIGNATURE) 607285809Sscottl { 608285809Sscottl bit32 hda_status; 609285809Sscottl 610285809Sscottl hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 611285809Sscottl 612285809Sscottl SA_DBG1(("siChipResetV: hda_status 0x%x\n",hda_status)); 613285809Sscottl 614285809Sscottl if((hda_status & SPC_V_HDAR_RSPCODE_MASK) != SPC_V_HDAR_IDLE) 615285809Sscottl { 616285809Sscottl SA_DBG1(("siChipResetV:SPC_HDASOFT_RESET_SIGNATURE SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 617285809Sscottl } 618285809Sscottl 619285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal)); 620285809Sscottl 621285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */ 622285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal)); 623285809Sscottl 624285809Sscottl if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset) 625285809Sscottl { 626285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 627285809Sscottl returnVal = AGSA_RC_FAILURE; 628285809Sscottl } 629285809Sscottl if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred ) 630285809Sscottl { 631285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 632285809Sscottl returnVal = AGSA_RC_FAILURE; 633285809Sscottl } 634285809Sscottl if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred) 635285809Sscottl { 636285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_SUCCESS %X\n",regVal)); 637285809Sscottl returnVal = AGSA_RC_SUCCESS; 638285809Sscottl } 639285809Sscottl if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred) 640285809Sscottl { 641285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 642285809Sscottl returnVal = AGSA_RC_FAILURE; 643285809Sscottl } 644285809Sscottl if(regVal == 0xFFFFFFFF) 645285809Sscottl { 646285809Sscottl SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 647285809Sscottl returnVal = AGSA_RC_FAILURE; 648285809Sscottl } 649285809Sscottl 650285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x a\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 651285809Sscottl 652285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3A"); 653285809Sscottl return returnVal; 654285809Sscottl } 655285809Sscottl else if (signature == SPC_SOFT_RESET_SIGNATURE) 656285809Sscottl { 657285809Sscottl bit32 SCRATCH_PAD1; 658285809Sscottl bit32 max_wait_time; 659285809Sscottl bit32 max_wait_count; 660285809Sscottl smTrace(hpDBG_LOUD,"Lw",ossaTimeStamp64(agRoot)); 661285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */ 662285809Sscottl SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); 663285809Sscottl 664285809Sscottl if(regVal == 0xFFFFFFFF) 665285809Sscottl { 666285809Sscottl SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 667285809Sscottl returnVal = AGSA_RC_FAILURE; 668285809Sscottl } 669285809Sscottl else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset) 670285809Sscottl { 671285809Sscottl SA_DBG1(("siChipResetV:SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal)); 672285809Sscottl returnVal = AGSA_RC_FAILURE; 673285809Sscottl } 674285809Sscottl else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred) 675285809Sscottl { 676285809Sscottl SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal)); 677285809Sscottl returnVal = AGSA_RC_FAILURE; 678285809Sscottl } 679285809Sscottl else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred) 680285809Sscottl { 681285809Sscottl SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal)); 682285809Sscottl returnVal = AGSA_RC_FAILURE; 683285809Sscottl } 684285809Sscottl else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred ) 685285809Sscottl { 686285809Sscottl SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_SUCCESS 0x%X\n",regVal)); 687285809Sscottl returnVal = AGSA_RC_SUCCESS; 688285809Sscottl } 689285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x b\n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1))); 690285809Sscottl 691285809Sscottl if( returnVal != AGSA_RC_SUCCESS) 692285809Sscottl { 693285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_V_BOOTSTATE_MASK; 694285809Sscottl if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM ) 695285809Sscottl { 696285809Sscottl SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SEEPROM\n")); 697285809Sscottl return (returnVal); 698285809Sscottl } 699285809Sscottl else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP) 700285809Sscottl { 701285809Sscottl SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_BOOTSTRAP\n")); 702285809Sscottl return (returnVal); 703285809Sscottl } 704285809Sscottl else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET ) 705285809Sscottl { 706285809Sscottl SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_HDA_SOFTRESET\n")); 707285809Sscottl return (returnVal); 708285809Sscottl } 709285809Sscottl else if(SCRATCH_PAD1 == SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR ) 710285809Sscottl { 711285809Sscottl SA_DBG1(("siChipResetV: Reset done FW did not start BOOTSTATE_CRIT_ERROR\n")); 712285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "3A"); 713285809Sscottl return (returnVal); 714285809Sscottl } 715285809Sscottl } 716285809Sscottl 717285809Sscottl /* RESET */ 718285809Sscottl smTrace(hpDBG_LOUD,"Lx",ossaTimeStamp64(agRoot)); 719285809Sscottl max_wait_time = (100 * 1000); /* wait 100 milliseconds */ 720285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 721285809Sscottl do 722285809Sscottl { 723285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 724285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 725285809Sscottl } while ((SCRATCH_PAD1 == 0xFFFFFFFF ) && (max_wait_count -= WAIT_INCREMENT)); 726285809Sscottl 727285809Sscottl smTrace(hpDBG_LOUD,"Ly",ossaTimeStamp64(agRoot)); 728285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x (0x%x) PCIe ready took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 729285809Sscottl /* ILA */ 730285809Sscottl max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ 731285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 732285809Sscottl do 733285809Sscottl { 734285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 735285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 736285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); 737285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 738285809Sscottl 739285809Sscottl if (!max_wait_count) 740285809Sscottl { 741285809Sscottl returnVal = AGSA_RC_FAILURE; 742285809Sscottl SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); 743285809Sscottl } 744285809Sscottl /* RAAE */ 745285809Sscottl smTrace(hpDBG_LOUD,"Lz",ossaTimeStamp64(agRoot)); 746285809Sscottl max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */ 747285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 748285809Sscottl do 749285809Sscottl { 750285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 751285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 752285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); 753285809Sscottl 754285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 755285809Sscottl 756285809Sscottl if (!max_wait_count) 757285809Sscottl { 758285809Sscottl returnVal = AGSA_RC_FAILURE; 759285809Sscottl SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); 760285809Sscottl } 761285809Sscottl /* IOP0 */ 762285809Sscottl smTrace(hpDBG_LOUD,"La",ossaTimeStamp64(agRoot)); 763285809Sscottl max_wait_time = (600 * 1000); /* wait 600 milliseconds */ 764285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 765285809Sscottl do 766285809Sscottl { 767285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 768285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 769285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); 770285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 771285809Sscottl 772285809Sscottl if (!max_wait_count) 773285809Sscottl { 774285809Sscottl returnVal = AGSA_RC_FAILURE; 775285809Sscottl SA_DBG1(("siChipResetV:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); 776285809Sscottl } 777285809Sscottl 778285809Sscottl if(smIS_SPCV_2_IOP(agRoot)) 779285809Sscottl { 780285809Sscottl /* IOP1 */ 781285809Sscottl smTrace(hpDBG_LOUD,"Lb",ossaTimeStamp64(agRoot)); 782285809Sscottl max_wait_time = (200 * 1000); /* wait 200 milliseconds */ 783285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 784285809Sscottl do 785285809Sscottl { 786285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 787285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 788285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK) != SCRATCH_PAD1_V_IOP1_MASK) && (max_wait_count -= WAIT_INCREMENT)); 789285809Sscottl SA_DBG1(("siChipResetV:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP1_MASK (0x%x) (0x%x)(0x%x)\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP1_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 790285809Sscottl 791285809Sscottl if (!max_wait_count) 792285809Sscottl { 793285809Sscottl returnVal = AGSA_RC_FAILURE; 794285809Sscottl SA_DBG1(("siChipResetV: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1)); 795285809Sscottl } 796285809Sscottl } 797285809Sscottl smTrace(hpDBG_LOUD,"Lc",ossaTimeStamp64(agRoot)); 798285809Sscottl regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); 799285809Sscottl SA_DBG1(("siChipResetV: Reset done 0x%X ERROR_STATE 0x%X\n",regVal, 800285809Sscottl SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) )); 801285809Sscottl if(SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)) ) 802285809Sscottl { 803285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "3A"); 804285809Sscottl return AGSA_RC_FAILURE; 805285809Sscottl } 806285809Sscottl 807285809Sscottl } 808285809Sscottl else /* signature = unknown */ 809285809Sscottl { 810285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "3A"); 811285809Sscottl return AGSA_RC_FAILURE; 812285809Sscottl } 813285809Sscottl 814285809Sscottl smTrace(hpDBG_LOUD,"Ld",ossaTimeStamp64(agRoot)); 815285809Sscottl 816285809Sscottl SA_DBG1(("siChipResetV: out V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister) )); 817285809Sscottl#ifdef SOFT_RESET_TEST 818285809Sscottl DbgPrint("SCRATCH_PAD1 = 0x%x \n",ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)); 819285809Sscottl#endif 820285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "3A"); 821285809Sscottl return returnVal; 822285809Sscottl 823285809Sscottl} 824285809Sscottl/******************************************************************************/ 825285809Sscottl/*! \brief Function to Reset the SPC Hardware 826285809Sscottl * 827285809Sscottl * The siChipResetSpc() function is called to reset the SPC chip. Upon return, 828285809Sscottl * the SPC chip got reset. The PCIe bus got reset. 829285809Sscottl * 830285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 831285809Sscottl * 832285809Sscottl * \return -void- 833285809Sscottl */ 834285809Sscottl/*******************************************************************************/ 835285809SscottlGLOBAL void siChipResetSpc( 836285809Sscottl agsaRoot_t *agRoot 837285809Sscottl ) 838285809Sscottl{ 839285809Sscottl bit32 regVal; 840285809Sscottl 841285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"5c"); 842285809Sscottl 843285809Sscottl SA_DBG1(("siChipResetSpc: Chip Reset start\n")); 844285809Sscottl 845285809Sscottl /* Reset the chip */ 846285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 847285809Sscottl regVal &= ~(SPC_REG_RESET_DEVICE); 848285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */ 849285809Sscottl 850285809Sscottl /* delay 10 usec */ 851285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 852285809Sscottl 853285809Sscottl /* bring chip reset out of reset */ 854285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 855285809Sscottl regVal |= SPC_REG_RESET_DEVICE; 856285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */ 857285809Sscottl 858285809Sscottl /* delay 10 usec */ 859285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 860285809Sscottl 861285809Sscottl /* wait for 20 msec until the firmware gets reloaded */ 862285809Sscottl ossaStallThread(agRoot, (20 * 1000)); 863285809Sscottl 864285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5c"); 865285809Sscottl 866285809Sscottl SA_DBG1(("siChipResetSpc: Chip Reset Complete\n")); 867285809Sscottl 868285809Sscottl return; 869285809Sscottl} 870285809Sscottl 871285809Sscottl 872285809SscottlGLOBAL bit32 siSoftReset( 873285809Sscottl agsaRoot_t *agRoot, 874285809Sscottl bit32 signature 875285809Sscottl ) 876285809Sscottl{ 877285809Sscottl bit32 ret = AGSA_RC_SUCCESS; 878285809Sscottl 879285809Sscottl if(smIS_SPCV(agRoot)) 880285809Sscottl { 881285809Sscottl ret = si_V_SoftReset(agRoot, signature ); 882285809Sscottl } 883285809Sscottl else 884285809Sscottl { 885285809Sscottl ret = siSpcSoftReset(agRoot, signature ); 886285809Sscottl } 887285809Sscottl 888285809Sscottl return(ret); 889285809Sscottl} 890285809Sscottl 891285809SscottlLOCAL bit32 si_V_SoftReset( 892285809Sscottl agsaRoot_t *agRoot, 893285809Sscottl bit32 signature 894285809Sscottl ) 895285809Sscottl{ 896285809Sscottl 897285809Sscottl bit32 ret = AGSA_RC_SUCCESS; 898285809Sscottl 899285809Sscottl ret = siChipResetV(agRoot, signature); 900285809Sscottl 901285809Sscottl if (signature == SPC_SOFT_RESET_SIGNATURE) 902285809Sscottl { 903285809Sscottl SA_DBG1(("si_V_SoftReset:SPC_SOFT_RESET_SIGNATURE\n")); 904285809Sscottl } 905285809Sscottl else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 906285809Sscottl { 907285809Sscottl SA_DBG1(("si_V_SoftReset: SPC_HDASOFT_RESET_SIGNATURE\n")); 908285809Sscottl } 909285809Sscottl 910285809Sscottl SA_DBG1(("si_V_SoftReset: Reset Complete status 0x%X\n",ret)); 911285809Sscottl return ret; 912285809Sscottl} 913285809Sscottl 914285809Sscottl/******************************************************************************/ 915285809Sscottl/*! \brief Function to soft/FW reset the SPC 916285809Sscottl * 917285809Sscottl * The siSpcSoftReset() function is called to soft reset SPC. Upon return, 918285809Sscottl * the SPC FW got reset. The PCIe bus is not touched. 919285809Sscottl * 920285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 921285809Sscottl * \param signature soft reset normal signature or HDA soft reset signature 922285809Sscottl * 923285809Sscottl * \return -void- 924285809Sscottl */ 925285809Sscottl/*******************************************************************************/ 926285809SscottlGLOBAL bit32 siSpcSoftReset( 927285809Sscottl agsaRoot_t *agRoot, 928285809Sscottl bit32 signature 929285809Sscottl ) 930285809Sscottl{ 931285809Sscottl spc_configMainDescriptor_t mainCfg; 932285809Sscottl bit32 regVal, toggleVal; 933285809Sscottl bit32 max_wait_time; 934285809Sscottl bit32 max_wait_count; 935285809Sscottl bit32 regVal1, regVal2, regVal3; 936285809Sscottl 937285809Sscottl 938285809Sscottl /* sanity check */ 939285809Sscottl SA_ASSERT( (agNULL != agRoot), "agNULL != agRoot"); 940285809Sscottl if(agNULL != agRoot->sdkData) 941285809Sscottl { 942285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"5t"); 943285809Sscottl } 944285809Sscottl 945285809Sscottl SA_DBG1(("siSpcSoftReset: start\n")); 946285809Sscottl 947285809Sscottl 948285809Sscottl#if defined(SALLSDK_DEBUG) 949285809Sscottl /* count SoftReset */ 950285809Sscottl gLLSoftResetCounter++; 951285809Sscottl SA_DBG1(("siSpcSoftReset: ResetCount = 0x%x\n", gLLSoftResetCounter)); 952285809Sscottl#endif 953285809Sscottl 954285809Sscottl /* step1: Check FW is ready for soft reset */ 955285809Sscottl 956285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q1", 1); 957285809Sscottl /* TP:Q1 siSpcSoftReset */ 958285809Sscottl 959285809Sscottl if(AGSA_RC_FAILURE == siSpcSoftResetRDYChk(agRoot)) 960285809Sscottl { 961285809Sscottl SA_DBG1(("siSoftReset:siSoftResetRDYChk failed\n")); 962285809Sscottl if(agNULL != agRoot->sdkData) 963285809Sscottl { 964285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5t"); 965285809Sscottl } 966285809Sscottl return AGSA_RC_FAILURE; 967285809Sscottl } 968285809Sscottl 969285809Sscottl /* step 2: clear NMI status register on AAP1 and IOP, write the same value to clear */ 970285809Sscottl /* map 0x60000 to BAR4(0x20), BAR2(win) */ 971285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q2", 2); 972285809Sscottl /* TP:Q2 siSpcSoftReset */ 973285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_AAP1_ADDR_BASE)) 974285809Sscottl { 975285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_AAP1_ADDR_BASE)); 976285809Sscottl if(agNULL != agRoot->sdkData) 977285809Sscottl { 978285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5t"); 979285809Sscottl } 980285809Sscottl 981285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",1)); 982285809Sscottl return AGSA_RC_FAILURE; 983285809Sscottl } 984285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP); 985285809Sscottl SA_DBG1(("MBIC(A) - NMI Enable VPE0 (IOP): = 0x%x\n", regVal)); 986285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); /* siSpcSoftReset */ 987285809Sscottl 988285809Sscottl /* map 0x70000 to BAR4(0x20), BAR2(win) */ 989285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, MBIC_IOP_ADDR_BASE)) 990285809Sscottl { 991285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", MBIC_IOP_ADDR_BASE)); 992285809Sscottl if(agNULL != agRoot->sdkData) 993285809Sscottl { 994285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5t"); 995285809Sscottl } 996285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",2)); 997285809Sscottl return AGSA_RC_FAILURE; 998285809Sscottl } 999285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1); 1000285809Sscottl SA_DBG1(("MBIC(A) - NMI Enable VPE0 (AAP1): = 0x%x\n", regVal)); 1001285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); /* siSpcSoftReset */ 1002285809Sscottl 1003285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE); 1004285809Sscottl SA_DBG1(("PCIE - Event Interrupt Enable Register: = 0x%x\n", regVal)); 1005285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */ 1006285809Sscottl 1007285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT); 1008285809Sscottl SA_DBG1(("PCIE - Event Interrupt Register: = 0x%x\n", regVal)); 1009285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal); /* siSpcSoftReset */ 1010285809Sscottl 1011285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE); 1012285809Sscottl SA_DBG1(("PCIE - Error Interrupt Enable Register: = 0x%x\n", regVal)); 1013285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); /* siSpcSoftReset */ 1014285809Sscottl 1015285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT); 1016285809Sscottl SA_DBG1(("PCIE - Error Interrupt Register: = 0x%x\n", regVal)); 1017285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */ 1018285809Sscottl 1019285809Sscottl /* read the scratch pad 1 register bit 2 */ 1020285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; 1021285809Sscottl toggleVal = regVal ^ SCRATCH_PAD1_RST; 1022285809Sscottl 1023285809Sscottl /* set signature in host scratch pad0 register to tell SPC that the host performs the soft reset */ 1024285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, signature); 1025285809Sscottl 1026285809Sscottl /* read required registers for confirmming */ 1027285809Sscottl /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1028285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE)) 1029285809Sscottl { 1030285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE)); 1031285809Sscottl if(agNULL != agRoot->sdkData) 1032285809Sscottl { 1033285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5t"); 1034285809Sscottl } 1035285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",3)); 1036285809Sscottl return AGSA_RC_FAILURE; 1037285809Sscottl } 1038285809Sscottl 1039285809Sscottl SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1040285809Sscottl 1041285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q3", 3); 1042285809Sscottl /* TP:Q3 siSpcSoftReset */ 1043285809Sscottl 1044285809Sscottl /* step 3: host read GSM Configuration and Reset register */ 1045285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET); 1046285809Sscottl /* Put those bits to low */ 1047285809Sscottl /* GSM XCBI offset = 0x70 0000 1048285809Sscottl 0x00 Bit 13 COM_SLV_SW_RSTB 1 1049285809Sscottl 0x00 Bit 12 QSSP_SW_RSTB 1 1050285809Sscottl 0x00 Bit 11 RAAE_SW_RSTB 1 1051285809Sscottl 0x00 Bit 9 RB_1_SW_RSTB 1 1052285809Sscottl 0x00 Bit 8 SM_SW_RSTB 1 1053285809Sscottl */ 1054285809Sscottl regVal &= ~(0x00003b00); 1055285809Sscottl /* host write GSM Configuration and Reset register */ 1056285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */ 1057285809Sscottl SA_DBG1(("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1058285809Sscottl 1059285809Sscottl#if defined(SALLSDK_DEBUG) 1060285809Sscottl /* debugging messge */ 1061285809Sscottl SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR))); 1062285809Sscottl 1063285809Sscottl SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC))); 1064285809Sscottl SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC))); 1065285809Sscottl SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC))); 1066285809Sscottl#endif 1067285809Sscottl 1068285809Sscottl /* step 4: */ 1069285809Sscottl /* disable GSM - Read Address Parity Check */ 1070285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q4", 4); 1071285809Sscottl /* TP:Q4 siSpcSoftReset */ 1072285809Sscottl regVal1 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); 1073285809Sscottl SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal1)); 1074285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */ 1075285809Sscottl SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK))); 1076285809Sscottl 1077285809Sscottl /* disable GSM - Write Address Parity Check */ 1078285809Sscottl regVal2 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); 1079285809Sscottl SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal2)); 1080285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); /* siSpcSoftReset */ 1081285809Sscottl SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK))); 1082285809Sscottl 1083285809Sscottl /* disable GSM - Write Data Parity Check */ 1084285809Sscottl regVal3 = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); 1085285809Sscottl SA_DBG1(("GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", regVal3)); 1086285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); /* siSpcSoftReset */ 1087285809Sscottl SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK))); 1088285809Sscottl /* step 5-a: delay 10 usec */ 1089285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q5", 5); 1090285809Sscottl /* TP:Q5 siSpcSoftReset */ 1091285809Sscottl ossaStallThread(agRoot, 10); 1092285809Sscottl 1093285809Sscottl /* step 5-b: set GPIO-0 output control to tristate anyway */ 1094285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GPIO_ADDR_BASE)) 1095285809Sscottl { 1096285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GPIO_ADDR_BASE)); 1097285809Sscottl if(agNULL != agRoot->sdkData) 1098285809Sscottl { 1099285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5t"); 1100285809Sscottl } 1101285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",4)); 1102285809Sscottl return AGSA_RC_FAILURE; 1103285809Sscottl } 1104285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 1105285809Sscottl SA_DBG1(("GPIO Output Control Register: = 0x%x\n", regVal)); 1106285809Sscottl /* set GPIO-0 output control to tri-state */ 1107285809Sscottl regVal &= 0xFFFFFFFC; 1108285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); /* siSpcSoftReset */ 1109285809Sscottl 1110285809Sscottl /* Step 6: Reset the IOP and AAP1 */ 1111285809Sscottl /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1112285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q6", 6); 1113285809Sscottl /* TP:Q6 siSpcSoftReset */ 1114285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE)) 1115285809Sscottl { 1116285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE)); 1117285809Sscottl if(agNULL != agRoot->sdkData) 1118285809Sscottl { 1119285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5t"); 1120285809Sscottl } 1121285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5)); 1122285809Sscottl return AGSA_RC_FAILURE; 1123285809Sscottl } 1124285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1125285809Sscottl SA_DBG1(("Top Register before resetting IOP/AAP1: = 0x%x\n", regVal)); 1126285809Sscottl regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1127285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1128285809Sscottl 1129285809Sscottl /* step 7: Reset the BDMA/OSSP */ 1130285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q7", 7); 1131285809Sscottl /* TP:Q7 siSpcSoftReset */ 1132285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1133285809Sscottl SA_DBG1(("Top Register before resetting BDMA/OSSP: = 0x%x\n", regVal)); 1134285809Sscottl regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1135285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1136285809Sscottl 1137285809Sscottl /* step 8: delay 10 usec */ 1138285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q8", 8); 1139285809Sscottl /* TP:Q8 siSpcSoftReset */ 1140285809Sscottl 1141285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1142285809Sscottl 1143285809Sscottl /* step 9: bring the BDMA and OSSP out of reset */ 1144285809Sscottl smTrace(hpDBG_VERY_LOUD,"Q9", 9); 1145285809Sscottl /* TP:Q9 siSpcSoftReset */ 1146285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1147285809Sscottl SA_DBG1(("Top Register before bringing up BDMA/OSSP: = 0x%x\n", regVal)); 1148285809Sscottl regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 1149285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1150285809Sscottl 1151285809Sscottl /* step 10: delay 10 usec */ 1152285809Sscottl smTrace(hpDBG_VERY_LOUD,"QA", 10); 1153285809Sscottl /* TP:QA siSpcSoftReset */ 1154285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1155285809Sscottl 1156285809Sscottl /* step 11: reads and sets the GSM Configuration and Reset Register */ 1157285809Sscottl /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 1158285809Sscottl smTrace(hpDBG_VERY_LOUD,"QB", 11); 1159285809Sscottl /* TP:QB siSpcSoftReset */ 1160285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, GSM_ADDR_BASE)) 1161285809Sscottl { 1162285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", GSM_ADDR_BASE)); 1163285809Sscottl if(agNULL != agRoot->sdkData) 1164285809Sscottl { 1165285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5t"); 1166285809Sscottl } 1167285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",5)); 1168285809Sscottl return AGSA_RC_FAILURE; 1169285809Sscottl } 1170285809Sscottl SA_DBG1(("GSM 0x0 (0x00007b88) - GSM Configuration and Reset = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1171285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET); 1172285809Sscottl /* Put those bits to high */ 1173285809Sscottl /* GSM XCBI offset = 0x70 0000 1174285809Sscottl 0x00 Bit 13 COM_SLV_SW_RSTB 1 1175285809Sscottl 0x00 Bit 12 QSSP_SW_RSTB 1 1176285809Sscottl 0x00 Bit 11 RAAE_SW_RSTB 1 1177285809Sscottl 0x00 Bit 9 RB_1_SW_RSTB 1 1178285809Sscottl 0x00 Bit 8 SM_SW_RSTB 1 1179285809Sscottl */ 1180285809Sscottl regVal |= (GSM_CONFIG_RESET_VALUE); 1181285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */ 1182285809Sscottl SA_DBG1(("GSM 0x0 (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET))); 1183285809Sscottl 1184285809Sscottl#if defined(SALLSDK_DEBUG) 1185285809Sscottl /* debugging messge */ 1186285809Sscottl SA_DBG1(("GSM 0x700018 - RAM ECC Double Bit Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, RAM_ECC_DB_ERR))); 1187285809Sscottl SA_DBG1(("GSM 0x700058 - Read Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_INDIC))); 1188285809Sscottl SA_DBG1(("GSM 0x700060 - Write Address Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_INDIC))); 1189285809Sscottl SA_DBG1(("GSM 0x700068 - Write Data Parity Error Indication = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_INDIC))); 1190285809Sscottl#endif 1191285809Sscottl 1192285809Sscottl /* step 12: Restore GSM - Read Address Parity Check */ 1193285809Sscottl smTrace(hpDBG_VERY_LOUD,"QC", 12); 1194285809Sscottl /* TP:QC siSpcSoftReset */ 1195285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); /* just for debugging */ 1196285809Sscottl SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal)); 1197285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK, regVal1); /* siSpcSoftReset */ 1198285809Sscottl SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK))); 1199285809Sscottl 1200285809Sscottl /* Restore GSM - Write Address Parity Check */ 1201285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); /* just for debugging */ 1202285809Sscottl SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal)); 1203285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); /* siSpcSoftReset */ 1204285809Sscottl SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK))); 1205285809Sscottl 1206285809Sscottl /* Restore GSM - Write Data Parity Check */ 1207285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); /* just for debugging */ 1208285809Sscottl SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable = 0x%x\n", regVal)); 1209285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); /* siSpcSoftReset */ 1210285809Sscottl SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK))); 1211285809Sscottl 1212285809Sscottl /* step 13: bring the IOP and AAP1 out of reset */ 1213285809Sscottl /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1214285809Sscottl smTrace(hpDBG_VERY_LOUD,"QD", 13); 1215285809Sscottl /* TP:QD siSpcSoftReset */ 1216285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, SPC_TOP_LEVEL_ADDR_BASE)) 1217285809Sscottl { 1218285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", SPC_TOP_LEVEL_ADDR_BASE)); 1219285809Sscottl if(agNULL != agRoot->sdkData) 1220285809Sscottl { 1221285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5t"); 1222285809Sscottl } 1223285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",7)); 1224285809Sscottl return AGSA_RC_FAILURE; 1225285809Sscottl } 1226285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET); 1227285809Sscottl SA_DBG1(("Top Register before bringing up IOP/AAP1: = 0x%x\n", regVal)); 1228285809Sscottl regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1229285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */ 1230285809Sscottl 1231285809Sscottl if (signature == SPC_SOFT_RESET_SIGNATURE) 1232285809Sscottl { 1233285809Sscottl /* step 14: delay 20 milli - Normal Mode */ 1234285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1235285809Sscottl }else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 1236285809Sscottl { 1237285809Sscottl /* step 14: delay 200 milli - HDA Mode */ 1238285809Sscottl ossaStallThread(agRoot, 200 * 1000); 1239285809Sscottl } 1240285809Sscottl 1241285809Sscottl /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1242285809Sscottl if (signature == SPC_SOFT_RESET_SIGNATURE) 1243285809Sscottl { 1244285809Sscottl /* step 15 (Normal Mode): wait until scratch pad1 register bit 2 toggled */ 1245285809Sscottl max_wait_time = WAIT_SECONDS(2); /* 2 sec */ 1246285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1247285809Sscottl do 1248285809Sscottl { 1249285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1250285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; 1251285809Sscottl } while ((regVal != toggleVal) && (max_wait_count -=WAIT_INCREMENT)); 1252285809Sscottl 1253285809Sscottl if ( !max_wait_count) 1254285809Sscottl { 1255285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 1256285809Sscottl SA_DBG1(("siSpcSoftReset: TIMEOUT:ToggleVal 0x%x, MSGU_SCRATCH_PAD1 = 0x%x\n", toggleVal, regVal)); 1257285809Sscottl if(agNULL != agRoot->sdkData) 1258285809Sscottl { 1259285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5t"); 1260285809Sscottl } 1261285809Sscottl#if defined(SALLSDK_DEBUG) 1262285809Sscottl SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1263285809Sscottl SA_DBG1(("siSpcSoftReset: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1264285809Sscottl SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1265285809Sscottl#endif 1266285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",8)); 1267285809Sscottl return AGSA_RC_FAILURE; 1268285809Sscottl } 1269285809Sscottl 1270285809Sscottl /* step 16 (Normal)step 15 (HDA) - Clear ODMR and ODCR */ 1271285809Sscottl smTrace(hpDBG_VERY_LOUD,"QG", 16); 1272285809Sscottl /* TP:QG siSpcSoftReset */ 1273285809Sscottl 1274285809Sscottl ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 1275285809Sscottl ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL); 1276285809Sscottl } 1277285809Sscottl else if (signature == SPC_HDASOFT_RESET_SIGNATURE) 1278285809Sscottl { 1279285809Sscottl if(agNULL != agRoot->sdkData) 1280285809Sscottl { 1281285809Sscottl SA_DBG1(("siSpcSoftReset: HDA Soft Reset Complete\n")); 1282285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5t"); 1283285809Sscottl } 1284285809Sscottl return AGSA_RC_SUCCESS; 1285285809Sscottl } 1286285809Sscottl 1287285809Sscottl 1288285809Sscottl /* step 17 (Normal Mode): wait for the FW and IOP to get ready - 1 sec timeout */ 1289285809Sscottl /* Wait for the SPC Configuration Table to be ready */ 1290285809Sscottl if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE) 1291285809Sscottl { 1292285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 1293285809Sscottl /* return error if MPI Configuration Table not ready */ 1294285809Sscottl SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal)); 1295285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 1296285809Sscottl /* return error if MPI Configuration Table not ready */ 1297285809Sscottl SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal)); 1298285809Sscottl if(agNULL != agRoot->sdkData) 1299285809Sscottl { 1300285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5t"); 1301285809Sscottl } 1302285809Sscottl#if defined(SALLSDK_DEBUG) 1303285809Sscottl SA_DBG1(("siSpcSoftReset: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1304285809Sscottl SA_DBG1(("siSpcSoftReset: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1305285809Sscottl#endif 1306285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset AGSA_RC_FAILURE %d\n",9)); 1307285809Sscottl return AGSA_RC_FAILURE; 1308285809Sscottl } 1309285809Sscottl smTrace(hpDBG_VERY_LOUD,"QI", 18); 1310285809Sscottl /* TP:QI siSpcSoftReset */ 1311285809Sscottl 1312285809Sscottl if(agNULL != agRoot->sdkData) 1313285809Sscottl { 1314285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5t"); 1315285809Sscottl } 1316285809Sscottl 1317285809Sscottl SA_DBG1(("siSpcSoftReset: Soft Reset Complete\n")); 1318285809Sscottl 1319285809Sscottl return AGSA_RC_SUCCESS; 1320285809Sscottl} 1321285809Sscottl 1322285809Sscottl/******************************************************************************/ 1323285809Sscottl/*! \brief Function to do BAR shifting 1324285809Sscottl * 1325285809Sscottl * The siBarShift() function is called to shift BAR base address 1326285809Sscottl * 1327285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 1328285809Sscottl * \param shiftValue shifting value 1329285809Sscottl * 1330285809Sscottl * \return success or fail 1331285809Sscottl */ 1332285809Sscottl/*******************************************************************************/ 1333285809SscottlGLOBAL bit32 siBar4Shift( 1334285809Sscottl agsaRoot_t *agRoot, 1335285809Sscottl bit32 shiftValue 1336285809Sscottl ) 1337285809Sscottl{ 1338285809Sscottl bit32 regVal; 1339285809Sscottl bit32 max_wait_time; 1340285809Sscottl bit32 max_wait_count; 1341285809Sscottl 1342285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"5e"); 1343285809Sscottl smTrace(hpDBG_VERY_LOUD,"GA",shiftValue); 1344285809Sscottl /* TP:GA shiftValue */ 1345285809Sscottl 1346285809Sscottl SA_DBG2(("siBar4Shift: shiftValue 0x%x\n",shiftValue)); 1347285809Sscottl 1348285809Sscottl if(smIS_SPCV(agRoot) ) 1349285809Sscottl { 1350285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister, shiftValue); 1351285809Sscottl /* confirm the setting is written */ 1352285809Sscottl max_wait_time = WAIT_SECONDS(1); /* 1 sec */ 1353285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1354285809Sscottl do 1355285809Sscottl { 1356285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1357285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister); 1358285809Sscottl } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT)); 1359285809Sscottl 1360285809Sscottl if (!max_wait_count) 1361285809Sscottl { 1362285809Sscottl SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal)); 1363285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5e"); 1364285809Sscottl return AGSA_RC_FAILURE; 1365285809Sscottl } 1366285809Sscottl } 1367285809Sscottl else if(smIS_SPC(agRoot)) 1368285809Sscottl { 1369285809Sscottl /* program the inbound AXI translation Lower Address */ 1370285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 1371285809Sscottl 1372285809Sscottl /* confirm the setting is written */ 1373285809Sscottl max_wait_time = WAIT_SECONDS(1); /* 1 sec */ 1374285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1375285809Sscottl do 1376285809Sscottl { 1377285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1378285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW); 1379285809Sscottl } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT)); 1380285809Sscottl 1381285809Sscottl if (!max_wait_count) 1382285809Sscottl { 1383285809Sscottl SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal)); 1384285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5e"); 1385285809Sscottl return AGSA_RC_FAILURE; 1386285809Sscottl } 1387285809Sscottl } 1388285809Sscottl else 1389285809Sscottl { 1390285809Sscottl SA_DBG1(("siBar4Shift: hba type is not support\n")); 1391285809Sscottl return AGSA_RC_FAILURE; 1392285809Sscottl } 1393285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5e"); 1394285809Sscottl 1395285809Sscottl return AGSA_RC_SUCCESS; 1396285809Sscottl} 1397285809Sscottl 1398285809Sscottl#ifdef SA_ENABLE_HDA_FUNCTIONS 1399285809Sscottl/******************************************************************************/ 1400285809Sscottl/*! \brief Function to force HDA mode the SPC 1401285809Sscottl * 1402285809Sscottl * The siHDAMode() function is called to force to HDA mode. Upon return, 1403285809Sscottl * the SPC FW loaded. The PCIe bus is not touched. 1404285809Sscottl * 1405285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 1406285809Sscottl * \param HDAMode 0 - HDA soft reset mode, 1 - HDA mode 1407285809Sscottl * \param fwImg points to structure containing fw images 1408285809Sscottl * 1409285809Sscottl * \return -void- 1410285809Sscottl */ 1411285809Sscottl/*******************************************************************************/ 1412285809SscottlGLOBAL bit32 siHDAMode( 1413285809Sscottl agsaRoot_t *agRoot, 1414285809Sscottl bit32 HDAMode, 1415285809Sscottl agsaFwImg_t *userFwImg 1416285809Sscottl ) 1417285809Sscottl{ 1418285809Sscottl spc_configMainDescriptor_t mainCfg; 1419285809Sscottl bit32 regVal; 1420285809Sscottl bit32 max_wait_time; 1421285809Sscottl bit32 max_wait_count; 1422285809Sscottl agsaFwImg_t flashImg; 1423285809Sscottl bit32 startTime, endTime; // TestBase 1424285809Sscottl bit32 stepTime[12]; // TestBase 1425285809Sscottl 1426285809Sscottl bit32 HDA_Been_Reset = agFALSE; 1427285809Sscottl 1428285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"5d"); 1429285809Sscottl 1430285809Sscottl /* sanity check */ 1431285809Sscottl SA_ASSERT( (agNULL != agRoot), ""); 1432285809Sscottl 1433285809Sscottl SA_DBG1(("siHDAMode: start\n")); 1434285809Sscottl 1435285809Sscottl si_memset(&flashImg, 0, sizeof(flashImg)); 1436285809Sscottl#ifndef SA_EXCLUDE_FW_IMG 1437285809Sscottl 1438285809Sscottl /* Set up built-in (default) FW image pointers */ 1439285809Sscottl/* 1440285809Sscottl flashImg.aap1Img = (bit8*)(&aap1array); 1441285809Sscottl flashImg.aap1Len = sizeof(aap1array); 1442285809Sscottl flashImg.ilaImg = (bit8*)(&ilaarray); 1443285809Sscottl flashImg.ilaLen = sizeof(ilaarray); 1444285809Sscottl flashImg.iopImg = (bit8*)(&ioparray); 1445285809Sscottl flashImg.iopLen = sizeof(ioparray); 1446285809Sscottl*/ 1447285809Sscottl#endif 1448285809Sscottl TryAfterReset: 1449285809Sscottl 1450285809Sscottl /* Set up user FW image pointers (if passed in) */ 1451285809Sscottl if (userFwImg) 1452285809Sscottl { 1453285809Sscottl SA_DBG1(("siHDAMode: User fw structure @ %p\n",userFwImg)); 1454285809Sscottl if (userFwImg->aap1Img && userFwImg->aap1Len) 1455285809Sscottl { 1456285809Sscottl flashImg.aap1Img = userFwImg->aap1Img; 1457285809Sscottl flashImg.aap1Len = userFwImg->aap1Len; 1458285809Sscottl SA_DBG1(("siHDAMode: User fw aap1 @ %p (%d)\n", flashImg.aap1Img, flashImg.aap1Len)); 1459285809Sscottl } 1460285809Sscottl if (userFwImg->ilaImg && userFwImg->ilaLen) 1461285809Sscottl { 1462285809Sscottl flashImg.ilaImg = userFwImg->ilaImg; 1463285809Sscottl flashImg.ilaLen = userFwImg->ilaLen; 1464285809Sscottl SA_DBG1(("siHDAMode: User fw ila @ %p (%d)\n", flashImg.ilaImg, flashImg.ilaLen)); 1465285809Sscottl } 1466285809Sscottl if (userFwImg->iopImg && userFwImg->iopLen) 1467285809Sscottl { 1468285809Sscottl flashImg.iopImg = userFwImg->iopImg; 1469285809Sscottl flashImg.iopLen = userFwImg->iopLen; 1470285809Sscottl SA_DBG1(("siHDAMode: User fw iop @ %p (%d)\n", flashImg.iopImg, flashImg.iopLen)); 1471285809Sscottl } 1472285809Sscottl if (userFwImg->istrImg && userFwImg->istrLen) 1473285809Sscottl { 1474285809Sscottl flashImg.istrImg = userFwImg->istrImg; 1475285809Sscottl flashImg.istrLen = userFwImg->istrLen; 1476285809Sscottl SA_DBG1(("siHDAMode: User fw istr @ %p (%d)\n", flashImg.istrImg, flashImg.istrLen)); 1477285809Sscottl } 1478285809Sscottl } 1479285809Sscottl else 1480285809Sscottl { 1481285809Sscottl SA_DBG1(("siHDAMode: user supplied FW is not found\n")); 1482285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5d"); 1483285809Sscottl return AGSA_RC_FAILURE; 1484285809Sscottl } 1485285809Sscottl 1486285809Sscottl#ifdef SA_EXCLUDE_FW_IMG 1487285809Sscottl /* Check that fw images are setup properly */ 1488285809Sscottl if (!(flashImg.aap1Img && flashImg.aap1Len && 1489285809Sscottl flashImg.ilaImg && flashImg.ilaLen && 1490285809Sscottl flashImg.iopImg && flashImg.iopLen && 1491285809Sscottl flashImg.istrImg && flashImg.istrLen)) 1492285809Sscottl { 1493285809Sscottl SA_DBG1(("siHDAMode: Built-in FW img excluded and not user defined.\n")); 1494285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5d"); 1495285809Sscottl return AGSA_RC_FAILURE; 1496285809Sscottl } 1497285809Sscottl#endif 1498285809Sscottl 1499285809Sscottl /* Check HDA mode with Soft Reset */ 1500285809Sscottl if (!HDAMode) 1501285809Sscottl { 1502285809Sscottl /* Try soft reset until it goes into HDA mode */ 1503285809Sscottl siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1504285809Sscottl 1505285809Sscottl /* read response state */ 1506285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 1507285809Sscottl if (regVal != BOOTTLOADERHDA_IDLE) 1508285809Sscottl { 1509285809Sscottl /* Can not go into HDA mode with 200 ms wait - HDA Soft Reset failed */ 1510285809Sscottl SA_DBG1(("siHDAMode: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1511285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5d"); 1512285809Sscottl return AGSA_RC_FAILURE; 1513285809Sscottl } 1514285809Sscottl 1515285809Sscottl /* HDA Mode - Clear ODMR and ODCR */ 1516285809Sscottl ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 1517285809Sscottl ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_CLEAR_ALL); 1518285809Sscottl } 1519285809Sscottl 1520285809Sscottl /* Step 1: Poll BOOTTLOADERHDA_IDLE - HDA mode */ 1521285809Sscottl SA_DBG1(("siHDAMode: Step1:Poll for HDAR_IDLE\n")); 1522285809Sscottl max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 1523285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1524285809Sscottl do 1525285809Sscottl { 1526285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1527285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 1528285809Sscottl } while ((regVal != BOOTTLOADERHDA_IDLE) && (max_wait_count -= WAIT_INCREMENT)); 1529285809Sscottl 1530285809Sscottl if (!max_wait_count) 1531285809Sscottl { 1532285809Sscottl 1533285809Sscottl if( !HDA_Been_Reset ) 1534285809Sscottl { 1535285809Sscottl 1536285809Sscottl SA_DBG1(("siHDAMode: Reset: Step1:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); 1537285809Sscottl siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1538285809Sscottl HDA_Been_Reset = agTRUE; 1539285809Sscottl goto TryAfterReset; 1540285809Sscottl 1541285809Sscottl } 1542285809Sscottl 1543285809Sscottl SA_DBG1(("siHDAMode: Step1:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1544285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "5d"); 1545285809Sscottl return AGSA_RC_FAILURE; 1546285809Sscottl } 1547285809Sscottl 1548285809Sscottl /* Step 2: Push the init string to 0x0047E000 & data compare */ 1549285809Sscottl SA_DBG1(("siHDAMode: Step2:Push the init string to 0x0047E000!\n")); 1550285809Sscottl 1551285809Sscottl if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, ILA_ISTR_ADDROFFSETHDA, flashImg.istrImg, flashImg.istrLen)) 1552285809Sscottl { 1553285809Sscottl SA_DBG1(("siHDAMode: Step2:Copy ISTR array to 0x%x failed\n", ILA_ISTR_ADDROFFSETHDA)); 1554285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "5d"); 1555285809Sscottl return AGSA_RC_FAILURE; 1556285809Sscottl } 1557285809Sscottl 1558285809Sscottl /* Tell FW ISTR is ready */ 1559285809Sscottl regVal = (HDA_ISTR_DONE | (bit32)flashImg.istrLen); 1560285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); 1561285809Sscottl SA_DBG1(("siHDAMode: Step2:Host Scratchpad 3 (AAP1-ISTR): 0x%x\n", regVal)); 1562285809Sscottl 1563285809Sscottl stepTime[2] = ossaTimeStamp(agRoot); // TestBase 1564285809Sscottl SA_DBG1(("siHDAMode: End Step2: (step_time[2] = %d)\n", stepTime[2])); // TestBase 1565285809Sscottl 1566285809Sscottl /* Step 3: Write the HDA mode SoftReset signature */ 1567285809Sscottl SA_DBG1(("siHDAMode: Step3:Set Signature!\n")); 1568285809Sscottl /* set signature in host scratch pad0 register to tell SPC that the host performs the HDA mode */ 1569285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, SPC_HDASOFT_RESET_SIGNATURE); 1570285809Sscottl 1571285809Sscottl stepTime[3] = ossaTimeStamp(agRoot); // TestBase 1572285809Sscottl SA_DBG1(("siHDAMode: End Step3: (step_time[3] = %d)\n", stepTime[3])); // TestBase 1573285809Sscottl 1574285809Sscottl // Priya (Apps) requested that the FW load time measurement be started here 1575285809Sscottl startTime = ossaTimeStamp(agRoot); 1576285809Sscottl SA_DBG1(("siHDAMode: Step4: Ready to push ILA to 0x00400000! (start_time = %d)\n", startTime)); // TestBase 1577285809Sscottl 1578285809Sscottl /* Step 4: Push the ILA image to 0x00400000 */ 1579285809Sscottl SA_DBG1(("siHDAMode: Step4:Push the ILA to 0x00400000!\n")); 1580285809Sscottl 1581285809Sscottl if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, 0x0, flashImg.ilaImg, flashImg.ilaLen)) 1582285809Sscottl { 1583285809Sscottl SA_DBG1(("siHDAMode:Step4:Copy ILA array to 0x%x failed\n", 0x0)); 1584285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "5d"); 1585285809Sscottl return AGSA_RC_FAILURE; 1586285809Sscottl } 1587285809Sscottl 1588285809Sscottl stepTime[4] = ossaTimeStamp(agRoot); 1589285809Sscottl SA_DBG1(("siHDAMode: End Step4: (step_time[4] = %d, %d ms)\n", stepTime[4], (stepTime[4] - startTime))); // TestBase 1590285809Sscottl 1591285809Sscottl /* Step 5: Tell boot ROM to authenticate ILA and execute it */ 1592285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB, 0); 1593285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_PAR_LEN_OFFSET, flashImg.ilaLen); 1594285809Sscottl regVal = (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_SEQ_ID_BITS ) >> SHIFT16; 1595285809Sscottl regVal ++; 1596285809Sscottl regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD; 1597285809Sscottl SA_DBG1(("siHDAMode: Step5:Execute ILA CMD: 0x%x\n", regVal)); 1598285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_CMD_CODE_OFFSET, regVal); /* Execute Command */ 1599285809Sscottl 1600285809Sscottl stepTime[5] = ossaTimeStamp(agRoot); 1601285809Sscottl SA_DBG1(("siHDAMode: End Step5: (step_time[5] = %d, %d ms)\n", stepTime[5], (stepTime[5] - startTime))); // TestBase 1602285809Sscottl 1603285809Sscottl 1604285809Sscottl /* Step 6: Checking response status from boot ROM, HDAR_EXEC (good), HDAR_BAD_CMD and HDAR_BAD_IMG */ 1605285809Sscottl SA_DBG1(("siHDAMode: Step6:Checking boot ROM reponse status!\n")); 1606285809Sscottl max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 1607285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1608285809Sscottl do 1609285809Sscottl { 1610285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1611285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 1612285809Sscottl if ((HDAR_EXEC == regVal) || (HDAR_BAD_IMG == regVal) || (HDAR_BAD_CMD == regVal)) 1613285809Sscottl break; 1614285809Sscottl } while (max_wait_count-=WAIT_INCREMENT); 1615285809Sscottl 1616285809Sscottl if (HDAR_BAD_IMG == regVal) 1617285809Sscottl { 1618285809Sscottl SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1619285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "5d"); 1620285809Sscottl return AGSA_RC_FAILURE; 1621285809Sscottl } 1622285809Sscottl if (HDAR_BAD_CMD == regVal) 1623285809Sscottl { 1624285809Sscottl SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1625285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "5d"); 1626285809Sscottl return AGSA_RC_FAILURE; 1627285809Sscottl } 1628285809Sscottl if (!max_wait_count) 1629285809Sscottl { 1630285809Sscottl SA_DBG1(("siHDAMode: Step6:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal)); 1631285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "5d"); 1632285809Sscottl return AGSA_RC_FAILURE; 1633285809Sscottl } 1634285809Sscottl 1635285809Sscottl stepTime[6] = ossaTimeStamp(agRoot); 1636285809Sscottl SA_DBG1(("siHDAMode: End Step6: (step_time[6] = %d, %d ms)\n", stepTime[6], (stepTime[6] - startTime))); // TestBase 1637285809Sscottl 1638285809Sscottl /* Step 7: Poll ILAHDA_AAP1IMGGET/Offset in MSGU Scratchpad 0 */ 1639285809Sscottl /* Check MSGU Scratchpad 1 [1,0] == 00 */ 1640285809Sscottl SA_DBG1(("siHDAMode: Step7:Poll ILAHDA_AAP1_IMG_GET!\n")); 1641285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST; 1642285809Sscottl SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 1: 0x%x\n", regVal)); 1643285809Sscottl max_wait_time = WAIT_SECONDS(gWait_3); /* 3 sec */ 1644285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1645285809Sscottl do 1646285809Sscottl { 1647285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1648285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24; 1649285809Sscottl } while ((regVal != ILAHDA_AAP1_IMG_GET) && (max_wait_count -= WAIT_INCREMENT)); 1650285809Sscottl 1651285809Sscottl if (!max_wait_count) 1652285809Sscottl { 1653285809Sscottl 1654285809Sscottl if( !HDA_Been_Reset ) 1655285809Sscottl { 1656285809Sscottl 1657285809Sscottl SA_DBG1(("siHDAMode: Reset: Step7:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); 1658285809Sscottl siSpcSoftReset(agRoot, SPC_HDASOFT_RESET_SIGNATURE); 1659285809Sscottl HDA_Been_Reset = agTRUE; 1660285809Sscottl goto TryAfterReset; 1661285809Sscottl 1662285809Sscottl } 1663285809Sscottl 1664285809Sscottl SA_DBG1(("siHDAMode: TIMEOUT: Step7:regVal =0x%x expect 0x%x\n", regVal,ILAHDA_AAP1_IMG_GET )); 1665285809Sscottl#if defined(SALLSDK_DEBUG) 1666285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1667285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1668285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1669285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1670285809Sscottl#endif 1671285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "5d"); 1672285809Sscottl return AGSA_RC_FAILURE; 1673285809Sscottl } 1674285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); 1675285809Sscottl SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 0: 0x%x\n", regVal)); 1676285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & 0x00FFFFFF; 1677285809Sscottl 1678285809Sscottl stepTime[7] = ossaTimeStamp(agRoot); 1679285809Sscottl SA_DBG1(("siHDAMode: End Step7: (step_time[7] = %d, %d ms)\n", stepTime[7], (stepTime[7] - startTime))); // TestBase 1680285809Sscottl 1681285809Sscottl /* Step 8: Copy AAP1 image, update the Host Scratchpad 3 */ 1682285809Sscottl SA_DBG1(("siHDAMode: Step8:Push the AAP1 to 0x00400000 plus 0x%x\n", regVal)); 1683285809Sscottl 1684285809Sscottl if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.aap1Img, flashImg.aap1Len)) 1685285809Sscottl { 1686285809Sscottl SA_DBG1(("siHDAMode: Step8:Copy AAP1 array to 0x%x failed\n", regVal)); 1687285809Sscottl#if defined(SALLSDK_DEBUG) 1688285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 1689285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1690285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1691285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1692285809Sscottl#endif 1693285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "5d"); 1694285809Sscottl return AGSA_RC_FAILURE; 1695285809Sscottl } 1696285809Sscottl 1697285809Sscottl regVal = (HDA_AAP1_DONE | (bit32)flashImg.aap1Len); 1698285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); 1699285809Sscottl SA_DBG1(("siHDAMode: Step8:Host Scratchpad 3 (AAP1): 0x%x\n", regVal)); 1700285809Sscottl 1701285809Sscottl stepTime[8] = ossaTimeStamp(agRoot); 1702285809Sscottl SA_DBG1(("siHDAMode: End Step8: (step_time[8] = %d, %d ms)\n", stepTime[8], (stepTime[8] - startTime))); // TestBase 1703285809Sscottl 1704285809Sscottl /* Step 9: Poll ILAHDA_IOPIMGGET/Offset in MSGU Scratchpad 0 */ 1705285809Sscottl SA_DBG1(("siHDAMode: Step9:Poll ILAHDA_IOP_IMG_GET!\n")); 1706285809Sscottl max_wait_time = WAIT_SECONDS(gWait_2); /* 2 sec */ 1707285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 1708285809Sscottl do 1709285809Sscottl { 1710285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 1711285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24; 1712285809Sscottl } while ((regVal != ILAHDA_IOP_IMG_GET) && (max_wait_count -= WAIT_INCREMENT)); 1713285809Sscottl 1714285809Sscottl if (!max_wait_count) 1715285809Sscottl { 1716285809Sscottl SA_DBG1(("siHDAMode: Step9:TIMEOUT:MSGU_SCRATCH_PAD_0 = 0x%x\n", regVal)); 1717285809Sscottl#if defined(SALLSDK_DEBUG) 1718285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1719285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1720285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1721285809Sscottl#endif 1722285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "5d"); 1723285809Sscottl return AGSA_RC_FAILURE; 1724285809Sscottl } 1725285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); 1726285809Sscottl SA_DBG1(("siHDAMode: Step9:MSG Scratchpad 0: 0x%x\n", regVal)); 1727285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & HDA_GSM_OFFSET_BITS; 1728285809Sscottl 1729285809Sscottl stepTime[9] = ossaTimeStamp(agRoot); 1730285809Sscottl SA_DBG1(("siHDAMode: End Step9: (step_time[9] = %d, %d ms)\n", stepTime[9], (stepTime[9] - startTime))); // TestBase 1731285809Sscottl 1732285809Sscottl // saHdaLoadForceHalt(agRoot); // TestBase 1733285809Sscottl 1734285809Sscottl /* Step 10: Copy IOP image, update the Host Scratchpad 3 */ 1735285809Sscottl SA_DBG1(("siHDAMode: Step10:Push the IOP to 0x00400000 plus 0x%x!\n", regVal)); 1736285809Sscottl 1737285809Sscottl if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.iopImg, flashImg.iopLen)) 1738285809Sscottl { 1739285809Sscottl SA_DBG1(("siHDAMode: Step10:Copy IOP array to 0x%x failed\n", regVal)); 1740285809Sscottl#if defined(SALLSDK_DEBUG) 1741285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1))); 1742285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2))); 1743285809Sscottl SA_DBG1(("siHDAMode: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 1744285809Sscottl#endif 1745285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "5d"); 1746285809Sscottl return AGSA_RC_FAILURE; 1747285809Sscottl } 1748285809Sscottl 1749285809Sscottl regVal = (HDA_IOP_DONE | (bit32)flashImg.iopLen); 1750285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal); 1751285809Sscottl SA_DBG1(("siHDAMode: Step10:Host Scratchpad 3 (IOP): 0x%x\n", regVal)); 1752285809Sscottl 1753285809Sscottl stepTime[10] = ossaTimeStamp(agRoot); 1754285809Sscottl SA_DBG1(("siHDAMode: End Step10: (step_time[10] = %d, %d ms)\n", stepTime[10], (stepTime[10] - startTime))); // TestBase 1755285809Sscottl 1756285809Sscottl /* Clear the signature */ 1757285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_0, 0); 1758285809Sscottl 1759285809Sscottl /* step 11: wait for the FW and IOP to get ready - 1 sec timeout */ 1760285809Sscottl /* Wait for the SPC Configuration Table to be ready */ 1761285809Sscottl stepTime[11] = ossaTimeStamp(agRoot); 1762285809Sscottl SA_DBG1(("siHDAMode: Start Step11: Wait for FW ready. (step_time[11.1] = %d, %d ms)\n", stepTime[11], (stepTime[11] - startTime))); // TestBase 1763285809Sscottl 1764285809Sscottl endTime = ossaTimeStamp(agRoot); 1765285809Sscottl SA_DBG1(("siHDAMode: End Step11: FW ready! (end_time= %d, fw_load_time = %d ms)\n", endTime, endTime - startTime)); // TestBase 1766285809Sscottl 1767285809Sscottl SA_DBG1(("siHDAMode: Step11:Poll for FW ready!\n")); 1768285809Sscottl if (mpiWaitForConfigTable(agRoot, &mainCfg) == AGSA_RC_FAILURE) 1769285809Sscottl { 1770285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 1771285809Sscottl /* return error if MPI Configuration Table not ready */ 1772285809Sscottl SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal)); 1773285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 1774285809Sscottl /* return error if MPI Configuration Table not ready */ 1775285809Sscottl SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal)); 1776285809Sscottl /* read detail fatal errors */ 1777285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0); 1778285809Sscottl SA_DBG1(("siHDAMode: Step11:ScratchPad0 AAP error code 0x%x\n", regVal)); 1779285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3); 1780285809Sscottl SA_DBG1(("siHDAMode: Step11:ScratchPad3 IOP error code 0x%x\n", regVal)); 1781285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'n', "5d"); 1782285809Sscottl return AGSA_RC_FAILURE; 1783285809Sscottl } 1784285809Sscottl 1785285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'o', "5d"); 1786285809Sscottl 1787285809Sscottl SA_DBG1(("siHDAMode: HDA Mode Complete\n")); 1788285809Sscottl 1789285809Sscottl return AGSA_RC_SUCCESS; 1790285809Sscottl} 1791285809Sscottl 1792285809Sscottl/******************************************************************************/ 1793285809Sscottl/*! \brief memcopy cross PCI from host memory to card memory 1794285809Sscottl * 1795285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 1796285809Sscottl * \param dstoffset distination offset 1797285809Sscottl * \param src source pointer 1798285809Sscottl * \param DWcount DWord count 1799285809Sscottl * \param busBaseNumber PCI Bus Base number 1800285809Sscottl * 1801285809Sscottl * \return -void- 1802285809Sscottl * 1803285809Sscottl */ 1804285809Sscottl/*******************************************************************************/ 1805285809SscottlLOCAL void siPciMemCpy(agsaRoot_t *agRoot, 1806285809Sscottl bit32 dstoffset, 1807285809Sscottl void *src, 1808285809Sscottl bit32 DWcount, 1809285809Sscottl bit32 busBaseNumber 1810285809Sscottl ) 1811285809Sscottl{ 1812285809Sscottl bit32 i, val; 1813285809Sscottl bit32 *src1; 1814285809Sscottl 1815285809Sscottl src1 = (bit32 *)src; 1816285809Sscottl 1817285809Sscottl for (i= 0; i < DWcount; i++) 1818285809Sscottl { 1819285809Sscottl val = BIT32_TO_LEBIT32(src1[i]); 1820285809Sscottl ossaHwRegWriteExt(agRoot, busBaseNumber, (dstoffset + i * 4), val); 1821285809Sscottl } 1822285809Sscottl 1823285809Sscottl return; 1824285809Sscottl} 1825285809Sscottl 1826285809Sscottl/******************************************************************************/ 1827285809Sscottl/*! \brief Function to copy FW array 1828285809Sscottl * 1829285809Sscottl * The siBar4Cpy() function is called to copy FW array via BAR4 1830285809Sscottl * (PCIe spec: BAR4, MEMBASE-III in PM, PCIBAR2 in host driver) 1831285809Sscottl * in 64-KB MEMBASE MODE. 1832285809Sscottl * 1833285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 1834285809Sscottl * \param offset destination offset 1835285809Sscottl * \param parray pointer of array 1836285809Sscottl * \param array_size size of array 1837285809Sscottl * 1838285809Sscottl * \return AGSA_RC_SUCCESS or AGSA_RC_FAILURE 1839285809Sscottl */ 1840285809Sscottl/*******************************************************************************/ 1841285809SscottlLOCAL bit32 siBar4Cpy( 1842285809Sscottl agsaRoot_t *agRoot, 1843285809Sscottl bit32 offset, 1844285809Sscottl bit8 * parray, 1845285809Sscottl bit32 array_size 1846285809Sscottl ) 1847285809Sscottl{ 1848285809Sscottl bit32 dest_shift_addr, dest_offset, cpy_size; 1849285809Sscottl 1850285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"5f"); 1851285809Sscottl 1852285809Sscottl /* first time to shift */ 1853285809Sscottl dest_shift_addr = (GSMSM_AXI_LOWERADDR+offset) & SHIFT_MASK; 1854285809Sscottl dest_offset = offset & OFFSET_MASK; 1855285809Sscottl do 1856285809Sscottl { 1857285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, dest_shift_addr)) 1858285809Sscottl { 1859285809Sscottl SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", dest_shift_addr)); 1860285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5f"); 1861285809Sscottl return AGSA_RC_FAILURE; 1862285809Sscottl } 1863285809Sscottl 1864285809Sscottl if ((dest_offset+array_size) > SIZE_64KB) 1865285809Sscottl { 1866285809Sscottl cpy_size = SIZE_64KB - dest_offset; 1867285809Sscottl } 1868285809Sscottl else 1869285809Sscottl cpy_size = array_size; 1870285809Sscottl 1871285809Sscottl siPciMemCpy(agRoot, dest_offset, parray, (bit32)(CEILING(cpy_size,4)), PCIBAR2); 1872285809Sscottl 1873285809Sscottl array_size -= cpy_size; 1874285809Sscottl dest_shift_addr += SIZE_64KB; 1875285809Sscottl dest_offset = 0; 1876285809Sscottl parray = parray + cpy_size; 1877285809Sscottl } while (array_size !=0 ); 1878285809Sscottl 1879285809Sscottl /* Shift back to BAR4 original address */ 1880285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, 0x0)) 1881285809Sscottl { 1882285809Sscottl SA_DBG1(("siHDAMode:Shift Bar4 to 0x%x failed\n", 0x0)); 1883285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5f"); 1884285809Sscottl return AGSA_RC_FAILURE; 1885285809Sscottl } 1886285809Sscottl 1887285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "5f"); 1888285809Sscottl 1889285809Sscottl return AGSA_RC_SUCCESS; 1890285809Sscottl} 1891285809Sscottl 1892285809SscottlGLOBAL 1893285809Sscottlbit32 siHDAMode_V( 1894285809Sscottl agsaRoot_t *agRoot, 1895285809Sscottl bit32 HDAMode, 1896285809Sscottl agsaFwImg_t *userFwImg 1897285809Sscottl ) 1898285809Sscottl{ 1899285809Sscottl bit32 returnVal = AGSA_RC_FAILURE; 1900285809Sscottl bit32 save,i,biggest; 1901285809Sscottl bit32 hda_status; 1902285809Sscottl bit32 hda_command_complete = 0; 1903285809Sscottl bit32 max_wait_time; 1904285809Sscottl bit32 max_wait_count; 1905285809Sscottl bit32 seq_id = 0; 1906285809Sscottl bit32 base_Hi = 0; 1907285809Sscottl bit32 base_Lo = 0; 1908285809Sscottl bit8 * pbase; 1909285809Sscottl 1910285809Sscottl spcv_hda_cmd_t hdacmd; 1911285809Sscottl spcv_hda_rsp_t hdarsp; 1912285809Sscottl 1913285809Sscottl agsaLLRoot_t *saRoot; 1914285809Sscottl 1915285809Sscottl /* sanity check */ 1916285809Sscottl SA_ASSERT( (agNULL != agRoot), ""); 1917285809Sscottl 1918285809Sscottl saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1919285809Sscottl 1920285809Sscottl /* sanity check */ 1921285809Sscottl SA_ASSERT( (agNULL != saRoot), "saRoot is NULL"); 1922285809Sscottl 1923285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"2W"); 1924285809Sscottl 1925285809Sscottl SA_DBG1(("siHDAMode_V: HDAMode %X\n",HDAMode)); 1926285809Sscottl 1927285809Sscottl siScratchDump(agRoot); 1928285809Sscottl if( agNULL == userFwImg) 1929285809Sscottl { 1930285809Sscottl SA_DBG1(("siHDAMode_V: No image agNULL == userFwImg\n" )); 1931285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2W"); 1932285809Sscottl return returnVal; 1933285809Sscottl } 1934285809Sscottl 1935285809Sscottl hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28)); 1936285809Sscottl 1937285809Sscottl SA_DBG1(("siHDAMode_V: hda_status 0x%08X\n",hda_status )); 1938285809Sscottl SA_DBG1(("siHDAMode_V: STEP 1\n")); 1939285809Sscottl 1940285809Sscottl smTrace(hpDBG_VERY_LOUD,"2X",1 ); 1941285809Sscottl /* TP:2X STEP 1 */ 1942285809Sscottl 1943285809Sscottl /* Find largest Physical chunk memory */ 1944285809Sscottl for(i=0,biggest = 0,save = 0; i < saRoot->memoryAllocated.count; i++) 1945285809Sscottl { 1946285809Sscottl if( saRoot->memoryAllocated.agMemory[i].totalLength > biggest) 1947285809Sscottl { 1948285809Sscottl 1949285809Sscottl if(biggest < saRoot->memoryAllocated.agMemory[i].totalLength) 1950285809Sscottl { 1951285809Sscottl save = i; 1952285809Sscottl biggest = saRoot->memoryAllocated.agMemory[i].totalLength; 1953285809Sscottl } 1954285809Sscottl 1955285809Sscottl } 1956285809Sscottl } 1957285809Sscottl/* 1958285809SscottlStep 1 The host reads the HDA response field RSP_CODE at byte offset 28:29 of the response block 1959285809Sscottlfor HDAR_IDLE (0x8002) via MEMBASE-I. A value other than HDAR_IDLE (0x8002) indicates that the 1960285809SscottlSPCv controller is not in HDA mode. Follow the steps described in Section 4.21.1 to bring the 1961285809SscottlSPCv controller into HDA mode. When the host reads the correct RSP_CODE, it indicates that the 1962285809SscottlSPCv controller boot ROM is ready to proceed to the next step of HDA initialization 1963285809Sscottl*/ 1964285809Sscottl 1965285809Sscottl base_Hi = saRoot->memoryAllocated.agMemory[save].phyAddrUpper; 1966285809Sscottl base_Lo = saRoot->memoryAllocated.agMemory[save].phyAddrLower; 1967285809Sscottl pbase = saRoot->memoryAllocated.agMemory[save].virtPtr; 1968285809Sscottl SA_DBG1(("siHDAMode_V:Use DMA memory at [%d] size 0x%x (%d) DMA Loc U 0x%08x L 0x%08x @%p\n",save, 1969285809Sscottl biggest, 1970285809Sscottl biggest, 1971285809Sscottl base_Hi, 1972285809Sscottl base_Lo, 1973285809Sscottl pbase 1974285809Sscottl )); 1975285809Sscottl 1976285809Sscottl 1977285809Sscottl SA_DBG1(("siHDAMode_V: HDA aap1Img %p len %8d 0x%x\n", userFwImg->aap1Img, userFwImg->aap1Len , userFwImg->aap1Len )); 1978285809Sscottl SA_DBG1(("siHDAMode_V: HDA ilaImg %p len %8d 0x%x\n", userFwImg->ilaImg, userFwImg->ilaLen , userFwImg->ilaLen )); 1979285809Sscottl SA_DBG1(("siHDAMode_V: HDA iopImg %p len %8d 0x%x\n", userFwImg->iopImg, userFwImg->iopLen , userFwImg->iopLen )); 1980285809Sscottl if(userFwImg->aap1Len > biggest) 1981285809Sscottl { 1982285809Sscottl SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d aap1Len\n", biggest ,userFwImg->aap1Len)); 1983285809Sscottl SA_ASSERT( (agNULL != agRoot), "aap1Len > biggest"); 1984285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2W"); 1985285809Sscottl return returnVal; 1986285809Sscottl } 1987285809Sscottl if(userFwImg->ilaLen > biggest) 1988285809Sscottl { 1989285809Sscottl SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d ilaLen\n", biggest ,userFwImg->ilaLen)); 1990285809Sscottl SA_ASSERT( (agNULL != agRoot), "ilaLen > biggest"); 1991285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'c', "2W"); 1992285809Sscottl return returnVal; 1993285809Sscottl } 1994285809Sscottl if(userFwImg->iopLen > biggest) 1995285809Sscottl { 1996285809Sscottl SA_DBG1(("siHDAMode_V: HDA DMA area too small %d < %d iopLen\n", biggest ,userFwImg->iopLen)); 1997285809Sscottl SA_ASSERT( (agNULL != agRoot), "iopLen > biggest"); 1998285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'd', "2W"); 1999285809Sscottl return returnVal; 2000285809Sscottl } 2001285809Sscottl 2002285809Sscottl 2003285809Sscottl if(HDA_STEP_2) 2004285809Sscottl { /* ILA */ 2005285809Sscottl si_memset(pbase, 0, biggest); 2006285809Sscottl 2007285809Sscottl if( userFwImg->ilaLen < biggest) 2008285809Sscottl { 2009285809Sscottl si_memcpy(pbase,userFwImg->ilaImg, userFwImg->ilaLen ); 2010285809Sscottl } 2011285809Sscottl else 2012285809Sscottl { 2013285809Sscottl SA_DBG1(("siHDAMode_V: userFwImg->ilaLen 0x%x < biggest 0x%x\n",userFwImg->ilaLen,biggest)); 2014285809Sscottl } 2015285809Sscottl 2016285809Sscottl si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t)); 2017285809Sscottl si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t)); 2018285809Sscottl 2019285809Sscottl hda_status = ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28); 2020285809Sscottl if((hda_status & SPC_V_HDAR_RSPCODE_MASK) == SPC_V_HDAR_IDLE) 2021285809Sscottl { 2022285809Sscottl 2023285809Sscottl hdacmd.cmdparm_0 = base_Lo; /* source DmaBase_l*/ 2024285809Sscottl hdacmd.cmdparm_1 = base_Hi; /* source DmaBase_u*/ 2025285809Sscottl hdacmd.cmdparm_2 = 0x1e200000; /* destin */ 2026285809Sscottl hdacmd.cmdparm_3 = 0; /* destin */ 2027285809Sscottl hdacmd.cmdparm_4 = userFwImg->ilaLen ; /* length */ 2028285809Sscottl hdacmd.cmdparm_5 = 0;/* not used */ 2029285809Sscottl hdacmd.cmdparm_6 = 0;/* not used */ 2030285809Sscottl seq_id++; 2031285809Sscottl hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_DMA; 2032285809Sscottl 2033285809Sscottl SA_DBG1(("siHDAMode_V: Write SPC_V_HDAC_DMA STEP 2\n")); 2034285809Sscottl /* 2035285809Sscottl Step 2 2036285809Sscottl The host writes the HDAC_DMA (0x000 24) in the command field CMD_CODE via MEMBASE-I 2037285809Sscottl for issuing the DMA command to ask the boot ROM to pull the ILA image via DMA into 2038285809Sscottl GSM with the following parameters set up first: 2039285809Sscottl Parameter 1:0: Host physical address for holding the HDA-ILA image. 2040285809Sscottl Parameter 3:2: GSM physical address 0x1E20_0000. 2041285809Sscottl Parameter 4: the length of the HDAILA image. 2042285809Sscottl */ 2043285809Sscottl 2044285809Sscottl SA_DBG2(("siHDAMode_V: Write ILA to offset %X\n",hdacmd.cmdparm_2)); 2045285809Sscottl 2046285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0,hdacmd.cmdparm_0); 2047285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4,hdacmd.cmdparm_1); 2048285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8,hdacmd.cmdparm_2); 2049285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3); 2050285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4); 2051285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5); 2052285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6); 2053285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE); 2054285809Sscottl 2055285809Sscottl SA_DBG2(("siHDAMode_V: Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2056285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0), 2057285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4), 2058285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8), 2059285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12), 2060285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16), 2061285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20), 2062285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24), 2063285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) )); 2064285809Sscottl 2065285809Sscottl SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE )); 2066285809Sscottl 2067285809Sscottl max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2068285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2069285809Sscottl hda_command_complete = 0; 2070285809Sscottl do 2071285809Sscottl { 2072285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2073285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2074285809Sscottl } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2075285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 2 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2076285809Sscottl 2077285809Sscottl smTrace(hpDBG_VERY_LOUD,"2Y",(max_wait_time - max_wait_count) ); 2078285809Sscottl /* TP:2Y STEP 2 took */ 2079285809Sscottl 2080285809Sscottl 2081285809Sscottl if(! hda_command_complete) 2082285809Sscottl { 2083285809Sscottl SA_DBG1(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2084285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2085285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2086285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2087285809Sscottl SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 2\n" )); 2088285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'e', "2W"); 2089285809Sscottl return returnVal; 2090285809Sscottl } 2091285809Sscottl 2092285809Sscottl 2093285809Sscottl SA_DBG2(("siHDAMode_V:2SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2094285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2095285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2096285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2097285809Sscottl 2098285809Sscottl } 2099285809Sscottl 2100285809Sscottl SA_DBG1(("siHDAMode_V: ILA DMA done\n" )); 2101285809Sscottl } /* end ila */ 2102285809Sscottl 2103285809Sscottl if(HDA_STEP_3) 2104285809Sscottl { 2105285809Sscottl 2106285809Sscottl SA_DBG1(("siHDAMode_V: STEP 3\n")); 2107285809Sscottl /* 2108285809Sscottl Step 3 2109285809Sscottl The host polls the HDA response field RSP_CODE for HDAR_IDLE (0x8002) via MEMBASE-I. The polling timeout 2110285809Sscottl should be no more than 1 second. The response status, HDAR_IDLE with its status equal to 0x10, 2111285809Sscottl indicates a DMA success response from the boot ROM. Response states that indicate a failure are: 2112285809Sscottl HDAR_BAD_CMD HDAR_BAD_IMG HDAR_IDLE with its status equal to 0x11 2113285809Sscottl 2114285809Sscottl */ 2115285809Sscottl 2116285809Sscottl max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2117285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2118285809Sscottl hda_command_complete = 0; 2119285809Sscottl do 2120285809Sscottl { 2121285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2122285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2123285809Sscottl } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2124285809Sscottl 2125285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 3 took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2126285809Sscottl smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time - max_wait_count) ); 2127285809Sscottl /* TP:2Z STEP 3 took */ 2128285809Sscottl 2129285809Sscottl if(! hda_command_complete) 2130285809Sscottl { 2131285809Sscottl 2132285809Sscottl SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2133285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2134285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2135285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2136285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2137285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2138285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2139285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2140285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2141285809Sscottl 2142285809Sscottl 2143285809Sscottl SA_DBG1(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2144285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2145285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2146285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2147285809Sscottl SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 3\n" )); 2148285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'f', "2W"); 2149285809Sscottl return returnVal; 2150285809Sscottl } 2151285809Sscottl 2152285809Sscottl 2153285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2154285809Sscottl hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); 2155285809Sscottl 2156285809Sscottl SA_DBG2(("siHDAMode_V:ILA is ready hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete)); 2157285809Sscottl 2158285809Sscottl /* Tell FW ILA is ready */ 2159285809Sscottl SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2160285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2161285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2162285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2163285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2164285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2165285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2166285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2167285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2168285809Sscottl 2169285809Sscottl SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2170285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2171285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2172285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2173285809Sscottl 2174285809Sscottl SA_DBG2(("siHDAMode_V: Step 3 MSGU_HOST_SCRATCH_PAD_3 write %X\n",HDA_ISTR_DONE)); 2175285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,HDA_ISTR_DONE ); 2176285809Sscottl 2177285809Sscottl SA_DBG2(("siHDAMode_V:3SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2178285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2179285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2180285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2181285809Sscottl 2182285809Sscottl } 2183285809Sscottl 2184285809Sscottl if(HDA_STEP_4) 2185285809Sscottl { 2186285809Sscottl 2187285809Sscottl SA_DBG2(("siHDAMode_V: Exec ILA\n")); 2188285809Sscottl si_memset(&hdacmd,0,sizeof(spcv_hda_cmd_t)); 2189285809Sscottl si_memset(&hdarsp,0,sizeof(spcv_hda_rsp_t)); 2190285809Sscottl 2191285809Sscottl hdacmd.cmdparm_0 = 0x200000; /* length SPC_V_HDAC_EXEC*/; 2192285809Sscottl hdacmd.cmdparm_1 = userFwImg->ilaLen ; /* length SPC_V_HDAC_EXEC*/; 2193285809Sscottl seq_id++; 2194285809Sscottl 2195285809Sscottl hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_EXEC; 2196285809Sscottl 2197285809Sscottl SA_DBG1(("siHDAMode_V: STEP 4\n")); 2198285809Sscottl 2199285809Sscottl /* 2200285809Sscottl Step 4 2201285809Sscottl The host writes the HDAC_EXEC command (0x0002) via MEMBASE-I for the boot ROM to authenticate 2202285809Sscottl and execute the HDA-ILA image. The host sets parameter 0 and parameter 1 for the HDA-ILA image 2203285809Sscottl appropriately: 2204285809Sscottl Parameter 0: Entry offset this value must be 0x20_0000. 2205285809Sscottl Parameter 1: the HDA-ILA image length. 2206285809Sscottl */ 2207285809Sscottl 2208285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0 ,hdacmd.cmdparm_0); 2209285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4 ,hdacmd.cmdparm_1); 2210285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8 ,hdacmd.cmdparm_2); 2211285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12,hdacmd.cmdparm_3); 2212285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16,hdacmd.cmdparm_4); 2213285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20,hdacmd.cmdparm_5); 2214285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24,hdacmd.cmdparm_6); 2215285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28,hdacmd.C_PA_SEQ_ID_CMD_CODE); 2216285809Sscottl 2217285809Sscottl SA_DBG1(("siHDAMode_V: Exec ILA\n" )); 2218285809Sscottl 2219285809Sscottl SA_DBG2(("siHDAMode_V: Command 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2220285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+0), 2221285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+4), 2222285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+8), 2223285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+12), 2224285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+16), 2225285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+20), 2226285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+24), 2227285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_COMMAND_OFFSET+28) )); 2228285809Sscottl 2229285809Sscottl SA_DBG2(("siHDAMode_V: command %X\n",hdacmd.C_PA_SEQ_ID_CMD_CODE )); 2230285809Sscottl 2231285809Sscottl SA_DBG2(("siHDAMode_V:4SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2232285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2233285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2234285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2235285809Sscottl } // End Step 4 2236285809Sscottl if(HDA_STEP_5) 2237285809Sscottl { 2238285809Sscottl SA_DBG1(("siHDAMode_V: start wait STEP 5\n")); 2239285809Sscottl 2240285809Sscottl /* 2241285809Sscottl Step 5 2242285809Sscottl The host continues polling for the HDA-ILA status via MEMBASE-I. The polling timeout should 2243285809Sscottl be no more than 1 second. The response status HDAR_EXEC indicates a good response from the 2244285809Sscottl boot ROM. Response states that indicate a failure are: 2245285809Sscottl HDAR_BAD_CMD 2246285809Sscottl HDAR_BAD_IMG 2247285809Sscottl */ 2248285809Sscottl 2249285809Sscottl max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2250285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2251285809Sscottl hda_command_complete = 0; 2252285809Sscottl hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); 2253285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x Begin STEP 5\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),hda_status)); 2254285809Sscottl hda_status = 0; 2255285809Sscottl do 2256285809Sscottl { 2257285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2258285809Sscottl hda_status = (ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_RSPCODE_MASK ); 2259285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id; 2260285809Sscottl } while (hda_status != SPC_V_HDAR_EXEC && (max_wait_count -= WAIT_INCREMENT)); 2261285809Sscottl 2262285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x hda_status 0x%x hda_command_complete 0x%x STEP 5 wait for seq_id took %d\n", 2263285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1), 2264285809Sscottl hda_status, 2265285809Sscottl hda_command_complete, 2266285809Sscottl (max_wait_time - max_wait_count))); 2267285809Sscottl 2268285809Sscottl smTrace(hpDBG_VERY_LOUD,"2Z",(max_wait_time - max_wait_count) ); 2269285809Sscottl /* TP:2Z STEP 5 took */ 2270285809Sscottl 2271285809Sscottl if(! hda_command_complete) 2272285809Sscottl { 2273285809Sscottl SA_DBG1(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2274285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2275285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2276285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2277285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2278285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2279285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2280285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2281285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2282285809Sscottl 2283285809Sscottl SA_DBG1(("siHDAMode_V:5SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2284285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2285285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2286285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2287285809Sscottl SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 5\n" )); 2288285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'g', "2W"); 2289285809Sscottl return returnVal; 2290285809Sscottl } 2291285809Sscottl 2292285809Sscottl if (hda_status != SPC_V_HDAR_EXEC) 2293285809Sscottl { 2294285809Sscottl SA_DBG1(("siHDAMode_V:ILA_EXEC_ERROR hda_status %X hda_command_complete %d\n",hda_status ,hda_command_complete)); 2295285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'h', "2W"); 2296285809Sscottl goto bootrom_err; 2297285809Sscottl } 2298285809Sscottl SA_DBG1(("siHDAMode_V: end seq_id updated STEP 5\n")); 2299285809Sscottl } // End Step 5 2300285809Sscottl 2301285809Sscottl if(HDA_STEP_6) 2302285809Sscottl { 2303285809Sscottl SA_DBG1(("siHDAMode_V: start STEP 6\n")); 2304285809Sscottl 2305285809Sscottl /* 2306285809Sscottl Step 6 2307285809Sscottl The host polls the upper 8 bits [31:24] 5 of the Scratchpad 0 Register 2308285809Sscottl (page 609) for the ILAHDA_RAAE_IMG_GET (0x11) state. Polling timeout 2309285809Sscottl should be no more than 2 seconds. If a polling timeout occurs, the host 2310285809Sscottl should check for a fatal error as described in Section 12.2. 2311285809Sscottl If successful, the Host Scratchpad 4 Register (page 620) and Host 2312285809Sscottl Scratchpad 5 Register (page 621) are set as follows: Host Scratchpad 4 2313285809Sscottl Register (page 620) holds the lower 32-bit host address of 2314285809Sscottl the RAAE image. Host Scratchpad 5 Register (page 621) 2315285809Sscottl holds the upper 32-bit host address of the RAAE image. 2316285809Sscottl Then the host writes the command ILAHDAC_RAAE_IMG_DONE(0x81) to the upper 2317285809Sscottl 8 bits [31:24] of the Host Scratchpad 3 Register (page 619) and writes the 2318285809Sscottl sizeof the RAAE image to the lower 24 bits [23:0]. 2319285809Sscottl */ 2320285809Sscottl 2321285809Sscottl max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2322285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2323285809Sscottl hda_command_complete = 0; 2324285809Sscottl do 2325285809Sscottl { 2326285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2327285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_RAAE_IMG_GET; 2328285809Sscottl } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2329285809Sscottl 2330285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 6 wait for ILAHDA_RAAE_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time - max_wait_count))); 2331285809Sscottl smTrace(hpDBG_VERY_LOUD,"2b",(max_wait_time - max_wait_count) ); 2332285809Sscottl /* TP:2b STEP 6 took */ 2333285809Sscottl if(! hda_command_complete) 2334285809Sscottl { 2335285809Sscottl SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 6\n" )); 2336285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'i', "2W"); 2337285809Sscottl goto fw_err; 2338285809Sscottl } 2339285809Sscottl 2340285809Sscottl si_memset(pbase, 0, biggest); 2341285809Sscottl 2342285809Sscottl if( userFwImg->aap1Len < biggest) 2343285809Sscottl { 2344285809Sscottl si_memcpy(pbase,userFwImg->aap1Img, userFwImg->aap1Len ); 2345285809Sscottl } 2346285809Sscottl else 2347285809Sscottl { 2348285809Sscottl SA_DBG1(("siHDAMode_V: userFwImg->aap1Len 0x%x < biggest 0x%x\n",userFwImg->aap1Len,biggest)); 2349285809Sscottl } 2350285809Sscottl /* 2351285809Sscottl */ 2352285809Sscottl /* upper */ 2353285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi ); 2354285809Sscottl SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi)); 2355285809Sscottl /* lower */ 2356285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo ); 2357285809Sscottl SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo)); 2358285809Sscottl /* len */ 2359285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len ); 2360285809Sscottl SA_DBG1(("siHDAMode_V: write ILAHDAC_RAAE_IMG_DONE to MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len)); 2361285809Sscottl // ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_4 , userFwImg->DmaBase_l); 2362285809Sscottl 2363285809Sscottl ossaStallThread(agRoot, gWaitmSec * 1000); 2364285809Sscottl if(1) /* step in question */ 2365285809Sscottl { 2366285809Sscottl max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2367285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2368285809Sscottl hda_command_complete = 0; 2369285809Sscottl do 2370285809Sscottl { 2371285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2372285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET; 2373285809Sscottl } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2374285809Sscottl 2375285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2376285809Sscottl smTrace(hpDBG_VERY_LOUD,"2c",(max_wait_time - max_wait_count) ); 2377285809Sscottl /* TP:2c STEP 6a ILAHDA_IOP_IMG_GET took */ 2378285809Sscottl smTrace(hpDBG_VERY_LOUD,"2y",hda_command_complete ); 2379285809Sscottl /* TP:2y hda_command_complete */ 2380285809Sscottl 2381285809Sscottl if(! hda_command_complete) 2382285809Sscottl { 2383285809Sscottl SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" )); 2384285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'j', "2W"); 2385285809Sscottl goto fw_err; 2386285809Sscottl } 2387285809Sscottl } 2388285809Sscottl SA_DBG1(("siHDAMode_V: End V_Scratchpad_0_Register 0x%08X STEP 6\n",ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register))); 2389285809Sscottl } 2390285809Sscottl 2391285809Sscottl if(HDA_STEP_7) 2392285809Sscottl { 2393285809Sscottl SA_DBG1(("siHDAMode_V: STEP 7\n")); 2394285809Sscottl /* 2395285809Sscottl Step 7 2396285809Sscottl The host polls (reads) the upper 8 bits 7 [31:24] of the Scratchpad 0 Register (page 609) 2397285809Sscottl for ILAHDA_IOP_IMG_GET (0x10) state. The polling timeout should be no more than 2 seconds. 2398285809Sscottl If a polling timeout occurs, the host should check for a fatal error as described in 2399285809Sscottl Section 12.2. If successful, the Host Scratchpad 4 Register (page 620) and Host 2400285809Sscottl Scratchpad 5 Register (page 621) are set as follows: 2401285809Sscottl Host Scratchpad 4 Register (page 620) holds the lower host address of the IOP image. 2402285809Sscottl Host Scratchpad 5 Register (page 621) holds the upper host address of the IOP image. 2403285809Sscottl Then host writes the command ILAHDAC_IOP_IMG_DONE(0x80) to the upper 8 bits [31:24] of the 2404285809Sscottl Host Scratchpad 3 Register (page 614)and writes the sizeof the IOP image to the lower 24 2405285809Sscottl bits [23:0]. 2406285809Sscottl 2407285809Sscottl */ 2408285809Sscottl 2409285809Sscottl si_memset(pbase, 0, biggest); 2410285809Sscottl 2411285809Sscottl if( userFwImg->iopLen < biggest) 2412285809Sscottl { 2413285809Sscottl si_memcpy(pbase,userFwImg->iopImg, userFwImg->iopLen ); 2414285809Sscottl } 2415285809Sscottl else 2416285809Sscottl { 2417285809Sscottl SA_DBG1(("siHDAMode_V: userFwImg->iopImg 0x%x < biggest 0x%x\n",userFwImg->iopLen,biggest)); 2418285809Sscottl } 2419285809Sscottl 2420285809Sscottl /* upper */ 2421285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_5, base_Hi ); 2422285809Sscottl SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_5 0x%X\n", base_Hi)); 2423285809Sscottl /* lower */ 2424285809Sscottl ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_4, base_Lo ); 2425285809Sscottl SA_DBG3(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4 0x%X\n",base_Lo)); 2426285809Sscottl SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_4\n")); 2427285809Sscottl /* len */ 2428285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen ); 2429285809Sscottl SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen)); 2430285809Sscottl 2431285809Sscottl 2432285809Sscottl if(saRoot->swConfig.hostDirectAccessMode & 2 ) 2433285809Sscottl { 2434285809Sscottl /* Hda AES DIF offload */ 2435285809Sscottl ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC); 2436285809Sscottl SA_DBG1(("siHDAMode_V: V_Scratchpad_Rsvd_0_Register, HDA_AES_DIF_FUNC 0x%X\n",HDA_AES_DIF_FUNC)); 2437285809Sscottl /* Hda AES DIF offload */ 2438285809Sscottl } 2439285809Sscottl 2440285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2441285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2442285809Sscottl 2443285809Sscottl 2444285809Sscottl max_wait_time = (2000 * 1000); /* wait 2 seconds */ 2445285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2446285809Sscottl hda_command_complete = 0; 2447285809Sscottl do 2448285809Sscottl { 2449285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2450285809Sscottl hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET; 2451285809Sscottl } while (!hda_command_complete && (max_wait_count -= WAIT_INCREMENT)); 2452285809Sscottl 2453285809Sscottl smTrace(hpDBG_VERY_LOUD,"2d",(max_wait_time - max_wait_count) ); 2454285809Sscottl /* TP:2d STEP 7 ILAHDA_IOP_IMG_GET took */ 2455285809Sscottl smTrace(hpDBG_VERY_LOUD,"2z",hda_command_complete ); 2456285809Sscottl /* TP:2z hda_command_complete */ 2457285809Sscottl 2458285809Sscottl SA_DBG2(("siHDAMode_V:SCRATCH_PAD0 = 0x%x STEP 7 wait for ILAHDA_IOP_IMG_GET took %d\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register),(max_wait_time - max_wait_count))); 2459285809Sscottl 2460285809Sscottl if(! hda_command_complete) 2461285809Sscottl { 2462285809Sscottl SA_DBG1(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2463285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2464285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2465285809Sscottl SA_DBG1(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2466285809Sscottl SA_DBG1(("siHDAMode_V:hda_command_complete failed Step 7\n" )); 2467285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'k', "2W"); 2468285809Sscottl return returnVal; 2469285809Sscottl } 2470285809Sscottl 2471285809Sscottl 2472285809Sscottl SA_DBG2(("siHDAMode_V:7SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2473285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2474285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2475285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2476285809Sscottl SA_DBG1(("siHDAMode_V: End STEP 7\n")); 2477285809Sscottl } 2478285809Sscottl 2479285809Sscottl 2480285809Sscottl if(HDA_STEP_8) 2481285809Sscottl { 2482285809Sscottl bit32 SCRATCH_PAD1; 2483285809Sscottl 2484285809Sscottl SA_DBG1(("siHDAMode_V: Check fw ready Step 8\n")); 2485285809Sscottl 2486285809Sscottl /* 2487285809Sscottl Step 8 2488285809Sscottl IOP0/1 start-up sequence. The host polls the Scratchpad 1 Register (page 610) 2489285809Sscottl bits [1:0] for RAAE_STATE, bits [13:12] for IOP1_STATE, and 2490285809Sscottl bits [11:10] for IOP0_STATE to go to 11b (Ready state). 2491285809Sscottl The polling timeout should be no more than 1 second. If a polling timeout occurs, 2492285809Sscottl the host should check for a fatal error in Section 12.2. 2493285809Sscottl */ 2494285809Sscottl 2495285809Sscottl returnVal = AGSA_RC_SUCCESS; 2496285809Sscottl 2497285809Sscottl max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ 2498285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2499285809Sscottl do 2500285809Sscottl { 2501285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2502285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2503285809Sscottl } while ((SCRATCH_PAD1 == 0xFFFFFFFF ) && (max_wait_count -= WAIT_INCREMENT)); 2504285809Sscottl smTrace(hpDBG_VERY_LOUD,"HZ",(max_wait_time - max_wait_count) ); 2505285809Sscottl /* TP:2f Step 8 PCI took */ 2506285809Sscottl 2507285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x (0x%x) Step 8 PCIe took %d\n", SCRATCH_PAD1,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2508285809Sscottl /* ILA */ 2509285809Sscottl max_wait_time = (1000 * 1000); /* wait 1000 milliseconds */ 2510285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2511285809Sscottl do 2512285809Sscottl { 2513285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2514285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2515285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK) != SCRATCH_PAD1_V_ILA_MASK) && (max_wait_count -= WAIT_INCREMENT)); 2516285809Sscottl 2517285809Sscottl smTrace(hpDBG_VERY_LOUD,"2g",(max_wait_time - max_wait_count) ); 2518285809Sscottl /* TP:2g Step 8 ILA took */ 2519285809Sscottl 2520285809Sscottl SA_DBG2(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2521285809Sscottl 2522285809Sscottl if (!max_wait_count) 2523285809Sscottl { 2524285809Sscottl // Ignore for now returnVal = AGSA_RC_FAILURE; 2525285809Sscottl SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1)); 2526285809Sscottl } 2527285809Sscottl 2528285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_ILA_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_ILA_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2529285809Sscottl 2530285809Sscottl /* RAAE */ 2531285809Sscottl max_wait_time = (1800 * 1000); /* wait 1800 milliseconds */ 2532285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2533285809Sscottl do 2534285809Sscottl { 2535285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2536285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2537285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK) != SCRATCH_PAD1_V_RAAE_MASK) && (max_wait_count -= WAIT_INCREMENT)); 2538285809Sscottl 2539285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_RAAE_MASK (0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_RAAE_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2540285809Sscottl smTrace(hpDBG_VERY_LOUD,"2h",(max_wait_time - max_wait_count) ); 2541285809Sscottl /* TP:2h Step 8 RAAE took */ 2542285809Sscottl 2543285809Sscottl if (!max_wait_count) 2544285809Sscottl { 2545285809Sscottl SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1)); 2546285809Sscottl 2547285809Sscottl } 2548285809Sscottl /* IOP0 */ 2549285809Sscottl max_wait_time = (600 * 1000); /* wait 600 milliseconds */ 2550285809Sscottl max_wait_count = MAKE_MODULO(max_wait_time,WAIT_INCREMENT) - WAIT_INCREMENT; 2551285809Sscottl do 2552285809Sscottl { 2553285809Sscottl ossaStallThread(agRoot, WAIT_INCREMENT); 2554285809Sscottl SCRATCH_PAD1 = ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1); 2555285809Sscottl } while (((SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK) != SCRATCH_PAD1_V_IOP0_MASK) && (max_wait_count -= WAIT_INCREMENT)); 2556285809Sscottl 2557285809Sscottl SA_DBG1(("siHDAMode_V:SCRATCH_PAD1 = 0x%x SCRATCH_PAD1_V_IOP0_MASK(0x%x)(0x%x) took %d\n", SCRATCH_PAD1,SCRATCH_PAD1_V_IOP0_MASK,ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1),(max_wait_time - max_wait_count))); 2558285809Sscottl smTrace(hpDBG_VERY_LOUD,"2i",(max_wait_time - max_wait_count) ); 2559285809Sscottl /* TP:2i Step 8 IOP took */ 2560285809Sscottl 2561285809Sscottl if (!max_wait_count) 2562285809Sscottl { 2563285809Sscottl returnVal = AGSA_RC_FAILURE; 2564285809Sscottl SA_DBG1(("siHDAMode_V:Timeout SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1)); 2565285809Sscottl 2566285809Sscottl } 2567285809Sscottl 2568285809Sscottl 2569285809Sscottl SA_DBG1(("siHDAMode_V: Step 8 0x%X ERROR_STATE 0x%X\n",ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ), 2570285809Sscottl SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) ) )); 2571285809Sscottl if (SCRATCH_PAD1_V_ERROR_STATE( ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1) )) 2572285809Sscottl { 2573285809Sscottl if(smIS_ENCRYPT(agRoot)) 2574285809Sscottl { 2575285809Sscottl SA_DBG1(("siHDAMode_V: Encryption and HDA mode not supported - failed Step 8\n" )); 2576285809Sscottl } 2577285809Sscottl else 2578285809Sscottl { 2579285809Sscottl SA_DBG1(("siHDAMode_V: ERROR_STATE failed Step 8\n" )); 2580285809Sscottl } 2581285809Sscottl returnVal = AGSA_RC_FAILURE; 2582285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'l', "2W"); 2583285809Sscottl goto fw_err; 2584285809Sscottl } 2585285809Sscottl 2586285809Sscottl } 2587285809Sscottl SA_DBG1(("siHDAMode_V: returnVal 0x%X Step 8\n",returnVal)); 2588285809Sscottl/* 2589285809SscottlStep 10 2590285809SscottlThe host continues with the normal SPCv Configuration Table initialization sequence 2591285809Sscottlas described in Section 6.2.8.1. 2592285809Sscottl*/ 2593285809Sscottl if(saRoot->swConfig.hostDirectAccessMode & 2 ) 2594285809Sscottl { 2595285809Sscottl /* Hda AES DIF offload */ 2596285809Sscottl SA_DBG1(("siHDAMode_V: AES/DIF 0x%08X offload enabled %s\n",ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ), 2597285809Sscottl ((ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3 ) & (1 << SHIFT15)) ? "yes" :"no") )); 2598285809Sscottl /* Hda AES DIF offload */ 2599285809Sscottl /* ossaHwRegWrite(agRoot, V_Scratchpad_Rsvd_0_Register, 0); */ 2600285809Sscottl /* Hda AES DIF offload */ 2601285809Sscottl } 2602285809Sscottl 2603285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'm', "2W"); 2604285809Sscottl return returnVal; 2605285809Sscottl 2606285809Sscottlbootrom_err: 2607285809Sscottl SA_DBG2(("siHDAMode_V: Response 0 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 2608285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+0), 2609285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+4), 2610285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+8), 2611285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+12), 2612285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+16), 2613285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+20), 2614285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+24), 2615285809Sscottl ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) )); 2616285809Sscottl 2617285809Sscottlfw_err: 2618285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_0_Register))); 2619285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_1_Register))); 2620285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_2_Register))); 2621285809Sscottl SA_DBG2(("siHDAMode_V: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_Scratchpad_3_Register))); 2622285809Sscottl return returnVal; 2623285809Sscottl} 2624285809Sscottl 2625285809Sscottl#endif /* SA_ENABLE_HDA_FUNCTIONS */ 2626285809Sscottl 2627285809Sscottl 2628285809Sscottl 2629285809Sscottl 2630285809Sscottl/******************************************************************************/ 2631285809Sscottl/*! \brief Function to check FW is ready for soft reset 2632285809Sscottl * 2633285809Sscottl * The siSpcSoftResetRDYChk() function is called to check status of FW 2634285809Sscottl * 2635285809Sscottl * \param agRoot handles for this instance of SAS/SATA hardware 2636285809Sscottl * 2637285809Sscottl * \return success or fail 2638285809Sscottl */ 2639285809Sscottl/*******************************************************************************/ 2640285809SscottlLOCAL bit32 siSpcSoftResetRDYChk(agsaRoot_t *agRoot) 2641285809Sscottl{ 2642285809Sscottl bit32 regVal; 2643285809Sscottl bit32 Scratchpad1; 2644285809Sscottl bit32 Scratchpad2; 2645285809Sscottl bit32 spad2notready = 0; 2646285809Sscottl#if defined(SALLSDK_DEBUG) 2647285809Sscottl bit32 regVal1; 2648285809Sscottl bit32 regVal2; 2649285809Sscottl#endif /* SALLSDK_DEBUG */ 2650285809Sscottl 2651285809Sscottl /* read the scratch pad 2 register bit 2 */ 2652285809Sscottl regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_FWRDY_RST; 2653285809Sscottl Scratchpad1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 2654285809Sscottl if (regVal == SCRATCH_PAD2_FWRDY_RST) 2655285809Sscottl { 2656285809Sscottl /* FW assert happened, it is ready for soft reset */ 2657285809Sscottl /* Do nothing */ 2658285809Sscottl } 2659285809Sscottl else 2660285809Sscottl { 2661285809Sscottl /* read bootloader response state */ 2662285809Sscottl regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS; 2663285809Sscottl if (regVal == BOOTTLOADERHDA_IDLE) 2664285809Sscottl { 2665285809Sscottl /* For customers wants to do soft reset even the chip is already in HDA mode */ 2666285809Sscottl /* Do not need to trigger RB6 twice */ 2667285809Sscottl ; 2668285809Sscottl } 2669285809Sscottl else 2670285809Sscottl { 2671285809Sscottl /* Trigger NMI twice via RB6 */ 2672285809Sscottl if (AGSA_RC_FAILURE == siBar4Shift(agRoot, RB6_ACCESS_REG)) 2673285809Sscottl { 2674285809Sscottl SA_DBG1(("siSpcSoftReset:Shift Bar4 to 0x%x failed\n", RB6_ACCESS_REG)); 2675285809Sscottl return AGSA_RC_FAILURE; 2676285809Sscottl } 2677285809Sscottl 2678285809Sscottl if(Scratchpad1 != (SCRATCH_PAD1_FW_INIT_ERR | SCRATCH_PAD1_AAP_ERROR_STATE)) 2679285809Sscottl { 2680285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST); 2681285809Sscottl 2682285809Sscottl ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_RB6_OFFSET , RB6_MAGIC_NUMBER_RST); 2683285809Sscottl } 2684285809Sscottl else 2685285809Sscottl { 2686285809Sscottl SA_DBG1(("siSoftReset: ILA load fail SKIP RB6 access 0x%x\n",Scratchpad1 )); 2687285809Sscottl } 2688285809Sscottl SPAD2_NOT_READY: 2689285809Sscottl /* wait for 100 ms */ 2690285809Sscottl ossaStallThread(agRoot, ONE_HUNDRED_MILLISECS ); 2691285809Sscottl Scratchpad2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 2692285809Sscottl regVal = Scratchpad2 & SCRATCH_PAD2_FWRDY_RST; 2693285809Sscottl if (regVal != SCRATCH_PAD2_FWRDY_RST) 2694285809Sscottl { 2695285809Sscottl if (spad2notready > WAIT_SECONDS(12) / ONE_HUNDRED_MILLISECS ) /**/ 2696285809Sscottl { 2697285809Sscottl#if defined(SALLSDK_DEBUG) 2698285809Sscottl regVal1 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1); 2699285809Sscottl regVal2 = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2); 2700285809Sscottl SA_DBG1(("siSpcSoftResetRDYChk: TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", regVal1, regVal2)); 2701285809Sscottl SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0))); 2702285809Sscottl SA_DBG1(("siSpcSoftResetRDYChk: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3))); 2703285809Sscottl#endif /* SALLSDK_DEBUG */ 2704285809Sscottl return AGSA_RC_SUCCESS; /* Timeout Ok reset anyway */ 2705285809Sscottl } 2706285809Sscottl 2707285809Sscottl spad2notready++; 2708285809Sscottl goto SPAD2_NOT_READY; 2709285809Sscottl } 2710285809Sscottl } 2711285809Sscottl } 2712285809Sscottl 2713285809Sscottl return AGSA_RC_SUCCESS; 2714285809Sscottl} 2715285809Sscottl 2716285809Sscottl 2717285809SscottlagsaBarOffset_t SPCTable[] = 2718285809Sscottl{ 2719285809Sscottl 2720285809Sscottl { GEN_MSGU_IBDB_SET, PCIBAR0, MSGU_IBDB_SET, SIZE_DW }, /* 0x00 */ 2721285809Sscottl { GEN_MSGU_ODR, PCIBAR0, MSGU_ODR, SIZE_DW }, /* 0x01 */ 2722285809Sscottl { GEN_MSGU_ODCR, PCIBAR0, MSGU_ODCR, SIZE_DW }, /* 0x02 */ 2723285809Sscottl { GEN_MSGU_SCRATCH_PAD_0, PCIBAR0, MSGU_SCRATCH_PAD_0, SIZE_DW }, /* 0x03 */ 2724285809Sscottl { GEN_MSGU_SCRATCH_PAD_1, PCIBAR0, MSGU_SCRATCH_PAD_1, SIZE_DW }, /* 0x04 */ 2725285809Sscottl { GEN_MSGU_SCRATCH_PAD_2, PCIBAR0, MSGU_SCRATCH_PAD_2, SIZE_DW }, /* 0x05 */ 2726285809Sscottl { GEN_MSGU_SCRATCH_PAD_3, PCIBAR0, MSGU_SCRATCH_PAD_3, SIZE_DW }, /* 0x06 */ 2727285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_0, PCIBAR0, MSGU_HOST_SCRATCH_PAD_0, SIZE_DW }, /* 0x07 */ 2728285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_1, PCIBAR0, MSGU_HOST_SCRATCH_PAD_1, SIZE_DW }, /* 0x08 */ 2729285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_2, PCIBAR0, MSGU_HOST_SCRATCH_PAD_2, SIZE_DW }, /* 0x09 */ 2730285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_3, PCIBAR0, MSGU_HOST_SCRATCH_PAD_3, SIZE_DW }, /* 0x0a */ 2731285809Sscottl { GEN_MSGU_ODMR, PCIBAR0, MSGU_ODMR, SIZE_DW }, /* 0x0b */ 2732285809Sscottl { GEN_PCIE_TRIGGER, PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ, SIZE_DW }, /* 0x0c */ 2733285809Sscottl { GEN_SPC_REG_RESET, PCIBAR2, SPC_REG_RESET, SIZE_DW }, /* 0x0d */ 2734285809Sscottl}; 2735285809Sscottl 2736285809SscottlagsaBarOffset_t SPC_V_Table[] = 2737285809Sscottl{ 2738285809Sscottl 2739285809Sscottl { GEN_MSGU_IBDB_SET, PCIBAR0, V_Inbound_Doorbell_Set_Register, SIZE_DW }, /* 0x00 */ 2740285809Sscottl { GEN_MSGU_ODR, PCIBAR0, V_Outbound_Doorbell_Set_Register, SIZE_DW }, /* 0x01 */ 2741285809Sscottl { GEN_MSGU_ODCR, PCIBAR0, V_Outbound_Doorbell_Clear_Register, SIZE_DW }, /* 0x02 */ 2742285809Sscottl { GEN_MSGU_SCRATCH_PAD_0, PCIBAR0, V_Scratchpad_0_Register, SIZE_DW }, /* 0x03 */ 2743285809Sscottl { GEN_MSGU_SCRATCH_PAD_1, PCIBAR0, V_Scratchpad_1_Register, SIZE_DW }, /* 0x04 */ 2744285809Sscottl { GEN_MSGU_SCRATCH_PAD_2, PCIBAR0, V_Scratchpad_2_Register, SIZE_DW }, /* 0x05 */ 2745285809Sscottl { GEN_MSGU_SCRATCH_PAD_3, PCIBAR0, V_Scratchpad_3_Register, SIZE_DW }, /* 0x06 */ 2746285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_0, PCIBAR0, V_Host_Scratchpad_0_Register, SIZE_DW }, /* 0x07 */ 2747285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_1, PCIBAR0, V_Host_Scratchpad_1_Register, SIZE_DW }, /* 0x08 */ 2748285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_2, PCIBAR0, V_Host_Scratchpad_2_Register, SIZE_DW }, /* 0x09 */ 2749285809Sscottl { GEN_MSGU_HOST_SCRATCH_PAD_3, PCIBAR0, V_Host_Scratchpad_3_Register, SIZE_DW }, /* 0x0a */ 2750285809Sscottl { GEN_MSGU_ODMR, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register, SIZE_DW }, /* 0x0b */ 2751285809Sscottl { GEN_PCIE_TRIGGER, PCIBAR0, PCIE_TRIGGER_ON_REGISTER_READ, SIZE_DW }, /* 0x0c */ 2752285809Sscottl { GEN_SPC_REG_RESET, PCIBAR0, V_SoftResetRegister, SIZE_DW }, /* 0x0d */ 2753285809Sscottl}; 2754285809Sscottl 2755285809Sscottl 2756285809Sscottl/*******************************************************************************/ 2757285809Sscottl/** 2758285809Sscottl * 2759285809Sscottl * \brief 2760285809Sscottl * \param agsaRoot Pointer to a data structure containing both application 2761285809Sscottl * and LL layer context handles 2762285809Sscottl * \param Spc_type Device Id of hardware 2763285809Sscottl * 2764285809Sscottl * Return: 2765285809Sscottl * None 2766285809Sscottl */ 2767285809Sscottl/*******************************************************************************/ 2768285809SscottlGLOBAL void siUpdateBarOffsetTable(agsaRoot_t *agRoot, 2769285809Sscottl bit32 Spc_Type 2770285809Sscottl ) 2771285809Sscottl{ 2772285809Sscottl 2773285809Sscottl agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); 2774285809Sscottl bit32 x; 2775285809Sscottl 2776285809Sscottl smTraceFuncEnter(hpDBG_VERY_LOUD,"mf"); 2777285809Sscottl 2778285809Sscottl smTrace(hpDBG_VERY_LOUD,"9A",Spc_Type); 2779285809Sscottl /* TP:9A Spc_Type */ 2780285809Sscottl 2781285809Sscottl if(Spc_Type == VEN_DEV_SPC) 2782285809Sscottl { 2783285809Sscottl si_memcpy(&saRoot->SpcBarOffset, SPCTable, sizeof(SPCTable)); 2784285809Sscottl SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPCTable) sizeof(agsaBarOffset_t)sizeof(SPCTable) / sizeof(agsaBarOffset_t) %X %X %X\n", 2785285809Sscottl (unsigned int)sizeof(SPCTable), (unsigned int)sizeof(agsaBarOffset_t), 2786285809Sscottl (unsigned int)(sizeof(SPCTable) / sizeof(agsaBarOffset_t)) 2787285809Sscottl )); 2788285809Sscottl } 2789285809Sscottl else /* VEN_DEV_SPCV */ 2790285809Sscottl { 2791285809Sscottl si_memcpy(&saRoot->SpcBarOffset, SPC_V_Table, sizeof(SPC_V_Table)); 2792285809Sscottl SA_DBG5(("siUpdateBarOffsetTable:sizeof(SPC_V_Table) sizeof(agsaBarOffset_t)sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t) %X %X %X\n", 2793285809Sscottl (unsigned int)sizeof(SPC_V_Table), 2794285809Sscottl (unsigned int)sizeof(agsaBarOffset_t), 2795285809Sscottl (unsigned int)(sizeof(SPC_V_Table) / sizeof(agsaBarOffset_t)) 2796285809Sscottl )); 2797285809Sscottl } 2798285809Sscottl 2799285809Sscottl for(x=0;x < sizeof(SPCTable) / sizeof(agsaBarOffset_t);x++) 2800285809Sscottl { 2801285809Sscottl 2802285809Sscottl SA_DBG4(("%8X: %8X %8X %8X\n",saRoot->SpcBarOffset[x].Generic, 2803285809Sscottl saRoot->SpcBarOffset[x].Bar, 2804285809Sscottl saRoot->SpcBarOffset[x].Offset, 2805285809Sscottl saRoot->SpcBarOffset[x].Length 2806285809Sscottl )); 2807285809Sscottl if(saRoot->SpcBarOffset[x].Generic != x) 2808285809Sscottl { 2809285809Sscottl SA_DBG1(("siUpdateBarOffsetTable: saRoot->SpcBarOffset[%x].Generic %X != %X\n",x, saRoot->SpcBarOffset[x].Generic, x)); 2810285809Sscottl } 2811285809Sscottl } 2812285809Sscottl 2813285809Sscottl smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "mf"); 2814285809Sscottl} 2815285809Sscottl 2816285809Sscottl 2817285809Sscottl 2818285809SscottlGLOBAL bit32 siHalRegReadExt( agsaRoot_t *agRoot, 2819285809Sscottl bit32 generic, 2820285809Sscottl bit32 regOffset 2821285809Sscottl ) 2822285809Sscottl{ 2823285809Sscottl 2824285809Sscottl agsaBarOffset_t * Table = agNULL; 2825285809Sscottl bit32 retVal; 2826285809Sscottl 2827285809Sscottl /* sanity check */ 2828285809Sscottl SA_ASSERT( (agNULL != agRoot), "agRoot"); 2829285809Sscottl Table = WHATTABLE(agRoot); 2830285809Sscottl SA_ASSERT( (agNULL != Table), "Table"); 2831285809Sscottl 2832285809Sscottl/* 2833285809Sscottl if(Table[generic].Offset != regOffset) 2834285809Sscottl { 2835285809Sscottl 2836285809Sscottl SA_DBG1(("siHalRegReadExt: Table[%x].Offset %x != regOffset %x\n",generic, 2837285809Sscottl Table[generic].Offset, 2838285809Sscottl regOffset )); 2839285809Sscottl } 2840285809Sscottl*/ 2841285809Sscottl 2842285809Sscottl if(Table[generic].Bar) 2843285809Sscottl { 2844285809Sscottl retVal = ossaHwRegReadExt(agRoot, 2845285809Sscottl Table[generic].Bar, 2846285809Sscottl Table[generic].Offset); 2847285809Sscottl } 2848285809Sscottl else 2849285809Sscottl { 2850285809Sscottl retVal = ossaHwRegRead(agRoot, 2851285809Sscottl Table[generic].Offset); 2852285809Sscottl } 2853285809Sscottl 2854285809Sscottl return(retVal); 2855285809Sscottl} 2856285809Sscottl 2857285809Sscottl 2858285809SscottlGLOBAL void siHalRegWriteExt( 2859285809Sscottl agsaRoot_t *agRoot, 2860285809Sscottl bit32 generic, 2861285809Sscottl bit32 regOffset, 2862285809Sscottl bit32 regValue 2863285809Sscottl ) 2864285809Sscottl{ 2865285809Sscottl agsaBarOffset_t * Table = agNULL; 2866285809Sscottl 2867285809Sscottl /* sanity check */ 2868285809Sscottl SA_ASSERT( (agNULL != agRoot), "agRoot"); 2869285809Sscottl 2870285809Sscottl Table = WHATTABLE(agRoot); 2871285809Sscottl SA_ASSERT( (agNULL != Table), "Table"); 2872285809Sscottl 2873285809Sscottl 2874285809Sscottl/* 2875285809Sscottl if(Table[generic].Offset != regOffset) 2876285809Sscottl { 2877285809Sscottl 2878285809Sscottl SA_DBG1(("siHalRegWriteExt: Table[%x].Offset %x != regOffset %x\n",generic, 2879285809Sscottl Table[generic].Offset, 2880285809Sscottl regOffset )); 2881285809Sscottl } 2882285809Sscottl*/ 2883285809Sscottl 2884285809Sscottl SA_DBG6(("siHalRegWriteExt: Bar %x Offset %8X Wrote %8X\n", 2885285809Sscottl Table[generic].Bar, 2886285809Sscottl Table[generic].Offset, 2887285809Sscottl regValue )); 2888285809Sscottl 2889285809Sscottl 2890285809Sscottl if(Table[generic].Bar) 2891285809Sscottl { 2892285809Sscottl ossaHwRegWriteExt(agRoot, 2893285809Sscottl Table[generic].Bar, 2894285809Sscottl Table[generic].Offset, 2895285809Sscottl regValue ); 2896285809Sscottl }else 2897285809Sscottl { 2898285809Sscottl ossaHwRegWrite(agRoot, 2899285809Sscottl Table[generic].Offset, 2900285809Sscottl regValue ); 2901285809Sscottl } 2902285809Sscottl} 2903285809Sscottl 2904285809Sscottl 2905285809Sscottl 2906285809Sscottl 2907285809SscottlGLOBAL void siPCITriger(agsaRoot_t *agRoot) 2908285809Sscottl{ 2909285809Sscottl 2910285809Sscottl SA_DBG1(("siPCITriger: Read PCIe Bar zero plus 0x%x\n", PCIE_TRIGGER_ON_REGISTER_READ)); 2911285809Sscottl ossaHwRegReadExt(agRoot,PCIBAR0 ,PCIE_TRIGGER_ON_REGISTER_READ ); 2912285809Sscottl} 2913285809Sscottl 2914285809Sscottl 2915285809SscottlGLOBAL bit32 siGetPciBar( 2916285809Sscottl agsaRoot_t *agRoot 2917285809Sscottl ) 2918285809Sscottl{ 2919285809Sscottl bit32 MSGUCfgTblBase = 0; 2920285809Sscottl bit32 pcibar = 0; 2921285809Sscottl MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2922285809Sscottl pcibar = (MSGUCfgTblBase & SCRATCH_PAD0_BAR_MASK) >> SHIFT26; 2923285809Sscottl /* get pci Bar index */ 2924285809Sscottl pcibar = (bit8)mpiGetPCIBarIndex(agRoot, pcibar); 2925285809Sscottl 2926285809Sscottl return(pcibar); 2927285809Sscottl} 2928285809Sscottl 2929285809SscottlGLOBAL bit32 siGetTableOffset( 2930285809Sscottl agsaRoot_t *agRoot, 2931285809Sscottl bit32 TableOffsetInTable 2932285809Sscottl ) 2933285809Sscottl{ 2934285809Sscottl bit32 TableOffset; 2935285809Sscottl bit32 MSGUCfgTblBase; 2936285809Sscottl /* read scratch pad0 to get PCI BAR and offset of configuration table */ 2937285809Sscottl MSGUCfgTblBase = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0); 2938285809Sscottl 2939285809Sscottl MSGUCfgTblBase &= SCRATCH_PAD0_OFFSET_MASK; 2940285809Sscottl 2941285809Sscottl TableOffset = ossaHwRegReadExt(agRoot,siGetPciBar(agRoot) ,MSGUCfgTblBase +TableOffsetInTable ); 2942285809Sscottl SA_DBG4(("GetTableOffset:TableOffset with size 0x%x\n", TableOffset)); 2943285809Sscottl 2944285809Sscottl /* Mask off size */ 2945285809Sscottl TableOffset &= 0xFFFFFF; 2946285809Sscottl TableOffset +=MSGUCfgTblBase; 2947285809Sscottl return(TableOffset); 2948285809Sscottl 2949285809Sscottl} 2950285809Sscottl 2951285809Sscottl 2952285809SscottlGLOBAL void siCheckQs( 2953285809Sscottl agsaRoot_t *agRoot 2954285809Sscottl ) 2955285809Sscottl{ 2956285809Sscottl agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData); 2957285809Sscottl 2958285809Sscottl mpiOCQueue_t *circularOQ; 2959285809Sscottl mpiICQueue_t *circularIQ; 2960285809Sscottl int i; 2961285809Sscottl 2962285809Sscottl for ( i = 0; i < saRoot->QueueConfig.numInboundQueues; i++ ) 2963285809Sscottl { 2964285809Sscottl circularIQ = &saRoot->inboundQueue[i]; 2965285809Sscottl 2966285809Sscottl OSSA_READ_LE_32(circularIQ->agRoot, &circularIQ->consumerIdx, circularIQ->ciPointer, 0); 2967285809Sscottl if(circularIQ->producerIdx != circularIQ->consumerIdx) 2968285809Sscottl { 2969285809Sscottl SA_DBG1(("siCheckQs: In Q %d PI 0x%03x CI 0x%03x (%d) \n",i, 2970285809Sscottl circularIQ->producerIdx, 2971285809Sscottl circularIQ->consumerIdx, 2972285809Sscottl (circularIQ->producerIdx > circularIQ->consumerIdx ? (circularIQ->producerIdx - circularIQ->consumerIdx) : (circularIQ->numElements - circularIQ->consumerIdx ) + circularIQ->producerIdx))); 2973285809Sscottl } 2974285809Sscottl } 2975285809Sscottl 2976285809Sscottl for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 2977285809Sscottl { 2978285809Sscottl circularOQ = &saRoot->outboundQueue[i]; 2979285809Sscottl OSSA_READ_LE_32(circularOQ->agRoot, &circularOQ->producerIdx, circularOQ->piPointer, 0); 2980285809Sscottl if(circularOQ->producerIdx != circularOQ->consumerIdx) 2981285809Sscottl { 2982285809Sscottl SA_DBG1(("siCheckQs: Out Q %d PI 0x%03x CI 0x%03x (%d) \n",i, 2983285809Sscottl circularOQ->producerIdx, 2984285809Sscottl circularOQ->consumerIdx, 2985285809Sscottl (circularOQ->producerIdx > circularOQ->consumerIdx ? (circularOQ->producerIdx - circularOQ->consumerIdx) : (circularOQ->numElements - circularOQ->consumerIdx ) + circularOQ->producerIdx))); 2986285809Sscottl 2987285809Sscottl } 2988285809Sscottl } 2989285809Sscottl 2990285809Sscottl} 2991285809SscottlGLOBAL void siPciCpyMem(agsaRoot_t *agRoot, 2992285809Sscottl bit32 soffset, 2993285809Sscottl const void *dst, 2994285809Sscottl bit32 DWcount, 2995285809Sscottl bit32 busBaseNumber 2996285809Sscottl ) 2997285809Sscottl{ 2998285809Sscottl bit32 i, val,offset; 2999285809Sscottl bit32 *dst1; 3000285809Sscottl 3001285809Sscottl dst1 = (bit32 *)dst; 3002285809Sscottl 3003285809Sscottl SA_DBG1(("siPciCpyMem:copy DWcount %d from offset 0x%x to %p\n",DWcount,soffset,dst)); 3004285809Sscottl 3005285809Sscottl for (i= 0; i < DWcount; i+=4,dst1++) 3006285809Sscottl { 3007285809Sscottl offset = (soffset + i / 4); 3008285809Sscottl SA_ASSERT( (offset < (64 * 1024)), "siPciCpyMem offset too large"); 3009285809Sscottl if(offset < (64 * 1024)) 3010285809Sscottl { 3011285809Sscottl val = ossaHwRegReadExt(agRoot, busBaseNumber, offset); 3012285809Sscottl *dst1 = BIT32_TO_LEBIT32(val); 3013285809Sscottl } 3014285809Sscottl } 3015285809Sscottl 3016285809Sscottl return; 3017285809Sscottl} 3018