if_pcn.c revision 67089
11573Srgrimes/* 21573Srgrimes * Copyright (c) 2000 Berkeley Software Design, Inc. 31573Srgrimes * Copyright (c) 1997, 1998, 1999, 2000 41573Srgrimes * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 51573Srgrimes * 61573Srgrimes * Redistribution and use in source and binary forms, with or without 71573Srgrimes * modification, are permitted provided that the following conditions 81573Srgrimes * are met: 91573Srgrimes * 1. Redistributions of source code must retain the above copyright 101573Srgrimes * notice, this list of conditions and the following disclaimer. 111573Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121573Srgrimes * notice, this list of conditions and the following disclaimer in the 131573Srgrimes * documentation and/or other materials provided with the distribution. 141573Srgrimes * 3. All advertising materials mentioning features or use of this software 151573Srgrimes * must display the following acknowledgement: 16249808Semaste * This product includes software developed by Bill Paul. 171573Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 181573Srgrimes * may be used to endorse or promote products derived from this software 191573Srgrimes * without specific prior written permission. 201573Srgrimes * 211573Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 221573Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 231573Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 241573Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 251573Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 261573Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 271573Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 281573Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 291573Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 301573Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 311573Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 321573Srgrimes * 331573Srgrimes * $FreeBSD: head/sys/pci/if_pcn.c 67089 2000-10-13 18:35:49Z wpaul $ 341573Srgrimes */ 351573Srgrimes 3692986Sobrien/* 3792986Sobrien * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 381573Srgrimes * from http://www.amd.com. 3971579Sdeischen * 401573Srgrimes * Written by Bill Paul <wpaul@osd.bsdi.com> 411573Srgrimes */ 421573Srgrimes 431573Srgrimes/* 441573Srgrimes * The AMD PCnet/PCI controllers are more advanced and functional 45176629Sjhb * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 4671579Sdeischen * backwards compatibility with the LANCE and thus can be made 471573Srgrimes * to work with older LANCE drivers. This is in fact how the 481573Srgrimes * PCnet/PCI chips were supported in FreeBSD originally. The trouble 491573Srgrimes * is that the PCnet/PCI devices offer several performance enhancements 501573Srgrimes * which can't be exploited in LANCE compatibility mode. Chief among 511573Srgrimes * these enhancements is the ability to perform PCI DMA operations 521573Srgrimes * using 32-bit addressing (which eliminates the need for ISA 531573Srgrimes * bounce-buffering), and special receive buffer alignment (which 5492889Sobrien * allows the receive handler to pass packets to the upper protocol 551573Srgrimes * layers without copying on both the x86 and alpha platforms). 561573Srgrimes */ 57176628Sjhb 58176628Sjhb#include <sys/param.h> 59176628Sjhb#include <sys/systm.h> 60176628Sjhb#include <sys/sockio.h> 61176628Sjhb#include <sys/mbuf.h> 62176628Sjhb#include <sys/malloc.h> 63176628Sjhb#include <sys/kernel.h> 64176628Sjhb#include <sys/socket.h> 65176628Sjhb 66176628Sjhb#include <net/if.h> 67176628Sjhb#include <net/if_arp.h> 68176628Sjhb#include <net/ethernet.h> 691573Srgrimes#include <net/if_dl.h> 701573Srgrimes#include <net/if_media.h> 711573Srgrimes 721573Srgrimes#include <net/bpf.h> 7356698Sjasone 741573Srgrimes#include <vm/vm.h> /* for vtophys */ 751573Srgrimes#include <vm/pmap.h> /* for vtophys */ 761573Srgrimes#include <machine/clock.h> /* for DELAY */ 771573Srgrimes#include <machine/bus_pio.h> 781573Srgrimes#include <machine/bus_memio.h> 791573Srgrimes#include <machine/bus.h> 801573Srgrimes#include <machine/resource.h> 811573Srgrimes#include <sys/bus.h> 821573Srgrimes#include <sys/rman.h> 83243731Sjilles 84243731Sjilles#include <dev/mii/mii.h> 85243731Sjilles#include <dev/mii/miivar.h> 86243731Sjilles 87243731Sjilles#include <pci/pcireg.h> 88243731Sjilles#include <pci/pcivar.h> 891573Srgrimes 901573Srgrimes#define PCN_USEIOSPACE 911573Srgrimes 9282807Sache#include <pci/if_pcnreg.h> 9382807Sache 941573SrgrimesMODULE_DEPEND(pcn, miibus, 1, 1, 1); 951573Srgrimes 961573Srgrimes/* "controller miibus0" required. See GENERIC if you get errors here. */ 971573Srgrimes#include "miibus_if.h" 981573Srgrimes 991573Srgrimes#ifndef lint 1001573Srgrimesstatic const char rcsid[] = 1011573Srgrimes "$FreeBSD: head/sys/pci/if_pcn.c 67089 2000-10-13 18:35:49Z wpaul $"; 1021573Srgrimes#endif 1031573Srgrimes 1041573Srgrimes/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct pcn_type pcn_devs[] = { 108 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 109 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 110 { 0, 0, NULL } 111}; 112 113static u_int32_t pcn_csr_read __P((struct pcn_softc *, int)); 114static void pcn_csr_write __P((struct pcn_softc *, int, int)); 115static u_int32_t pcn_bcr_read __P((struct pcn_softc *, int)); 116static void pcn_bcr_write __P((struct pcn_softc *, int, int)); 117 118static int pcn_probe __P((device_t)); 119static int pcn_attach __P((device_t)); 120static int pcn_detach __P((device_t)); 121 122static int pcn_newbuf __P((struct pcn_softc *, int, struct mbuf *)); 123static int pcn_encap __P((struct pcn_softc *, 124 struct mbuf *, u_int32_t *)); 125static void pcn_rxeof __P((struct pcn_softc *)); 126static void pcn_txeof __P((struct pcn_softc *)); 127static void pcn_intr __P((void *)); 128static void pcn_tick __P((void *)); 129static void pcn_start __P((struct ifnet *)); 130static int pcn_ioctl __P((struct ifnet *, u_long, caddr_t)); 131static void pcn_init __P((void *)); 132static void pcn_stop __P((struct pcn_softc *)); 133static void pcn_watchdog __P((struct ifnet *)); 134static void pcn_shutdown __P((device_t)); 135static int pcn_ifmedia_upd __P((struct ifnet *)); 136static void pcn_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 137 138static int pcn_miibus_readreg __P((device_t, int, int)); 139static int pcn_miibus_writereg __P((device_t, int, int, int)); 140static void pcn_miibus_statchg __P((device_t)); 141 142static void pcn_setmulti __P((struct pcn_softc *)); 143static u_int32_t pcn_crc __P((caddr_t)); 144static void pcn_reset __P((struct pcn_softc *)); 145static int pcn_list_rx_init __P((struct pcn_softc *)); 146static int pcn_list_tx_init __P((struct pcn_softc *)); 147 148#ifdef PCN_USEIOSPACE 149#define PCN_RES SYS_RES_IOPORT 150#define PCN_RID PCN_PCI_LOIO 151#else 152#define PCN_RES SYS_RES_MEMORY 153#define PCN_RID PCN_PCI_LOMEM 154#endif 155 156static device_method_t pcn_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, pcn_probe), 159 DEVMETHOD(device_attach, pcn_attach), 160 DEVMETHOD(device_detach, pcn_detach), 161 DEVMETHOD(device_shutdown, pcn_shutdown), 162 163 /* bus interface */ 164 DEVMETHOD(bus_print_child, bus_generic_print_child), 165 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 171 172 { 0, 0 } 173}; 174 175static driver_t pcn_driver = { 176 "pcn", 177 pcn_methods, 178 sizeof(struct pcn_softc) 179}; 180 181static devclass_t pcn_devclass; 182 183DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 184DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 185 186#define PCN_CSR_SETBIT(sc, reg, x) \ 187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 188 189#define PCN_CSR_CLRBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 191 192#define PCN_BCR_SETBIT(sc, reg, x) \ 193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 194 195#define PCN_BCR_CLRBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 197 198static u_int32_t pcn_csr_read(sc, reg) 199 struct pcn_softc *sc; 200 int reg; 201{ 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204} 205 206static void pcn_csr_write(sc, reg, val) 207 struct pcn_softc *sc; 208 int reg; 209{ 210 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 211 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 212 return; 213} 214 215static u_int32_t pcn_bcr_read(sc, reg) 216 struct pcn_softc *sc; 217 int reg; 218{ 219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 220 return(CSR_READ_4(sc, PCN_IO32_BDP)); 221} 222 223static void pcn_bcr_write(sc, reg, val) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 229 return; 230} 231 232static int pcn_miibus_readreg(dev, phy, reg) 233 device_t dev; 234 int phy, reg; 235{ 236 struct pcn_softc *sc; 237 int val; 238 239 sc = device_get_softc(dev); 240 241 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 242 return(0); 243 244 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 245 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 246 if (val == 0xFFFF) 247 return(0); 248 249 sc->pcn_phyaddr = phy; 250 251 return(val); 252} 253 254static int pcn_miibus_writereg(dev, phy, reg, data) 255 device_t dev; 256 int phy, reg, data; 257{ 258 struct pcn_softc *sc; 259 260 sc = device_get_softc(dev); 261 262 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 263 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 264 265 return(0); 266} 267 268static void pcn_miibus_statchg(dev) 269 device_t dev; 270{ 271 struct pcn_softc *sc; 272 struct mii_data *mii; 273 274 sc = device_get_softc(dev); 275 mii = device_get_softc(sc->pcn_miibus); 276 277 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 278 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 279 } else { 280 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 281 } 282 283 return; 284} 285 286#define DC_POLY 0xEDB88320 287 288static u_int32_t pcn_crc(addr) 289 caddr_t addr; 290{ 291 u_int32_t idx, bit, data, crc; 292 293 /* Compute CRC for the address value. */ 294 crc = 0xFFFFFFFF; /* initial value */ 295 296 for (idx = 0; idx < 6; idx++) { 297 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 298 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 299 } 300 301 return ((crc >> 26) & 0x3F); 302} 303 304static void pcn_setmulti(sc) 305 struct pcn_softc *sc; 306{ 307 struct ifnet *ifp; 308 struct ifmultiaddr *ifma; 309 u_int32_t h, i; 310 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 311 312 ifp = &sc->arpcom.ac_if; 313 314 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 315 316 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 317 for (i = 0; i < 4; i++) 318 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 319 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 320 return; 321 } 322 323 /* first, zot all the existing hash bits */ 324 for (i = 0; i < 4; i++) 325 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 326 327 /* now program new ones */ 328 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 329 ifma = ifma->ifma_link.le_next) { 330 if (ifma->ifma_addr->sa_family != AF_LINK) 331 continue; 332 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 333 hashes[h >> 4] |= 1 << (h & 0xF); 334 } 335 336 for (i = 0; i < 4; i++) 337 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 338 339 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 340 341 return; 342} 343 344static void pcn_reset(sc) 345 struct pcn_softc *sc; 346{ 347 /* 348 * Issue a reset by reading from the RESET register. 349 * Note that we don't know if the chip is operating in 350 * 16-bit or 32-bit mode at this point, so we attempt 351 * to reset the chip both ways. If one fails, the other 352 * will succeed. 353 */ 354 CSR_READ_2(sc, PCN_IO16_RESET); 355 CSR_READ_4(sc, PCN_IO32_RESET); 356 357 /* Wait a little while for the chip to get its brains in order. */ 358 DELAY(1000); 359 360 /* Select 32-bit (DWIO) mode */ 361 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 362 363 /* Select software style 3. */ 364 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 365 366 return; 367} 368 369/* 370 * Probe for an AMD chip. Check the PCI vendor and device 371 * IDs against our list and return a device name if we find a match. 372 */ 373static int pcn_probe(dev) 374 device_t dev; 375{ 376 struct pcn_type *t; 377 struct pcn_softc *sc; 378 int rid; 379 u_int32_t chip_id; 380 381 t = pcn_devs; 382 sc = device_get_softc(dev); 383 384 while(t->pcn_name != NULL) { 385 if ((pci_get_vendor(dev) == t->pcn_vid) && 386 (pci_get_device(dev) == t->pcn_did)) { 387 /* 388 * Temporarily map the I/O space 389 * so we can read the chip ID register. 390 */ 391 rid = PCN_RID; 392 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 393 0, ~0, 1, RF_ACTIVE); 394 if (sc->pcn_res == NULL) { 395 device_printf(dev, 396 "couldn't map ports/memory\n"); 397 return(ENXIO); 398 } 399 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 400 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 401 mtx_init(&sc->pcn_mtx, 402 device_get_nameunit(dev), MTX_DEF); 403 PCN_LOCK(sc); 404 pcn_reset(sc); 405 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 406 chip_id <<= 16; 407 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 408 bus_release_resource(dev, PCN_RES, 409 PCN_RID, sc->pcn_res); 410 PCN_UNLOCK(sc); 411 mtx_destroy(&sc->pcn_mtx); 412 chip_id >>= 12; 413 sc->pcn_type = chip_id & PART_MASK; 414 switch(sc->pcn_type) { 415 case Am79C971: 416 case Am79C972: 417 case Am79C973: 418 case Am79C975: 419 case Am79C976: 420 case Am79C978: 421 break; 422 default: 423 return(ENXIO); 424 break; 425 } 426 device_set_desc(dev, t->pcn_name); 427 return(0); 428 } 429 t++; 430 } 431 432 return(ENXIO); 433} 434 435/* 436 * Attach the interface. Allocate softc structures, do ifmedia 437 * setup and ethernet/BPF attach. 438 */ 439static int pcn_attach(dev) 440 device_t dev; 441{ 442 u_int32_t eaddr[2]; 443 u_int32_t command; 444 struct pcn_softc *sc; 445 struct ifnet *ifp; 446 int unit, error = 0, rid; 447 448 sc = device_get_softc(dev); 449 unit = device_get_unit(dev); 450 451 /* 452 * Handle power management nonsense. 453 */ 454 455 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 456 if (command == 0x01) { 457 458 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 459 if (command & PCN_PSTATE_MASK) { 460 u_int32_t iobase, membase, irq; 461 462 /* Save important PCI config data. */ 463 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 464 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 465 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 466 467 /* Reset the power state. */ 468 printf("pcn%d: chip is in D%d power mode " 469 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 470 command &= 0xFFFFFFFC; 471 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 472 473 /* Restore PCI config data. */ 474 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 475 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 476 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 477 } 478 } 479 480 /* 481 * Map control/status registers. 482 */ 483 command = pci_read_config(dev, PCIR_COMMAND, 4); 484 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 485 pci_write_config(dev, PCIR_COMMAND, command, 4); 486 command = pci_read_config(dev, PCIR_COMMAND, 4); 487 488#ifdef PCN_USEIOSPACE 489 if (!(command & PCIM_CMD_PORTEN)) { 490 printf("pcn%d: failed to enable I/O ports!\n", unit); 491 error = ENXIO;; 492 goto fail; 493 } 494#else 495 if (!(command & PCIM_CMD_MEMEN)) { 496 printf("pcn%d: failed to enable memory mapping!\n", unit); 497 error = ENXIO;; 498 goto fail; 499 } 500#endif 501 502 rid = PCN_RID; 503 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 504 0, ~0, 1, RF_ACTIVE); 505 506 if (sc->pcn_res == NULL) { 507 printf("pcn%d: couldn't map ports/memory\n", unit); 508 error = ENXIO; 509 goto fail; 510 } 511 512 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 513 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 514 515 /* Allocate interrupt */ 516 rid = 0; 517 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 518 RF_SHAREABLE | RF_ACTIVE); 519 520 if (sc->pcn_irq == NULL) { 521 printf("pcn%d: couldn't map interrupt\n", unit); 522 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 523 error = ENXIO; 524 goto fail; 525 } 526 527 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 528 pcn_intr, sc, &sc->pcn_intrhand); 529 530 if (error) { 531 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 532 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 533 printf("pcn%d: couldn't set up irq\n", unit); 534 goto fail; 535 } 536 537 /* Initialize our mutex. */ 538 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_DEF); 539 PCN_LOCK(sc); 540 541 /* Reset the adapter. */ 542 pcn_reset(sc); 543 544 /* 545 * Get station address from the EEPROM. 546 */ 547 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 548 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 549 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 550 551 /* 552 * An AMD chip was detected. Inform the world. 553 */ 554 printf("pcn%d: Ethernet address: %6D\n", unit, 555 sc->arpcom.ac_enaddr, ":"); 556 557 sc->pcn_unit = unit; 558 callout_handle_init(&sc->pcn_stat_ch); 559 560 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 561 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 562 563 if (sc->pcn_ldata == NULL) { 564 printf("pcn%d: no memory for list buffers!\n", unit); 565 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 566 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 567 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 568 error = ENXIO; 569 goto fail; 570 } 571 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 572 573 ifp = &sc->arpcom.ac_if; 574 ifp->if_softc = sc; 575 ifp->if_unit = unit; 576 ifp->if_name = "pcn"; 577 ifp->if_mtu = ETHERMTU; 578 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 579 ifp->if_ioctl = pcn_ioctl; 580 ifp->if_output = ether_output; 581 ifp->if_start = pcn_start; 582 ifp->if_watchdog = pcn_watchdog; 583 ifp->if_init = pcn_init; 584 ifp->if_baudrate = 10000000; 585 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 586 587 /* 588 * Do MII setup. 589 */ 590 if (mii_phy_probe(dev, &sc->pcn_miibus, 591 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 592 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 593 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 594 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 595 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 596 error = ENXIO; 597 goto fail; 598 } 599 600 /* 601 * Call MI attach routine. 602 */ 603 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 604 callout_handle_init(&sc->pcn_stat_ch); 605 PCN_UNLOCK(sc); 606 return(0); 607 608fail: 609 PCN_UNLOCK(sc); 610 mtx_destroy(&sc->pcn_mtx); 611 612 return(error); 613} 614 615static int pcn_detach(dev) 616 device_t dev; 617{ 618 struct pcn_softc *sc; 619 struct ifnet *ifp; 620 621 sc = device_get_softc(dev); 622 ifp = &sc->arpcom.ac_if; 623 624 PCN_LOCK(sc); 625 626 pcn_reset(sc); 627 pcn_stop(sc); 628 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 629 630 if (sc->pcn_miibus != NULL) { 631 bus_generic_detach(dev); 632 device_delete_child(dev, sc->pcn_miibus); 633 } 634 635 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 636 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 637 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 638 639 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 640 PCN_UNLOCK(sc); 641 642 mtx_destroy(&sc->pcn_mtx); 643 644 return(0); 645} 646 647/* 648 * Initialize the transmit descriptors. 649 */ 650static int pcn_list_tx_init(sc) 651 struct pcn_softc *sc; 652{ 653 struct pcn_list_data *ld; 654 struct pcn_ring_data *cd; 655 int i; 656 657 cd = &sc->pcn_cdata; 658 ld = sc->pcn_ldata; 659 660 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 661 cd->pcn_tx_chain[i] = NULL; 662 ld->pcn_tx_list[i].pcn_tbaddr = 0; 663 ld->pcn_tx_list[i].pcn_txctl = 0; 664 ld->pcn_tx_list[i].pcn_txstat = 0; 665 } 666 667 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 668 669 return(0); 670} 671 672 673/* 674 * Initialize the RX descriptors and allocate mbufs for them. 675 */ 676static int pcn_list_rx_init(sc) 677 struct pcn_softc *sc; 678{ 679 struct pcn_list_data *ld; 680 struct pcn_ring_data *cd; 681 int i; 682 683 ld = sc->pcn_ldata; 684 cd = &sc->pcn_cdata; 685 686 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 687 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 688 return(ENOBUFS); 689 } 690 691 cd->pcn_rx_prod = 0; 692 693 return(0); 694} 695 696/* 697 * Initialize an RX descriptor and attach an MBUF cluster. 698 */ 699static int pcn_newbuf(sc, idx, m) 700 struct pcn_softc *sc; 701 int idx; 702 struct mbuf *m; 703{ 704 struct mbuf *m_new = NULL; 705 struct pcn_rx_desc *c; 706 707 c = &sc->pcn_ldata->pcn_rx_list[idx]; 708 709 if (m == NULL) { 710 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 711 if (m_new == NULL) { 712 printf("pcn%d: no memory for rx list " 713 "-- packet dropped!\n", sc->pcn_unit); 714 return(ENOBUFS); 715 } 716 717 MCLGET(m_new, M_DONTWAIT); 718 if (!(m_new->m_flags & M_EXT)) { 719 printf("pcn%d: no memory for rx list " 720 "-- packet dropped!\n", sc->pcn_unit); 721 m_freem(m_new); 722 return(ENOBUFS); 723 } 724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 725 } else { 726 m_new = m; 727 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 728 m_new->m_data = m_new->m_ext.ext_buf; 729 } 730 731 m_adj(m_new, ETHER_ALIGN); 732 733 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 734 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 735 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 736 c->pcn_bufsz |= PCN_RXLEN_MBO; 737 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 738 739 return(0); 740} 741 742/* 743 * A frame has been uploaded: pass the resulting mbuf chain up to 744 * the higher level protocols. 745 */ 746static void pcn_rxeof(sc) 747 struct pcn_softc *sc; 748{ 749 struct ether_header *eh; 750 struct mbuf *m; 751 struct ifnet *ifp; 752 struct pcn_rx_desc *cur_rx; 753 int i; 754 755 ifp = &sc->arpcom.ac_if; 756 i = sc->pcn_cdata.pcn_rx_prod; 757 758 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 759 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 760 m = sc->pcn_cdata.pcn_rx_chain[i]; 761 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 762 763 /* 764 * If an error occurs, update stats, clear the 765 * status word and leave the mbuf cluster in place: 766 * it should simply get re-used next time this descriptor 767 * comes up in the ring. 768 */ 769 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 770 ifp->if_ierrors++; 771 pcn_newbuf(sc, i, m); 772 PCN_INC(i, PCN_RX_LIST_CNT); 773 continue; 774 } 775 776 if (pcn_newbuf(sc, i, NULL)) { 777 /* Ran out of mbufs; recycle this one. */ 778 pcn_newbuf(sc, i, m); 779 ifp->if_ierrors++; 780 PCN_INC(i, PCN_RX_LIST_CNT); 781 continue; 782 } 783 784 PCN_INC(i, PCN_RX_LIST_CNT); 785 786 /* No errors; receive the packet. */ 787 ifp->if_ipackets++; 788 eh = mtod(m, struct ether_header *); 789 m->m_len = m->m_pkthdr.len = 790 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 791 m->m_pkthdr.rcvif = ifp; 792 793 /* Remove header from mbuf and pass it on. */ 794 m_adj(m, sizeof(struct ether_header)); 795 ether_input(ifp, eh, m); 796 } 797 798 sc->pcn_cdata.pcn_rx_prod = i; 799 800 return; 801} 802 803/* 804 * A frame was downloaded to the chip. It's safe for us to clean up 805 * the list buffers. 806 */ 807 808static void pcn_txeof(sc) 809 struct pcn_softc *sc; 810{ 811 struct pcn_tx_desc *cur_tx = NULL; 812 struct ifnet *ifp; 813 u_int32_t idx; 814 815 ifp = &sc->arpcom.ac_if; 816 817 /* Clear the timeout timer. */ 818 ifp->if_timer = 0; 819 820 /* 821 * Go through our tx list and free mbufs for those 822 * frames that have been transmitted. 823 */ 824 idx = sc->pcn_cdata.pcn_tx_cons; 825 while (idx != sc->pcn_cdata.pcn_tx_prod) { 826 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 827 828 if (!PCN_OWN_TXDESC(cur_tx)) 829 break; 830 831 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 832 sc->pcn_cdata.pcn_tx_cnt--; 833 PCN_INC(idx, PCN_TX_LIST_CNT); 834 continue; 835 } 836 837 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 838 ifp->if_oerrors++; 839 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 840 ifp->if_collisions++; 841 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 842 ifp->if_collisions++; 843 } 844 845 ifp->if_collisions += 846 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 847 848 ifp->if_opackets++; 849 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 850 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 851 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 852 } 853 854 sc->pcn_cdata.pcn_tx_cnt--; 855 PCN_INC(idx, PCN_TX_LIST_CNT); 856 ifp->if_timer = 0; 857 } 858 859 sc->pcn_cdata.pcn_tx_cons = idx; 860 861 if (cur_tx != NULL) 862 ifp->if_flags &= ~IFF_OACTIVE; 863 864 return; 865} 866 867static void pcn_tick(xsc) 868 void *xsc; 869{ 870 struct pcn_softc *sc; 871 struct mii_data *mii; 872 struct ifnet *ifp; 873 874 sc = xsc; 875 ifp = &sc->arpcom.ac_if; 876 PCN_LOCK(sc); 877 878 mii = device_get_softc(sc->pcn_miibus); 879 mii_tick(mii); 880 881 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 882 sc->pcn_link = 0; 883 884 if (!sc->pcn_link) { 885 mii_pollstat(mii); 886 if (mii->mii_media_status & IFM_ACTIVE && 887 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 888 sc->pcn_link++; 889 if (ifp->if_snd.ifq_head != NULL) 890 pcn_start(ifp); 891 } 892 893 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 894 895 PCN_UNLOCK(sc); 896 897 return; 898} 899 900static void pcn_intr(arg) 901 void *arg; 902{ 903 struct pcn_softc *sc; 904 struct ifnet *ifp; 905 u_int32_t status; 906 907 sc = arg; 908 ifp = &sc->arpcom.ac_if; 909 910 /* Supress unwanted interrupts */ 911 if (!(ifp->if_flags & IFF_UP)) { 912 pcn_stop(sc); 913 return; 914 } 915 916 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 917 918 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 919 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 920 921 if (status & PCN_CSR_RINT) 922 pcn_rxeof(sc); 923 924 if (status & PCN_CSR_TINT) 925 pcn_txeof(sc); 926 927 if (status & PCN_CSR_ERR) { 928 pcn_init(sc); 929 break; 930 } 931 } 932 933 if (ifp->if_snd.ifq_head != NULL) 934 pcn_start(ifp); 935 936 return; 937} 938 939/* 940 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 941 * pointers to the fragment pointers. 942 */ 943static int pcn_encap(sc, m_head, txidx) 944 struct pcn_softc *sc; 945 struct mbuf *m_head; 946 u_int32_t *txidx; 947{ 948 struct pcn_tx_desc *f = NULL; 949 struct mbuf *m; 950 int frag, cur, cnt = 0; 951 952 /* 953 * Start packing the mbufs in this chain into 954 * the fragment pointers. Stop when we run out 955 * of fragments or hit the end of the mbuf chain. 956 */ 957 m = m_head; 958 cur = frag = *txidx; 959 960 for (m = m_head; m != NULL; m = m->m_next) { 961 if (m->m_len != 0) { 962 if ((PCN_TX_LIST_CNT - 963 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 964 return(ENOBUFS); 965 f = &sc->pcn_ldata->pcn_tx_list[frag]; 966 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 967 f->pcn_txctl |= PCN_TXCTL_MBO; 968 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 969 if (cnt == 0) 970 f->pcn_txctl |= PCN_TXCTL_STP; 971 else 972 f->pcn_txctl |= PCN_TXCTL_OWN; 973 cur = frag; 974 PCN_INC(frag, PCN_TX_LIST_CNT); 975 cnt++; 976 } 977 } 978 979 if (m != NULL) 980 return(ENOBUFS); 981 982 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 983 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 984 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 985 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 986 sc->pcn_cdata.pcn_tx_cnt += cnt; 987 *txidx = frag; 988 989 return(0); 990} 991 992/* 993 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 994 * to the mbuf data regions directly in the transmit lists. We also save a 995 * copy of the pointers since the transmit list fragment pointers are 996 * physical addresses. 997 */ 998static void pcn_start(ifp) 999 struct ifnet *ifp; 1000{ 1001 struct pcn_softc *sc; 1002 struct mbuf *m_head = NULL; 1003 u_int32_t idx; 1004 1005 sc = ifp->if_softc; 1006 1007 PCN_LOCK(sc); 1008 1009 if (!sc->pcn_link) { 1010 PCN_UNLOCK(sc); 1011 return; 1012 } 1013 1014 idx = sc->pcn_cdata.pcn_tx_prod; 1015 1016 if (ifp->if_flags & IFF_OACTIVE) { 1017 PCN_UNLOCK(sc); 1018 return; 1019 } 1020 1021 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1022 IF_DEQUEUE(&ifp->if_snd, m_head); 1023 if (m_head == NULL) 1024 break; 1025 1026 if (pcn_encap(sc, m_head, &idx)) { 1027 IF_PREPEND(&ifp->if_snd, m_head); 1028 ifp->if_flags |= IFF_OACTIVE; 1029 break; 1030 } 1031 1032 /* 1033 * If there's a BPF listener, bounce a copy of this frame 1034 * to him. 1035 */ 1036 if (ifp->if_bpf) 1037 bpf_mtap(ifp, m_head); 1038 1039 } 1040 1041 /* Transmit */ 1042 sc->pcn_cdata.pcn_tx_prod = idx; 1043 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1044 1045 /* 1046 * Set a timeout in case the chip goes out to lunch. 1047 */ 1048 ifp->if_timer = 5; 1049 1050 PCN_UNLOCK(sc); 1051 1052 return; 1053} 1054 1055static void pcn_init(xsc) 1056 void *xsc; 1057{ 1058 struct pcn_softc *sc = xsc; 1059 struct ifnet *ifp = &sc->arpcom.ac_if; 1060 struct mii_data *mii = NULL; 1061 1062 PCN_LOCK(sc); 1063 1064 /* 1065 * Cancel pending I/O and free all RX/TX buffers. 1066 */ 1067 pcn_stop(sc); 1068 pcn_reset(sc); 1069 1070 mii = device_get_softc(sc->pcn_miibus); 1071 1072 /* Set MAC address */ 1073 pcn_csr_write(sc, PCN_CSR_PAR0, 1074 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1075 pcn_csr_write(sc, PCN_CSR_PAR1, 1076 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1077 pcn_csr_write(sc, PCN_CSR_PAR2, 1078 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1079 1080 /* Init circular RX list. */ 1081 if (pcn_list_rx_init(sc) == ENOBUFS) { 1082 printf("pcn%d: initialization failed: no " 1083 "memory for rx buffers\n", sc->pcn_unit); 1084 pcn_stop(sc); 1085 PCN_UNLOCK(sc); 1086 return; 1087 } 1088 1089 /* 1090 * Init tx descriptors. 1091 */ 1092 pcn_list_tx_init(sc); 1093 1094 /* Set up the mode register. */ 1095 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1096 1097 /* If we want promiscuous mode, set the allframes bit. */ 1098 if (ifp->if_flags & IFF_PROMISC) { 1099 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1100 } else { 1101 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1102 } 1103 1104 /* Set the capture broadcast bit to capture broadcast frames. */ 1105 if (ifp->if_flags & IFF_BROADCAST) { 1106 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1107 } else { 1108 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1109 } 1110 1111 /* 1112 * Load the multicast filter. 1113 */ 1114 pcn_setmulti(sc); 1115 1116 /* 1117 * Load the addresses of the RX and TX lists. 1118 */ 1119 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1120 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1121 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1122 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1123 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1124 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1125 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1126 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1127 1128 /* Set the RX and TX ring sizes. */ 1129 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1130 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1131 1132 /* We're not using the initialization block. */ 1133 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1134 1135 /* Enable fast suspend mode. */ 1136 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1137 1138 /* 1139 * Enable burst read and write. Also set the no underflow 1140 * bit. This will avoid transmit underruns in certain 1141 * conditions while still providing decent performance. 1142 */ 1143 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1144 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1145 1146 /* Enable graceful recovery from underflow. */ 1147 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1148 1149 /* Enable auto-padding of short TX frames. */ 1150 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1151 1152 /* Disable MII autoneg (we handle this ourselves). */ 1153 PCN_BCR_CLRBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1154 1155 if (sc->pcn_type == Am79C978) 1156 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1157 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1158 1159 /* Enable interrupts and start the controller running. */ 1160 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1161 1162 mii_mediachg(mii); 1163 1164 ifp->if_flags |= IFF_RUNNING; 1165 ifp->if_flags &= ~IFF_OACTIVE; 1166 1167 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1168 PCN_UNLOCK(sc); 1169 1170 return; 1171} 1172 1173/* 1174 * Set media options. 1175 */ 1176static int pcn_ifmedia_upd(ifp) 1177 struct ifnet *ifp; 1178{ 1179 struct pcn_softc *sc; 1180 struct mii_data *mii; 1181 1182 sc = ifp->if_softc; 1183 mii = device_get_softc(sc->pcn_miibus); 1184 1185 sc->pcn_link = 0; 1186 if (mii->mii_instance) { 1187 struct mii_softc *miisc; 1188 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1189 miisc = LIST_NEXT(miisc, mii_list)) 1190 mii_phy_reset(miisc); 1191 } 1192 mii_mediachg(mii); 1193 1194 return(0); 1195} 1196 1197/* 1198 * Report current media status. 1199 */ 1200static void pcn_ifmedia_sts(ifp, ifmr) 1201 struct ifnet *ifp; 1202 struct ifmediareq *ifmr; 1203{ 1204 struct pcn_softc *sc; 1205 struct mii_data *mii; 1206 1207 sc = ifp->if_softc; 1208 1209 mii = device_get_softc(sc->pcn_miibus); 1210 mii_pollstat(mii); 1211 ifmr->ifm_active = mii->mii_media_active; 1212 ifmr->ifm_status = mii->mii_media_status; 1213 1214 return; 1215} 1216 1217static int pcn_ioctl(ifp, command, data) 1218 struct ifnet *ifp; 1219 u_long command; 1220 caddr_t data; 1221{ 1222 struct pcn_softc *sc = ifp->if_softc; 1223 struct ifreq *ifr = (struct ifreq *) data; 1224 struct mii_data *mii = NULL; 1225 int error = 0; 1226 1227 PCN_LOCK(sc); 1228 1229 switch(command) { 1230 case SIOCSIFADDR: 1231 case SIOCGIFADDR: 1232 case SIOCSIFMTU: 1233 error = ether_ioctl(ifp, command, data); 1234 break; 1235 case SIOCSIFFLAGS: 1236 if (ifp->if_flags & IFF_UP) { 1237 if (ifp->if_flags & IFF_RUNNING && 1238 ifp->if_flags & IFF_PROMISC && 1239 !(sc->pcn_if_flags & IFF_PROMISC)) { 1240 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1241 PCN_EXTCTL1_SPND); 1242 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, 1243 PCN_MODE_PROMISC); 1244 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1245 PCN_EXTCTL1_SPND); 1246 pcn_csr_write(sc, PCN_CSR_CSR, 1247 PCN_CSR_INTEN|PCN_CSR_START); 1248 } else if (ifp->if_flags & IFF_RUNNING && 1249 !(ifp->if_flags & IFF_PROMISC) && 1250 sc->pcn_if_flags & IFF_PROMISC) { 1251 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1252 PCN_EXTCTL1_SPND); 1253 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, 1254 PCN_MODE_PROMISC); 1255 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1256 PCN_EXTCTL1_SPND); 1257 pcn_csr_write(sc, PCN_CSR_CSR, 1258 PCN_CSR_INTEN|PCN_CSR_START); 1259 } else if (!(ifp->if_flags & IFF_RUNNING)) 1260 pcn_init(sc); 1261 } else { 1262 if (ifp->if_flags & IFF_RUNNING) 1263 pcn_stop(sc); 1264 } 1265 sc->pcn_if_flags = ifp->if_flags; 1266 error = 0; 1267 break; 1268 case SIOCADDMULTI: 1269 case SIOCDELMULTI: 1270 pcn_setmulti(sc); 1271 error = 0; 1272 break; 1273 case SIOCGIFMEDIA: 1274 case SIOCSIFMEDIA: 1275 mii = device_get_softc(sc->pcn_miibus); 1276 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1277 break; 1278 default: 1279 error = EINVAL; 1280 break; 1281 } 1282 1283 PCN_UNLOCK(sc); 1284 1285 return(error); 1286} 1287 1288static void pcn_watchdog(ifp) 1289 struct ifnet *ifp; 1290{ 1291 struct pcn_softc *sc; 1292 1293 sc = ifp->if_softc; 1294 1295 PCN_LOCK(sc); 1296 1297 ifp->if_oerrors++; 1298 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1299 1300 pcn_stop(sc); 1301 pcn_reset(sc); 1302 pcn_init(sc); 1303 1304 if (ifp->if_snd.ifq_head != NULL) 1305 pcn_start(ifp); 1306 1307 PCN_UNLOCK(sc); 1308 1309 return; 1310} 1311 1312/* 1313 * Stop the adapter and free any mbufs allocated to the 1314 * RX and TX lists. 1315 */ 1316static void pcn_stop(sc) 1317 struct pcn_softc *sc; 1318{ 1319 register int i; 1320 struct ifnet *ifp; 1321 1322 ifp = &sc->arpcom.ac_if; 1323 PCN_LOCK(sc); 1324 ifp->if_timer = 0; 1325 1326 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1327 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1328 sc->pcn_link = 0; 1329 1330 /* 1331 * Free data in the RX lists. 1332 */ 1333 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1334 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1335 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1336 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1337 } 1338 } 1339 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1340 sizeof(sc->pcn_ldata->pcn_rx_list)); 1341 1342 /* 1343 * Free the TX list buffers. 1344 */ 1345 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1346 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1347 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1348 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1349 } 1350 } 1351 1352 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1353 sizeof(sc->pcn_ldata->pcn_tx_list)); 1354 1355 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1356 PCN_UNLOCK(sc); 1357 1358 return; 1359} 1360 1361/* 1362 * Stop all chip I/O so that the kernel's probe routines don't 1363 * get confused by errant DMAs when rebooting. 1364 */ 1365static void pcn_shutdown(dev) 1366 device_t dev; 1367{ 1368 struct pcn_softc *sc; 1369 1370 sc = device_get_softc(dev); 1371 1372 PCN_LOCK(sc); 1373 pcn_reset(sc); 1374 pcn_stop(sc); 1375 PCN_UNLOCK(sc); 1376 1377 return; 1378} 1379