if_pcn.c revision 148654
1/*- 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 148654 2005-08-03 00:18:35Z rwatson $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/ethernet.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_types.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <dev/pci/pcireg.h> 84#include <dev/pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static struct pcn_chipid { 107 u_int32_t id; 108 char * name; 109} pcn_chipid[] = { 110 { Am79C960, "Am79C960" }, 111 { Am79C961, "Am79C961" }, 112 { Am79C961A, "Am79C961A" }, 113 { Am79C965, "Am79C965" }, 114 { Am79C970, "Am79C970" }, 115 { Am79C970A, "Am79C970A" }, 116 { Am79C971, "Am79C971" }, 117 { Am79C972, "Am79C972" }, 118 { Am79C973, "Am79C973" }, 119 { Am79C978, "Am79C978" }, 120 { Am79C975, "Am79C975" }, 121 { Am79C976, "Am79C976" }, 122 { 0, NULL }, 123}; 124 125static char * pcn_chipid_name(u_int32_t); 126static u_int32_t pcn_chip_id(device_t); 127 128static u_int32_t pcn_csr_read(struct pcn_softc *, int); 129static u_int16_t pcn_csr_read16(struct pcn_softc *, int); 130static u_int16_t pcn_bcr_read16(struct pcn_softc *, int); 131static void pcn_csr_write(struct pcn_softc *, int, int); 132static u_int32_t pcn_bcr_read(struct pcn_softc *, int); 133static void pcn_bcr_write(struct pcn_softc *, int, int); 134 135static int pcn_probe(device_t); 136static int pcn_attach(device_t); 137static int pcn_detach(device_t); 138 139static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *); 140static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *); 141static void pcn_rxeof(struct pcn_softc *); 142static void pcn_txeof(struct pcn_softc *); 143static void pcn_intr(void *); 144static void pcn_tick(void *); 145static void pcn_start(struct ifnet *); 146static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 147static void pcn_init(void *); 148static void pcn_stop(struct pcn_softc *); 149static void pcn_watchdog(struct ifnet *); 150static void pcn_shutdown(device_t); 151static int pcn_ifmedia_upd(struct ifnet *); 152static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *); 153 154static int pcn_miibus_readreg(device_t, int, int); 155static int pcn_miibus_writereg(device_t, int, int, int); 156static void pcn_miibus_statchg(device_t); 157 158static void pcn_setfilt(struct ifnet *); 159static void pcn_setmulti(struct pcn_softc *); 160static void pcn_reset(struct pcn_softc *); 161static int pcn_list_rx_init(struct pcn_softc *); 162static int pcn_list_tx_init(struct pcn_softc *); 163 164#ifdef PCN_USEIOSPACE 165#define PCN_RES SYS_RES_IOPORT 166#define PCN_RID PCN_PCI_LOIO 167#else 168#define PCN_RES SYS_RES_MEMORY 169#define PCN_RID PCN_PCI_LOMEM 170#endif 171 172static device_method_t pcn_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, pcn_probe), 175 DEVMETHOD(device_attach, pcn_attach), 176 DEVMETHOD(device_detach, pcn_detach), 177 DEVMETHOD(device_shutdown, pcn_shutdown), 178 179 /* bus interface */ 180 DEVMETHOD(bus_print_child, bus_generic_print_child), 181 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 182 183 /* MII interface */ 184 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 185 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 186 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 187 188 { 0, 0 } 189}; 190 191static driver_t pcn_driver = { 192 "pcn", 193 pcn_methods, 194 sizeof(struct pcn_softc) 195}; 196 197static devclass_t pcn_devclass; 198 199DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 200DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 201 202#define PCN_CSR_SETBIT(sc, reg, x) \ 203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 204 205#define PCN_CSR_CLRBIT(sc, reg, x) \ 206 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 207 208#define PCN_BCR_SETBIT(sc, reg, x) \ 209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 210 211#define PCN_BCR_CLRBIT(sc, reg, x) \ 212 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 213 214static u_int32_t 215pcn_csr_read(sc, reg) 216 struct pcn_softc *sc; 217 int reg; 218{ 219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 220 return(CSR_READ_4(sc, PCN_IO32_RDP)); 221} 222 223static u_int16_t 224pcn_csr_read16(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227{ 228 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 229 return(CSR_READ_2(sc, PCN_IO16_RDP)); 230} 231 232static void 233pcn_csr_write(sc, reg, val) 234 struct pcn_softc *sc; 235 int reg; 236 int val; 237{ 238 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 239 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 240 return; 241} 242 243static u_int32_t 244pcn_bcr_read(sc, reg) 245 struct pcn_softc *sc; 246 int reg; 247{ 248 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 249 return(CSR_READ_4(sc, PCN_IO32_BDP)); 250} 251 252static u_int16_t 253pcn_bcr_read16(sc, reg) 254 struct pcn_softc *sc; 255 int reg; 256{ 257 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 258 return(CSR_READ_2(sc, PCN_IO16_BDP)); 259} 260 261static void 262pcn_bcr_write(sc, reg, val) 263 struct pcn_softc *sc; 264 int reg; 265 int val; 266{ 267 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 268 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 269 return; 270} 271 272static int 273pcn_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276{ 277 struct pcn_softc *sc; 278 int val; 279 280 sc = device_get_softc(dev); 281 282 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 283 return(0); 284 285 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 286 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 287 if (val == 0xFFFF) 288 return(0); 289 290 sc->pcn_phyaddr = phy; 291 292 return(val); 293} 294 295static int 296pcn_miibus_writereg(dev, phy, reg, data) 297 device_t dev; 298 int phy, reg, data; 299{ 300 struct pcn_softc *sc; 301 302 sc = device_get_softc(dev); 303 304 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 305 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 306 307 return(0); 308} 309 310static void 311pcn_miibus_statchg(dev) 312 device_t dev; 313{ 314 struct pcn_softc *sc; 315 struct mii_data *mii; 316 317 sc = device_get_softc(dev); 318 mii = device_get_softc(sc->pcn_miibus); 319 320 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 321 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 322 } else { 323 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 324 } 325 326 return; 327} 328 329static void 330pcn_setmulti(sc) 331 struct pcn_softc *sc; 332{ 333 struct ifnet *ifp; 334 struct ifmultiaddr *ifma; 335 u_int32_t h, i; 336 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 337 338 ifp = sc->pcn_ifp; 339 340 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 341 342 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 343 for (i = 0; i < 4; i++) 344 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 345 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 346 return; 347 } 348 349 /* first, zot all the existing hash bits */ 350 for (i = 0; i < 4; i++) 351 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 352 353 /* now program new ones */ 354 IF_ADDR_LOCK(ifp); 355 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 356 if (ifma->ifma_addr->sa_family != AF_LINK) 357 continue; 358 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 359 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 360 hashes[h >> 4] |= 1 << (h & 0xF); 361 } 362 IF_ADDR_UNLOCK(ifp); 363 364 for (i = 0; i < 4; i++) 365 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 366 367 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 368 369 return; 370} 371 372static void 373pcn_reset(sc) 374 struct pcn_softc *sc; 375{ 376 /* 377 * Issue a reset by reading from the RESET register. 378 * Note that we don't know if the chip is operating in 379 * 16-bit or 32-bit mode at this point, so we attempt 380 * to reset the chip both ways. If one fails, the other 381 * will succeed. 382 */ 383 CSR_READ_2(sc, PCN_IO16_RESET); 384 CSR_READ_4(sc, PCN_IO32_RESET); 385 386 /* Wait a little while for the chip to get its brains in order. */ 387 DELAY(1000); 388 389 /* Select 32-bit (DWIO) mode */ 390 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 391 392 /* Select software style 3. */ 393 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 394 395 return; 396} 397 398static char * 399pcn_chipid_name (u_int32_t id) 400{ 401 struct pcn_chipid *p = pcn_chipid; 402 403 while (p->name) { 404 if (id == p->id) 405 return (p->name); 406 p++; 407 } 408 return ("Unknown"); 409} 410 411static u_int32_t 412pcn_chip_id (device_t dev) 413{ 414 struct pcn_softc *sc; 415 u_int32_t chip_id; 416 417 sc = device_get_softc(dev); 418 /* 419 * Note: we can *NOT* put the chip into 420 * 32-bit mode yet. The lnc driver will only 421 * work in 16-bit mode, and once the chip 422 * goes into 32-bit mode, the only way to 423 * get it out again is with a hardware reset. 424 * So if pcn_probe() is called before the 425 * lnc driver's probe routine, the chip will 426 * be locked into 32-bit operation and the lnc 427 * driver will be unable to attach to it. 428 * Note II: if the chip happens to already 429 * be in 32-bit mode, we still need to check 430 * the chip ID, but first we have to detect 431 * 32-bit mode using only 16-bit operations. 432 * The safest way to do this is to read the 433 * PCI subsystem ID from BCR23/24 and compare 434 * that with the value read from PCI config 435 * space. 436 */ 437 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 438 chip_id <<= 16; 439 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 440 /* 441 * Note III: the test for 0x10001000 is a hack to 442 * pacify VMware, who's pseudo-PCnet interface is 443 * broken. Reading the subsystem register from PCI 444 * config space yields 0x00000000 while reading the 445 * same value from I/O space yields 0x10001000. It's 446 * not supposed to be that way. 447 */ 448 if (chip_id == pci_read_config(dev, 449 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 450 /* We're in 16-bit mode. */ 451 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 454 } else { 455 /* We're in 32-bit mode. */ 456 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 457 chip_id <<= 16; 458 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 459 } 460 461 return (chip_id); 462} 463 464static struct pcn_type * 465pcn_match (u_int16_t vid, u_int16_t did) 466{ 467 struct pcn_type *t; 468 t = pcn_devs; 469 470 while(t->pcn_name != NULL) { 471 if ((vid == t->pcn_vid) && (did == t->pcn_did)) 472 return (t); 473 t++; 474 } 475 return (NULL); 476} 477 478/* 479 * Probe for an AMD chip. Check the PCI vendor and device 480 * IDs against our list and return a device name if we find a match. 481 */ 482static int 483pcn_probe(dev) 484 device_t dev; 485{ 486 struct pcn_type *t; 487 struct pcn_softc *sc; 488 int rid; 489 u_int32_t chip_id; 490 491 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev)); 492 if (t == NULL) 493 return (ENXIO); 494 sc = device_get_softc(dev); 495 496 /* 497 * Temporarily map the I/O space so we can read the chip ID register. 498 */ 499 rid = PCN_RID; 500 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 501 if (sc->pcn_res == NULL) { 502 device_printf(dev, "couldn't map ports/memory\n"); 503 return(ENXIO); 504 } 505 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 506 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 507 508 chip_id = pcn_chip_id(dev); 509 510 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 511 512 switch((chip_id >> 12) & PART_MASK) { 513 case Am79C971: 514 case Am79C972: 515 case Am79C973: 516 case Am79C975: 517 case Am79C976: 518 case Am79C978: 519 break; 520 default: 521 return(ENXIO); 522 } 523 device_set_desc(dev, t->pcn_name); 524 return(BUS_PROBE_DEFAULT); 525} 526 527/* 528 * Attach the interface. Allocate softc structures, do ifmedia 529 * setup and ethernet/BPF attach. 530 */ 531static int 532pcn_attach(dev) 533 device_t dev; 534{ 535 u_int32_t eaddr[2]; 536 struct pcn_softc *sc; 537 struct ifnet *ifp; 538 int unit, error = 0, rid; 539 540 sc = device_get_softc(dev); 541 unit = device_get_unit(dev); 542 543 /* Initialize our mutex. */ 544 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 545 MTX_DEF | MTX_RECURSE); 546 /* 547 * Map control/status registers. 548 */ 549 pci_enable_busmaster(dev); 550 551 /* Retrieve the chip ID */ 552 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK; 553 device_printf(dev, "Chip ID %04x (%s)\n", 554 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 555 556 rid = PCN_RID; 557 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 558 559 if (sc->pcn_res == NULL) { 560 printf("pcn%d: couldn't map ports/memory\n", unit); 561 error = ENXIO; 562 goto fail; 563 } 564 565 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 566 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 567 568 /* Allocate interrupt */ 569 rid = 0; 570 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 571 RF_SHAREABLE | RF_ACTIVE); 572 573 if (sc->pcn_irq == NULL) { 574 printf("pcn%d: couldn't map interrupt\n", unit); 575 error = ENXIO; 576 goto fail; 577 } 578 579 /* Reset the adapter. */ 580 pcn_reset(sc); 581 582 /* 583 * Get station address from the EEPROM. 584 */ 585 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 586 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 587 588 sc->pcn_unit = unit; 589 callout_handle_init(&sc->pcn_stat_ch); 590 591 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 592 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 593 594 if (sc->pcn_ldata == NULL) { 595 printf("pcn%d: no memory for list buffers!\n", unit); 596 error = ENXIO; 597 goto fail; 598 } 599 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 600 601 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER); 602 if (ifp == NULL) { 603 printf("pcn%d: can not if_alloc()\n", unit); 604 error = ENOSPC; 605 goto fail; 606 } 607 ifp->if_softc = sc; 608 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 609 ifp->if_mtu = ETHERMTU; 610 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 611 IFF_NEEDSGIANT; 612 ifp->if_ioctl = pcn_ioctl; 613 ifp->if_start = pcn_start; 614 ifp->if_watchdog = pcn_watchdog; 615 ifp->if_init = pcn_init; 616 ifp->if_baudrate = 10000000; 617 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 618 619 /* 620 * Do MII setup. 621 */ 622 if (mii_phy_probe(dev, &sc->pcn_miibus, 623 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 624 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 625 if_free(ifp); 626 error = ENXIO; 627 goto fail; 628 } 629 630 /* 631 * Call MI attach routine. 632 */ 633 ether_ifattach(ifp, (u_int8_t *) eaddr); 634 635 /* Hook interrupt last to avoid having to lock softc */ 636 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 637 pcn_intr, sc, &sc->pcn_intrhand); 638 639 if (error) { 640 printf("pcn%d: couldn't set up irq\n", unit); 641 ether_ifdetach(ifp); 642 goto fail; 643 } 644 645fail: 646 if (error) 647 pcn_detach(dev); 648 649 return(error); 650} 651 652/* 653 * Shutdown hardware and free up resources. This can be called any 654 * time after the mutex has been initialized. It is called in both 655 * the error case in attach and the normal detach case so it needs 656 * to be careful about only freeing resources that have actually been 657 * allocated. 658 */ 659static int 660pcn_detach(dev) 661 device_t dev; 662{ 663 struct pcn_softc *sc; 664 struct ifnet *ifp; 665 666 sc = device_get_softc(dev); 667 ifp = sc->pcn_ifp; 668 669 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 670 PCN_LOCK(sc); 671 672 /* These should only be active if attach succeeded */ 673 if (device_is_attached(dev)) { 674 pcn_reset(sc); 675 pcn_stop(sc); 676 ether_ifdetach(ifp); 677 if_free(ifp); 678 } 679 if (sc->pcn_miibus) 680 device_delete_child(dev, sc->pcn_miibus); 681 bus_generic_detach(dev); 682 683 if (sc->pcn_intrhand) 684 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 685 if (sc->pcn_irq) 686 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 687 if (sc->pcn_res) 688 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 689 690 if (sc->pcn_ldata) { 691 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 692 M_DEVBUF); 693 } 694 PCN_UNLOCK(sc); 695 696 mtx_destroy(&sc->pcn_mtx); 697 698 return(0); 699} 700 701/* 702 * Initialize the transmit descriptors. 703 */ 704static int 705pcn_list_tx_init(sc) 706 struct pcn_softc *sc; 707{ 708 struct pcn_list_data *ld; 709 struct pcn_ring_data *cd; 710 int i; 711 712 cd = &sc->pcn_cdata; 713 ld = sc->pcn_ldata; 714 715 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 716 cd->pcn_tx_chain[i] = NULL; 717 ld->pcn_tx_list[i].pcn_tbaddr = 0; 718 ld->pcn_tx_list[i].pcn_txctl = 0; 719 ld->pcn_tx_list[i].pcn_txstat = 0; 720 } 721 722 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 723 724 return(0); 725} 726 727 728/* 729 * Initialize the RX descriptors and allocate mbufs for them. 730 */ 731static int 732pcn_list_rx_init(sc) 733 struct pcn_softc *sc; 734{ 735 struct pcn_ring_data *cd; 736 int i; 737 738 cd = &sc->pcn_cdata; 739 740 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 741 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 742 return(ENOBUFS); 743 } 744 745 cd->pcn_rx_prod = 0; 746 747 return(0); 748} 749 750/* 751 * Initialize an RX descriptor and attach an MBUF cluster. 752 */ 753static int 754pcn_newbuf(sc, idx, m) 755 struct pcn_softc *sc; 756 int idx; 757 struct mbuf *m; 758{ 759 struct mbuf *m_new = NULL; 760 struct pcn_rx_desc *c; 761 762 c = &sc->pcn_ldata->pcn_rx_list[idx]; 763 764 if (m == NULL) { 765 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 766 if (m_new == NULL) 767 return(ENOBUFS); 768 769 MCLGET(m_new, M_DONTWAIT); 770 if (!(m_new->m_flags & M_EXT)) { 771 m_freem(m_new); 772 return(ENOBUFS); 773 } 774 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 775 } else { 776 m_new = m; 777 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 778 m_new->m_data = m_new->m_ext.ext_buf; 779 } 780 781 m_adj(m_new, ETHER_ALIGN); 782 783 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 784 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 785 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 786 c->pcn_bufsz |= PCN_RXLEN_MBO; 787 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 788 789 return(0); 790} 791 792/* 793 * A frame has been uploaded: pass the resulting mbuf chain up to 794 * the higher level protocols. 795 */ 796static void 797pcn_rxeof(sc) 798 struct pcn_softc *sc; 799{ 800 struct mbuf *m; 801 struct ifnet *ifp; 802 struct pcn_rx_desc *cur_rx; 803 int i; 804 805 PCN_LOCK_ASSERT(sc); 806 807 ifp = sc->pcn_ifp; 808 i = sc->pcn_cdata.pcn_rx_prod; 809 810 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 811 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 812 m = sc->pcn_cdata.pcn_rx_chain[i]; 813 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 814 815 /* 816 * If an error occurs, update stats, clear the 817 * status word and leave the mbuf cluster in place: 818 * it should simply get re-used next time this descriptor 819 * comes up in the ring. 820 */ 821 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 822 ifp->if_ierrors++; 823 pcn_newbuf(sc, i, m); 824 PCN_INC(i, PCN_RX_LIST_CNT); 825 continue; 826 } 827 828 if (pcn_newbuf(sc, i, NULL)) { 829 /* Ran out of mbufs; recycle this one. */ 830 pcn_newbuf(sc, i, m); 831 ifp->if_ierrors++; 832 PCN_INC(i, PCN_RX_LIST_CNT); 833 continue; 834 } 835 836 PCN_INC(i, PCN_RX_LIST_CNT); 837 838 /* No errors; receive the packet. */ 839 ifp->if_ipackets++; 840 m->m_len = m->m_pkthdr.len = 841 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 842 m->m_pkthdr.rcvif = ifp; 843 844 PCN_UNLOCK(sc); 845 (*ifp->if_input)(ifp, m); 846 PCN_LOCK(sc); 847 } 848 849 sc->pcn_cdata.pcn_rx_prod = i; 850 851 return; 852} 853 854/* 855 * A frame was downloaded to the chip. It's safe for us to clean up 856 * the list buffers. 857 */ 858 859static void 860pcn_txeof(sc) 861 struct pcn_softc *sc; 862{ 863 struct pcn_tx_desc *cur_tx = NULL; 864 struct ifnet *ifp; 865 u_int32_t idx; 866 867 ifp = sc->pcn_ifp; 868 869 /* 870 * Go through our tx list and free mbufs for those 871 * frames that have been transmitted. 872 */ 873 idx = sc->pcn_cdata.pcn_tx_cons; 874 while (idx != sc->pcn_cdata.pcn_tx_prod) { 875 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 876 877 if (!PCN_OWN_TXDESC(cur_tx)) 878 break; 879 880 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 881 sc->pcn_cdata.pcn_tx_cnt--; 882 PCN_INC(idx, PCN_TX_LIST_CNT); 883 continue; 884 } 885 886 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 887 ifp->if_oerrors++; 888 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 889 ifp->if_collisions++; 890 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 891 ifp->if_collisions++; 892 } 893 894 ifp->if_collisions += 895 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 896 897 ifp->if_opackets++; 898 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 899 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 900 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 901 } 902 903 sc->pcn_cdata.pcn_tx_cnt--; 904 PCN_INC(idx, PCN_TX_LIST_CNT); 905 } 906 907 if (idx != sc->pcn_cdata.pcn_tx_cons) { 908 /* Some buffers have been freed. */ 909 sc->pcn_cdata.pcn_tx_cons = idx; 910 ifp->if_flags &= ~IFF_OACTIVE; 911 } 912 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 913 914 return; 915} 916 917static void 918pcn_tick(xsc) 919 void *xsc; 920{ 921 struct pcn_softc *sc; 922 struct mii_data *mii; 923 struct ifnet *ifp; 924 925 sc = xsc; 926 ifp = sc->pcn_ifp; 927 PCN_LOCK(sc); 928 929 mii = device_get_softc(sc->pcn_miibus); 930 mii_tick(mii); 931 932 /* link just died */ 933 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 934 sc->pcn_link = 0; 935 936 /* link just came up, restart */ 937 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 938 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 939 sc->pcn_link++; 940 if (ifp->if_snd.ifq_head != NULL) 941 pcn_start(ifp); 942 } 943 944 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 945 946 PCN_UNLOCK(sc); 947 948 return; 949} 950 951static void 952pcn_intr(arg) 953 void *arg; 954{ 955 struct pcn_softc *sc; 956 struct ifnet *ifp; 957 u_int32_t status; 958 959 sc = arg; 960 ifp = sc->pcn_ifp; 961 962 /* Suppress unwanted interrupts */ 963 if (!(ifp->if_flags & IFF_UP)) { 964 pcn_stop(sc); 965 return; 966 } 967 968 PCN_LOCK(sc); 969 970 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 971 972 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 973 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 974 975 if (status & PCN_CSR_RINT) 976 pcn_rxeof(sc); 977 978 if (status & PCN_CSR_TINT) 979 pcn_txeof(sc); 980 981 if (status & PCN_CSR_ERR) { 982 pcn_init(sc); 983 break; 984 } 985 } 986 987 if (ifp->if_snd.ifq_head != NULL) 988 pcn_start(ifp); 989 990 PCN_UNLOCK(sc); 991 return; 992} 993 994/* 995 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 996 * pointers to the fragment pointers. 997 */ 998static int 999pcn_encap(sc, m_head, txidx) 1000 struct pcn_softc *sc; 1001 struct mbuf *m_head; 1002 u_int32_t *txidx; 1003{ 1004 struct pcn_tx_desc *f = NULL; 1005 struct mbuf *m; 1006 int frag, cur, cnt = 0; 1007 1008 /* 1009 * Start packing the mbufs in this chain into 1010 * the fragment pointers. Stop when we run out 1011 * of fragments or hit the end of the mbuf chain. 1012 */ 1013 m = m_head; 1014 cur = frag = *txidx; 1015 1016 for (m = m_head; m != NULL; m = m->m_next) { 1017 if (m->m_len == 0) 1018 continue; 1019 1020 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1021 return(ENOBUFS); 1022 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1023 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1024 f->pcn_txctl |= PCN_TXCTL_MBO; 1025 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1026 if (cnt == 0) 1027 f->pcn_txctl |= PCN_TXCTL_STP; 1028 else 1029 f->pcn_txctl |= PCN_TXCTL_OWN; 1030 cur = frag; 1031 PCN_INC(frag, PCN_TX_LIST_CNT); 1032 cnt++; 1033 } 1034 1035 if (m != NULL) 1036 return(ENOBUFS); 1037 1038 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1039 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1040 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1041 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1042 sc->pcn_cdata.pcn_tx_cnt += cnt; 1043 *txidx = frag; 1044 1045 return(0); 1046} 1047 1048/* 1049 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1050 * to the mbuf data regions directly in the transmit lists. We also save a 1051 * copy of the pointers since the transmit list fragment pointers are 1052 * physical addresses. 1053 */ 1054static void 1055pcn_start(ifp) 1056 struct ifnet *ifp; 1057{ 1058 struct pcn_softc *sc; 1059 struct mbuf *m_head = NULL; 1060 u_int32_t idx; 1061 1062 sc = ifp->if_softc; 1063 1064 PCN_LOCK(sc); 1065 1066 if (!sc->pcn_link) { 1067 PCN_UNLOCK(sc); 1068 return; 1069 } 1070 1071 idx = sc->pcn_cdata.pcn_tx_prod; 1072 1073 if (ifp->if_flags & IFF_OACTIVE) { 1074 PCN_UNLOCK(sc); 1075 return; 1076 } 1077 1078 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1079 IF_DEQUEUE(&ifp->if_snd, m_head); 1080 if (m_head == NULL) 1081 break; 1082 1083 if (pcn_encap(sc, m_head, &idx)) { 1084 IF_PREPEND(&ifp->if_snd, m_head); 1085 ifp->if_flags |= IFF_OACTIVE; 1086 break; 1087 } 1088 1089 /* 1090 * If there's a BPF listener, bounce a copy of this frame 1091 * to him. 1092 */ 1093 BPF_MTAP(ifp, m_head); 1094 1095 } 1096 1097 /* Transmit */ 1098 sc->pcn_cdata.pcn_tx_prod = idx; 1099 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1100 1101 /* 1102 * Set a timeout in case the chip goes out to lunch. 1103 */ 1104 ifp->if_timer = 5; 1105 1106 PCN_UNLOCK(sc); 1107 1108 return; 1109} 1110 1111static void 1112pcn_setfilt(ifp) 1113 struct ifnet *ifp; 1114{ 1115 struct pcn_softc *sc; 1116 1117 sc = ifp->if_softc; 1118 1119 /* If we want promiscuous mode, set the allframes bit. */ 1120 if (ifp->if_flags & IFF_PROMISC) { 1121 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1122 } else { 1123 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1124 } 1125 1126 /* Set the capture broadcast bit to capture broadcast frames. */ 1127 if (ifp->if_flags & IFF_BROADCAST) { 1128 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1129 } else { 1130 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1131 } 1132 1133 return; 1134} 1135 1136static void 1137pcn_init(xsc) 1138 void *xsc; 1139{ 1140 struct pcn_softc *sc = xsc; 1141 struct ifnet *ifp = sc->pcn_ifp; 1142 struct mii_data *mii = NULL; 1143 1144 PCN_LOCK(sc); 1145 1146 /* 1147 * Cancel pending I/O and free all RX/TX buffers. 1148 */ 1149 pcn_stop(sc); 1150 pcn_reset(sc); 1151 1152 mii = device_get_softc(sc->pcn_miibus); 1153 1154 /* Set MAC address */ 1155 pcn_csr_write(sc, PCN_CSR_PAR0, 1156 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[0]); 1157 pcn_csr_write(sc, PCN_CSR_PAR1, 1158 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[1]); 1159 pcn_csr_write(sc, PCN_CSR_PAR2, 1160 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[2]); 1161 1162 /* Init circular RX list. */ 1163 if (pcn_list_rx_init(sc) == ENOBUFS) { 1164 printf("pcn%d: initialization failed: no " 1165 "memory for rx buffers\n", sc->pcn_unit); 1166 pcn_stop(sc); 1167 PCN_UNLOCK(sc); 1168 return; 1169 } 1170 1171 /* 1172 * Init tx descriptors. 1173 */ 1174 pcn_list_tx_init(sc); 1175 1176 /* Set up the mode register. */ 1177 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1178 1179 /* Set up RX filter. */ 1180 pcn_setfilt(ifp); 1181 1182 /* 1183 * Load the multicast filter. 1184 */ 1185 pcn_setmulti(sc); 1186 1187 /* 1188 * Load the addresses of the RX and TX lists. 1189 */ 1190 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1191 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1192 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1193 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1194 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1195 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1196 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1197 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1198 1199 /* Set the RX and TX ring sizes. */ 1200 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1201 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1202 1203 /* We're not using the initialization block. */ 1204 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1205 1206 /* Enable fast suspend mode. */ 1207 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1208 1209 /* 1210 * Enable burst read and write. Also set the no underflow 1211 * bit. This will avoid transmit underruns in certain 1212 * conditions while still providing decent performance. 1213 */ 1214 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1215 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1216 1217 /* Enable graceful recovery from underflow. */ 1218 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1219 1220 /* Enable auto-padding of short TX frames. */ 1221 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1222 1223 /* Disable MII autoneg (we handle this ourselves). */ 1224 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1225 1226 if (sc->pcn_type == Am79C978) 1227 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1228 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1229 1230 /* Enable interrupts and start the controller running. */ 1231 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1232 1233 mii_mediachg(mii); 1234 1235 ifp->if_flags |= IFF_RUNNING; 1236 ifp->if_flags &= ~IFF_OACTIVE; 1237 1238 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1239 PCN_UNLOCK(sc); 1240 1241 return; 1242} 1243 1244/* 1245 * Set media options. 1246 */ 1247static int 1248pcn_ifmedia_upd(ifp) 1249 struct ifnet *ifp; 1250{ 1251 struct pcn_softc *sc; 1252 struct mii_data *mii; 1253 1254 sc = ifp->if_softc; 1255 mii = device_get_softc(sc->pcn_miibus); 1256 1257 sc->pcn_link = 0; 1258 if (mii->mii_instance) { 1259 struct mii_softc *miisc; 1260 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1261 mii_phy_reset(miisc); 1262 } 1263 mii_mediachg(mii); 1264 1265 return(0); 1266} 1267 1268/* 1269 * Report current media status. 1270 */ 1271static void 1272pcn_ifmedia_sts(ifp, ifmr) 1273 struct ifnet *ifp; 1274 struct ifmediareq *ifmr; 1275{ 1276 struct pcn_softc *sc; 1277 struct mii_data *mii; 1278 1279 sc = ifp->if_softc; 1280 1281 mii = device_get_softc(sc->pcn_miibus); 1282 mii_pollstat(mii); 1283 ifmr->ifm_active = mii->mii_media_active; 1284 ifmr->ifm_status = mii->mii_media_status; 1285 1286 return; 1287} 1288 1289static int 1290pcn_ioctl(ifp, command, data) 1291 struct ifnet *ifp; 1292 u_long command; 1293 caddr_t data; 1294{ 1295 struct pcn_softc *sc = ifp->if_softc; 1296 struct ifreq *ifr = (struct ifreq *) data; 1297 struct mii_data *mii = NULL; 1298 int error = 0; 1299 1300 PCN_LOCK(sc); 1301 1302 switch(command) { 1303 case SIOCSIFFLAGS: 1304 if (ifp->if_flags & IFF_UP) { 1305 if (ifp->if_flags & IFF_RUNNING && 1306 ifp->if_flags & IFF_PROMISC && 1307 !(sc->pcn_if_flags & IFF_PROMISC)) { 1308 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1309 PCN_EXTCTL1_SPND); 1310 pcn_setfilt(ifp); 1311 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1312 PCN_EXTCTL1_SPND); 1313 pcn_csr_write(sc, PCN_CSR_CSR, 1314 PCN_CSR_INTEN|PCN_CSR_START); 1315 } else if (ifp->if_flags & IFF_RUNNING && 1316 !(ifp->if_flags & IFF_PROMISC) && 1317 sc->pcn_if_flags & IFF_PROMISC) { 1318 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1319 PCN_EXTCTL1_SPND); 1320 pcn_setfilt(ifp); 1321 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1322 PCN_EXTCTL1_SPND); 1323 pcn_csr_write(sc, PCN_CSR_CSR, 1324 PCN_CSR_INTEN|PCN_CSR_START); 1325 } else if (!(ifp->if_flags & IFF_RUNNING)) 1326 pcn_init(sc); 1327 } else { 1328 if (ifp->if_flags & IFF_RUNNING) 1329 pcn_stop(sc); 1330 } 1331 sc->pcn_if_flags = ifp->if_flags; 1332 error = 0; 1333 break; 1334 case SIOCADDMULTI: 1335 case SIOCDELMULTI: 1336 pcn_setmulti(sc); 1337 error = 0; 1338 break; 1339 case SIOCGIFMEDIA: 1340 case SIOCSIFMEDIA: 1341 mii = device_get_softc(sc->pcn_miibus); 1342 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1343 break; 1344 default: 1345 error = ether_ioctl(ifp, command, data); 1346 break; 1347 } 1348 1349 PCN_UNLOCK(sc); 1350 1351 return(error); 1352} 1353 1354static void 1355pcn_watchdog(ifp) 1356 struct ifnet *ifp; 1357{ 1358 struct pcn_softc *sc; 1359 1360 sc = ifp->if_softc; 1361 1362 PCN_LOCK(sc); 1363 1364 ifp->if_oerrors++; 1365 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1366 1367 pcn_stop(sc); 1368 pcn_reset(sc); 1369 pcn_init(sc); 1370 1371 if (ifp->if_snd.ifq_head != NULL) 1372 pcn_start(ifp); 1373 1374 PCN_UNLOCK(sc); 1375 1376 return; 1377} 1378 1379/* 1380 * Stop the adapter and free any mbufs allocated to the 1381 * RX and TX lists. 1382 */ 1383static void 1384pcn_stop(sc) 1385 struct pcn_softc *sc; 1386{ 1387 register int i; 1388 struct ifnet *ifp; 1389 1390 ifp = sc->pcn_ifp; 1391 PCN_LOCK(sc); 1392 ifp->if_timer = 0; 1393 1394 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1395 1396 /* Turn off interrupts */ 1397 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1398 /* Stop adapter */ 1399 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1400 sc->pcn_link = 0; 1401 1402 /* 1403 * Free data in the RX lists. 1404 */ 1405 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1406 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1407 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1408 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1409 } 1410 } 1411 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1412 sizeof(sc->pcn_ldata->pcn_rx_list)); 1413 1414 /* 1415 * Free the TX list buffers. 1416 */ 1417 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1418 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1419 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1420 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1421 } 1422 } 1423 1424 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1425 sizeof(sc->pcn_ldata->pcn_tx_list)); 1426 1427 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1428 PCN_UNLOCK(sc); 1429 1430 return; 1431} 1432 1433/* 1434 * Stop all chip I/O so that the kernel's probe routines don't 1435 * get confused by errant DMAs when rebooting. 1436 */ 1437static void 1438pcn_shutdown(dev) 1439 device_t dev; 1440{ 1441 struct pcn_softc *sc; 1442 1443 sc = device_get_softc(dev); 1444 1445 PCN_LOCK(sc); 1446 pcn_reset(sc); 1447 pcn_stop(sc); 1448 PCN_UNLOCK(sc); 1449 1450 return; 1451} 1452