if_pcn.c revision 126966
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 126966 2004-03-14 07:12:25Z mdodd $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <dev/pci/pcireg.h> 84#include <dev/pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static uint32_t pcn_mchash (const uint8_t *); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216 int val; 217{ 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221} 222 223static u_int32_t 224pcn_bcr_read(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227{ 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230} 231 232static u_int16_t 233pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void 242pcn_bcr_write(sc, reg, val) 243 struct pcn_softc *sc; 244 int reg; 245 int val; 246{ 247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 248 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 249 return; 250} 251 252static int 253pcn_miibus_readreg(dev, phy, reg) 254 device_t dev; 255 int phy, reg; 256{ 257 struct pcn_softc *sc; 258 int val; 259 260 sc = device_get_softc(dev); 261 262 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 263 return(0); 264 265 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 266 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 267 if (val == 0xFFFF) 268 return(0); 269 270 sc->pcn_phyaddr = phy; 271 272 return(val); 273} 274 275static int 276pcn_miibus_writereg(dev, phy, reg, data) 277 device_t dev; 278 int phy, reg, data; 279{ 280 struct pcn_softc *sc; 281 282 sc = device_get_softc(dev); 283 284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 285 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 286 287 return(0); 288} 289 290static void 291pcn_miibus_statchg(dev) 292 device_t dev; 293{ 294 struct pcn_softc *sc; 295 struct mii_data *mii; 296 297 sc = device_get_softc(dev); 298 mii = device_get_softc(sc->pcn_miibus); 299 300 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 301 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } else { 303 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 304 } 305 306 return; 307} 308 309#define DC_POLY 0xEDB88320 310 311static u_int32_t 312pcn_mchash(addr) 313 const uint8_t *addr; 314{ 315 uint32_t crc; 316 int idx, bit; 317 uint8_t data; 318 319 /* Compute CRC for the address value. */ 320 crc = 0xFFFFFFFF; /* initial value */ 321 322 for (idx = 0; idx < 6; idx++) { 323 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 324 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 325 } 326 327 return ((crc >> 26) & 0x3F); 328} 329 330static void 331pcn_setmulti(sc) 332 struct pcn_softc *sc; 333{ 334 struct ifnet *ifp; 335 struct ifmultiaddr *ifma; 336 u_int32_t h, i; 337 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 338 339 ifp = &sc->arpcom.ac_if; 340 341 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 342 343 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 344 for (i = 0; i < 4; i++) 345 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 346 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 347 return; 348 } 349 350 /* first, zot all the existing hash bits */ 351 for (i = 0; i < 4; i++) 352 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 353 354 /* now program new ones */ 355 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 356 if (ifma->ifma_addr->sa_family != AF_LINK) 357 continue; 358 h = pcn_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 359 hashes[h >> 4] |= 1 << (h & 0xF); 360 } 361 362 for (i = 0; i < 4; i++) 363 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 364 365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 366 367 return; 368} 369 370static void 371pcn_reset(sc) 372 struct pcn_softc *sc; 373{ 374 /* 375 * Issue a reset by reading from the RESET register. 376 * Note that we don't know if the chip is operating in 377 * 16-bit or 32-bit mode at this point, so we attempt 378 * to reset the chip both ways. If one fails, the other 379 * will succeed. 380 */ 381 CSR_READ_2(sc, PCN_IO16_RESET); 382 CSR_READ_4(sc, PCN_IO32_RESET); 383 384 /* Wait a little while for the chip to get its brains in order. */ 385 DELAY(1000); 386 387 /* Select 32-bit (DWIO) mode */ 388 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 389 390 /* Select software style 3. */ 391 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 392 393 return; 394} 395 396/* 397 * Probe for an AMD chip. Check the PCI vendor and device 398 * IDs against our list and return a device name if we find a match. 399 */ 400static int 401pcn_probe(dev) 402 device_t dev; 403{ 404 struct pcn_type *t; 405 struct pcn_softc *sc; 406 int rid; 407 u_int32_t chip_id; 408 409 t = pcn_devs; 410 sc = device_get_softc(dev); 411 412 while(t->pcn_name != NULL) { 413 if ((pci_get_vendor(dev) == t->pcn_vid) && 414 (pci_get_device(dev) == t->pcn_did)) { 415 /* 416 * Temporarily map the I/O space 417 * so we can read the chip ID register. 418 */ 419 rid = PCN_RID; 420 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 421 0, ~0, 1, RF_ACTIVE); 422 if (sc->pcn_res == NULL) { 423 device_printf(dev, 424 "couldn't map ports/memory\n"); 425 return(ENXIO); 426 } 427 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 428 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 429 mtx_init(&sc->pcn_mtx, 430 device_get_nameunit(dev), MTX_NETWORK_LOCK, 431 MTX_DEF); 432 PCN_LOCK(sc); 433 /* 434 * Note: we can *NOT* put the chip into 435 * 32-bit mode yet. The lnc driver will only 436 * work in 16-bit mode, and once the chip 437 * goes into 32-bit mode, the only way to 438 * get it out again is with a hardware reset. 439 * So if pcn_probe() is called before the 440 * lnc driver's probe routine, the chip will 441 * be locked into 32-bit operation and the lnc 442 * driver will be unable to attach to it. 443 * Note II: if the chip happens to already 444 * be in 32-bit mode, we still need to check 445 * the chip ID, but first we have to detect 446 * 32-bit mode using only 16-bit operations. 447 * The safest way to do this is to read the 448 * PCI subsystem ID from BCR23/24 and compare 449 * that with the value read from PCI config 450 * space. 451 */ 452 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 453 chip_id <<= 16; 454 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 455 /* 456 * Note III: the test for 0x10001000 is a hack to 457 * pacify VMware, who's pseudo-PCnet interface is 458 * broken. Reading the subsystem register from PCI 459 * config space yeilds 0x00000000 while reading the 460 * same value from I/O space yeilds 0x10001000. It's 461 * not supposed to be that way. 462 */ 463 if (chip_id == pci_read_config(dev, 464 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 465 /* We're in 16-bit mode. */ 466 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 467 chip_id <<= 16; 468 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 469 } else { 470 /* We're in 32-bit mode. */ 471 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 472 chip_id <<= 16; 473 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 474 } 475 bus_release_resource(dev, PCN_RES, 476 PCN_RID, sc->pcn_res); 477 PCN_UNLOCK(sc); 478 mtx_destroy(&sc->pcn_mtx); 479 chip_id >>= 12; 480 sc->pcn_type = chip_id & PART_MASK; 481 switch(sc->pcn_type) { 482 case Am79C971: 483 case Am79C972: 484 case Am79C973: 485 case Am79C975: 486 case Am79C976: 487 case Am79C978: 488 break; 489 default: 490 return(ENXIO); 491 } 492 device_set_desc(dev, t->pcn_name); 493 return(0); 494 } 495 t++; 496 } 497 498 return(ENXIO); 499} 500 501/* 502 * Attach the interface. Allocate softc structures, do ifmedia 503 * setup and ethernet/BPF attach. 504 */ 505static int 506pcn_attach(dev) 507 device_t dev; 508{ 509 u_int32_t eaddr[2]; 510 struct pcn_softc *sc; 511 struct ifnet *ifp; 512 int unit, error = 0, rid; 513 514 sc = device_get_softc(dev); 515 unit = device_get_unit(dev); 516 517 /* Initialize our mutex. */ 518 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 519 MTX_DEF | MTX_RECURSE); 520#ifndef BURN_BRIDGES 521 /* 522 * Handle power management nonsense. 523 */ 524 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 525 u_int32_t iobase, membase, irq; 526 527 /* Save important PCI config data. */ 528 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 529 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 530 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 531 532 /* Reset the power state. */ 533 printf("pcn%d: chip is in D%d power mode " 534 "-- setting to D0\n", unit, 535 pci_get_powerstate(dev)); 536 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 537 538 /* Restore PCI config data. */ 539 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 540 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 541 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 542 } 543#endif 544 /* 545 * Map control/status registers. 546 */ 547 pci_enable_busmaster(dev); 548 549 rid = PCN_RID; 550 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 551 0, ~0, 1, RF_ACTIVE); 552 553 if (sc->pcn_res == NULL) { 554 printf("pcn%d: couldn't map ports/memory\n", unit); 555 error = ENXIO; 556 goto fail; 557 } 558 559 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 560 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 561 562 /* Allocate interrupt */ 563 rid = 0; 564 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 565 RF_SHAREABLE | RF_ACTIVE); 566 567 if (sc->pcn_irq == NULL) { 568 printf("pcn%d: couldn't map interrupt\n", unit); 569 error = ENXIO; 570 goto fail; 571 } 572 573 /* Reset the adapter. */ 574 pcn_reset(sc); 575 576 /* 577 * Get station address from the EEPROM. 578 */ 579 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 580 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 581 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 582 583 sc->pcn_unit = unit; 584 callout_handle_init(&sc->pcn_stat_ch); 585 586 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 587 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 588 589 if (sc->pcn_ldata == NULL) { 590 printf("pcn%d: no memory for list buffers!\n", unit); 591 error = ENXIO; 592 goto fail; 593 } 594 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 595 596 ifp = &sc->arpcom.ac_if; 597 ifp->if_softc = sc; 598 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 599 ifp->if_mtu = ETHERMTU; 600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 601 ifp->if_ioctl = pcn_ioctl; 602 ifp->if_start = pcn_start; 603 ifp->if_watchdog = pcn_watchdog; 604 ifp->if_init = pcn_init; 605 ifp->if_baudrate = 10000000; 606 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 607 608 /* 609 * Do MII setup. 610 */ 611 if (mii_phy_probe(dev, &sc->pcn_miibus, 612 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 613 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 614 error = ENXIO; 615 goto fail; 616 } 617 618 /* 619 * Call MI attach routine. 620 */ 621 ether_ifattach(ifp, (u_int8_t *) eaddr); 622 623 /* Hook interrupt last to avoid having to lock softc */ 624 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 625 pcn_intr, sc, &sc->pcn_intrhand); 626 627 if (error) { 628 printf("pcn%d: couldn't set up irq\n", unit); 629 ether_ifdetach(ifp); 630 goto fail; 631 } 632 633fail: 634 if (error) 635 pcn_detach(dev); 636 637 return(error); 638} 639 640/* 641 * Shutdown hardware and free up resources. This can be called any 642 * time after the mutex has been initialized. It is called in both 643 * the error case in attach and the normal detach case so it needs 644 * to be careful about only freeing resources that have actually been 645 * allocated. 646 */ 647static int 648pcn_detach(dev) 649 device_t dev; 650{ 651 struct pcn_softc *sc; 652 struct ifnet *ifp; 653 654 sc = device_get_softc(dev); 655 ifp = &sc->arpcom.ac_if; 656 657 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 658 PCN_LOCK(sc); 659 660 /* These should only be active if attach succeeded */ 661 if (device_is_attached(dev)) { 662 pcn_reset(sc); 663 pcn_stop(sc); 664 ether_ifdetach(ifp); 665 } 666 if (sc->pcn_miibus) 667 device_delete_child(dev, sc->pcn_miibus); 668 bus_generic_detach(dev); 669 670 if (sc->pcn_intrhand) 671 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 672 if (sc->pcn_irq) 673 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 674 if (sc->pcn_res) 675 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 676 677 if (sc->pcn_ldata) { 678 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 679 M_DEVBUF); 680 } 681 PCN_UNLOCK(sc); 682 683 mtx_destroy(&sc->pcn_mtx); 684 685 return(0); 686} 687 688/* 689 * Initialize the transmit descriptors. 690 */ 691static int 692pcn_list_tx_init(sc) 693 struct pcn_softc *sc; 694{ 695 struct pcn_list_data *ld; 696 struct pcn_ring_data *cd; 697 int i; 698 699 cd = &sc->pcn_cdata; 700 ld = sc->pcn_ldata; 701 702 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 703 cd->pcn_tx_chain[i] = NULL; 704 ld->pcn_tx_list[i].pcn_tbaddr = 0; 705 ld->pcn_tx_list[i].pcn_txctl = 0; 706 ld->pcn_tx_list[i].pcn_txstat = 0; 707 } 708 709 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 710 711 return(0); 712} 713 714 715/* 716 * Initialize the RX descriptors and allocate mbufs for them. 717 */ 718static int 719pcn_list_rx_init(sc) 720 struct pcn_softc *sc; 721{ 722 struct pcn_ring_data *cd; 723 int i; 724 725 cd = &sc->pcn_cdata; 726 727 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 728 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 729 return(ENOBUFS); 730 } 731 732 cd->pcn_rx_prod = 0; 733 734 return(0); 735} 736 737/* 738 * Initialize an RX descriptor and attach an MBUF cluster. 739 */ 740static int 741pcn_newbuf(sc, idx, m) 742 struct pcn_softc *sc; 743 int idx; 744 struct mbuf *m; 745{ 746 struct mbuf *m_new = NULL; 747 struct pcn_rx_desc *c; 748 749 c = &sc->pcn_ldata->pcn_rx_list[idx]; 750 751 if (m == NULL) { 752 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 753 if (m_new == NULL) 754 return(ENOBUFS); 755 756 MCLGET(m_new, M_DONTWAIT); 757 if (!(m_new->m_flags & M_EXT)) { 758 m_freem(m_new); 759 return(ENOBUFS); 760 } 761 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 762 } else { 763 m_new = m; 764 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 765 m_new->m_data = m_new->m_ext.ext_buf; 766 } 767 768 m_adj(m_new, ETHER_ALIGN); 769 770 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 771 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 772 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 773 c->pcn_bufsz |= PCN_RXLEN_MBO; 774 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 775 776 return(0); 777} 778 779/* 780 * A frame has been uploaded: pass the resulting mbuf chain up to 781 * the higher level protocols. 782 */ 783static void 784pcn_rxeof(sc) 785 struct pcn_softc *sc; 786{ 787 struct mbuf *m; 788 struct ifnet *ifp; 789 struct pcn_rx_desc *cur_rx; 790 int i; 791 792 PCN_LOCK_ASSERT(sc); 793 794 ifp = &sc->arpcom.ac_if; 795 i = sc->pcn_cdata.pcn_rx_prod; 796 797 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 798 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 799 m = sc->pcn_cdata.pcn_rx_chain[i]; 800 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 801 802 /* 803 * If an error occurs, update stats, clear the 804 * status word and leave the mbuf cluster in place: 805 * it should simply get re-used next time this descriptor 806 * comes up in the ring. 807 */ 808 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 809 ifp->if_ierrors++; 810 pcn_newbuf(sc, i, m); 811 PCN_INC(i, PCN_RX_LIST_CNT); 812 continue; 813 } 814 815 if (pcn_newbuf(sc, i, NULL)) { 816 /* Ran out of mbufs; recycle this one. */ 817 pcn_newbuf(sc, i, m); 818 ifp->if_ierrors++; 819 PCN_INC(i, PCN_RX_LIST_CNT); 820 continue; 821 } 822 823 PCN_INC(i, PCN_RX_LIST_CNT); 824 825 /* No errors; receive the packet. */ 826 ifp->if_ipackets++; 827 m->m_len = m->m_pkthdr.len = 828 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 829 m->m_pkthdr.rcvif = ifp; 830 831 PCN_UNLOCK(sc); 832 (*ifp->if_input)(ifp, m); 833 PCN_LOCK(sc); 834 } 835 836 sc->pcn_cdata.pcn_rx_prod = i; 837 838 return; 839} 840 841/* 842 * A frame was downloaded to the chip. It's safe for us to clean up 843 * the list buffers. 844 */ 845 846static void 847pcn_txeof(sc) 848 struct pcn_softc *sc; 849{ 850 struct pcn_tx_desc *cur_tx = NULL; 851 struct ifnet *ifp; 852 u_int32_t idx; 853 854 ifp = &sc->arpcom.ac_if; 855 856 /* 857 * Go through our tx list and free mbufs for those 858 * frames that have been transmitted. 859 */ 860 idx = sc->pcn_cdata.pcn_tx_cons; 861 while (idx != sc->pcn_cdata.pcn_tx_prod) { 862 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 863 864 if (!PCN_OWN_TXDESC(cur_tx)) 865 break; 866 867 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 868 sc->pcn_cdata.pcn_tx_cnt--; 869 PCN_INC(idx, PCN_TX_LIST_CNT); 870 continue; 871 } 872 873 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 874 ifp->if_oerrors++; 875 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 876 ifp->if_collisions++; 877 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 878 ifp->if_collisions++; 879 } 880 881 ifp->if_collisions += 882 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 883 884 ifp->if_opackets++; 885 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 886 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 887 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 888 } 889 890 sc->pcn_cdata.pcn_tx_cnt--; 891 PCN_INC(idx, PCN_TX_LIST_CNT); 892 } 893 894 if (idx != sc->pcn_cdata.pcn_tx_cons) { 895 /* Some buffers have been freed. */ 896 sc->pcn_cdata.pcn_tx_cons = idx; 897 ifp->if_flags &= ~IFF_OACTIVE; 898 } 899 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 900 901 return; 902} 903 904static void 905pcn_tick(xsc) 906 void *xsc; 907{ 908 struct pcn_softc *sc; 909 struct mii_data *mii; 910 struct ifnet *ifp; 911 912 sc = xsc; 913 ifp = &sc->arpcom.ac_if; 914 PCN_LOCK(sc); 915 916 mii = device_get_softc(sc->pcn_miibus); 917 mii_tick(mii); 918 919 /* link just died */ 920 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 921 sc->pcn_link = 0; 922 923 /* link just came up, restart */ 924 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 925 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 926 sc->pcn_link++; 927 if (ifp->if_snd.ifq_head != NULL) 928 pcn_start(ifp); 929 } 930 931 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 932 933 PCN_UNLOCK(sc); 934 935 return; 936} 937 938static void 939pcn_intr(arg) 940 void *arg; 941{ 942 struct pcn_softc *sc; 943 struct ifnet *ifp; 944 u_int32_t status; 945 946 sc = arg; 947 ifp = &sc->arpcom.ac_if; 948 949 /* Supress unwanted interrupts */ 950 if (!(ifp->if_flags & IFF_UP)) { 951 pcn_stop(sc); 952 return; 953 } 954 955 PCN_LOCK(sc); 956 957 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 958 959 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 960 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 961 962 if (status & PCN_CSR_RINT) 963 pcn_rxeof(sc); 964 965 if (status & PCN_CSR_TINT) 966 pcn_txeof(sc); 967 968 if (status & PCN_CSR_ERR) { 969 pcn_init(sc); 970 break; 971 } 972 } 973 974 if (ifp->if_snd.ifq_head != NULL) 975 pcn_start(ifp); 976 977 PCN_UNLOCK(sc); 978 return; 979} 980 981/* 982 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 983 * pointers to the fragment pointers. 984 */ 985static int 986pcn_encap(sc, m_head, txidx) 987 struct pcn_softc *sc; 988 struct mbuf *m_head; 989 u_int32_t *txidx; 990{ 991 struct pcn_tx_desc *f = NULL; 992 struct mbuf *m; 993 int frag, cur, cnt = 0; 994 995 /* 996 * Start packing the mbufs in this chain into 997 * the fragment pointers. Stop when we run out 998 * of fragments or hit the end of the mbuf chain. 999 */ 1000 m = m_head; 1001 cur = frag = *txidx; 1002 1003 for (m = m_head; m != NULL; m = m->m_next) { 1004 if (m->m_len != 0) { 1005 if ((PCN_TX_LIST_CNT - 1006 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1007 return(ENOBUFS); 1008 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1009 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1010 f->pcn_txctl |= PCN_TXCTL_MBO; 1011 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1012 if (cnt == 0) 1013 f->pcn_txctl |= PCN_TXCTL_STP; 1014 else 1015 f->pcn_txctl |= PCN_TXCTL_OWN; 1016 cur = frag; 1017 PCN_INC(frag, PCN_TX_LIST_CNT); 1018 cnt++; 1019 } 1020 } 1021 1022 if (m != NULL) 1023 return(ENOBUFS); 1024 1025 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1026 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1027 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1028 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1029 sc->pcn_cdata.pcn_tx_cnt += cnt; 1030 *txidx = frag; 1031 1032 return(0); 1033} 1034 1035/* 1036 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1037 * to the mbuf data regions directly in the transmit lists. We also save a 1038 * copy of the pointers since the transmit list fragment pointers are 1039 * physical addresses. 1040 */ 1041static void 1042pcn_start(ifp) 1043 struct ifnet *ifp; 1044{ 1045 struct pcn_softc *sc; 1046 struct mbuf *m_head = NULL; 1047 u_int32_t idx; 1048 1049 sc = ifp->if_softc; 1050 1051 PCN_LOCK(sc); 1052 1053 if (!sc->pcn_link) { 1054 PCN_UNLOCK(sc); 1055 return; 1056 } 1057 1058 idx = sc->pcn_cdata.pcn_tx_prod; 1059 1060 if (ifp->if_flags & IFF_OACTIVE) { 1061 PCN_UNLOCK(sc); 1062 return; 1063 } 1064 1065 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1066 IF_DEQUEUE(&ifp->if_snd, m_head); 1067 if (m_head == NULL) 1068 break; 1069 1070 if (pcn_encap(sc, m_head, &idx)) { 1071 IF_PREPEND(&ifp->if_snd, m_head); 1072 ifp->if_flags |= IFF_OACTIVE; 1073 break; 1074 } 1075 1076 /* 1077 * If there's a BPF listener, bounce a copy of this frame 1078 * to him. 1079 */ 1080 BPF_MTAP(ifp, m_head); 1081 1082 } 1083 1084 /* Transmit */ 1085 sc->pcn_cdata.pcn_tx_prod = idx; 1086 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1087 1088 /* 1089 * Set a timeout in case the chip goes out to lunch. 1090 */ 1091 ifp->if_timer = 5; 1092 1093 PCN_UNLOCK(sc); 1094 1095 return; 1096} 1097 1098static void 1099pcn_setfilt(ifp) 1100 struct ifnet *ifp; 1101{ 1102 struct pcn_softc *sc; 1103 1104 sc = ifp->if_softc; 1105 1106 /* If we want promiscuous mode, set the allframes bit. */ 1107 if (ifp->if_flags & IFF_PROMISC) { 1108 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1109 } else { 1110 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1111 } 1112 1113 /* Set the capture broadcast bit to capture broadcast frames. */ 1114 if (ifp->if_flags & IFF_BROADCAST) { 1115 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1116 } else { 1117 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1118 } 1119 1120 return; 1121} 1122 1123static void 1124pcn_init(xsc) 1125 void *xsc; 1126{ 1127 struct pcn_softc *sc = xsc; 1128 struct ifnet *ifp = &sc->arpcom.ac_if; 1129 struct mii_data *mii = NULL; 1130 1131 PCN_LOCK(sc); 1132 1133 /* 1134 * Cancel pending I/O and free all RX/TX buffers. 1135 */ 1136 pcn_stop(sc); 1137 pcn_reset(sc); 1138 1139 mii = device_get_softc(sc->pcn_miibus); 1140 1141 /* Set MAC address */ 1142 pcn_csr_write(sc, PCN_CSR_PAR0, 1143 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1144 pcn_csr_write(sc, PCN_CSR_PAR1, 1145 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1146 pcn_csr_write(sc, PCN_CSR_PAR2, 1147 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1148 1149 /* Init circular RX list. */ 1150 if (pcn_list_rx_init(sc) == ENOBUFS) { 1151 printf("pcn%d: initialization failed: no " 1152 "memory for rx buffers\n", sc->pcn_unit); 1153 pcn_stop(sc); 1154 PCN_UNLOCK(sc); 1155 return; 1156 } 1157 1158 /* 1159 * Init tx descriptors. 1160 */ 1161 pcn_list_tx_init(sc); 1162 1163 /* Set up the mode register. */ 1164 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1165 1166 /* Set up RX filter. */ 1167 pcn_setfilt(ifp); 1168 1169 /* 1170 * Load the multicast filter. 1171 */ 1172 pcn_setmulti(sc); 1173 1174 /* 1175 * Load the addresses of the RX and TX lists. 1176 */ 1177 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1178 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1179 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1180 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1181 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1182 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1183 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1184 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1185 1186 /* Set the RX and TX ring sizes. */ 1187 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1188 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1189 1190 /* We're not using the initialization block. */ 1191 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1192 1193 /* Enable fast suspend mode. */ 1194 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1195 1196 /* 1197 * Enable burst read and write. Also set the no underflow 1198 * bit. This will avoid transmit underruns in certain 1199 * conditions while still providing decent performance. 1200 */ 1201 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1202 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1203 1204 /* Enable graceful recovery from underflow. */ 1205 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1206 1207 /* Enable auto-padding of short TX frames. */ 1208 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1209 1210 /* Disable MII autoneg (we handle this ourselves). */ 1211 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1212 1213 if (sc->pcn_type == Am79C978) 1214 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1215 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1216 1217 /* Enable interrupts and start the controller running. */ 1218 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1219 1220 mii_mediachg(mii); 1221 1222 ifp->if_flags |= IFF_RUNNING; 1223 ifp->if_flags &= ~IFF_OACTIVE; 1224 1225 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1226 PCN_UNLOCK(sc); 1227 1228 return; 1229} 1230 1231/* 1232 * Set media options. 1233 */ 1234static int 1235pcn_ifmedia_upd(ifp) 1236 struct ifnet *ifp; 1237{ 1238 struct pcn_softc *sc; 1239 struct mii_data *mii; 1240 1241 sc = ifp->if_softc; 1242 mii = device_get_softc(sc->pcn_miibus); 1243 1244 sc->pcn_link = 0; 1245 if (mii->mii_instance) { 1246 struct mii_softc *miisc; 1247 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1248 mii_phy_reset(miisc); 1249 } 1250 mii_mediachg(mii); 1251 1252 return(0); 1253} 1254 1255/* 1256 * Report current media status. 1257 */ 1258static void 1259pcn_ifmedia_sts(ifp, ifmr) 1260 struct ifnet *ifp; 1261 struct ifmediareq *ifmr; 1262{ 1263 struct pcn_softc *sc; 1264 struct mii_data *mii; 1265 1266 sc = ifp->if_softc; 1267 1268 mii = device_get_softc(sc->pcn_miibus); 1269 mii_pollstat(mii); 1270 ifmr->ifm_active = mii->mii_media_active; 1271 ifmr->ifm_status = mii->mii_media_status; 1272 1273 return; 1274} 1275 1276static int 1277pcn_ioctl(ifp, command, data) 1278 struct ifnet *ifp; 1279 u_long command; 1280 caddr_t data; 1281{ 1282 struct pcn_softc *sc = ifp->if_softc; 1283 struct ifreq *ifr = (struct ifreq *) data; 1284 struct mii_data *mii = NULL; 1285 int error = 0; 1286 1287 PCN_LOCK(sc); 1288 1289 switch(command) { 1290 case SIOCSIFFLAGS: 1291 if (ifp->if_flags & IFF_UP) { 1292 if (ifp->if_flags & IFF_RUNNING && 1293 ifp->if_flags & IFF_PROMISC && 1294 !(sc->pcn_if_flags & IFF_PROMISC)) { 1295 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1296 PCN_EXTCTL1_SPND); 1297 pcn_setfilt(ifp); 1298 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1299 PCN_EXTCTL1_SPND); 1300 pcn_csr_write(sc, PCN_CSR_CSR, 1301 PCN_CSR_INTEN|PCN_CSR_START); 1302 } else if (ifp->if_flags & IFF_RUNNING && 1303 !(ifp->if_flags & IFF_PROMISC) && 1304 sc->pcn_if_flags & IFF_PROMISC) { 1305 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1306 PCN_EXTCTL1_SPND); 1307 pcn_setfilt(ifp); 1308 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1309 PCN_EXTCTL1_SPND); 1310 pcn_csr_write(sc, PCN_CSR_CSR, 1311 PCN_CSR_INTEN|PCN_CSR_START); 1312 } else if (!(ifp->if_flags & IFF_RUNNING)) 1313 pcn_init(sc); 1314 } else { 1315 if (ifp->if_flags & IFF_RUNNING) 1316 pcn_stop(sc); 1317 } 1318 sc->pcn_if_flags = ifp->if_flags; 1319 error = 0; 1320 break; 1321 case SIOCADDMULTI: 1322 case SIOCDELMULTI: 1323 pcn_setmulti(sc); 1324 error = 0; 1325 break; 1326 case SIOCGIFMEDIA: 1327 case SIOCSIFMEDIA: 1328 mii = device_get_softc(sc->pcn_miibus); 1329 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1330 break; 1331 default: 1332 error = ether_ioctl(ifp, command, data); 1333 break; 1334 } 1335 1336 PCN_UNLOCK(sc); 1337 1338 return(error); 1339} 1340 1341static void 1342pcn_watchdog(ifp) 1343 struct ifnet *ifp; 1344{ 1345 struct pcn_softc *sc; 1346 1347 sc = ifp->if_softc; 1348 1349 PCN_LOCK(sc); 1350 1351 ifp->if_oerrors++; 1352 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1353 1354 pcn_stop(sc); 1355 pcn_reset(sc); 1356 pcn_init(sc); 1357 1358 if (ifp->if_snd.ifq_head != NULL) 1359 pcn_start(ifp); 1360 1361 PCN_UNLOCK(sc); 1362 1363 return; 1364} 1365 1366/* 1367 * Stop the adapter and free any mbufs allocated to the 1368 * RX and TX lists. 1369 */ 1370static void 1371pcn_stop(sc) 1372 struct pcn_softc *sc; 1373{ 1374 register int i; 1375 struct ifnet *ifp; 1376 1377 ifp = &sc->arpcom.ac_if; 1378 PCN_LOCK(sc); 1379 ifp->if_timer = 0; 1380 1381 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1382 1383 /* Turn off interrupts */ 1384 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1385 /* Stop adapter */ 1386 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1387 sc->pcn_link = 0; 1388 1389 /* 1390 * Free data in the RX lists. 1391 */ 1392 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1393 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1394 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1395 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1396 } 1397 } 1398 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1399 sizeof(sc->pcn_ldata->pcn_rx_list)); 1400 1401 /* 1402 * Free the TX list buffers. 1403 */ 1404 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1405 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1406 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1407 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1408 } 1409 } 1410 1411 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1412 sizeof(sc->pcn_ldata->pcn_tx_list)); 1413 1414 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1415 PCN_UNLOCK(sc); 1416 1417 return; 1418} 1419 1420/* 1421 * Stop all chip I/O so that the kernel's probe routines don't 1422 * get confused by errant DMAs when rebooting. 1423 */ 1424static void 1425pcn_shutdown(dev) 1426 device_t dev; 1427{ 1428 struct pcn_softc *sc; 1429 1430 sc = device_get_softc(dev); 1431 1432 PCN_LOCK(sc); 1433 pcn_reset(sc); 1434 pcn_stop(sc); 1435 PCN_UNLOCK(sc); 1436 1437 return; 1438} 1439