if_pcn.c revision 115531
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 115531 2003-05-31 20:02:43Z phk $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <pci/pcireg.h> 84#include <pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static u_int32_t pcn_crc (caddr_t); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216 int val; 217{ 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221} 222 223static u_int32_t 224pcn_bcr_read(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227{ 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230} 231 232static u_int16_t 233pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void 242pcn_bcr_write(sc, reg, val) 243 struct pcn_softc *sc; 244 int reg; 245 int val; 246{ 247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 248 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 249 return; 250} 251 252static int 253pcn_miibus_readreg(dev, phy, reg) 254 device_t dev; 255 int phy, reg; 256{ 257 struct pcn_softc *sc; 258 int val; 259 260 sc = device_get_softc(dev); 261 262 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 263 return(0); 264 265 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 266 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 267 if (val == 0xFFFF) 268 return(0); 269 270 sc->pcn_phyaddr = phy; 271 272 return(val); 273} 274 275static int 276pcn_miibus_writereg(dev, phy, reg, data) 277 device_t dev; 278 int phy, reg, data; 279{ 280 struct pcn_softc *sc; 281 282 sc = device_get_softc(dev); 283 284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 285 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 286 287 return(0); 288} 289 290static void 291pcn_miibus_statchg(dev) 292 device_t dev; 293{ 294 struct pcn_softc *sc; 295 struct mii_data *mii; 296 297 sc = device_get_softc(dev); 298 mii = device_get_softc(sc->pcn_miibus); 299 300 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 301 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } else { 303 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 304 } 305 306 return; 307} 308 309#define DC_POLY 0xEDB88320 310 311static u_int32_t 312pcn_crc(addr) 313 caddr_t addr; 314{ 315 u_int32_t idx, bit, data, crc; 316 317 /* Compute CRC for the address value. */ 318 crc = 0xFFFFFFFF; /* initial value */ 319 320 for (idx = 0; idx < 6; idx++) { 321 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 322 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 323 } 324 325 return ((crc >> 26) & 0x3F); 326} 327 328static void 329pcn_setmulti(sc) 330 struct pcn_softc *sc; 331{ 332 struct ifnet *ifp; 333 struct ifmultiaddr *ifma; 334 u_int32_t h, i; 335 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 336 337 ifp = &sc->arpcom.ac_if; 338 339 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 340 341 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 342 for (i = 0; i < 4; i++) 343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 344 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 345 return; 346 } 347 348 /* first, zot all the existing hash bits */ 349 for (i = 0; i < 4; i++) 350 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 351 352 /* now program new ones */ 353 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 354 if (ifma->ifma_addr->sa_family != AF_LINK) 355 continue; 356 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 357 hashes[h >> 4] |= 1 << (h & 0xF); 358 } 359 360 for (i = 0; i < 4; i++) 361 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 362 363 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 364 365 return; 366} 367 368static void 369pcn_reset(sc) 370 struct pcn_softc *sc; 371{ 372 /* 373 * Issue a reset by reading from the RESET register. 374 * Note that we don't know if the chip is operating in 375 * 16-bit or 32-bit mode at this point, so we attempt 376 * to reset the chip both ways. If one fails, the other 377 * will succeed. 378 */ 379 CSR_READ_2(sc, PCN_IO16_RESET); 380 CSR_READ_4(sc, PCN_IO32_RESET); 381 382 /* Wait a little while for the chip to get its brains in order. */ 383 DELAY(1000); 384 385 /* Select 32-bit (DWIO) mode */ 386 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 387 388 /* Select software style 3. */ 389 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 390 391 return; 392} 393 394/* 395 * Probe for an AMD chip. Check the PCI vendor and device 396 * IDs against our list and return a device name if we find a match. 397 */ 398static int 399pcn_probe(dev) 400 device_t dev; 401{ 402 struct pcn_type *t; 403 struct pcn_softc *sc; 404 int rid; 405 u_int32_t chip_id; 406 407 t = pcn_devs; 408 sc = device_get_softc(dev); 409 410 while(t->pcn_name != NULL) { 411 if ((pci_get_vendor(dev) == t->pcn_vid) && 412 (pci_get_device(dev) == t->pcn_did)) { 413 /* 414 * Temporarily map the I/O space 415 * so we can read the chip ID register. 416 */ 417 rid = PCN_RID; 418 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 419 0, ~0, 1, RF_ACTIVE); 420 if (sc->pcn_res == NULL) { 421 device_printf(dev, 422 "couldn't map ports/memory\n"); 423 return(ENXIO); 424 } 425 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 426 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 427 mtx_init(&sc->pcn_mtx, 428 device_get_nameunit(dev), MTX_NETWORK_LOCK, 429 MTX_DEF); 430 PCN_LOCK(sc); 431 /* 432 * Note: we can *NOT* put the chip into 433 * 32-bit mode yet. The lnc driver will only 434 * work in 16-bit mode, and once the chip 435 * goes into 32-bit mode, the only way to 436 * get it out again is with a hardware reset. 437 * So if pcn_probe() is called before the 438 * lnc driver's probe routine, the chip will 439 * be locked into 32-bit operation and the lnc 440 * driver will be unable to attach to it. 441 * Note II: if the chip happens to already 442 * be in 32-bit mode, we still need to check 443 * the chip ID, but first we have to detect 444 * 32-bit mode using only 16-bit operations. 445 * The safest way to do this is to read the 446 * PCI subsystem ID from BCR23/24 and compare 447 * that with the value read from PCI config 448 * space. 449 */ 450 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 451 chip_id <<= 16; 452 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 453 /* 454 * Note III: the test for 0x10001000 is a hack to 455 * pacify VMware, who's pseudo-PCnet interface is 456 * broken. Reading the subsystem register from PCI 457 * config space yeilds 0x00000000 while reading the 458 * same value from I/O space yeilds 0x10001000. It's 459 * not supposed to be that way. 460 */ 461 if (chip_id == pci_read_config(dev, 462 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 463 /* We're in 16-bit mode. */ 464 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 465 chip_id <<= 16; 466 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 467 } else { 468 /* We're in 32-bit mode. */ 469 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 470 chip_id <<= 16; 471 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 472 } 473 bus_release_resource(dev, PCN_RES, 474 PCN_RID, sc->pcn_res); 475 PCN_UNLOCK(sc); 476 mtx_destroy(&sc->pcn_mtx); 477 chip_id >>= 12; 478 sc->pcn_type = chip_id & PART_MASK; 479 switch(sc->pcn_type) { 480 case Am79C971: 481 case Am79C972: 482 case Am79C973: 483 case Am79C975: 484 case Am79C976: 485 case Am79C978: 486 break; 487 default: 488 return(ENXIO); 489 } 490 device_set_desc(dev, t->pcn_name); 491 return(0); 492 } 493 t++; 494 } 495 496 return(ENXIO); 497} 498 499/* 500 * Attach the interface. Allocate softc structures, do ifmedia 501 * setup and ethernet/BPF attach. 502 */ 503static int 504pcn_attach(dev) 505 device_t dev; 506{ 507 u_int32_t eaddr[2]; 508 struct pcn_softc *sc; 509 struct ifnet *ifp; 510 int unit, error = 0, rid; 511 512 sc = device_get_softc(dev); 513 unit = device_get_unit(dev); 514 515 /* Initialize our mutex. */ 516 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 517 MTX_DEF | MTX_RECURSE); 518 519 /* 520 * Handle power management nonsense. 521 */ 522 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 523 u_int32_t iobase, membase, irq; 524 525 /* Save important PCI config data. */ 526 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 527 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 528 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 529 530 /* Reset the power state. */ 531 printf("pcn%d: chip is in D%d power mode " 532 "-- setting to D0\n", unit, 533 pci_get_powerstate(dev)); 534 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 535 536 /* Restore PCI config data. */ 537 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 538 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 539 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 540 } 541 542 /* 543 * Map control/status registers. 544 */ 545 pci_enable_busmaster(dev); 546 547 rid = PCN_RID; 548 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 549 0, ~0, 1, RF_ACTIVE); 550 551 if (sc->pcn_res == NULL) { 552 printf("pcn%d: couldn't map ports/memory\n", unit); 553 error = ENXIO; 554 goto fail; 555 } 556 557 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 558 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 559 560 /* Allocate interrupt */ 561 rid = 0; 562 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 563 RF_SHAREABLE | RF_ACTIVE); 564 565 if (sc->pcn_irq == NULL) { 566 printf("pcn%d: couldn't map interrupt\n", unit); 567 error = ENXIO; 568 goto fail; 569 } 570 571 /* Reset the adapter. */ 572 pcn_reset(sc); 573 574 /* 575 * Get station address from the EEPROM. 576 */ 577 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 578 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 579 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 580 581 /* 582 * An AMD chip was detected. Inform the world. 583 */ 584 printf("pcn%d: Ethernet address: %6D\n", unit, 585 sc->arpcom.ac_enaddr, ":"); 586 587 sc->pcn_unit = unit; 588 callout_handle_init(&sc->pcn_stat_ch); 589 590 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 591 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 592 593 if (sc->pcn_ldata == NULL) { 594 printf("pcn%d: no memory for list buffers!\n", unit); 595 error = ENXIO; 596 goto fail; 597 } 598 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 599 600 ifp = &sc->arpcom.ac_if; 601 ifp->if_softc = sc; 602 ifp->if_unit = unit; 603 ifp->if_name = "pcn"; 604 ifp->if_mtu = ETHERMTU; 605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 606 ifp->if_ioctl = pcn_ioctl; 607 ifp->if_output = ether_output; 608 ifp->if_start = pcn_start; 609 ifp->if_watchdog = pcn_watchdog; 610 ifp->if_init = pcn_init; 611 ifp->if_baudrate = 10000000; 612 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 613 614 /* 615 * Do MII setup. 616 */ 617 if (mii_phy_probe(dev, &sc->pcn_miibus, 618 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 619 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 620 error = ENXIO; 621 goto fail; 622 } 623 624 /* 625 * Call MI attach routine. 626 */ 627 ether_ifattach(ifp, (u_int8_t *) eaddr); 628 629 /* Hook interrupt last to avoid having to lock softc */ 630 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 631 pcn_intr, sc, &sc->pcn_intrhand); 632 633 if (error) { 634 printf("pcn%d: couldn't set up irq\n", unit); 635 ether_ifdetach(ifp); 636 goto fail; 637 } 638 639fail: 640 if (error) 641 pcn_detach(dev); 642 643 return(error); 644} 645 646/* 647 * Shutdown hardware and free up resources. This can be called any 648 * time after the mutex has been initialized. It is called in both 649 * the error case in attach and the normal detach case so it needs 650 * to be careful about only freeing resources that have actually been 651 * allocated. 652 */ 653static int 654pcn_detach(dev) 655 device_t dev; 656{ 657 struct pcn_softc *sc; 658 struct ifnet *ifp; 659 660 sc = device_get_softc(dev); 661 ifp = &sc->arpcom.ac_if; 662 663 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 664 PCN_LOCK(sc); 665 666 /* These should only be active if attach succeeded */ 667 if (device_is_attached(dev)) { 668 pcn_reset(sc); 669 pcn_stop(sc); 670 ether_ifdetach(ifp); 671 } 672 if (sc->pcn_miibus) 673 device_delete_child(dev, sc->pcn_miibus); 674 bus_generic_detach(dev); 675 676 if (sc->pcn_intrhand) 677 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 678 if (sc->pcn_irq) 679 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 680 if (sc->pcn_res) 681 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 682 683 if (sc->pcn_ldata) { 684 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 685 M_DEVBUF); 686 } 687 PCN_UNLOCK(sc); 688 689 mtx_destroy(&sc->pcn_mtx); 690 691 return(0); 692} 693 694/* 695 * Initialize the transmit descriptors. 696 */ 697static int 698pcn_list_tx_init(sc) 699 struct pcn_softc *sc; 700{ 701 struct pcn_list_data *ld; 702 struct pcn_ring_data *cd; 703 int i; 704 705 cd = &sc->pcn_cdata; 706 ld = sc->pcn_ldata; 707 708 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 709 cd->pcn_tx_chain[i] = NULL; 710 ld->pcn_tx_list[i].pcn_tbaddr = 0; 711 ld->pcn_tx_list[i].pcn_txctl = 0; 712 ld->pcn_tx_list[i].pcn_txstat = 0; 713 } 714 715 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 716 717 return(0); 718} 719 720 721/* 722 * Initialize the RX descriptors and allocate mbufs for them. 723 */ 724static int 725pcn_list_rx_init(sc) 726 struct pcn_softc *sc; 727{ 728 struct pcn_ring_data *cd; 729 int i; 730 731 cd = &sc->pcn_cdata; 732 733 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 734 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 735 return(ENOBUFS); 736 } 737 738 cd->pcn_rx_prod = 0; 739 740 return(0); 741} 742 743/* 744 * Initialize an RX descriptor and attach an MBUF cluster. 745 */ 746static int 747pcn_newbuf(sc, idx, m) 748 struct pcn_softc *sc; 749 int idx; 750 struct mbuf *m; 751{ 752 struct mbuf *m_new = NULL; 753 struct pcn_rx_desc *c; 754 755 c = &sc->pcn_ldata->pcn_rx_list[idx]; 756 757 if (m == NULL) { 758 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 759 if (m_new == NULL) 760 return(ENOBUFS); 761 762 MCLGET(m_new, M_DONTWAIT); 763 if (!(m_new->m_flags & M_EXT)) { 764 m_freem(m_new); 765 return(ENOBUFS); 766 } 767 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 768 } else { 769 m_new = m; 770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 771 m_new->m_data = m_new->m_ext.ext_buf; 772 } 773 774 m_adj(m_new, ETHER_ALIGN); 775 776 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 777 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 778 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 779 c->pcn_bufsz |= PCN_RXLEN_MBO; 780 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 781 782 return(0); 783} 784 785/* 786 * A frame has been uploaded: pass the resulting mbuf chain up to 787 * the higher level protocols. 788 */ 789static void 790pcn_rxeof(sc) 791 struct pcn_softc *sc; 792{ 793 struct mbuf *m; 794 struct ifnet *ifp; 795 struct pcn_rx_desc *cur_rx; 796 int i; 797 798 ifp = &sc->arpcom.ac_if; 799 i = sc->pcn_cdata.pcn_rx_prod; 800 801 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 802 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 803 m = sc->pcn_cdata.pcn_rx_chain[i]; 804 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 805 806 /* 807 * If an error occurs, update stats, clear the 808 * status word and leave the mbuf cluster in place: 809 * it should simply get re-used next time this descriptor 810 * comes up in the ring. 811 */ 812 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 813 ifp->if_ierrors++; 814 pcn_newbuf(sc, i, m); 815 PCN_INC(i, PCN_RX_LIST_CNT); 816 continue; 817 } 818 819 if (pcn_newbuf(sc, i, NULL)) { 820 /* Ran out of mbufs; recycle this one. */ 821 pcn_newbuf(sc, i, m); 822 ifp->if_ierrors++; 823 PCN_INC(i, PCN_RX_LIST_CNT); 824 continue; 825 } 826 827 PCN_INC(i, PCN_RX_LIST_CNT); 828 829 /* No errors; receive the packet. */ 830 ifp->if_ipackets++; 831 m->m_len = m->m_pkthdr.len = 832 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 833 m->m_pkthdr.rcvif = ifp; 834 835 (*ifp->if_input)(ifp, m); 836 } 837 838 sc->pcn_cdata.pcn_rx_prod = i; 839 840 return; 841} 842 843/* 844 * A frame was downloaded to the chip. It's safe for us to clean up 845 * the list buffers. 846 */ 847 848static void 849pcn_txeof(sc) 850 struct pcn_softc *sc; 851{ 852 struct pcn_tx_desc *cur_tx = NULL; 853 struct ifnet *ifp; 854 u_int32_t idx; 855 856 ifp = &sc->arpcom.ac_if; 857 858 /* 859 * Go through our tx list and free mbufs for those 860 * frames that have been transmitted. 861 */ 862 idx = sc->pcn_cdata.pcn_tx_cons; 863 while (idx != sc->pcn_cdata.pcn_tx_prod) { 864 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 865 866 if (!PCN_OWN_TXDESC(cur_tx)) 867 break; 868 869 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 870 sc->pcn_cdata.pcn_tx_cnt--; 871 PCN_INC(idx, PCN_TX_LIST_CNT); 872 continue; 873 } 874 875 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 876 ifp->if_oerrors++; 877 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 878 ifp->if_collisions++; 879 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 880 ifp->if_collisions++; 881 } 882 883 ifp->if_collisions += 884 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 885 886 ifp->if_opackets++; 887 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 888 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 889 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 890 } 891 892 sc->pcn_cdata.pcn_tx_cnt--; 893 PCN_INC(idx, PCN_TX_LIST_CNT); 894 } 895 896 if (idx != sc->pcn_cdata.pcn_tx_cons) { 897 /* Some buffers have been freed. */ 898 sc->pcn_cdata.pcn_tx_cons = idx; 899 ifp->if_flags &= ~IFF_OACTIVE; 900 } 901 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 902 903 return; 904} 905 906static void 907pcn_tick(xsc) 908 void *xsc; 909{ 910 struct pcn_softc *sc; 911 struct mii_data *mii; 912 struct ifnet *ifp; 913 914 sc = xsc; 915 ifp = &sc->arpcom.ac_if; 916 PCN_LOCK(sc); 917 918 mii = device_get_softc(sc->pcn_miibus); 919 mii_tick(mii); 920 921 /* link just died */ 922 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 923 sc->pcn_link = 0; 924 925 /* link just came up, restart */ 926 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 927 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 928 sc->pcn_link++; 929 if (ifp->if_snd.ifq_head != NULL) 930 pcn_start(ifp); 931 } 932 933 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 934 935 PCN_UNLOCK(sc); 936 937 return; 938} 939 940static void 941pcn_intr(arg) 942 void *arg; 943{ 944 struct pcn_softc *sc; 945 struct ifnet *ifp; 946 u_int32_t status; 947 948 sc = arg; 949 ifp = &sc->arpcom.ac_if; 950 951 /* Supress unwanted interrupts */ 952 if (!(ifp->if_flags & IFF_UP)) { 953 pcn_stop(sc); 954 return; 955 } 956 957 PCN_LOCK(sc); 958 959 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 960 961 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 962 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 963 964 if (status & PCN_CSR_RINT) 965 pcn_rxeof(sc); 966 967 if (status & PCN_CSR_TINT) 968 pcn_txeof(sc); 969 970 if (status & PCN_CSR_ERR) { 971 pcn_init(sc); 972 break; 973 } 974 } 975 976 if (ifp->if_snd.ifq_head != NULL) 977 pcn_start(ifp); 978 979 PCN_UNLOCK(sc); 980 return; 981} 982 983/* 984 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 985 * pointers to the fragment pointers. 986 */ 987static int 988pcn_encap(sc, m_head, txidx) 989 struct pcn_softc *sc; 990 struct mbuf *m_head; 991 u_int32_t *txidx; 992{ 993 struct pcn_tx_desc *f = NULL; 994 struct mbuf *m; 995 int frag, cur, cnt = 0; 996 997 /* 998 * Start packing the mbufs in this chain into 999 * the fragment pointers. Stop when we run out 1000 * of fragments or hit the end of the mbuf chain. 1001 */ 1002 m = m_head; 1003 cur = frag = *txidx; 1004 1005 for (m = m_head; m != NULL; m = m->m_next) { 1006 if (m->m_len != 0) { 1007 if ((PCN_TX_LIST_CNT - 1008 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1009 return(ENOBUFS); 1010 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1011 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1012 f->pcn_txctl |= PCN_TXCTL_MBO; 1013 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1014 if (cnt == 0) 1015 f->pcn_txctl |= PCN_TXCTL_STP; 1016 else 1017 f->pcn_txctl |= PCN_TXCTL_OWN; 1018 cur = frag; 1019 PCN_INC(frag, PCN_TX_LIST_CNT); 1020 cnt++; 1021 } 1022 } 1023 1024 if (m != NULL) 1025 return(ENOBUFS); 1026 1027 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1028 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1029 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1030 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1031 sc->pcn_cdata.pcn_tx_cnt += cnt; 1032 *txidx = frag; 1033 1034 return(0); 1035} 1036 1037/* 1038 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1039 * to the mbuf data regions directly in the transmit lists. We also save a 1040 * copy of the pointers since the transmit list fragment pointers are 1041 * physical addresses. 1042 */ 1043static void 1044pcn_start(ifp) 1045 struct ifnet *ifp; 1046{ 1047 struct pcn_softc *sc; 1048 struct mbuf *m_head = NULL; 1049 u_int32_t idx; 1050 1051 sc = ifp->if_softc; 1052 1053 PCN_LOCK(sc); 1054 1055 if (!sc->pcn_link) { 1056 PCN_UNLOCK(sc); 1057 return; 1058 } 1059 1060 idx = sc->pcn_cdata.pcn_tx_prod; 1061 1062 if (ifp->if_flags & IFF_OACTIVE) { 1063 PCN_UNLOCK(sc); 1064 return; 1065 } 1066 1067 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1068 IF_DEQUEUE(&ifp->if_snd, m_head); 1069 if (m_head == NULL) 1070 break; 1071 1072 if (pcn_encap(sc, m_head, &idx)) { 1073 IF_PREPEND(&ifp->if_snd, m_head); 1074 ifp->if_flags |= IFF_OACTIVE; 1075 break; 1076 } 1077 1078 /* 1079 * If there's a BPF listener, bounce a copy of this frame 1080 * to him. 1081 */ 1082 BPF_MTAP(ifp, m_head); 1083 1084 } 1085 1086 /* Transmit */ 1087 sc->pcn_cdata.pcn_tx_prod = idx; 1088 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1089 1090 /* 1091 * Set a timeout in case the chip goes out to lunch. 1092 */ 1093 ifp->if_timer = 5; 1094 1095 PCN_UNLOCK(sc); 1096 1097 return; 1098} 1099 1100static void 1101pcn_setfilt(ifp) 1102 struct ifnet *ifp; 1103{ 1104 struct pcn_softc *sc; 1105 1106 sc = ifp->if_softc; 1107 1108 /* If we want promiscuous mode, set the allframes bit. */ 1109 if (ifp->if_flags & IFF_PROMISC) { 1110 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1111 } else { 1112 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1113 } 1114 1115 /* Set the capture broadcast bit to capture broadcast frames. */ 1116 if (ifp->if_flags & IFF_BROADCAST) { 1117 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1118 } else { 1119 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1120 } 1121 1122 return; 1123} 1124 1125static void 1126pcn_init(xsc) 1127 void *xsc; 1128{ 1129 struct pcn_softc *sc = xsc; 1130 struct ifnet *ifp = &sc->arpcom.ac_if; 1131 struct mii_data *mii = NULL; 1132 1133 PCN_LOCK(sc); 1134 1135 /* 1136 * Cancel pending I/O and free all RX/TX buffers. 1137 */ 1138 pcn_stop(sc); 1139 pcn_reset(sc); 1140 1141 mii = device_get_softc(sc->pcn_miibus); 1142 1143 /* Set MAC address */ 1144 pcn_csr_write(sc, PCN_CSR_PAR0, 1145 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1146 pcn_csr_write(sc, PCN_CSR_PAR1, 1147 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1148 pcn_csr_write(sc, PCN_CSR_PAR2, 1149 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1150 1151 /* Init circular RX list. */ 1152 if (pcn_list_rx_init(sc) == ENOBUFS) { 1153 printf("pcn%d: initialization failed: no " 1154 "memory for rx buffers\n", sc->pcn_unit); 1155 pcn_stop(sc); 1156 PCN_UNLOCK(sc); 1157 return; 1158 } 1159 1160 /* 1161 * Init tx descriptors. 1162 */ 1163 pcn_list_tx_init(sc); 1164 1165 /* Set up the mode register. */ 1166 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1167 1168 /* Set up RX filter. */ 1169 pcn_setfilt(ifp); 1170 1171 /* 1172 * Load the multicast filter. 1173 */ 1174 pcn_setmulti(sc); 1175 1176 /* 1177 * Load the addresses of the RX and TX lists. 1178 */ 1179 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1180 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1181 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1182 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1183 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1184 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1185 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1186 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1187 1188 /* Set the RX and TX ring sizes. */ 1189 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1190 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1191 1192 /* We're not using the initialization block. */ 1193 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1194 1195 /* Enable fast suspend mode. */ 1196 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1197 1198 /* 1199 * Enable burst read and write. Also set the no underflow 1200 * bit. This will avoid transmit underruns in certain 1201 * conditions while still providing decent performance. 1202 */ 1203 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1204 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1205 1206 /* Enable graceful recovery from underflow. */ 1207 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1208 1209 /* Enable auto-padding of short TX frames. */ 1210 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1211 1212 /* Disable MII autoneg (we handle this ourselves). */ 1213 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1214 1215 if (sc->pcn_type == Am79C978) 1216 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1217 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1218 1219 /* Enable interrupts and start the controller running. */ 1220 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1221 1222 mii_mediachg(mii); 1223 1224 ifp->if_flags |= IFF_RUNNING; 1225 ifp->if_flags &= ~IFF_OACTIVE; 1226 1227 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1228 PCN_UNLOCK(sc); 1229 1230 return; 1231} 1232 1233/* 1234 * Set media options. 1235 */ 1236static int 1237pcn_ifmedia_upd(ifp) 1238 struct ifnet *ifp; 1239{ 1240 struct pcn_softc *sc; 1241 struct mii_data *mii; 1242 1243 sc = ifp->if_softc; 1244 mii = device_get_softc(sc->pcn_miibus); 1245 1246 sc->pcn_link = 0; 1247 if (mii->mii_instance) { 1248 struct mii_softc *miisc; 1249 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1250 mii_phy_reset(miisc); 1251 } 1252 mii_mediachg(mii); 1253 1254 return(0); 1255} 1256 1257/* 1258 * Report current media status. 1259 */ 1260static void 1261pcn_ifmedia_sts(ifp, ifmr) 1262 struct ifnet *ifp; 1263 struct ifmediareq *ifmr; 1264{ 1265 struct pcn_softc *sc; 1266 struct mii_data *mii; 1267 1268 sc = ifp->if_softc; 1269 1270 mii = device_get_softc(sc->pcn_miibus); 1271 mii_pollstat(mii); 1272 ifmr->ifm_active = mii->mii_media_active; 1273 ifmr->ifm_status = mii->mii_media_status; 1274 1275 return; 1276} 1277 1278static int 1279pcn_ioctl(ifp, command, data) 1280 struct ifnet *ifp; 1281 u_long command; 1282 caddr_t data; 1283{ 1284 struct pcn_softc *sc = ifp->if_softc; 1285 struct ifreq *ifr = (struct ifreq *) data; 1286 struct mii_data *mii = NULL; 1287 int error = 0; 1288 1289 PCN_LOCK(sc); 1290 1291 switch(command) { 1292 case SIOCSIFFLAGS: 1293 if (ifp->if_flags & IFF_UP) { 1294 if (ifp->if_flags & IFF_RUNNING && 1295 ifp->if_flags & IFF_PROMISC && 1296 !(sc->pcn_if_flags & IFF_PROMISC)) { 1297 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1298 PCN_EXTCTL1_SPND); 1299 pcn_setfilt(ifp); 1300 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1301 PCN_EXTCTL1_SPND); 1302 pcn_csr_write(sc, PCN_CSR_CSR, 1303 PCN_CSR_INTEN|PCN_CSR_START); 1304 } else if (ifp->if_flags & IFF_RUNNING && 1305 !(ifp->if_flags & IFF_PROMISC) && 1306 sc->pcn_if_flags & IFF_PROMISC) { 1307 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1308 PCN_EXTCTL1_SPND); 1309 pcn_setfilt(ifp); 1310 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1311 PCN_EXTCTL1_SPND); 1312 pcn_csr_write(sc, PCN_CSR_CSR, 1313 PCN_CSR_INTEN|PCN_CSR_START); 1314 } else if (!(ifp->if_flags & IFF_RUNNING)) 1315 pcn_init(sc); 1316 } else { 1317 if (ifp->if_flags & IFF_RUNNING) 1318 pcn_stop(sc); 1319 } 1320 sc->pcn_if_flags = ifp->if_flags; 1321 error = 0; 1322 break; 1323 case SIOCADDMULTI: 1324 case SIOCDELMULTI: 1325 pcn_setmulti(sc); 1326 error = 0; 1327 break; 1328 case SIOCGIFMEDIA: 1329 case SIOCSIFMEDIA: 1330 mii = device_get_softc(sc->pcn_miibus); 1331 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1332 break; 1333 default: 1334 error = ether_ioctl(ifp, command, data); 1335 break; 1336 } 1337 1338 PCN_UNLOCK(sc); 1339 1340 return(error); 1341} 1342 1343static void 1344pcn_watchdog(ifp) 1345 struct ifnet *ifp; 1346{ 1347 struct pcn_softc *sc; 1348 1349 sc = ifp->if_softc; 1350 1351 PCN_LOCK(sc); 1352 1353 ifp->if_oerrors++; 1354 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1355 1356 pcn_stop(sc); 1357 pcn_reset(sc); 1358 pcn_init(sc); 1359 1360 if (ifp->if_snd.ifq_head != NULL) 1361 pcn_start(ifp); 1362 1363 PCN_UNLOCK(sc); 1364 1365 return; 1366} 1367 1368/* 1369 * Stop the adapter and free any mbufs allocated to the 1370 * RX and TX lists. 1371 */ 1372static void 1373pcn_stop(sc) 1374 struct pcn_softc *sc; 1375{ 1376 register int i; 1377 struct ifnet *ifp; 1378 1379 ifp = &sc->arpcom.ac_if; 1380 PCN_LOCK(sc); 1381 ifp->if_timer = 0; 1382 1383 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1384 1385 /* Turn off interrupts */ 1386 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1387 /* Stop adapter */ 1388 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1389 sc->pcn_link = 0; 1390 1391 /* 1392 * Free data in the RX lists. 1393 */ 1394 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1395 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1396 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1397 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1398 } 1399 } 1400 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1401 sizeof(sc->pcn_ldata->pcn_rx_list)); 1402 1403 /* 1404 * Free the TX list buffers. 1405 */ 1406 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1407 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1408 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1409 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1410 } 1411 } 1412 1413 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1414 sizeof(sc->pcn_ldata->pcn_tx_list)); 1415 1416 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1417 PCN_UNLOCK(sc); 1418 1419 return; 1420} 1421 1422/* 1423 * Stop all chip I/O so that the kernel's probe routines don't 1424 * get confused by errant DMAs when rebooting. 1425 */ 1426static void 1427pcn_shutdown(dev) 1428 device_t dev; 1429{ 1430 struct pcn_softc *sc; 1431 1432 sc = device_get_softc(dev); 1433 1434 PCN_LOCK(sc); 1435 pcn_reset(sc); 1436 pcn_stop(sc); 1437 PCN_UNLOCK(sc); 1438 1439 return; 1440} 1441