if_pcn.c revision 113506
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 113506 2003-04-15 06:37:30Z mdodd $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <pci/pcireg.h> 84#include <pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static u_int32_t pcn_crc (caddr_t); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216{ 217 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 218 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 219 return; 220} 221 222static u_int32_t 223pcn_bcr_read(sc, reg) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 return(CSR_READ_4(sc, PCN_IO32_BDP)); 229} 230 231static u_int16_t 232pcn_bcr_read16(sc, reg) 233 struct pcn_softc *sc; 234 int reg; 235{ 236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 237 return(CSR_READ_2(sc, PCN_IO16_BDP)); 238} 239 240static void 241pcn_bcr_write(sc, reg, val) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 247 return; 248} 249 250static int 251pcn_miibus_readreg(dev, phy, reg) 252 device_t dev; 253 int phy, reg; 254{ 255 struct pcn_softc *sc; 256 int val; 257 258 sc = device_get_softc(dev); 259 260 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 261 return(0); 262 263 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 264 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 265 if (val == 0xFFFF) 266 return(0); 267 268 sc->pcn_phyaddr = phy; 269 270 return(val); 271} 272 273static int 274pcn_miibus_writereg(dev, phy, reg, data) 275 device_t dev; 276 int phy, reg, data; 277{ 278 struct pcn_softc *sc; 279 280 sc = device_get_softc(dev); 281 282 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 283 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 284 285 return(0); 286} 287 288static void 289pcn_miibus_statchg(dev) 290 device_t dev; 291{ 292 struct pcn_softc *sc; 293 struct mii_data *mii; 294 295 sc = device_get_softc(dev); 296 mii = device_get_softc(sc->pcn_miibus); 297 298 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 299 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 300 } else { 301 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } 303 304 return; 305} 306 307#define DC_POLY 0xEDB88320 308 309static u_int32_t 310pcn_crc(addr) 311 caddr_t addr; 312{ 313 u_int32_t idx, bit, data, crc; 314 315 /* Compute CRC for the address value. */ 316 crc = 0xFFFFFFFF; /* initial value */ 317 318 for (idx = 0; idx < 6; idx++) { 319 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 320 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 321 } 322 323 return ((crc >> 26) & 0x3F); 324} 325 326static void 327pcn_setmulti(sc) 328 struct pcn_softc *sc; 329{ 330 struct ifnet *ifp; 331 struct ifmultiaddr *ifma; 332 u_int32_t h, i; 333 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 334 335 ifp = &sc->arpcom.ac_if; 336 337 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 338 339 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 340 for (i = 0; i < 4; i++) 341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 342 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 343 return; 344 } 345 346 /* first, zot all the existing hash bits */ 347 for (i = 0; i < 4; i++) 348 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 349 350 /* now program new ones */ 351 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 352 if (ifma->ifma_addr->sa_family != AF_LINK) 353 continue; 354 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 355 hashes[h >> 4] |= 1 << (h & 0xF); 356 } 357 358 for (i = 0; i < 4; i++) 359 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 360 361 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 362 363 return; 364} 365 366static void 367pcn_reset(sc) 368 struct pcn_softc *sc; 369{ 370 /* 371 * Issue a reset by reading from the RESET register. 372 * Note that we don't know if the chip is operating in 373 * 16-bit or 32-bit mode at this point, so we attempt 374 * to reset the chip both ways. If one fails, the other 375 * will succeed. 376 */ 377 CSR_READ_2(sc, PCN_IO16_RESET); 378 CSR_READ_4(sc, PCN_IO32_RESET); 379 380 /* Wait a little while for the chip to get its brains in order. */ 381 DELAY(1000); 382 383 /* Select 32-bit (DWIO) mode */ 384 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 385 386 /* Select software style 3. */ 387 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 388 389 return; 390} 391 392/* 393 * Probe for an AMD chip. Check the PCI vendor and device 394 * IDs against our list and return a device name if we find a match. 395 */ 396static int 397pcn_probe(dev) 398 device_t dev; 399{ 400 struct pcn_type *t; 401 struct pcn_softc *sc; 402 int rid; 403 u_int32_t chip_id; 404 405 t = pcn_devs; 406 sc = device_get_softc(dev); 407 408 while(t->pcn_name != NULL) { 409 if ((pci_get_vendor(dev) == t->pcn_vid) && 410 (pci_get_device(dev) == t->pcn_did)) { 411 /* 412 * Temporarily map the I/O space 413 * so we can read the chip ID register. 414 */ 415 rid = PCN_RID; 416 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 417 0, ~0, 1, RF_ACTIVE); 418 if (sc->pcn_res == NULL) { 419 device_printf(dev, 420 "couldn't map ports/memory\n"); 421 return(ENXIO); 422 } 423 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 424 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 425 mtx_init(&sc->pcn_mtx, 426 device_get_nameunit(dev), MTX_NETWORK_LOCK, 427 MTX_DEF); 428 PCN_LOCK(sc); 429 /* 430 * Note: we can *NOT* put the chip into 431 * 32-bit mode yet. The lnc driver will only 432 * work in 16-bit mode, and once the chip 433 * goes into 32-bit mode, the only way to 434 * get it out again is with a hardware reset. 435 * So if pcn_probe() is called before the 436 * lnc driver's probe routine, the chip will 437 * be locked into 32-bit operation and the lnc 438 * driver will be unable to attach to it. 439 * Note II: if the chip happens to already 440 * be in 32-bit mode, we still need to check 441 * the chip ID, but first we have to detect 442 * 32-bit mode using only 16-bit operations. 443 * The safest way to do this is to read the 444 * PCI subsystem ID from BCR23/24 and compare 445 * that with the value read from PCI config 446 * space. 447 */ 448 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 449 chip_id <<= 16; 450 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 451 /* 452 * Note III: the test for 0x10001000 is a hack to 453 * pacify VMware, who's pseudo-PCnet interface is 454 * broken. Reading the subsystem register from PCI 455 * config space yeilds 0x00000000 while reading the 456 * same value from I/O space yeilds 0x10001000. It's 457 * not supposed to be that way. 458 */ 459 if (chip_id == pci_read_config(dev, 460 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 461 /* We're in 16-bit mode. */ 462 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 463 chip_id <<= 16; 464 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 465 } else { 466 /* We're in 32-bit mode. */ 467 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 468 chip_id <<= 16; 469 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 470 } 471 bus_release_resource(dev, PCN_RES, 472 PCN_RID, sc->pcn_res); 473 PCN_UNLOCK(sc); 474 mtx_destroy(&sc->pcn_mtx); 475 chip_id >>= 12; 476 sc->pcn_type = chip_id & PART_MASK; 477 switch(sc->pcn_type) { 478 case Am79C971: 479 case Am79C972: 480 case Am79C973: 481 case Am79C975: 482 case Am79C976: 483 case Am79C978: 484 break; 485 default: 486 return(ENXIO); 487 break; 488 } 489 device_set_desc(dev, t->pcn_name); 490 return(0); 491 } 492 t++; 493 } 494 495 return(ENXIO); 496} 497 498/* 499 * Attach the interface. Allocate softc structures, do ifmedia 500 * setup and ethernet/BPF attach. 501 */ 502static int 503pcn_attach(dev) 504 device_t dev; 505{ 506 u_int32_t eaddr[2]; 507 u_int32_t command; 508 struct pcn_softc *sc; 509 struct ifnet *ifp; 510 int unit, error = 0, rid; 511 512 sc = device_get_softc(dev); 513 unit = device_get_unit(dev); 514 515 /* Initialize our mutex. */ 516 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 517 MTX_DEF | MTX_RECURSE); 518 519 /* 520 * Handle power management nonsense. 521 */ 522 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 523 u_int32_t iobase, membase, irq; 524 525 /* Save important PCI config data. */ 526 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 527 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 528 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 529 530 /* Reset the power state. */ 531 printf("pcn%d: chip is in D%d power mode " 532 "-- setting to D0\n", unit, 533 pci_get_powerstate(dev)); 534 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 535 536 /* Restore PCI config data. */ 537 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 538 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 539 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 540 } 541 542 /* 543 * Map control/status registers. 544 */ 545 pci_enable_busmaster(dev); 546 pci_enable_io(dev, SYS_RES_IOPORT); 547 pci_enable_io(dev, SYS_RES_MEMORY); 548 command = pci_read_config(dev, PCIR_COMMAND, 4); 549 550#ifdef PCN_USEIOSPACE 551 if (!(command & PCIM_CMD_PORTEN)) { 552 printf("pcn%d: failed to enable I/O ports!\n", unit); 553 error = ENXIO; 554 goto fail; 555 } 556#else 557 if (!(command & PCIM_CMD_MEMEN)) { 558 printf("pcn%d: failed to enable memory mapping!\n", unit); 559 error = ENXIO; 560 goto fail; 561 } 562#endif 563 564 rid = PCN_RID; 565 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 566 0, ~0, 1, RF_ACTIVE); 567 568 if (sc->pcn_res == NULL) { 569 printf("pcn%d: couldn't map ports/memory\n", unit); 570 error = ENXIO; 571 goto fail; 572 } 573 574 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 575 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 576 577 /* Allocate interrupt */ 578 rid = 0; 579 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 580 RF_SHAREABLE | RF_ACTIVE); 581 582 if (sc->pcn_irq == NULL) { 583 printf("pcn%d: couldn't map interrupt\n", unit); 584 error = ENXIO; 585 goto fail; 586 } 587 588 /* Reset the adapter. */ 589 pcn_reset(sc); 590 591 /* 592 * Get station address from the EEPROM. 593 */ 594 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 595 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 596 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 597 598 /* 599 * An AMD chip was detected. Inform the world. 600 */ 601 printf("pcn%d: Ethernet address: %6D\n", unit, 602 sc->arpcom.ac_enaddr, ":"); 603 604 sc->pcn_unit = unit; 605 callout_handle_init(&sc->pcn_stat_ch); 606 607 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 608 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 609 610 if (sc->pcn_ldata == NULL) { 611 printf("pcn%d: no memory for list buffers!\n", unit); 612 error = ENXIO; 613 goto fail; 614 } 615 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 616 617 ifp = &sc->arpcom.ac_if; 618 ifp->if_softc = sc; 619 ifp->if_unit = unit; 620 ifp->if_name = "pcn"; 621 ifp->if_mtu = ETHERMTU; 622 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 623 ifp->if_ioctl = pcn_ioctl; 624 ifp->if_output = ether_output; 625 ifp->if_start = pcn_start; 626 ifp->if_watchdog = pcn_watchdog; 627 ifp->if_init = pcn_init; 628 ifp->if_baudrate = 10000000; 629 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 630 631 /* 632 * Do MII setup. 633 */ 634 if (mii_phy_probe(dev, &sc->pcn_miibus, 635 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 636 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 637 error = ENXIO; 638 goto fail; 639 } 640 641 /* 642 * Call MI attach routine. 643 */ 644 ether_ifattach(ifp, (u_int8_t *) eaddr); 645 646 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 647 pcn_intr, sc, &sc->pcn_intrhand); 648 649 if (error) { 650 printf("pcn%d: couldn't set up irq\n", unit); 651 goto fail; 652 } 653 654fail: 655 if (error) 656 pcn_detach(dev); 657 658 return(error); 659} 660 661static int 662pcn_detach(dev) 663 device_t dev; 664{ 665 struct pcn_softc *sc; 666 struct ifnet *ifp; 667 668 sc = device_get_softc(dev); 669 ifp = &sc->arpcom.ac_if; 670 671 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 672 PCN_LOCK(sc); 673 674 if (device_is_alive(dev)) { 675 if (bus_child_present(dev)) { 676 pcn_reset(sc); 677 pcn_stop(sc); 678 } 679 ether_ifdetach(ifp); 680 device_delete_child(dev, sc->pcn_miibus); 681 bus_generic_detach(dev); 682 } 683 684 if (sc->pcn_intrhand) 685 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 686 if (sc->pcn_irq) 687 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 688 if (sc->pcn_res) 689 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 690 691 if (sc->pcn_ldata) { 692 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 693 M_DEVBUF); 694 } 695 PCN_UNLOCK(sc); 696 697 mtx_destroy(&sc->pcn_mtx); 698 699 return(0); 700} 701 702/* 703 * Initialize the transmit descriptors. 704 */ 705static int 706pcn_list_tx_init(sc) 707 struct pcn_softc *sc; 708{ 709 struct pcn_list_data *ld; 710 struct pcn_ring_data *cd; 711 int i; 712 713 cd = &sc->pcn_cdata; 714 ld = sc->pcn_ldata; 715 716 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 717 cd->pcn_tx_chain[i] = NULL; 718 ld->pcn_tx_list[i].pcn_tbaddr = 0; 719 ld->pcn_tx_list[i].pcn_txctl = 0; 720 ld->pcn_tx_list[i].pcn_txstat = 0; 721 } 722 723 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 724 725 return(0); 726} 727 728 729/* 730 * Initialize the RX descriptors and allocate mbufs for them. 731 */ 732static int 733pcn_list_rx_init(sc) 734 struct pcn_softc *sc; 735{ 736 struct pcn_list_data *ld; 737 struct pcn_ring_data *cd; 738 int i; 739 740 ld = sc->pcn_ldata; 741 cd = &sc->pcn_cdata; 742 743 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 744 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 745 return(ENOBUFS); 746 } 747 748 cd->pcn_rx_prod = 0; 749 750 return(0); 751} 752 753/* 754 * Initialize an RX descriptor and attach an MBUF cluster. 755 */ 756static int 757pcn_newbuf(sc, idx, m) 758 struct pcn_softc *sc; 759 int idx; 760 struct mbuf *m; 761{ 762 struct mbuf *m_new = NULL; 763 struct pcn_rx_desc *c; 764 765 c = &sc->pcn_ldata->pcn_rx_list[idx]; 766 767 if (m == NULL) { 768 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 769 if (m_new == NULL) 770 return(ENOBUFS); 771 772 MCLGET(m_new, M_DONTWAIT); 773 if (!(m_new->m_flags & M_EXT)) { 774 m_freem(m_new); 775 return(ENOBUFS); 776 } 777 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 778 } else { 779 m_new = m; 780 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 781 m_new->m_data = m_new->m_ext.ext_buf; 782 } 783 784 m_adj(m_new, ETHER_ALIGN); 785 786 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 787 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 788 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 789 c->pcn_bufsz |= PCN_RXLEN_MBO; 790 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 791 792 return(0); 793} 794 795/* 796 * A frame has been uploaded: pass the resulting mbuf chain up to 797 * the higher level protocols. 798 */ 799static void 800pcn_rxeof(sc) 801 struct pcn_softc *sc; 802{ 803 struct ether_header *eh; 804 struct mbuf *m; 805 struct ifnet *ifp; 806 struct pcn_rx_desc *cur_rx; 807 int i; 808 809 ifp = &sc->arpcom.ac_if; 810 i = sc->pcn_cdata.pcn_rx_prod; 811 812 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 813 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 814 m = sc->pcn_cdata.pcn_rx_chain[i]; 815 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 816 817 /* 818 * If an error occurs, update stats, clear the 819 * status word and leave the mbuf cluster in place: 820 * it should simply get re-used next time this descriptor 821 * comes up in the ring. 822 */ 823 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 824 ifp->if_ierrors++; 825 pcn_newbuf(sc, i, m); 826 PCN_INC(i, PCN_RX_LIST_CNT); 827 continue; 828 } 829 830 if (pcn_newbuf(sc, i, NULL)) { 831 /* Ran out of mbufs; recycle this one. */ 832 pcn_newbuf(sc, i, m); 833 ifp->if_ierrors++; 834 PCN_INC(i, PCN_RX_LIST_CNT); 835 continue; 836 } 837 838 PCN_INC(i, PCN_RX_LIST_CNT); 839 840 /* No errors; receive the packet. */ 841 ifp->if_ipackets++; 842 eh = mtod(m, struct ether_header *); 843 m->m_len = m->m_pkthdr.len = 844 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 845 m->m_pkthdr.rcvif = ifp; 846 847 (*ifp->if_input)(ifp, m); 848 } 849 850 sc->pcn_cdata.pcn_rx_prod = i; 851 852 return; 853} 854 855/* 856 * A frame was downloaded to the chip. It's safe for us to clean up 857 * the list buffers. 858 */ 859 860static void 861pcn_txeof(sc) 862 struct pcn_softc *sc; 863{ 864 struct pcn_tx_desc *cur_tx = NULL; 865 struct ifnet *ifp; 866 u_int32_t idx; 867 868 ifp = &sc->arpcom.ac_if; 869 870 /* 871 * Go through our tx list and free mbufs for those 872 * frames that have been transmitted. 873 */ 874 idx = sc->pcn_cdata.pcn_tx_cons; 875 while (idx != sc->pcn_cdata.pcn_tx_prod) { 876 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 877 878 if (!PCN_OWN_TXDESC(cur_tx)) 879 break; 880 881 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 882 sc->pcn_cdata.pcn_tx_cnt--; 883 PCN_INC(idx, PCN_TX_LIST_CNT); 884 continue; 885 } 886 887 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 888 ifp->if_oerrors++; 889 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 890 ifp->if_collisions++; 891 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 892 ifp->if_collisions++; 893 } 894 895 ifp->if_collisions += 896 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 897 898 ifp->if_opackets++; 899 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 900 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 901 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 902 } 903 904 sc->pcn_cdata.pcn_tx_cnt--; 905 PCN_INC(idx, PCN_TX_LIST_CNT); 906 } 907 908 if (idx != sc->pcn_cdata.pcn_tx_cons) { 909 /* Some buffers have been freed. */ 910 sc->pcn_cdata.pcn_tx_cons = idx; 911 ifp->if_flags &= ~IFF_OACTIVE; 912 } 913 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 914 915 return; 916} 917 918static void 919pcn_tick(xsc) 920 void *xsc; 921{ 922 struct pcn_softc *sc; 923 struct mii_data *mii; 924 struct ifnet *ifp; 925 926 sc = xsc; 927 ifp = &sc->arpcom.ac_if; 928 PCN_LOCK(sc); 929 930 mii = device_get_softc(sc->pcn_miibus); 931 mii_tick(mii); 932 933 /* link just died */ 934 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 935 sc->pcn_link = 0; 936 937 /* link just came up, restart */ 938 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 939 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 940 sc->pcn_link++; 941 if (ifp->if_snd.ifq_head != NULL) 942 pcn_start(ifp); 943 } 944 945 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 946 947 PCN_UNLOCK(sc); 948 949 return; 950} 951 952static void 953pcn_intr(arg) 954 void *arg; 955{ 956 struct pcn_softc *sc; 957 struct ifnet *ifp; 958 u_int32_t status; 959 960 sc = arg; 961 ifp = &sc->arpcom.ac_if; 962 963 /* Supress unwanted interrupts */ 964 if (!(ifp->if_flags & IFF_UP)) { 965 pcn_stop(sc); 966 return; 967 } 968 969 PCN_LOCK(sc); 970 971 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 972 973 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 974 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 975 976 if (status & PCN_CSR_RINT) 977 pcn_rxeof(sc); 978 979 if (status & PCN_CSR_TINT) 980 pcn_txeof(sc); 981 982 if (status & PCN_CSR_ERR) { 983 pcn_init(sc); 984 break; 985 } 986 } 987 988 if (ifp->if_snd.ifq_head != NULL) 989 pcn_start(ifp); 990 991 PCN_UNLOCK(sc); 992 return; 993} 994 995/* 996 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 997 * pointers to the fragment pointers. 998 */ 999static int 1000pcn_encap(sc, m_head, txidx) 1001 struct pcn_softc *sc; 1002 struct mbuf *m_head; 1003 u_int32_t *txidx; 1004{ 1005 struct pcn_tx_desc *f = NULL; 1006 struct mbuf *m; 1007 int frag, cur, cnt = 0; 1008 1009 /* 1010 * Start packing the mbufs in this chain into 1011 * the fragment pointers. Stop when we run out 1012 * of fragments or hit the end of the mbuf chain. 1013 */ 1014 m = m_head; 1015 cur = frag = *txidx; 1016 1017 for (m = m_head; m != NULL; m = m->m_next) { 1018 if (m->m_len != 0) { 1019 if ((PCN_TX_LIST_CNT - 1020 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1021 return(ENOBUFS); 1022 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1023 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1024 f->pcn_txctl |= PCN_TXCTL_MBO; 1025 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1026 if (cnt == 0) 1027 f->pcn_txctl |= PCN_TXCTL_STP; 1028 else 1029 f->pcn_txctl |= PCN_TXCTL_OWN; 1030 cur = frag; 1031 PCN_INC(frag, PCN_TX_LIST_CNT); 1032 cnt++; 1033 } 1034 } 1035 1036 if (m != NULL) 1037 return(ENOBUFS); 1038 1039 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1040 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1041 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1042 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1043 sc->pcn_cdata.pcn_tx_cnt += cnt; 1044 *txidx = frag; 1045 1046 return(0); 1047} 1048 1049/* 1050 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1051 * to the mbuf data regions directly in the transmit lists. We also save a 1052 * copy of the pointers since the transmit list fragment pointers are 1053 * physical addresses. 1054 */ 1055static void 1056pcn_start(ifp) 1057 struct ifnet *ifp; 1058{ 1059 struct pcn_softc *sc; 1060 struct mbuf *m_head = NULL; 1061 u_int32_t idx; 1062 1063 sc = ifp->if_softc; 1064 1065 PCN_LOCK(sc); 1066 1067 if (!sc->pcn_link) { 1068 PCN_UNLOCK(sc); 1069 return; 1070 } 1071 1072 idx = sc->pcn_cdata.pcn_tx_prod; 1073 1074 if (ifp->if_flags & IFF_OACTIVE) { 1075 PCN_UNLOCK(sc); 1076 return; 1077 } 1078 1079 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1080 IF_DEQUEUE(&ifp->if_snd, m_head); 1081 if (m_head == NULL) 1082 break; 1083 1084 if (pcn_encap(sc, m_head, &idx)) { 1085 IF_PREPEND(&ifp->if_snd, m_head); 1086 ifp->if_flags |= IFF_OACTIVE; 1087 break; 1088 } 1089 1090 /* 1091 * If there's a BPF listener, bounce a copy of this frame 1092 * to him. 1093 */ 1094 BPF_MTAP(ifp, m_head); 1095 1096 } 1097 1098 /* Transmit */ 1099 sc->pcn_cdata.pcn_tx_prod = idx; 1100 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1101 1102 /* 1103 * Set a timeout in case the chip goes out to lunch. 1104 */ 1105 ifp->if_timer = 5; 1106 1107 PCN_UNLOCK(sc); 1108 1109 return; 1110} 1111 1112static void 1113pcn_setfilt(ifp) 1114 struct ifnet *ifp; 1115{ 1116 struct pcn_softc *sc; 1117 1118 sc = ifp->if_softc; 1119 1120 /* If we want promiscuous mode, set the allframes bit. */ 1121 if (ifp->if_flags & IFF_PROMISC) { 1122 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1123 } else { 1124 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1125 } 1126 1127 /* Set the capture broadcast bit to capture broadcast frames. */ 1128 if (ifp->if_flags & IFF_BROADCAST) { 1129 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1130 } else { 1131 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1132 } 1133 1134 return; 1135} 1136 1137static void 1138pcn_init(xsc) 1139 void *xsc; 1140{ 1141 struct pcn_softc *sc = xsc; 1142 struct ifnet *ifp = &sc->arpcom.ac_if; 1143 struct mii_data *mii = NULL; 1144 1145 PCN_LOCK(sc); 1146 1147 /* 1148 * Cancel pending I/O and free all RX/TX buffers. 1149 */ 1150 pcn_stop(sc); 1151 pcn_reset(sc); 1152 1153 mii = device_get_softc(sc->pcn_miibus); 1154 1155 /* Set MAC address */ 1156 pcn_csr_write(sc, PCN_CSR_PAR0, 1157 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1158 pcn_csr_write(sc, PCN_CSR_PAR1, 1159 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1160 pcn_csr_write(sc, PCN_CSR_PAR2, 1161 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1162 1163 /* Init circular RX list. */ 1164 if (pcn_list_rx_init(sc) == ENOBUFS) { 1165 printf("pcn%d: initialization failed: no " 1166 "memory for rx buffers\n", sc->pcn_unit); 1167 pcn_stop(sc); 1168 PCN_UNLOCK(sc); 1169 return; 1170 } 1171 1172 /* 1173 * Init tx descriptors. 1174 */ 1175 pcn_list_tx_init(sc); 1176 1177 /* Set up the mode register. */ 1178 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1179 1180 /* Set up RX filter. */ 1181 pcn_setfilt(ifp); 1182 1183 /* 1184 * Load the multicast filter. 1185 */ 1186 pcn_setmulti(sc); 1187 1188 /* 1189 * Load the addresses of the RX and TX lists. 1190 */ 1191 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1192 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1193 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1194 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1195 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1196 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1197 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1198 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1199 1200 /* Set the RX and TX ring sizes. */ 1201 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1202 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1203 1204 /* We're not using the initialization block. */ 1205 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1206 1207 /* Enable fast suspend mode. */ 1208 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1209 1210 /* 1211 * Enable burst read and write. Also set the no underflow 1212 * bit. This will avoid transmit underruns in certain 1213 * conditions while still providing decent performance. 1214 */ 1215 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1216 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1217 1218 /* Enable graceful recovery from underflow. */ 1219 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1220 1221 /* Enable auto-padding of short TX frames. */ 1222 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1223 1224 /* Disable MII autoneg (we handle this ourselves). */ 1225 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1226 1227 if (sc->pcn_type == Am79C978) 1228 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1229 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1230 1231 /* Enable interrupts and start the controller running. */ 1232 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1233 1234 mii_mediachg(mii); 1235 1236 ifp->if_flags |= IFF_RUNNING; 1237 ifp->if_flags &= ~IFF_OACTIVE; 1238 1239 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1240 PCN_UNLOCK(sc); 1241 1242 return; 1243} 1244 1245/* 1246 * Set media options. 1247 */ 1248static int 1249pcn_ifmedia_upd(ifp) 1250 struct ifnet *ifp; 1251{ 1252 struct pcn_softc *sc; 1253 struct mii_data *mii; 1254 1255 sc = ifp->if_softc; 1256 mii = device_get_softc(sc->pcn_miibus); 1257 1258 sc->pcn_link = 0; 1259 if (mii->mii_instance) { 1260 struct mii_softc *miisc; 1261 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1262 mii_phy_reset(miisc); 1263 } 1264 mii_mediachg(mii); 1265 1266 return(0); 1267} 1268 1269/* 1270 * Report current media status. 1271 */ 1272static void 1273pcn_ifmedia_sts(ifp, ifmr) 1274 struct ifnet *ifp; 1275 struct ifmediareq *ifmr; 1276{ 1277 struct pcn_softc *sc; 1278 struct mii_data *mii; 1279 1280 sc = ifp->if_softc; 1281 1282 mii = device_get_softc(sc->pcn_miibus); 1283 mii_pollstat(mii); 1284 ifmr->ifm_active = mii->mii_media_active; 1285 ifmr->ifm_status = mii->mii_media_status; 1286 1287 return; 1288} 1289 1290static int 1291pcn_ioctl(ifp, command, data) 1292 struct ifnet *ifp; 1293 u_long command; 1294 caddr_t data; 1295{ 1296 struct pcn_softc *sc = ifp->if_softc; 1297 struct ifreq *ifr = (struct ifreq *) data; 1298 struct mii_data *mii = NULL; 1299 int error = 0; 1300 1301 PCN_LOCK(sc); 1302 1303 switch(command) { 1304 case SIOCSIFFLAGS: 1305 if (ifp->if_flags & IFF_UP) { 1306 if (ifp->if_flags & IFF_RUNNING && 1307 ifp->if_flags & IFF_PROMISC && 1308 !(sc->pcn_if_flags & IFF_PROMISC)) { 1309 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1310 PCN_EXTCTL1_SPND); 1311 pcn_setfilt(ifp); 1312 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1313 PCN_EXTCTL1_SPND); 1314 pcn_csr_write(sc, PCN_CSR_CSR, 1315 PCN_CSR_INTEN|PCN_CSR_START); 1316 } else if (ifp->if_flags & IFF_RUNNING && 1317 !(ifp->if_flags & IFF_PROMISC) && 1318 sc->pcn_if_flags & IFF_PROMISC) { 1319 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1320 PCN_EXTCTL1_SPND); 1321 pcn_setfilt(ifp); 1322 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1323 PCN_EXTCTL1_SPND); 1324 pcn_csr_write(sc, PCN_CSR_CSR, 1325 PCN_CSR_INTEN|PCN_CSR_START); 1326 } else if (!(ifp->if_flags & IFF_RUNNING)) 1327 pcn_init(sc); 1328 } else { 1329 if (ifp->if_flags & IFF_RUNNING) 1330 pcn_stop(sc); 1331 } 1332 sc->pcn_if_flags = ifp->if_flags; 1333 error = 0; 1334 break; 1335 case SIOCADDMULTI: 1336 case SIOCDELMULTI: 1337 pcn_setmulti(sc); 1338 error = 0; 1339 break; 1340 case SIOCGIFMEDIA: 1341 case SIOCSIFMEDIA: 1342 mii = device_get_softc(sc->pcn_miibus); 1343 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1344 break; 1345 default: 1346 error = ether_ioctl(ifp, command, data); 1347 break; 1348 } 1349 1350 PCN_UNLOCK(sc); 1351 1352 return(error); 1353} 1354 1355static void 1356pcn_watchdog(ifp) 1357 struct ifnet *ifp; 1358{ 1359 struct pcn_softc *sc; 1360 1361 sc = ifp->if_softc; 1362 1363 PCN_LOCK(sc); 1364 1365 ifp->if_oerrors++; 1366 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1367 1368 pcn_stop(sc); 1369 pcn_reset(sc); 1370 pcn_init(sc); 1371 1372 if (ifp->if_snd.ifq_head != NULL) 1373 pcn_start(ifp); 1374 1375 PCN_UNLOCK(sc); 1376 1377 return; 1378} 1379 1380/* 1381 * Stop the adapter and free any mbufs allocated to the 1382 * RX and TX lists. 1383 */ 1384static void 1385pcn_stop(sc) 1386 struct pcn_softc *sc; 1387{ 1388 register int i; 1389 struct ifnet *ifp; 1390 1391 ifp = &sc->arpcom.ac_if; 1392 PCN_LOCK(sc); 1393 ifp->if_timer = 0; 1394 1395 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1396 1397 /* Turn off interrupts */ 1398 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1399 /* Stop adapter */ 1400 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1401 sc->pcn_link = 0; 1402 1403 /* 1404 * Free data in the RX lists. 1405 */ 1406 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1407 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1408 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1409 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1410 } 1411 } 1412 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1413 sizeof(sc->pcn_ldata->pcn_rx_list)); 1414 1415 /* 1416 * Free the TX list buffers. 1417 */ 1418 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1419 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1420 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1421 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1422 } 1423 } 1424 1425 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1426 sizeof(sc->pcn_ldata->pcn_tx_list)); 1427 1428 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1429 PCN_UNLOCK(sc); 1430 1431 return; 1432} 1433 1434/* 1435 * Stop all chip I/O so that the kernel's probe routines don't 1436 * get confused by errant DMAs when rebooting. 1437 */ 1438static void 1439pcn_shutdown(dev) 1440 device_t dev; 1441{ 1442 struct pcn_softc *sc; 1443 1444 sc = device_get_softc(dev); 1445 1446 PCN_LOCK(sc); 1447 pcn_reset(sc); 1448 pcn_stop(sc); 1449 PCN_UNLOCK(sc); 1450 1451 return; 1452} 1453