oce_if.h revision 246799
1/*- 2 * Copyright (C) 2012 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39/* $FreeBSD: head/sys/dev/oce/oce_if.h 246799 2013-02-14 17:34:17Z jpaetzel $ */ 40 41#include <sys/param.h> 42#include <sys/endian.h> 43#include <sys/module.h> 44#include <sys/kernel.h> 45#include <sys/bus.h> 46#include <sys/mbuf.h> 47#include <sys/rman.h> 48#include <sys/socket.h> 49#include <sys/sockio.h> 50#include <sys/sockopt.h> 51#include <sys/queue.h> 52#include <sys/taskqueue.h> 53#include <sys/lock.h> 54#include <sys/mutex.h> 55#include <sys/sysctl.h> 56#include <sys/random.h> 57#include <sys/firmware.h> 58#include <sys/systm.h> 59#include <sys/proc.h> 60 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcivar.h> 63 64#include <net/bpf.h> 65#include <net/ethernet.h> 66#include <net/if.h> 67#include <net/if_types.h> 68#include <net/if_media.h> 69#include <net/if_vlan_var.h> 70#include <net/if_dl.h> 71 72#include <netinet/in.h> 73#include <netinet/in_systm.h> 74#include <netinet/in_var.h> 75#include <netinet/if_ether.h> 76#include <netinet/ip.h> 77#include <netinet/ip6.h> 78#include <netinet6/in6_var.h> 79#include <netinet6/ip6_mroute.h> 80 81#include <netinet/udp.h> 82#include <netinet/tcp.h> 83#include <netinet/sctp.h> 84#include <netinet/tcp_lro.h> 85 86#include <machine/bus.h> 87 88#include "oce_hw.h" 89 90/* OCE device driver module component revision informaiton */ 91#define COMPONENT_REVISION "4.2.127.0" 92 93 94/* OCE devices supported by this driver */ 95#define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 96#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 97#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 98#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 99#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 100#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 101 102#define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 103 (sc->flags & OCE_FLAGS_BE2))? 1:0) 104#define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 105#define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 106 107 108/* proportion Service Level Interface queues */ 109#define OCE_MAX_UNITS 2 110#define OCE_MAX_PPORT OCE_MAX_UNITS 111#define OCE_MAX_VPORT OCE_MAX_UNITS 112 113extern int mp_ncpus; /* system's total active cpu cores */ 114#define OCE_NCPUS mp_ncpus 115 116/* This should be powers of 2. Like 2,4,8 & 16 */ 117#define OCE_MAX_RSS 4 /* TODO: 8*/ 118#define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 119 120#define OCE_MIN_RQ 1 121#define OCE_MIN_WQ 1 122 123#define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 124#define OCE_MAX_WQ 8 125 126#define OCE_MAX_EQ 32 127#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 128#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 129 130#define OCE_DEFAULT_WQ_EQD 16 131#define OCE_MAX_PACKET_Q 16 132#define OCE_RQ_BUF_SIZE 2048 133#define OCE_LSO_MAX_SIZE (64 * 1024) 134#define LONG_TIMEOUT 30 135#define OCE_MAX_JUMBO_FRAME_SIZE 16360 136#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 137 ETHER_VLAN_ENCAP_LEN - \ 138 ETHER_HDR_LEN) 139 140#define OCE_MAX_TX_ELEMENTS 29 141#define OCE_MAX_TX_DESC 1024 142#define OCE_MAX_TX_SIZE 65535 143#define OCE_MAX_RX_SIZE 4096 144#define OCE_MAX_RQ_POSTS 255 145#define OCE_DEFAULT_PROMISCUOUS 0 146 147 148#define RSS_ENABLE_IPV4 0x1 149#define RSS_ENABLE_TCP_IPV4 0x2 150#define RSS_ENABLE_IPV6 0x4 151#define RSS_ENABLE_TCP_IPV6 0x8 152 153 154/* flow control definitions */ 155#define OCE_FC_NONE 0x00000000 156#define OCE_FC_TX 0x00000001 157#define OCE_FC_RX 0x00000002 158#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 159 160 161/* Interface capabilities to give device when creating interface */ 162#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 163 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 164 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 165 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 166 MBX_RX_IFACE_FLAGS_RSS | \ 167 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 168 169/* Interface capabilities to enable by default (others set dynamically) */ 170#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 171 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 172 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 173 174#define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 175#define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 176 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 177 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 178#define OCE_IF_HWASSIST_NONE 0 179#define OCE_IF_CAPABILITIES_NONE 0 180 181 182#define ETH_ADDR_LEN 6 183#define MAX_VLANFILTER_SIZE 64 184#define MAX_VLANS 4096 185 186#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 187#define BSWAP_8(x) ((x) & 0xff) 188#define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 189#define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 190 BSWAP_16((x) >> 16)) 191#define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 192 BSWAP_32((x) >> 32)) 193 194#define for_all_wq_queues(sc, wq, i) \ 195 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 196#define for_all_rq_queues(sc, rq, i) \ 197 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 198#define for_all_evnt_queues(sc, eq, i) \ 199 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 200#define for_all_cq_queues(sc, cq, i) \ 201 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 202 203 204/* Flash specific */ 205#define IOCTL_COOKIE "SERVERENGINES CORP" 206#define MAX_FLASH_COMP 32 207 208#define IMG_ISCSI 160 209#define IMG_REDBOOT 224 210#define IMG_BIOS 34 211#define IMG_PXEBIOS 32 212#define IMG_FCOEBIOS 33 213#define IMG_ISCSI_BAK 176 214#define IMG_FCOE 162 215#define IMG_FCOE_BAK 178 216#define IMG_NCSI 16 217#define IMG_PHY 192 218#define FLASHROM_OPER_FLASH 1 219#define FLASHROM_OPER_SAVE 2 220#define FLASHROM_OPER_REPORT 4 221#define FLASHROM_OPER_FLASH_PHY 9 222#define FLASHROM_OPER_SAVE_PHY 10 223#define TN_8022 13 224 225enum { 226 PHY_TYPE_CX4_10GB = 0, 227 PHY_TYPE_XFP_10GB, 228 PHY_TYPE_SFP_1GB, 229 PHY_TYPE_SFP_PLUS_10GB, 230 PHY_TYPE_KR_10GB, 231 PHY_TYPE_KX4_10GB, 232 PHY_TYPE_BASET_10GB, 233 PHY_TYPE_BASET_1GB, 234 PHY_TYPE_BASEX_1GB, 235 PHY_TYPE_SGMII, 236 PHY_TYPE_DISABLED = 255 237}; 238 239/** 240 * @brief Define and hold all necessary info for a single interrupt 241 */ 242#define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 243#define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 244 245typedef struct oce_intr_info { 246 void *tag; /* cookie returned by bus_setup_intr */ 247 struct resource *intr_res; /* PCI resource container */ 248 int irq_rr; /* resource id for the interrupt */ 249 struct oce_softc *sc; /* pointer to the parent soft c */ 250 struct oce_eq *eq; /* pointer to the connected EQ */ 251 struct taskqueue *tq; /* Associated task queue */ 252 struct task task; /* task queue task */ 253 char task_name[32]; /* task name */ 254 int vector; /* interrupt vector number */ 255} OCE_INTR_INFO, *POCE_INTR_INFO; 256 257 258/* Ring related */ 259#define GET_Q_NEXT(_START, _STEP, _END) \ 260 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 261 : (((_START) + (_STEP)) - (_END))) 262 263#define DBUF_PA(obj) ((obj)->addr) 264#define DBUF_VA(obj) ((obj)->ptr) 265#define DBUF_TAG(obj) ((obj)->tag) 266#define DBUF_MAP(obj) ((obj)->map) 267#define DBUF_SYNC(obj, flags) \ 268 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 269 270#define RING_NUM_PENDING(ring) ring->num_used 271#define RING_FULL(ring) (ring->num_used == ring->num_items) 272#define RING_EMPTY(ring) (ring->num_used == 0) 273#define RING_NUM_FREE(ring) \ 274 (uint32_t)(ring->num_items - ring->num_used) 275#define RING_GET(ring, n) \ 276 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 277#define RING_PUT(ring, n) \ 278 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 279 280#define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 281 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 282#define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 283 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 284#define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 285 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 286#define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 287 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 288 289#define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 290 291struct oce_packet_desc { 292 struct mbuf *mbuf; 293 bus_dmamap_t map; 294 int nsegs; 295 uint32_t wqe_idx; 296}; 297 298typedef struct oce_dma_mem { 299 bus_dma_tag_t tag; 300 bus_dmamap_t map; 301 void *ptr; 302 bus_addr_t paddr; 303} OCE_DMA_MEM, *POCE_DMA_MEM; 304 305typedef struct oce_ring_buffer_s { 306 uint16_t cidx; /* Get ptr */ 307 uint16_t pidx; /* Put Ptr */ 308 size_t item_size; 309 size_t num_items; 310 uint32_t num_used; 311 OCE_DMA_MEM dma; 312} oce_ring_buffer_t; 313 314/* Stats */ 315#define OCE_UNICAST_PACKET 0 316#define OCE_MULTICAST_PACKET 1 317#define OCE_BROADCAST_PACKET 2 318#define OCE_RSVD_PACKET 3 319 320struct oce_rx_stats { 321 /* Total Receive Stats*/ 322 uint64_t t_rx_pkts; 323 uint64_t t_rx_bytes; 324 uint32_t t_rx_frags; 325 uint32_t t_rx_mcast_pkts; 326 uint32_t t_rx_ucast_pkts; 327 uint32_t t_rxcp_errs; 328}; 329struct oce_tx_stats { 330 /*Total Transmit Stats */ 331 uint64_t t_tx_pkts; 332 uint64_t t_tx_bytes; 333 uint32_t t_tx_reqs; 334 uint32_t t_tx_stops; 335 uint32_t t_tx_wrbs; 336 uint32_t t_tx_compl; 337 uint32_t t_ipv6_ext_hdr_tx_drop; 338}; 339 340struct oce_be_stats { 341 uint8_t be_on_die_temperature; 342 uint32_t be_tx_events; 343 uint32_t eth_red_drops; 344 uint32_t rx_drops_no_pbuf; 345 uint32_t rx_drops_no_txpb; 346 uint32_t rx_drops_no_erx_descr; 347 uint32_t rx_drops_no_tpre_descr; 348 uint32_t rx_drops_too_many_frags; 349 uint32_t rx_drops_invalid_ring; 350 uint32_t forwarded_packets; 351 uint32_t rx_drops_mtu; 352 uint32_t rx_crc_errors; 353 uint32_t rx_alignment_symbol_errors; 354 uint32_t rx_pause_frames; 355 uint32_t rx_priority_pause_frames; 356 uint32_t rx_control_frames; 357 uint32_t rx_in_range_errors; 358 uint32_t rx_out_range_errors; 359 uint32_t rx_frame_too_long; 360 uint32_t rx_address_match_errors; 361 uint32_t rx_dropped_too_small; 362 uint32_t rx_dropped_too_short; 363 uint32_t rx_dropped_header_too_small; 364 uint32_t rx_dropped_tcp_length; 365 uint32_t rx_dropped_runt; 366 uint32_t rx_ip_checksum_errs; 367 uint32_t rx_tcp_checksum_errs; 368 uint32_t rx_udp_checksum_errs; 369 uint32_t rx_switched_unicast_packets; 370 uint32_t rx_switched_multicast_packets; 371 uint32_t rx_switched_broadcast_packets; 372 uint32_t tx_pauseframes; 373 uint32_t tx_priority_pauseframes; 374 uint32_t tx_controlframes; 375 uint32_t rxpp_fifo_overflow_drop; 376 uint32_t rx_input_fifo_overflow_drop; 377 uint32_t pmem_fifo_overflow_drop; 378 uint32_t jabber_events; 379}; 380 381struct oce_xe201_stats { 382 uint64_t tx_pkts; 383 uint64_t tx_unicast_pkts; 384 uint64_t tx_multicast_pkts; 385 uint64_t tx_broadcast_pkts; 386 uint64_t tx_bytes; 387 uint64_t tx_unicast_bytes; 388 uint64_t tx_multicast_bytes; 389 uint64_t tx_broadcast_bytes; 390 uint64_t tx_discards; 391 uint64_t tx_errors; 392 uint64_t tx_pause_frames; 393 uint64_t tx_pause_on_frames; 394 uint64_t tx_pause_off_frames; 395 uint64_t tx_internal_mac_errors; 396 uint64_t tx_control_frames; 397 uint64_t tx_pkts_64_bytes; 398 uint64_t tx_pkts_65_to_127_bytes; 399 uint64_t tx_pkts_128_to_255_bytes; 400 uint64_t tx_pkts_256_to_511_bytes; 401 uint64_t tx_pkts_512_to_1023_bytes; 402 uint64_t tx_pkts_1024_to_1518_bytes; 403 uint64_t tx_pkts_1519_to_2047_bytes; 404 uint64_t tx_pkts_2048_to_4095_bytes; 405 uint64_t tx_pkts_4096_to_8191_bytes; 406 uint64_t tx_pkts_8192_to_9216_bytes; 407 uint64_t tx_lso_pkts; 408 uint64_t rx_pkts; 409 uint64_t rx_unicast_pkts; 410 uint64_t rx_multicast_pkts; 411 uint64_t rx_broadcast_pkts; 412 uint64_t rx_bytes; 413 uint64_t rx_unicast_bytes; 414 uint64_t rx_multicast_bytes; 415 uint64_t rx_broadcast_bytes; 416 uint32_t rx_unknown_protos; 417 uint64_t rx_discards; 418 uint64_t rx_errors; 419 uint64_t rx_crc_errors; 420 uint64_t rx_alignment_errors; 421 uint64_t rx_symbol_errors; 422 uint64_t rx_pause_frames; 423 uint64_t rx_pause_on_frames; 424 uint64_t rx_pause_off_frames; 425 uint64_t rx_frames_too_long; 426 uint64_t rx_internal_mac_errors; 427 uint32_t rx_undersize_pkts; 428 uint32_t rx_oversize_pkts; 429 uint32_t rx_fragment_pkts; 430 uint32_t rx_jabbers; 431 uint64_t rx_control_frames; 432 uint64_t rx_control_frames_unknown_opcode; 433 uint32_t rx_in_range_errors; 434 uint32_t rx_out_of_range_errors; 435 uint32_t rx_address_match_errors; 436 uint32_t rx_vlan_mismatch_errors; 437 uint32_t rx_dropped_too_small; 438 uint32_t rx_dropped_too_short; 439 uint32_t rx_dropped_header_too_small; 440 uint32_t rx_dropped_invalid_tcp_length; 441 uint32_t rx_dropped_runt; 442 uint32_t rx_ip_checksum_errors; 443 uint32_t rx_tcp_checksum_errors; 444 uint32_t rx_udp_checksum_errors; 445 uint32_t rx_non_rss_pkts; 446 uint64_t rx_ipv4_pkts; 447 uint64_t rx_ipv6_pkts; 448 uint64_t rx_ipv4_bytes; 449 uint64_t rx_ipv6_bytes; 450 uint64_t rx_nic_pkts; 451 uint64_t rx_tcp_pkts; 452 uint64_t rx_iscsi_pkts; 453 uint64_t rx_management_pkts; 454 uint64_t rx_switched_unicast_pkts; 455 uint64_t rx_switched_multicast_pkts; 456 uint64_t rx_switched_broadcast_pkts; 457 uint64_t num_forwards; 458 uint32_t rx_fifo_overflow; 459 uint32_t rx_input_fifo_overflow; 460 uint64_t rx_drops_too_many_frags; 461 uint32_t rx_drops_invalid_queue; 462 uint64_t rx_drops_mtu; 463 uint64_t rx_pkts_64_bytes; 464 uint64_t rx_pkts_65_to_127_bytes; 465 uint64_t rx_pkts_128_to_255_bytes; 466 uint64_t rx_pkts_256_to_511_bytes; 467 uint64_t rx_pkts_512_to_1023_bytes; 468 uint64_t rx_pkts_1024_to_1518_bytes; 469 uint64_t rx_pkts_1519_to_2047_bytes; 470 uint64_t rx_pkts_2048_to_4095_bytes; 471 uint64_t rx_pkts_4096_to_8191_bytes; 472 uint64_t rx_pkts_8192_to_9216_bytes; 473}; 474 475struct oce_drv_stats { 476 struct oce_rx_stats rx; 477 struct oce_tx_stats tx; 478 union { 479 struct oce_be_stats be; 480 struct oce_xe201_stats xe201; 481 } u0; 482}; 483 484 485 486#define MAX_LOCK_DESC_LEN 32 487struct oce_lock { 488 struct mtx mutex; 489 char name[MAX_LOCK_DESC_LEN+1]; 490}; 491#define OCE_LOCK struct oce_lock 492 493#define LOCK_CREATE(lock, desc) { \ 494 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 495 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 496 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 497} 498#define LOCK_DESTROY(lock) \ 499 if (mtx_initialized(&(lock)->mutex))\ 500 mtx_destroy(&(lock)->mutex) 501#define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 502#define LOCK(lock) mtx_lock(&(lock)->mutex) 503#define LOCKED(lock) mtx_owned(&(lock)->mutex) 504#define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 505 506#define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 507#define MBX_READY_TIMEOUT (1 * 1000 * 1000) 508#define DEFAULT_DRAIN_TIME 200 509#define MBX_TIMEOUT_SEC 5 510#define STAT_TIMEOUT 2000000 511 512/* size of the packet descriptor array in a transmit queue */ 513#define OCE_TX_RING_SIZE 2048 514#define OCE_RX_RING_SIZE 1024 515#define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 516#define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 517 518struct oce_dev; 519 520enum eq_len { 521 EQ_LEN_256 = 256, 522 EQ_LEN_512 = 512, 523 EQ_LEN_1024 = 1024, 524 EQ_LEN_2048 = 2048, 525 EQ_LEN_4096 = 4096 526}; 527 528enum eqe_size { 529 EQE_SIZE_4 = 4, 530 EQE_SIZE_16 = 16 531}; 532 533enum qtype { 534 QTYPE_EQ, 535 QTYPE_MQ, 536 QTYPE_WQ, 537 QTYPE_RQ, 538 QTYPE_CQ, 539 QTYPE_RSS 540}; 541 542typedef enum qstate_e { 543 QDELETED = 0x0, 544 QCREATED = 0x1 545} qstate_t; 546 547struct eq_config { 548 enum eq_len q_len; 549 enum eqe_size item_size; 550 uint32_t q_vector_num; 551 uint8_t min_eqd; 552 uint8_t max_eqd; 553 uint8_t cur_eqd; 554 uint8_t pad; 555}; 556 557struct oce_eq { 558 uint32_t eq_id; 559 void *parent; 560 void *cb_context; 561 oce_ring_buffer_t *ring; 562 uint32_t ref_count; 563 qstate_t qstate; 564 struct oce_cq *cq[OCE_MAX_CQ_EQ]; 565 int cq_valid; 566 struct eq_config eq_cfg; 567 int vector; 568}; 569 570enum cq_len { 571 CQ_LEN_256 = 256, 572 CQ_LEN_512 = 512, 573 CQ_LEN_1024 = 1024 574}; 575 576struct cq_config { 577 enum cq_len q_len; 578 uint32_t item_size; 579 boolean_t is_eventable; 580 boolean_t sol_eventable; 581 boolean_t nodelay; 582 uint16_t dma_coalescing; 583}; 584 585typedef uint16_t(*cq_handler_t) (void *arg1); 586 587struct oce_cq { 588 uint32_t cq_id; 589 void *parent; 590 struct oce_eq *eq; 591 cq_handler_t cq_handler; 592 void *cb_arg; 593 oce_ring_buffer_t *ring; 594 qstate_t qstate; 595 struct cq_config cq_cfg; 596 uint32_t ref_count; 597}; 598 599 600struct mq_config { 601 uint32_t eqd; 602 uint8_t q_len; 603 uint8_t pad[3]; 604}; 605 606 607struct oce_mq { 608 void *parent; 609 oce_ring_buffer_t *ring; 610 uint32_t mq_id; 611 struct oce_cq *cq; 612 struct oce_cq *async_cq; 613 uint32_t mq_free; 614 qstate_t qstate; 615 struct mq_config cfg; 616}; 617 618struct oce_mbx_ctx { 619 struct oce_mbx *mbx; 620 void (*cb) (void *ctx); 621 void *cb_ctx; 622}; 623 624struct wq_config { 625 uint8_t wq_type; 626 uint16_t buf_size; 627 uint8_t pad[1]; 628 uint32_t q_len; 629 uint16_t pd_id; 630 uint16_t pci_fn_num; 631 uint32_t eqd; /* interrupt delay */ 632 uint32_t nbufs; 633 uint32_t nhdl; 634}; 635 636struct oce_tx_queue_stats { 637 uint64_t tx_pkts; 638 uint64_t tx_bytes; 639 uint32_t tx_reqs; 640 uint32_t tx_stops; /* number of times TX Q was stopped */ 641 uint32_t tx_wrbs; 642 uint32_t tx_compl; 643 uint32_t tx_rate; 644 uint32_t ipv6_ext_hdr_tx_drop; 645}; 646 647struct oce_wq { 648 OCE_LOCK tx_lock; 649 void *parent; 650 oce_ring_buffer_t *ring; 651 struct oce_cq *cq; 652 bus_dma_tag_t tag; 653 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 654 uint32_t packets_in; 655 uint32_t packets_out; 656 uint32_t wqm_used; 657 boolean_t resched; 658 uint32_t wq_free; 659 uint32_t tx_deferd; 660 uint32_t pkt_drops; 661 qstate_t qstate; 662 uint16_t wq_id; 663 struct wq_config cfg; 664 int queue_index; 665 struct oce_tx_queue_stats tx_stats; 666 struct buf_ring *br; 667 struct task txtask; 668}; 669 670struct rq_config { 671 uint32_t q_len; 672 uint32_t frag_size; 673 uint32_t mtu; 674 uint32_t if_id; 675 uint32_t is_rss_queue; 676 uint32_t eqd; 677 uint32_t nbufs; 678}; 679 680struct oce_rx_queue_stats { 681 uint32_t rx_post_fail; 682 uint32_t rx_ucast_pkts; 683 uint32_t rx_compl; 684 uint64_t rx_bytes; 685 uint64_t rx_bytes_prev; 686 uint64_t rx_pkts; 687 uint32_t rx_rate; 688 uint32_t rx_mcast_pkts; 689 uint32_t rxcp_err; 690 uint32_t rx_frags; 691 uint32_t prev_rx_frags; 692 uint32_t rx_fps; 693}; 694 695 696struct oce_rq { 697 struct rq_config cfg; 698 uint32_t rq_id; 699 int queue_index; 700 uint32_t rss_cpuid; 701 void *parent; 702 oce_ring_buffer_t *ring; 703 struct oce_cq *cq; 704 void *pad1; 705 bus_dma_tag_t tag; 706 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 707 uint32_t packets_in; 708 uint32_t packets_out; 709 uint32_t pending; 710#ifdef notdef 711 struct mbuf *head; 712 struct mbuf *tail; 713 int fragsleft; 714#endif 715 qstate_t qstate; 716 OCE_LOCK rx_lock; 717 struct oce_rx_queue_stats rx_stats; 718 struct lro_ctrl lro; 719 int lro_pkts_queued; 720 721}; 722 723struct link_status { 724 uint8_t physical_port; 725 uint8_t mac_duplex; 726 uint8_t mac_speed; 727 uint8_t mac_fault; 728 uint8_t mgmt_mac_duplex; 729 uint8_t mgmt_mac_speed; 730 uint16_t qos_link_speed; 731 uint32_t logical_link_status; 732}; 733 734 735 736#define OCE_FLAGS_PCIX 0x00000001 737#define OCE_FLAGS_PCIE 0x00000002 738#define OCE_FLAGS_MSI_CAPABLE 0x00000004 739#define OCE_FLAGS_MSIX_CAPABLE 0x00000008 740#define OCE_FLAGS_USING_MSI 0x00000010 741#define OCE_FLAGS_USING_MSIX 0x00000020 742#define OCE_FLAGS_FUNCRESET_RQD 0x00000040 743#define OCE_FLAGS_VIRTUAL_PORT 0x00000080 744#define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 745#define OCE_FLAGS_BE3 0x00000200 746#define OCE_FLAGS_XE201 0x00000400 747#define OCE_FLAGS_BE2 0x00000800 748 749#define OCE_DEV_BE2_CFG_BAR 1 750#define OCE_DEV_CFG_BAR 0 751#define OCE_PCI_CSR_BAR 2 752#define OCE_PCI_DB_BAR 4 753 754typedef struct oce_softc { 755 device_t dev; 756 OCE_LOCK dev_lock; 757 758 uint32_t flags; 759 760 uint32_t pcie_link_speed; 761 uint32_t pcie_link_width; 762 763 uint8_t fn; /* PCI function number */ 764 765 struct resource *devcfg_res; 766 bus_space_tag_t devcfg_btag; 767 bus_space_handle_t devcfg_bhandle; 768 void *devcfg_vhandle; 769 770 struct resource *csr_res; 771 bus_space_tag_t csr_btag; 772 bus_space_handle_t csr_bhandle; 773 void *csr_vhandle; 774 775 struct resource *db_res; 776 bus_space_tag_t db_btag; 777 bus_space_handle_t db_bhandle; 778 void *db_vhandle; 779 780 OCE_INTR_INFO intrs[OCE_MAX_EQ]; 781 int intr_count; 782 783 struct ifnet *ifp; 784 785 struct ifmedia media; 786 uint8_t link_status; 787 uint8_t link_speed; 788 uint8_t duplex; 789 uint32_t qos_link_speed; 790 uint32_t speed; 791 792 char fw_version[32]; 793 struct mac_address_format macaddr; 794 795 OCE_DMA_MEM bsmbx; 796 OCE_LOCK bmbx_lock; 797 798 uint32_t config_number; 799 uint32_t asic_revision; 800 uint32_t port_id; 801 uint32_t function_mode; 802 uint32_t function_caps; 803 uint32_t max_tx_rings; 804 uint32_t max_rx_rings; 805 806 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 807 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 808 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 809 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 810 struct oce_mq *mq; /* Mailbox queue */ 811 812 uint32_t neqs; 813 uint32_t ncqs; 814 uint32_t nrqs; 815 uint32_t nwqs; 816 817 uint32_t tx_ring_size; 818 uint32_t rx_ring_size; 819 uint32_t rq_frag_size; 820 uint32_t rss_enable; 821 822 uint32_t if_id; /* interface ID */ 823 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 824 uint32_t pmac_id; /* PMAC id */ 825 826 uint32_t if_cap_flags; 827 828 uint32_t flow_control; 829 uint32_t promisc; 830 /*Vlan Filtering related */ 831 eventhandler_tag vlan_attach; 832 eventhandler_tag vlan_detach; 833 uint16_t vlans_added; 834 uint8_t vlan_tag[MAX_VLANS]; 835 /*stats */ 836 OCE_DMA_MEM stats_mem; 837 struct oce_drv_stats oce_stats_info; 838 struct callout timer; 839 int8_t be3_native; 840 uint32_t pvid; 841 842} OCE_SOFTC, *POCE_SOFTC; 843 844 845 846/************************************************** 847 * BUS memory read/write macros 848 * BE3: accesses three BAR spaces (CFG, CSR, DB) 849 * Lancer: accesses one BAR space (CFG) 850 **************************************************/ 851#define OCE_READ_REG32(sc, space, o) \ 852 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 853 (sc)->space##_bhandle,o)) \ 854 : (bus_space_read_4((sc)->devcfg_btag, \ 855 (sc)->devcfg_bhandle,o))) 856#define OCE_READ_REG16(sc, space, o) \ 857 ((IS_BE(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 858 (sc)->space##_bhandle,o)) \ 859 : (bus_space_read_2((sc)->devcfg_btag, \ 860 (sc)->devcfg_bhandle,o))) 861#define OCE_READ_REG8(sc, space, o) \ 862 ((IS_BE(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 863 (sc)->space##_bhandle,o)) \ 864 : (bus_space_read_1((sc)->devcfg_btag, \ 865 (sc)->devcfg_bhandle,o))) 866 867#define OCE_WRITE_REG32(sc, space, o, v) \ 868 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 869 (sc)->space##_bhandle,o,v)) \ 870 : (bus_space_write_4((sc)->devcfg_btag, \ 871 (sc)->devcfg_bhandle,o,v))) 872#define OCE_WRITE_REG16(sc, space, o, v) \ 873 ((IS_BE(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 874 (sc)->space##_bhandle,o,v)) \ 875 : (bus_space_write_2((sc)->devcfg_btag, \ 876 (sc)->devcfg_bhandle,o,v))) 877#define OCE_WRITE_REG8(sc, space, o, v) \ 878 ((IS_BE(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 879 (sc)->space##_bhandle,o,v)) \ 880 : (bus_space_write_1((sc)->devcfg_btag, \ 881 (sc)->devcfg_bhandle,o,v))) 882 883 884/*********************************************************** 885 * DMA memory functions 886 ***********************************************************/ 887#define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 888int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 889void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 890void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 891void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 892oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 893 uint32_t q_len, uint32_t num_entries); 894/************************************************************ 895 * oce_hw_xxx functions 896 ************************************************************/ 897int oce_clear_rx_buf(struct oce_rq *rq); 898int oce_hw_pci_alloc(POCE_SOFTC sc); 899int oce_hw_init(POCE_SOFTC sc); 900int oce_hw_start(POCE_SOFTC sc); 901int oce_create_nw_interface(POCE_SOFTC sc); 902int oce_pci_soft_reset(POCE_SOFTC sc); 903int oce_hw_update_multicast(POCE_SOFTC sc); 904void oce_delete_nw_interface(POCE_SOFTC sc); 905void oce_hw_shutdown(POCE_SOFTC sc); 906void oce_hw_intr_enable(POCE_SOFTC sc); 907void oce_hw_intr_disable(POCE_SOFTC sc); 908void oce_hw_pci_free(POCE_SOFTC sc); 909 910/*********************************************************** 911 * oce_queue_xxx functions 912 ***********************************************************/ 913int oce_queue_init_all(POCE_SOFTC sc); 914int oce_start_rq(struct oce_rq *rq); 915int oce_start_wq(struct oce_wq *wq); 916int oce_start_mq(struct oce_mq *mq); 917int oce_start_rx(POCE_SOFTC sc); 918void oce_arm_eq(POCE_SOFTC sc, 919 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 920void oce_queue_release_all(POCE_SOFTC sc); 921void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 922void oce_drain_eq(struct oce_eq *eq); 923void oce_drain_mq_cq(void *arg); 924void oce_drain_rq_cq(struct oce_rq *rq); 925void oce_drain_wq_cq(struct oce_wq *wq); 926 927uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 928 929/*********************************************************** 930 * cleanup functions 931 ***********************************************************/ 932void oce_stop_rx(POCE_SOFTC sc); 933void oce_intr_free(POCE_SOFTC sc); 934void oce_free_posted_rxbuf(struct oce_rq *rq); 935#if defined(INET6) || defined(INET) 936void oce_free_lro(POCE_SOFTC sc); 937#endif 938 939 940/************************************************************ 941 * Mailbox functions 942 ************************************************************/ 943int oce_fw_clean(POCE_SOFTC sc); 944int oce_reset_fun(POCE_SOFTC sc); 945int oce_mbox_init(POCE_SOFTC sc); 946int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 947int oce_get_fw_version(POCE_SOFTC sc); 948int oce_first_mcc_cmd(POCE_SOFTC sc); 949 950int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 951 uint8_t type, struct mac_address_format *mac); 952int oce_get_fw_config(POCE_SOFTC sc); 953int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 954 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 955int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 956int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 957 struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 958 uint32_t untagged, uint32_t enable_promisc); 959int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 960int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 961int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable); 962int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 963int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 964int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 965int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 966int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 967 uint32_t reset_stats); 968int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 969 uint32_t req_size, uint32_t reset_stats); 970int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 971int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 972int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 973int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 974 uint32_t if_id, uint32_t *pmac_id); 975int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 976 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 977 uint64_t pattern); 978 979int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 980 uint8_t loopback_type, uint8_t enable); 981 982int oce_mbox_check_native_mode(POCE_SOFTC sc); 983int oce_mbox_post(POCE_SOFTC sc, 984 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 985int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 986 POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 987int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 988 uint32_t data_offset,POCE_DMA_MEM pdma_mem, 989 uint32_t *written_data, uint32_t *additional_status); 990 991int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 992 uint32_t offset, uint32_t optype); 993int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 994int oce_mbox_create_rq(struct oce_rq *rq); 995int oce_mbox_create_wq(struct oce_wq *wq); 996int oce_mbox_create_eq(struct oce_eq *eq); 997int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 998 uint32_t is_eventable); 999void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1000 uint8_t dom, 1001 uint8_t port, 1002 uint8_t subsys, 1003 uint8_t opcode, 1004 uint32_t timeout, uint32_t pyld_len, 1005 uint8_t version); 1006 1007 1008uint16_t oce_mq_handler(void *arg); 1009 1010/************************************************************ 1011 * Transmit functions 1012 ************************************************************/ 1013uint16_t oce_wq_handler(void *arg); 1014void oce_start(struct ifnet *ifp); 1015void oce_tx_task(void *arg, int npending); 1016 1017/************************************************************ 1018 * Receive functions 1019 ************************************************************/ 1020int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1021uint16_t oce_rq_handler(void *arg); 1022 1023 1024/* Sysctl functions */ 1025void oce_add_sysctls(POCE_SOFTC sc); 1026void oce_refresh_queue_stats(POCE_SOFTC sc); 1027int oce_refresh_nic_stats(POCE_SOFTC sc); 1028int oce_stats_init(POCE_SOFTC sc); 1029void oce_stats_free(POCE_SOFTC sc); 1030 1031/* Capabilities */ 1032#define OCE_MODCAP_RSS 1 1033#define OCE_MAX_RSP_HANDLED 64 1034extern uint32_t oce_max_rsp_handled; /* max responses */ 1035 1036#define OCE_MAC_LOOPBACK 0x0 1037#define OCE_PHY_LOOPBACK 0x1 1038#define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1039#define OCE_NO_LOOPBACK 0xff 1040 1041#define atomic_inc_32(x) atomic_add_32(x, 1) 1042#define atomic_dec_32(x) atomic_subtract_32(x, 1) 1043 1044#define LE_64(x) htole64(x) 1045#define LE_32(x) htole32(x) 1046#define LE_16(x) htole16(x) 1047#define DW_SWAP(x, l) 1048#define IS_ALIGNED(x,a) ((x % a) == 0) 1049#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1050#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1051 1052#define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1053#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1054#define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1055 1056#define OCE_LOG2(x) (oce_highbit(x)) 1057static inline uint32_t oce_highbit(uint32_t x) 1058{ 1059 int i; 1060 int c; 1061 int b; 1062 1063 c = 0; 1064 b = 0; 1065 1066 for (i = 0; i < 32; i++) { 1067 if ((1 << i) & x) { 1068 c++; 1069 b = i; 1070 } 1071 } 1072 1073 if (c == 1) 1074 return b; 1075 1076 return 0; 1077} 1078 1079