xgehal-types.h revision 171095
1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nxge/include/xgehal-types.h 171095 2007-06-29 22:47:18Z sam $ 27 */ 28 29/* 30 * FileName : xgehal-types.h 31 * 32 * Description: HAL commonly used types and enumerations 33 * 34 * Created: 19 May 2004 35 */ 36 37#ifndef XGE_HAL_TYPES_H 38#define XGE_HAL_TYPES_H 39 40#include <dev/nxge/include/xge-os-pal.h> 41 42__EXTERN_BEGIN_DECLS 43 44/* 45 * BIT(loc) - set bit at offset 46 */ 47#define BIT(loc) (0x8000000000000000ULL >> (loc)) 48 49/* 50 * vBIT(val, loc, sz) - set bits at offset 51 */ 52#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 53#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 54 55/* 56 * bVALx(bits, loc) - Get the value of x bits at location 57 */ 58#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) 59#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) 60#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) 61#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) 62#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) 63#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) 64#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) 65#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) 66#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) 67#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF) 68#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) 69#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) 70#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) 71#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) 72#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) 73#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) 74#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) 75#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) 76#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) 77#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) 78#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) 79#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) 80#define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) 81 82#define XGE_HAL_BASE_INF 100 83#define XGE_HAL_BASE_ERR 200 84#define XGE_HAL_BASE_BADCFG 300 85 86#define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL 87 88/** 89 * enum xge_hal_status_e - HAL return codes. 90 * @XGE_HAL_OK: Success. 91 * @XGE_HAL_FAIL: Failure. 92 * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 93 * (specific to polling mode completion processing). 94 * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 95 * descriptors. See xge_hal_fifo_dtr_next_completed(). 96 * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 97 * descriptors 98 * are reserved (via xge_hal_fifo_dtr_reserve(), 99 * xge_hal_fifo_dtr_reserve()) 100 * and not yet freed (via xge_hal_fifo_dtr_free(), 101 * xge_hal_ring_dtr_free()). 102 * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for 103 * operation. 104 * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 105 * poll until PIO is executed. 106 * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because 107 * HAL and/or device is not yet initialized. 108 * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 109 * reserve. Internal use only. 110 * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 111 * callback when instructed to exit descriptor processing loop 112 * prematurely. Typical usage: polling mode of processing completed 113 * descriptors. 114 * Upon getting LRO_ISED, ll driver shall 115 * 1) initialise lro struct with mbuf if sg_num == 1. 116 * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 117 * append the new mbuf to the tail of mbuf chain in lro struct. 118 * 119 * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 120 * being initiated. 121 * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame 122 * is appended at the end of existing LRO. 123 * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new 124 * frame is not LRO capable. 125 * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame 126 * triggers LRO flush. 127 * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new 128 * frame triggers LRO flush. Lro frame should be flushed first then 129 * new frame should be flushed next. 130 * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new 131 * frame triggers close of current LRO session and opening of new LRO session 132 * with the frame. 133 * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 134 * more LRO sessions can be added. 135 * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD 136 * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 137 * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 138 * allocating descriptors). 139 * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this 140 * error if corresponding channel is not configured. 141 * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 142 * invoked not because of the Xframe-generated interrupt. 143 * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 144 * configure more than XGE_HAL_MAX_MAC_ADDRESSES mac addresses. 145 * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 146 * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 147 * in a scatter-gather list. 148 * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 149 * Typically means wrong sequence of API calls. 150 * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 151 * to set Xframe byte swapper in accordnace with the host 152 * endian-ness. 153 * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 154 * a "quiescent" state. 155 * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by 156 * caller is not in the (64, 9600) range. 157 * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 158 * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 159 * check for zero/non-zero only.) 160 * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base 161 * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 162 * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 163 * register value (with offset) outside of the BAR0 space. 164 * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 165 * (passed by ULD) is invalid. 166 * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 167 * management "get" routines when the retrieved information does 168 * not fit into the provided buffer. 169 * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 170 * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 171 * are not compatible. 172 * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 173 * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 174 * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 175 * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 176 * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 177 * SPDM table. 178 * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 179 * synch ith the actual one. 180 * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency, 181 * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register). 182 * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 183 * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR. 184 * Also returned when PIO read does not go through ("all-foxes") 185 * because of "slot-freeze". 186 * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 187 * Returned by xge_hal_device_reset(). One circumstance when it could 188 * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL). 189 * @XGE_HAL_ERR_TOO_MANY: This error is returned if there were laready 190 * maximum number of sessions or queues allocated 191 * @XGE_HAL_ERR_PKT_DROP: TBD 192 * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See 193 * the structure xge_hal_tti_config_t{} for valid values. 194 * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization 195 * range A. See the structure xge_hal_tti_config_t{} for valid values. 196 * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See 197 * the structure xge_hal_tti_config_t{} for valid values. 198 * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization 199 * range B. See the strucuture xge_hal_tti_config_t{} for valid values. 200 * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See 201 * the structure xge_hal_tti_config_t{} for valid values. 202 * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization 203 * range C. See the structure xge_hal_tti_config_t{} for valid values. 204 * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization 205 * range D. See the structure xge_hal_tti_config_t{} for valid values. 206 * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the 207 * structure xge_hal_tti_config_t{} for valid values. 208 * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt 209 * enable. See the structure xge_hal_tti_config_t{} for valid values. 210 * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See 211 * the structure xge_hal_rti_config_t{} for valid values. 212 * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization 213 * range A. See the structure xge_hal_rti_config_t{} for valid values. 214 * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See 215 * the structure xge_hal_rti_config_t{} for valid values. 216 * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization 217 * range B. See the structure xge_hal_rti_config_t{} for valid values. 218 * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See 219 * the structure xge_hal_rti_config_t{} for valid values. 220 * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization 221 * range C. See the structure xge_hal_rti_config_t{} for valid values. 222 * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization 223 * range D. See the structure xge_hal_rti_config_t{} for valid values. 224 * @XGE_HAL_BADCFG_RX_TIMER_VAL: Invalid Rx timer value. See the 225 * structure xge_hal_rti_config_t{} for valid values. 226 * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue 227 * length. See the structure xge_hal_fifo_queue_t for valid values. 228 * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length. 229 * See the structure xge_hal_fifo_queue_t for valid values. 230 * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode. 231 * See the structure xge_hal_fifo_queue_t for valid values. 232 * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of 233 * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for 234 * valid values. 235 * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD 236 * blocks for the ring. See the structure xge_hal_ring_queue_t for 237 * valid values. 238 * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See 239 * the structure xge_hal_ring_queue_t for valid values. 240 * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the 241 * structure xge_hal_ring_queue_t for valid values. 242 * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval 243 * for the ring. See the structure xge_hal_ring_queue_t for valid values. 244 * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the 245 * structure xge_hal_ring_queue_t for valid values. 246 * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the 247 * structure xge_hal_ring_queue_t for valid values. 248 * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the 249 * structure xge_hal_mac_config_t{} for valid values. 250 * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the 251 * structure xge_hal_mac_config_t{} for valid values. 252 * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the 253 * structure xge_hal_mac_config_t{} for valid values. 254 * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the 255 * structure xge_hal_mac_config_t{} for valid values. 256 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause 257 * frame generation for queues 0 through 3. See the structure 258 * xge_hal_mac_config_t{} for valid values. 259 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause 260 * frame generation for queues 4 through 7. See the structure 261 * xge_hal_mac_config_t{} for valid values. 262 * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See 263 * the structure xge_hal_fifo_config_t{} for valid values. 264 * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve 265 * threshold. See the structure xge_hal_fifo_config_t{} for valid values. 266 * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock 267 * size. See the structure xge_hal_fifo_config_t{} for valid values. 268 * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock 269 * size. See the structure xge_hal_ring_config_t{} for valid values. 270 * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the 271 * structure xge_hal_device_config_t{} for valid values. 272 * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the 273 * structure xge_hal_device_config_t{} for valid values. 274 * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the 275 * structure xge_hal_device_config_t{} for valid values. 276 * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum number of pci-x 277 * split transactions. See the structure xge_hal_device_config_t{} for valid 278 * values. 279 * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count. See the structure 280 * xge_hal_device_config_t{} for valid values. 281 * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split 282 * transactions that is shared by Tx and Rx requests. See the structure 283 * xge_hal_device_config_t{} for valid values. 284 * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for 285 * automatic statistics transfer to the host. See the structure 286 * xge_hal_device_config_t{} for valid values. 287 * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ: Invalid pci clock frequency. See the 288 * structure xge_hal_device_config_t{} for valid values. 289 * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure 290 * xge_hal_device_config_t{} for valid values. 291 * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure 292 * xge_hal_device_config_t{} for valid values. 293 * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to 294 * generate interrupt. See the structure xge_hal_device_config_t{} 295 * for valid values. 296 * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one 297 * shot. See the structure xge_hal_device_config_t{} for valid values. 298 * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial 299 * size. See the structure xge_hal_driver_config_t{} for valid values. 300 * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size. See 301 * the structure xge_hal_driver_config_t{} for valid values. 302 * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See 303 * the structure xge_hal_ring_queue_t for valid values. 304 * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for 305 * indicate_max_pkts variable. 306 * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer 307 * auto-cancel. See xge_hal_tti_config_t{}. 308 * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer 309 * auto-cancel. See xge_hal_rti_config_t{}. 310 * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO 311 * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO 312 * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO 313 * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO 314 * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular 315 * (in memory) trace buffer either too large or too small. See the 316 * the corresponding header file or README for the acceptable range. 317 * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid 318 * counter cannot have the specified value. Note that the link-valid 319 * counting is done only at device-open time, to determine with the 320 * specified certainty that the link is up. See the 321 * the corresponding header file or README for the acceptable range. 322 * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT. 323 * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified 324 * link-up retry count is out of the valid range. Note that the link-up 325 * retry counting is done only at device-open time. 326 * See also xge_hal_device_config_t{}. 327 * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period. 328 * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval. 329 * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD 330 * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD 331 * @XGE_HAL_BADCFG_MEDIA: TBD 332 * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD 333 * See the structure xge_hal_device_config_t{} for valid values. 334 * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer. 335 * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace 336 * past the buffer limits. Used to enable user to load the trace in two 337 * or more reads. 338 * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See 339 * the structure xge_hal_ring_queue_t for valid values. 340 * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size. 341 * See the structure xge_hal_device_config_t for valid values. 342 * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length. 343 * See the structure xge_hal_device_config_t for valid values. 344 * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD 345 * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts 346 * Enumerates status and error codes returned by HAL public 347 * API functions. 348 * @XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US: TBD 349 * @XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US: TBD 350 * @XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED: TBD 351 * @XGE_HAL_BADCFG_RTS_QOS_EN: TBD 352 * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR: TBD 353 * @XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR: TBD 354 * @XGE_HAL_BADCFG_RTS_PORT_EN: TBD 355 * @XGE_HAL_BADCFG_RING_RTS_PORT_EN: TBD 356 * 357 */ 358typedef enum xge_hal_status_e { 359 XGE_HAL_OK = 0, 360 XGE_HAL_FAIL = 1, 361 XGE_HAL_COMPLETIONS_REMAIN = 2, 362 363 XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, 364 XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, 365 XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, 366 XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, 367 XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, 368 XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, 369 XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, 370 XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, 371 XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, 372 XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, 373 XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, 374 XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, 375 XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, 376 XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, 377 XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, 378 XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, 379 XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, 380 XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, 381 XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, 382 XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, 383 XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, 384 XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, 385 XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, 386 XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, 387 XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, 388 XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, 389 XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, 390 XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, 391 XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, 392 XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, 393 XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, 394 XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, 395 XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, 396 XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, 397 XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, 398 XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, 399 XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, 400 XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, 401 XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, 402 XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, 403 XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, 404 XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, 405 XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, 406 XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, 407 XGE_HAL_ERR_PKT_DROP = XGE_HAL_BASE_ERR + 33, 408 409 XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, 410 XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, 411 XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, 412 XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, 413 XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, 414 XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, 415 XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, 416 XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, 417 XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, 418 XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, 419 XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, 420 XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, 421 XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, 422 XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, 423 XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, 424 XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, 425 XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, 426 XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, 427 XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, 428 XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, 429 XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, 430 XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, 431 XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, 432 XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, 433 XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, 434 XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, 435 XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, 436 XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, 437 XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, 438 XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, 439 XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, 440 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, 441 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, 442 XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, 443 XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, 444 XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, 445 XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, 446 XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, 447 XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, 448 XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, 449 XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, 450 XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, 451 XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, 452 XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, 453 XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, 454 XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, 455 XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, 456 XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, 457 XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, 458 XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, 459 XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, 460 XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, 461 XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, 462 XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, 463 XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, 464 XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, 465 XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, 466 XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, 467 XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, 468 XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, 469 XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, 470 XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, 471 XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, 472 XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, 473 XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, 474 XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, 475 XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, 476 XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, 477 XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, 478 XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, 479 XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, 480 XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, 481 XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, 482 XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, 483 XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, 484 XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, 485 XGE_HAL_BADCFG_RTS_QOS_EN = XGE_HAL_BASE_BADCFG + 79, 486 XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 80, 487 XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 81, 488 XGE_HAL_BADCFG_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 82, 489 XGE_HAL_BADCFG_RING_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 83, 490 XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP = XGE_HAL_BASE_BADCFG + 84, 491 XGE_HAL_EOF_TRACE_BUF = -1 492} xge_hal_status_e; 493 494#define XGE_HAL_ETH_ALEN 6 495typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; 496 497#define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 498 499/* frames sizes */ 500#define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 501#define XGE_HAL_HEADER_802_2_SIZE 3 502#define XGE_HAL_HEADER_SNAP_SIZE 5 503#define XGE_HAL_HEADER_VLAN_SIZE 4 504#define XGE_HAL_MAC_HEADER_MAX_SIZE \ 505 (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ 506 XGE_HAL_HEADER_802_2_SIZE + \ 507 XGE_HAL_HEADER_SNAP_SIZE) 508 509#define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) 510 511/* 32bit alignments */ 512#define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 513#define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 514#define XGE_HAL_HEADER_802_2_ALIGN 3 515#define XGE_HAL_HEADER_SNAP_ALIGN 1 516 517#define XGE_HAL_L3_CKSUM_OK 0xFFFF 518#define XGE_HAL_L4_CKSUM_OK 0xFFFF 519#define XGE_HAL_MIN_MTU 46 520#define XGE_HAL_MAX_MTU 9600 521#define XGE_HAL_DEFAULT_MTU 1500 522 523#define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 524 525#define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ 526#define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ 527 528#define XGE_HAL_MAX_MSIX_MESSAGES 64 529#define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2 530/* Highest level interrupt blocks */ 531#define XGE_HAL_TX_PIC_INTR (0x0001<<0) 532#define XGE_HAL_TX_DMA_INTR (0x0001<<1) 533#define XGE_HAL_TX_MAC_INTR (0x0001<<2) 534#define XGE_HAL_TX_XGXS_INTR (0x0001<<3) 535#define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4) 536#define XGE_HAL_RX_PIC_INTR (0x0001<<5) 537#define XGE_HAL_RX_DMA_INTR (0x0001<<6) 538#define XGE_HAL_RX_MAC_INTR (0x0001<<7) 539#define XGE_HAL_RX_XGXS_INTR (0x0001<<8) 540#define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9) 541#define XGE_HAL_MC_INTR (0x0001<<10) 542#define XGE_HAL_SCHED_INTR (0x0001<<11) 543#define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ 544 XGE_HAL_TX_DMA_INTR | \ 545 XGE_HAL_TX_MAC_INTR | \ 546 XGE_HAL_TX_XGXS_INTR | \ 547 XGE_HAL_TX_TRAFFIC_INTR | \ 548 XGE_HAL_RX_PIC_INTR | \ 549 XGE_HAL_RX_DMA_INTR | \ 550 XGE_HAL_RX_MAC_INTR | \ 551 XGE_HAL_RX_XGXS_INTR | \ 552 XGE_HAL_RX_TRAFFIC_INTR | \ 553 XGE_HAL_MC_INTR | \ 554 XGE_HAL_SCHED_INTR) 555#define XGE_HAL_GEN_MASK_INTR (0x0001<<12) 556 557/* Interrupt masks for the general interrupt mask register */ 558#define XGE_HAL_ALL_INTRS_DIS 0xFFFFFFFFFFFFFFFFULL 559 560#define XGE_HAL_TXPIC_INT_M BIT(0) 561#define XGE_HAL_TXDMA_INT_M BIT(1) 562#define XGE_HAL_TXMAC_INT_M BIT(2) 563#define XGE_HAL_TXXGXS_INT_M BIT(3) 564#define XGE_HAL_TXTRAFFIC_INT_M BIT(8) 565#define XGE_HAL_PIC_RX_INT_M BIT(32) 566#define XGE_HAL_RXDMA_INT_M BIT(33) 567#define XGE_HAL_RXMAC_INT_M BIT(34) 568#define XGE_HAL_MC_INT_M BIT(35) 569#define XGE_HAL_RXXGXS_INT_M BIT(36) 570#define XGE_HAL_RXTRAFFIC_INT_M BIT(40) 571 572/* MSI level Interrupts */ 573#define XGE_HAL_MAX_MSIX_VECTORS (16) 574 575typedef struct xge_hal_ipv4 { 576 u32 addr; 577}xge_hal_ipv4; 578 579typedef struct xge_hal_ipv6 { 580 u64 addr[2]; 581}xge_hal_ipv6; 582 583typedef union xge_hal_ipaddr_t { 584 xge_hal_ipv4 ipv4; 585 xge_hal_ipv6 ipv6; 586}xge_hal_ipaddr_t; 587 588/* DMA level Interrupts */ 589#define XGE_HAL_TXDMA_PFC_INT_M BIT(0) 590 591/* PFC block interrupts */ 592#define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO 593full */ 594 595/* basic handles */ 596typedef void* xge_hal_device_h; 597typedef void* xge_hal_dtr_h; 598typedef void* xge_hal_channel_h; 599#ifdef XGEHAL_RNIC 600typedef void* xge_hal_towi_h; 601typedef void* xge_hal_hw_wqe_h; 602typedef void* xge_hal_hw_cqe_h; 603typedef void* xge_hal_lro_wqe_h; 604typedef void* xge_hal_lro_cqe_h; 605typedef void* xge_hal_up_msg_h; 606typedef void* xge_hal_down_msg_h; 607typedef void* xge_hal_channel_callback_fh; 608typedef void* xge_hal_msg_queueh; 609typedef void* xge_hal_pblist_h; 610#endif 611/* 612 * I2C device id. Used in I2C control register for accessing EEPROM device 613 * memory. 614 */ 615#define XGE_DEV_ID 5 616 617typedef enum xge_hal_xpak_alarm_type_e { 618 XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 619 XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 620 XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 621} xge_hal_xpak_alarm_type_e; 622 623 624__EXTERN_END_DECLS 625 626#endif /* XGE_HAL_TYPES_H */ 627