if_nve.c revision 148412
1/* 2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>. 3 * Copyright (c) 2003,2004 by Quinton Dolan <q@onthenet.com.au>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 16 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id: if_nv.c,v 1.19 2004/08/12 14:00:05 q Exp $ 28 */ 29 30/* 31 * NVIDIA nForce MCP Networking Adapter driver 32 * 33 * This is a port of the NVIDIA MCP Linux ethernet driver distributed by NVIDIA 34 * through their web site. 35 * 36 * All mainstream nForce and nForce2 motherboards are supported. This module 37 * is as stable, sometimes more stable, than the linux version. (Recent 38 * Linux stability issues seem to be related to some issues with newer 39 * distributions using GCC 3.x, however this don't appear to effect FreeBSD 40 * 5.x). 41 * 42 * In accordance with the NVIDIA distribution license it is necessary to 43 * link this module against the nvlibnet.o binary object included in the 44 * Linux driver source distribution. The binary component is not modified in 45 * any way and is simply linked against a FreeBSD equivalent of the nvnet.c 46 * linux kernel module "wrapper". 47 * 48 * The Linux driver uses a common code API that is shared between Win32 and 49 * i386 Linux. This abstracts the low level driver functions and uses 50 * callbacks and hooks to access the underlying hardware device. By using 51 * this same API in a FreeBSD kernel module it is possible to support the 52 * hardware without breaching the Linux source distributions licensing 53 * requirements, or obtaining the hardware programming specifications. 54 * 55 * Although not conventional, it works, and given the relatively small 56 * amount of hardware centric code, it's hopefully no more buggy than its 57 * linux counterpart. 58 * 59 * NVIDIA now support the nForce3 AMD64 platform, however I have been 60 * unable to access such a system to verify support. However, the code is 61 * reported to work with little modification when compiled with the AMD64 62 * version of the NVIDIA Linux library. All that should be necessary to make 63 * the driver work is to link it directly into the kernel, instead of as a 64 * module, and apply the docs/amd64.diff patch in this source distribution to 65 * the NVIDIA Linux driver source. 66 * 67 * This driver should work on all versions of FreeBSD since 4.9/5.1 as well 68 * as recent versions of DragonFly. 69 * 70 * Written by Quinton Dolan <q@onthenet.com.au> 71 * Portions based on existing FreeBSD network drivers. 72 * NVIDIA API usage derived from distributed NVIDIA NVNET driver source files. 73 * 74 */ 75 76#include <sys/cdefs.h> 77__FBSDID("$FreeBSD: head/sys/dev/nve/if_nve.c 148412 2005-07-25 22:21:11Z mux $"); 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/sockio.h> 82#include <sys/mbuf.h> 83#include <sys/malloc.h> 84#include <sys/kernel.h> 85#include <sys/socket.h> 86#include <sys/sysctl.h> 87#include <sys/queue.h> 88#include <sys/module.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95#include <net/if_types.h> 96#include <net/bpf.h> 97#include <net/if_vlan_var.h> 98 99#include <machine/bus.h> 100#include <machine/resource.h> 101 102#include <vm/vm.h> /* for vtophys */ 103#include <vm/pmap.h> /* for vtophys */ 104#include <machine/clock.h> /* for DELAY */ 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/pci/pcireg.h> 109#include <dev/pci/pcivar.h> 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112#include "miibus_if.h" 113 114/* Include NVIDIA Linux driver header files */ 115#define linux 116#include <contrib/dev/nve/basetype.h> 117#include <contrib/dev/nve/phy.h> 118#include "os+%DIKED-nve.h" 119#include <contrib/dev/nve/drvinfo.h> 120#include <contrib/dev/nve/adapter.h> 121#undef linux 122 123#include <dev/nve/if_nvereg.h> 124 125MODULE_DEPEND(nve, pci, 1, 1, 1); 126MODULE_DEPEND(nve, ether, 1, 1, 1); 127MODULE_DEPEND(nve, miibus, 1, 1, 1); 128 129static int nve_probe(device_t); 130static int nve_attach(device_t); 131static int nve_detach(device_t); 132static void nve_init(void *); 133static void nve_stop(struct nve_softc *); 134static void nve_shutdown(device_t); 135static int nve_init_rings(struct nve_softc *); 136static void nve_free_rings(struct nve_softc *); 137 138static void nve_ifstart(struct ifnet *); 139static int nve_ioctl(struct ifnet *, u_long, caddr_t); 140static void nve_intr(void *); 141static void nve_tick(void *); 142static void nve_setmulti(struct nve_softc *); 143static void nve_watchdog(struct ifnet *); 144static void nve_update_stats(struct nve_softc *); 145 146static int nve_ifmedia_upd(struct ifnet *); 147static void nve_ifmedia_sts(struct ifnet *, struct ifmediareq *); 148static int nve_miibus_readreg(device_t, int, int); 149static void nve_miibus_writereg(device_t, int, int, int); 150 151static void nve_dmamap_cb(void *, bus_dma_segment_t *, int, int); 152static void nve_dmamap_tx_cb(void *, bus_dma_segment_t *, int, bus_size_t, int); 153 154static NV_SINT32 nve_osalloc(PNV_VOID, PMEMORY_BLOCK); 155static NV_SINT32 nve_osfree(PNV_VOID, PMEMORY_BLOCK); 156static NV_SINT32 nve_osallocex(PNV_VOID, PMEMORY_BLOCKEX); 157static NV_SINT32 nve_osfreeex(PNV_VOID, PMEMORY_BLOCKEX); 158static NV_SINT32 nve_osclear(PNV_VOID, PNV_VOID, NV_SINT32); 159static NV_SINT32 nve_osdelay(PNV_VOID, NV_UINT32); 160static NV_SINT32 nve_osallocrxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID *); 161static NV_SINT32 nve_osfreerxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID); 162static NV_SINT32 nve_ospackettx(PNV_VOID, PNV_VOID, NV_UINT32); 163static NV_SINT32 nve_ospacketrx(PNV_VOID, PNV_VOID, NV_UINT32, NV_UINT8 *, NV_UINT8); 164static NV_SINT32 nve_oslinkchg(PNV_VOID, NV_SINT32); 165static NV_SINT32 nve_osalloctimer(PNV_VOID, PNV_VOID *); 166static NV_SINT32 nve_osfreetimer(PNV_VOID, PNV_VOID); 167static NV_SINT32 nve_osinittimer(PNV_VOID, PNV_VOID, PTIMER_FUNC, PNV_VOID); 168static NV_SINT32 nve_ossettimer(PNV_VOID, PNV_VOID, NV_UINT32); 169static NV_SINT32 nve_oscanceltimer(PNV_VOID, PNV_VOID); 170 171static NV_SINT32 nve_ospreprocpkt(PNV_VOID, PNV_VOID, PNV_VOID *, NV_UINT8 *, NV_UINT8); 172static PNV_VOID nve_ospreprocpktnopq(PNV_VOID, PNV_VOID); 173static NV_SINT32 nve_osindicatepkt(PNV_VOID, PNV_VOID *, NV_UINT32); 174static NV_SINT32 nve_oslockalloc(PNV_VOID, NV_SINT32, PNV_VOID *); 175static NV_SINT32 nve_oslockacquire(PNV_VOID, NV_SINT32, PNV_VOID); 176static NV_SINT32 nve_oslockrelease(PNV_VOID, NV_SINT32, PNV_VOID); 177static PNV_VOID nve_osreturnbufvirt(PNV_VOID, PNV_VOID); 178 179static device_method_t nve_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_probe, nve_probe), 182 DEVMETHOD(device_attach, nve_attach), 183 DEVMETHOD(device_detach, nve_detach), 184 DEVMETHOD(device_shutdown, nve_shutdown), 185 186 /* Bus interface */ 187 DEVMETHOD(bus_print_child, bus_generic_print_child), 188 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 189 190 /* MII interface */ 191 DEVMETHOD(miibus_readreg, nve_miibus_readreg), 192 DEVMETHOD(miibus_writereg, nve_miibus_writereg), 193 194 {0, 0} 195}; 196 197static driver_t nve_driver = { 198 "nve", 199 nve_methods, 200 sizeof(struct nve_softc) 201}; 202 203static devclass_t nve_devclass; 204 205static int nve_pollinterval = 0; 206SYSCTL_INT(_hw, OID_AUTO, nve_pollinterval, CTLFLAG_RW, 207 &nve_pollinterval, 0, "delay between interface polls"); 208 209DRIVER_MODULE(nve, pci, nve_driver, nve_devclass, 0, 0); 210DRIVER_MODULE(miibus, nve, miibus_driver, miibus_devclass, 0, 0); 211 212static struct nve_type nve_devs[] = { 213 {NVIDIA_VENDORID, NFORCE_MCPNET1_DEVICEID, 214 "NVIDIA nForce MCP Networking Adapter"}, 215 {NVIDIA_VENDORID, NFORCE_MCPNET2_DEVICEID, 216 "NVIDIA nForce MCP2 Networking Adapter"}, 217 {NVIDIA_VENDORID, NFORCE_MCPNET3_DEVICEID, 218 "NVIDIA nForce MCP3 Networking Adapter"}, 219 {NVIDIA_VENDORID, NFORCE_MCPNET4_DEVICEID, 220 "NVIDIA nForce MCP4 Networking Adapter"}, 221 {NVIDIA_VENDORID, NFORCE_MCPNET5_DEVICEID, 222 "NVIDIA nForce MCP5 Networking Adapter"}, 223 {NVIDIA_VENDORID, NFORCE_MCPNET6_DEVICEID, 224 "NVIDIA nForce MCP6 Networking Adapter"}, 225 {NVIDIA_VENDORID, NFORCE_MCPNET7_DEVICEID, 226 "NVIDIA nForce MCP7 Networking Adapter"}, 227 {NVIDIA_VENDORID, NFORCE_MCPNET8_DEVICEID, 228 "NVIDIA nForce MCP8 Networking Adapter"}, 229 {NVIDIA_VENDORID, NFORCE_MCPNET9_DEVICEID, 230 "NVIDIA nForce MCP9 Networking Adapter"}, 231 {NVIDIA_VENDORID, NFORCE_MCPNET10_DEVICEID, 232 "NVIDIA nForce MCP10 Networking Adapter"}, 233 {NVIDIA_VENDORID, NFORCE_MCPNET11_DEVICEID, 234 "NVIDIA nForce MCP11 Networking Adapter"}, 235 {0, 0, NULL} 236}; 237 238/* DMA MEM map callback function to get data segment physical address */ 239static void 240nve_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error) 241{ 242 if (error) 243 return; 244 245 KASSERT(nsegs == 1, 246 ("Too many DMA segments returned when mapping DMA memory")); 247 *(bus_addr_t *)arg = segs->ds_addr; 248} 249 250/* DMA RX map callback function to get data segment physical address */ 251static void 252nve_dmamap_rx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, 253 bus_size_t mapsize, int error) 254{ 255 if (error) 256 return; 257 *(bus_addr_t *)arg = segs->ds_addr; 258} 259 260/* 261 * DMA TX buffer callback function to allocate fragment data segment 262 * addresses 263 */ 264static void 265nve_dmamap_tx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error) 266{ 267 struct nve_tx_desc *info; 268 269 info = arg; 270 if (error) 271 return; 272 KASSERT(nsegs < NV_MAX_FRAGS, 273 ("Too many DMA segments returned when mapping mbuf")); 274 info->numfrags = nsegs; 275 bcopy(segs, info->frags, nsegs * sizeof(bus_dma_segment_t)); 276} 277 278/* Probe for supported hardware ID's */ 279static int 280nve_probe(device_t dev) 281{ 282 struct nve_type *t; 283 284 t = nve_devs; 285 /* Check for matching PCI DEVICE ID's */ 286 while (t->name != NULL) { 287 if ((pci_get_vendor(dev) == t->vid_id) && 288 (pci_get_device(dev) == t->dev_id)) { 289 device_set_desc(dev, t->name); 290 return (0); 291 } 292 t++; 293 } 294 295 return (ENXIO); 296} 297 298/* Attach driver and initialise hardware for use */ 299static int 300nve_attach(device_t dev) 301{ 302 u_char eaddr[ETHER_ADDR_LEN]; 303 struct nve_softc *sc; 304 struct ifnet *ifp; 305 OS_API *osapi; 306 ADAPTER_OPEN_PARAMS OpenParams; 307 int error = 0, i, rid, unit; 308 309 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - entry\n"); 310 311 sc = device_get_softc(dev); 312 unit = device_get_unit(dev); 313 314 /* Allocate mutex */ 315 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 316 MTX_DEF | MTX_RECURSE); 317 mtx_init(&sc->osmtx, device_get_nameunit(dev), NULL, MTX_SPIN); 318 319 sc->dev = dev; 320 sc->unit = unit; 321 322 /* Preinitialize data structures */ 323 bzero(&OpenParams, sizeof(ADAPTER_OPEN_PARAMS)); 324 325 /* Enable bus mastering */ 326 pci_enable_busmaster(dev); 327 328 /* Allocate memory mapped address space */ 329 rid = NV_RID; 330 sc->res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, 331 RF_ACTIVE); 332 333 if (sc->res == NULL) { 334 device_printf(dev, "couldn't map memory\n"); 335 error = ENXIO; 336 goto fail; 337 } 338 sc->sc_st = rman_get_bustag(sc->res); 339 sc->sc_sh = rman_get_bushandle(sc->res); 340 341 /* Allocate interrupt */ 342 rid = 0; 343 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 344 RF_SHAREABLE | RF_ACTIVE); 345 346 if (sc->irq == NULL) { 347 device_printf(dev, "couldn't map interrupt\n"); 348 error = ENXIO; 349 goto fail; 350 } 351 /* Allocate DMA tags */ 352 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 353 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * NV_MAX_FRAGS, 354 NV_MAX_FRAGS, MCLBYTES, 0, 355 busdma_lock_mutex, &Giant, 356 &sc->mtag); 357 if (error) { 358 device_printf(dev, "couldn't allocate dma tag\n"); 359 goto fail; 360 } 361 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 362 BUS_SPACE_MAXADDR, NULL, NULL, 363 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 1, 364 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 0, 365 busdma_lock_mutex, &Giant, 366 &sc->rtag); 367 if (error) { 368 device_printf(dev, "couldn't allocate dma tag\n"); 369 goto fail; 370 } 371 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 372 BUS_SPACE_MAXADDR, NULL, NULL, 373 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 1, 374 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 0, 375 busdma_lock_mutex, &Giant, 376 &sc->ttag); 377 if (error) { 378 device_printf(dev, "couldn't allocate dma tag\n"); 379 goto fail; 380 } 381 /* Allocate DMA safe memory and get the DMA addresses. */ 382 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc, 383 BUS_DMA_WAITOK, &sc->tmap); 384 if (error) { 385 device_printf(dev, "couldn't allocate dma memory\n"); 386 goto fail; 387 } 388 bzero(sc->tx_desc, sizeof(struct nve_tx_desc) * TX_RING_SIZE); 389 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc, 390 sizeof(struct nve_tx_desc) * TX_RING_SIZE, nve_dmamap_cb, 391 &sc->tx_addr, 0); 392 if (error) { 393 device_printf(dev, "couldn't map dma memory\n"); 394 goto fail; 395 } 396 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc, 397 BUS_DMA_WAITOK, &sc->rmap); 398 if (error) { 399 device_printf(dev, "couldn't allocate dma memory\n"); 400 goto fail; 401 } 402 bzero(sc->rx_desc, sizeof(struct nve_rx_desc) * RX_RING_SIZE); 403 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc, 404 sizeof(struct nve_rx_desc) * RX_RING_SIZE, nve_dmamap_cb, 405 &sc->rx_addr, 0); 406 if (error) { 407 device_printf(dev, "couldn't map dma memory\n"); 408 goto fail; 409 } 410 /* Initialize rings. */ 411 if (nve_init_rings(sc)) { 412 device_printf(dev, "failed to init rings\n"); 413 error = ENXIO; 414 goto fail; 415 } 416 /* Setup NVIDIA API callback routines */ 417 osapi = &sc->osapi; 418 osapi->pOSCX = sc; 419 osapi->pfnAllocMemory = nve_osalloc; 420 osapi->pfnFreeMemory = nve_osfree; 421 osapi->pfnAllocMemoryEx = nve_osallocex; 422 osapi->pfnFreeMemoryEx = nve_osfreeex; 423 osapi->pfnClearMemory = nve_osclear; 424 osapi->pfnStallExecution = nve_osdelay; 425 osapi->pfnAllocReceiveBuffer = nve_osallocrxbuf; 426 osapi->pfnFreeReceiveBuffer = nve_osfreerxbuf; 427 osapi->pfnPacketWasSent = nve_ospackettx; 428 osapi->pfnPacketWasReceived = nve_ospacketrx; 429 osapi->pfnLinkStateHasChanged = nve_oslinkchg; 430 osapi->pfnAllocTimer = nve_osalloctimer; 431 osapi->pfnFreeTimer = nve_osfreetimer; 432 osapi->pfnInitializeTimer = nve_osinittimer; 433 osapi->pfnSetTimer = nve_ossettimer; 434 osapi->pfnCancelTimer = nve_oscanceltimer; 435 osapi->pfnPreprocessPacket = nve_ospreprocpkt; 436 osapi->pfnPreprocessPacketNopq = nve_ospreprocpktnopq; 437 osapi->pfnIndicatePackets = nve_osindicatepkt; 438 osapi->pfnLockAlloc = nve_oslockalloc; 439 osapi->pfnLockAcquire = nve_oslockacquire; 440 osapi->pfnLockRelease = nve_oslockrelease; 441 osapi->pfnReturnBufferVirtual = nve_osreturnbufvirt; 442 443 sc->linkup = FALSE; 444 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + FCS_LEN; 445 446 /* TODO - We don't support hardware offload yet */ 447 sc->hwmode = 1; 448 sc->media = 0; 449 450 /* Set NVIDIA API startup parameters */ 451 OpenParams.MaxDpcLoop = 2; 452 OpenParams.MaxRxPkt = RX_RING_SIZE; 453 OpenParams.MaxTxPkt = TX_RING_SIZE; 454 OpenParams.SentPacketStatusSuccess = 1; 455 OpenParams.SentPacketStatusFailure = 0; 456 OpenParams.MaxRxPktToAccumulate = 6; 457 OpenParams.ulPollInterval = nve_pollinterval; 458 OpenParams.SetForcedModeEveryNthRxPacket = 0; 459 OpenParams.SetForcedModeEveryNthTxPacket = 0; 460 OpenParams.RxForcedInterrupt = 0; 461 OpenParams.TxForcedInterrupt = 0; 462 OpenParams.pOSApi = osapi; 463 OpenParams.pvHardwareBaseAddress = rman_get_virtual(sc->res); 464 OpenParams.bASFEnabled = 0; 465 OpenParams.ulDescriptorVersion = sc->hwmode; 466 OpenParams.ulMaxPacketSize = sc->max_frame_size; 467 OpenParams.DeviceId = pci_get_device(dev); 468 469 /* Open NVIDIA Hardware API */ 470 error = ADAPTER_Open(&OpenParams, (void **)&(sc->hwapi), &sc->phyaddr); 471 if (error) { 472 device_printf(dev, 473 "failed to open NVIDIA Hardware API: 0x%x\n", error); 474 goto fail; 475 } 476 477 /* TODO - Add support for MODE2 hardware offload */ 478 479 bzero(&sc->adapterdata, sizeof(sc->adapterdata)); 480 481 sc->adapterdata.ulMediaIF = sc->media; 482 sc->adapterdata.ulModeRegTxReadCompleteEnable = 1; 483 sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata); 484 485 /* MAC is loaded backwards into h/w reg */ 486 sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr); 487 for (i = 0; i < 6; i++) { 488 eaddr[i] = sc->original_mac_addr[5 - i]; 489 } 490 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr); 491 492 /* Display ethernet address ,... */ 493 device_printf(dev, "Ethernet address %6D\n", eaddr, ":"); 494 495 /* Allocate interface structures */ 496 ifp = sc->ifp = if_alloc(IFT_ETHER); 497 if (ifp == NULL) { 498 device_printf(dev, "can not if_alloc()\n"); 499 error = ENOSPC; 500 goto fail; 501 } 502 503 /* Probe device for MII interface to PHY */ 504 DEBUGOUT(NVE_DEBUG_INIT, "nve: do mii_phy_probe\n"); 505 if (mii_phy_probe(dev, &sc->miibus, nve_ifmedia_upd, nve_ifmedia_sts)) { 506 device_printf(dev, "MII without any phy!\n"); 507 error = ENXIO; 508 goto fail; 509 } 510 511 /* Setup interface parameters */ 512 ifp->if_softc = sc; 513 if_initname(ifp, "nve", unit); 514 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 515 ifp->if_ioctl = nve_ioctl; 516 ifp->if_output = ether_output; 517 ifp->if_start = nve_ifstart; 518 ifp->if_watchdog = nve_watchdog; 519 ifp->if_timer = 0; 520 ifp->if_init = nve_init; 521 ifp->if_mtu = ETHERMTU; 522 ifp->if_baudrate = IF_Mbps(100); 523 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1; 524 ifp->if_capabilities |= IFCAP_VLAN_MTU; 525 526 /* Attach to OS's managers. */ 527 ether_ifattach(ifp, eaddr); 528 callout_handle_init(&sc->stat_ch); 529 530 /* Activate our interrupt handler. - attach last to avoid lock */ 531 error = bus_setup_intr(sc->dev, sc->irq, INTR_TYPE_NET, nve_intr, 532 sc, &sc->sc_ih); 533 if (error) { 534 device_printf(sc->dev, "couldn't set up interrupt handler\n"); 535 goto fail; 536 } 537 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - exit\n"); 538 539fail: 540 if (error) 541 nve_detach(dev); 542 543 return (error); 544} 545 546/* Detach interface for module unload */ 547static int 548nve_detach(device_t dev) 549{ 550 struct nve_softc *sc = device_get_softc(dev); 551 struct ifnet *ifp; 552 553 KASSERT(mtx_initialized(&sc->mtx), ("mutex not initialized")); 554 NVE_LOCK(sc); 555 556 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - entry\n"); 557 558 ifp = sc->ifp; 559 560 if (device_is_attached(dev)) { 561 nve_stop(sc); 562 ether_ifdetach(ifp); 563 if_free(ifp); 564 } 565 566 if (sc->miibus) 567 device_delete_child(dev, sc->miibus); 568 bus_generic_detach(dev); 569 570 /* Reload unreversed address back into MAC in original state */ 571 if (sc->original_mac_addr) 572 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, 573 sc->original_mac_addr); 574 575 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnClose\n"); 576 /* Detach from NVIDIA hardware API */ 577 if (sc->hwapi->pfnClose) 578 sc->hwapi->pfnClose(sc->hwapi->pADCX, FALSE); 579 /* Release resources */ 580 if (sc->sc_ih) 581 bus_teardown_intr(sc->dev, sc->irq, sc->sc_ih); 582 if (sc->irq) 583 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 584 if (sc->res) 585 bus_release_resource(sc->dev, SYS_RES_MEMORY, NV_RID, sc->res); 586 587 nve_free_rings(sc); 588 589 if (sc->tx_desc) { 590 bus_dmamap_unload(sc->rtag, sc->rmap); 591 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap); 592 bus_dmamap_destroy(sc->rtag, sc->rmap); 593 } 594 if (sc->mtag) 595 bus_dma_tag_destroy(sc->mtag); 596 if (sc->ttag) 597 bus_dma_tag_destroy(sc->ttag); 598 if (sc->rtag) 599 bus_dma_tag_destroy(sc->rtag); 600 601 NVE_UNLOCK(sc); 602 mtx_destroy(&sc->mtx); 603 mtx_destroy(&sc->osmtx); 604 605 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - exit\n"); 606 607 return (0); 608} 609 610/* Initialise interface and start it "RUNNING" */ 611static void 612nve_init(void *xsc) 613{ 614 struct nve_softc *sc = xsc; 615 struct ifnet *ifp; 616 int error; 617 618 NVE_LOCK(sc); 619 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - entry (%d)\n", sc->linkup); 620 621 ifp = sc->ifp; 622 623 /* Do nothing if already running */ 624 if (ifp->if_flags & IFF_RUNNING) 625 goto fail; 626 627 nve_stop(sc); 628 DEBUGOUT(NVE_DEBUG_INIT, "nve: do pfnInit\n"); 629 630 /* Setup Hardware interface and allocate memory structures */ 631 error = sc->hwapi->pfnInit(sc->hwapi->pADCX, 632 0, /* force speed */ 633 0, /* force full duplex */ 634 0, /* force mode */ 635 0, /* force async mode */ 636 &sc->linkup); 637 638 if (error) { 639 device_printf(sc->dev, 640 "failed to start NVIDIA Hardware interface\n"); 641 goto fail; 642 } 643 /* Set the MAC address */ 644 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, IFP2ENADDR(sc->ifp)); 645 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX); 646 sc->hwapi->pfnStart(sc->hwapi->pADCX); 647 648 /* Setup multicast filter */ 649 nve_setmulti(sc); 650 nve_ifmedia_upd(ifp); 651 652 /* Update interface parameters */ 653 ifp->if_flags |= IFF_RUNNING; 654 ifp->if_flags &= ~IFF_OACTIVE; 655 656 sc->stat_ch = timeout(nve_tick, sc, hz); 657 658 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - exit\n"); 659 660fail: 661 NVE_UNLOCK(sc); 662 663 return; 664} 665 666/* Stop interface activity ie. not "RUNNING" */ 667static void 668nve_stop(struct nve_softc *sc) 669{ 670 struct ifnet *ifp; 671 672 NVE_LOCK(sc); 673 674 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - entry\n"); 675 676 ifp = sc->ifp; 677 ifp->if_timer = 0; 678 679 /* Cancel tick timer */ 680 untimeout(nve_tick, sc, sc->stat_ch); 681 682 /* Stop hardware activity */ 683 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX); 684 sc->hwapi->pfnStop(sc->hwapi->pADCX, 0); 685 686 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnDeinit\n"); 687 /* Shutdown interface and deallocate memory buffers */ 688 if (sc->hwapi->pfnDeinit) 689 sc->hwapi->pfnDeinit(sc->hwapi->pADCX, 0); 690 691 sc->linkup = 0; 692 sc->cur_rx = 0; 693 sc->pending_rxs = 0; 694 695 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 696 697 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - exit\n"); 698 699 NVE_UNLOCK(sc); 700 701 return; 702} 703 704/* Shutdown interface for unload/reboot */ 705static void 706nve_shutdown(device_t dev) 707{ 708 struct nve_softc *sc; 709 710 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_shutdown\n"); 711 712 sc = device_get_softc(dev); 713 714 /* Stop hardware activity */ 715 nve_stop(sc); 716} 717 718/* Allocate TX ring buffers */ 719static int 720nve_init_rings(struct nve_softc *sc) 721{ 722 int error, i; 723 724 NVE_LOCK(sc); 725 726 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - entry\n"); 727 728 sc->cur_rx = sc->cur_tx = sc->pending_rxs = sc->pending_txs = 0; 729 /* Initialise RX ring */ 730 for (i = 0; i < RX_RING_SIZE; i++) { 731 struct nve_rx_desc *desc = sc->rx_desc + i; 732 struct nve_map_buffer *buf = &desc->buf; 733 734 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 735 if (buf->mbuf == NULL) { 736 device_printf(sc->dev, "couldn't allocate mbuf\n"); 737 nve_free_rings(sc); 738 error = ENOBUFS; 739 goto fail; 740 } 741 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES; 742 m_adj(buf->mbuf, ETHER_ALIGN); 743 744 error = bus_dmamap_create(sc->mtag, 0, &buf->map); 745 if (error) { 746 device_printf(sc->dev, "couldn't create dma map\n"); 747 nve_free_rings(sc); 748 goto fail; 749 } 750 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf, 751 nve_dmamap_rx_cb, &desc->paddr, 0); 752 if (error) { 753 device_printf(sc->dev, "couldn't dma map mbuf\n"); 754 nve_free_rings(sc); 755 goto fail; 756 } 757 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD); 758 759 desc->buflength = buf->mbuf->m_len; 760 desc->vaddr = mtod(buf->mbuf, caddr_t); 761 } 762 bus_dmamap_sync(sc->rtag, sc->rmap, 763 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 764 765 /* Initialize TX ring */ 766 for (i = 0; i < TX_RING_SIZE; i++) { 767 struct nve_tx_desc *desc = sc->tx_desc + i; 768 struct nve_map_buffer *buf = &desc->buf; 769 770 buf->mbuf = NULL; 771 772 error = bus_dmamap_create(sc->mtag, 0, &buf->map); 773 if (error) { 774 device_printf(sc->dev, "couldn't create dma map\n"); 775 nve_free_rings(sc); 776 goto fail; 777 } 778 } 779 bus_dmamap_sync(sc->ttag, sc->tmap, 780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 781 782 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - exit\n"); 783 784fail: 785 NVE_UNLOCK(sc); 786 787 return (error); 788} 789 790/* Free the TX ring buffers */ 791static void 792nve_free_rings(struct nve_softc *sc) 793{ 794 int i; 795 796 NVE_LOCK(sc); 797 798 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - entry\n"); 799 800 for (i = 0; i < RX_RING_SIZE; i++) { 801 struct nve_rx_desc *desc = sc->rx_desc + i; 802 struct nve_map_buffer *buf = &desc->buf; 803 804 if (buf->mbuf) { 805 bus_dmamap_unload(sc->mtag, buf->map); 806 bus_dmamap_destroy(sc->mtag, buf->map); 807 m_freem(buf->mbuf); 808 } 809 buf->mbuf = NULL; 810 } 811 812 for (i = 0; i < TX_RING_SIZE; i++) { 813 struct nve_tx_desc *desc = sc->tx_desc + i; 814 struct nve_map_buffer *buf = &desc->buf; 815 816 if (buf->mbuf) { 817 bus_dmamap_unload(sc->mtag, buf->map); 818 bus_dmamap_destroy(sc->mtag, buf->map); 819 m_freem(buf->mbuf); 820 } 821 buf->mbuf = NULL; 822 } 823 824 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - exit\n"); 825 826 NVE_UNLOCK(sc); 827} 828 829/* Main loop for sending packets from OS to interface */ 830static void 831nve_ifstart(struct ifnet *ifp) 832{ 833 struct nve_softc *sc = ifp->if_softc; 834 struct nve_map_buffer *buf; 835 struct mbuf *m0, *m; 836 struct nve_tx_desc *desc; 837 ADAPTER_WRITE_DATA txdata; 838 int error, i; 839 840 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - entry\n"); 841 842 /* If link is down/busy or queue is empty do nothing */ 843 if (ifp->if_flags & IFF_OACTIVE || ifp->if_snd.ifq_head == NULL) 844 return; 845 846 /* Transmit queued packets until sent or TX ring is full */ 847 while (sc->pending_txs < TX_RING_SIZE) { 848 desc = sc->tx_desc + sc->cur_tx; 849 buf = &desc->buf; 850 851 /* Get next packet to send. */ 852 IF_DEQUEUE(&ifp->if_snd, m0); 853 854 /* If nothing to send, return. */ 855 if (m0 == NULL) 856 return; 857 858 /* Map MBUF for DMA access */ 859 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0, 860 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT); 861 862 if (error && error != EFBIG) { 863 m_freem(m0); 864 sc->tx_errors++; 865 continue; 866 } 867 /* 868 * Packet has too many fragments - defrag into new mbuf 869 * cluster 870 */ 871 if (error) { 872 m = m_defrag(m0, M_DONTWAIT); 873 if (m == NULL) { 874 m_freem(m0); 875 sc->tx_errors++; 876 continue; 877 } 878 m0 = m; 879 880 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m, 881 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT); 882 if (error) { 883 m_freem(m); 884 sc->tx_errors++; 885 continue; 886 } 887 } 888 /* Do sync on DMA bounce buffer */ 889 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE); 890 891 buf->mbuf = m0; 892 txdata.ulNumberOfElements = desc->numfrags; 893 txdata.pvID = (PVOID)desc; 894 895 /* Put fragments into API element list */ 896 txdata.ulTotalLength = buf->mbuf->m_len; 897 for (i = 0; i < desc->numfrags; i++) { 898 txdata.sElement[i].ulLength = 899 (ulong)desc->frags[i].ds_len; 900 txdata.sElement[i].pPhysical = 901 (PVOID)desc->frags[i].ds_addr; 902 } 903 904 /* Send packet to Nvidia API for transmission */ 905 error = sc->hwapi->pfnWrite(sc->hwapi->pADCX, &txdata); 906 907 switch (error) { 908 case ADAPTERERR_NONE: 909 /* Packet was queued in API TX queue successfully */ 910 sc->pending_txs++; 911 sc->cur_tx = (sc->cur_tx + 1) % TX_RING_SIZE; 912 break; 913 914 case ADAPTERERR_TRANSMIT_QUEUE_FULL: 915 /* The API TX queue is full - requeue the packet */ 916 device_printf(sc->dev, 917 "nve_ifstart: transmit queue is full\n"); 918 ifp->if_flags |= IFF_OACTIVE; 919 bus_dmamap_unload(sc->mtag, buf->map); 920 IF_PREPEND(&ifp->if_snd, buf->mbuf); 921 buf->mbuf = NULL; 922 return; 923 924 default: 925 /* The API failed to queue/send the packet so dump it */ 926 device_printf(sc->dev, "nve_ifstart: transmit error\n"); 927 bus_dmamap_unload(sc->mtag, buf->map); 928 m_freem(buf->mbuf); 929 buf->mbuf = NULL; 930 sc->tx_errors++; 931 return; 932 } 933 /* Set watchdog timer. */ 934 ifp->if_timer = 8; 935 936 /* Copy packet to BPF tap */ 937 BPF_MTAP(ifp, m0); 938 } 939 ifp->if_flags |= IFF_OACTIVE; 940 941 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - exit\n"); 942} 943 944/* Handle IOCTL events */ 945static int 946nve_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 947{ 948 struct nve_softc *sc = ifp->if_softc; 949 struct ifreq *ifr = (struct ifreq *) data; 950 struct mii_data *mii; 951 int error = 0; 952 953 NVE_LOCK(sc); 954 955 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - entry\n"); 956 957 switch (command) { 958 case SIOCSIFMTU: 959 /* Set MTU size */ 960 if (ifp->if_mtu == ifr->ifr_mtu) 961 break; 962 if (ifr->ifr_mtu + ifp->if_hdrlen <= MAX_PACKET_SIZE_1518) { 963 ifp->if_mtu = ifr->ifr_mtu; 964 nve_stop(sc); 965 nve_init(sc); 966 } else 967 error = EINVAL; 968 break; 969 970 case SIOCSIFFLAGS: 971 /* Setup interface flags */ 972 if (ifp->if_flags & IFF_UP) { 973 if ((ifp->if_flags & IFF_RUNNING) == 0) { 974 nve_init(sc); 975 break; 976 } 977 } else { 978 if (ifp->if_flags & IFF_RUNNING) { 979 nve_stop(sc); 980 break; 981 } 982 } 983 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */ 984 nve_setmulti(sc); 985 break; 986 987 case SIOCADDMULTI: 988 case SIOCDELMULTI: 989 /* Setup multicast filter */ 990 if (ifp->if_flags & IFF_RUNNING) { 991 nve_setmulti(sc); 992 } 993 break; 994 995 case SIOCGIFMEDIA: 996 case SIOCSIFMEDIA: 997 /* Get/Set interface media parameters */ 998 mii = device_get_softc(sc->miibus); 999 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1000 break; 1001 1002 default: 1003 /* Everything else we forward to generic ether ioctl */ 1004 error = ether_ioctl(ifp, (int)command, data); 1005 break; 1006 } 1007 1008 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - exit\n"); 1009 1010 NVE_UNLOCK(sc); 1011 1012 return (error); 1013} 1014 1015/* Interrupt service routine */ 1016static void 1017nve_intr(void *arg) 1018{ 1019 struct nve_softc *sc = arg; 1020 struct ifnet *ifp = sc->ifp; 1021 1022 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - entry\n"); 1023 1024 if (!ifp->if_flags & IFF_UP) { 1025 nve_stop(sc); 1026 return; 1027 } 1028 /* Handle interrupt event */ 1029 if (sc->hwapi->pfnQueryInterrupt(sc->hwapi->pADCX)) { 1030 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX); 1031 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX); 1032 } 1033 if (ifp->if_snd.ifq_head != NULL) 1034 nve_ifstart(ifp); 1035 1036 /* If no pending packets we don't need a timeout */ 1037 if (sc->pending_txs == 0) 1038 sc->ifp->if_timer = 0; 1039 1040 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - exit\n"); 1041 1042 return; 1043} 1044 1045/* Setup multicast filters */ 1046static void 1047nve_setmulti(struct nve_softc *sc) 1048{ 1049 struct ifnet *ifp; 1050 struct ifmultiaddr *ifma; 1051 PACKET_FILTER hwfilter; 1052 int i; 1053 u_int8_t andaddr[6], oraddr[6]; 1054 1055 NVE_LOCK(sc); 1056 1057 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - entry\n"); 1058 1059 ifp = sc->ifp; 1060 1061 /* Initialize filter */ 1062 hwfilter.ulFilterFlags = 0; 1063 for (i = 0; i < 6; i++) { 1064 hwfilter.acMulticastAddress[i] = 0; 1065 hwfilter.acMulticastMask[i] = 0; 1066 } 1067 1068 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1069 /* Accept all packets */ 1070 hwfilter.ulFilterFlags |= ACCEPT_ALL_PACKETS; 1071 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter); 1072 NVE_UNLOCK(sc); 1073 return; 1074 } 1075 /* Setup multicast filter */ 1076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1077 u_char *addrp; 1078 1079 if (ifma->ifma_addr->sa_family != AF_LINK) 1080 continue; 1081 1082 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1083 for (i = 0; i < 6; i++) { 1084 u_int8_t mcaddr = addrp[i]; 1085 andaddr[i] &= mcaddr; 1086 oraddr[i] |= mcaddr; 1087 } 1088 } 1089 for (i = 0; i < 6; i++) { 1090 hwfilter.acMulticastAddress[i] = andaddr[i] & oraddr[i]; 1091 hwfilter.acMulticastMask[i] = andaddr[i] | (~oraddr[i]); 1092 } 1093 1094 /* Send filter to NVIDIA API */ 1095 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter); 1096 1097 NVE_UNLOCK(sc); 1098 1099 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - exit\n"); 1100 1101 return; 1102} 1103 1104/* Change the current media/mediaopts */ 1105static int 1106nve_ifmedia_upd(struct ifnet *ifp) 1107{ 1108 struct nve_softc *sc = ifp->if_softc; 1109 struct mii_data *mii; 1110 1111 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_upd\n"); 1112 1113 mii = device_get_softc(sc->miibus); 1114 1115 if (mii->mii_instance) { 1116 struct mii_softc *miisc; 1117 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1118 miisc = LIST_NEXT(miisc, mii_list)) { 1119 mii_phy_reset(miisc); 1120 } 1121 } 1122 mii_mediachg(mii); 1123 1124 return (0); 1125} 1126 1127/* Update current miibus PHY status of media */ 1128static void 1129nve_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1130{ 1131 struct nve_softc *sc; 1132 struct mii_data *mii; 1133 1134 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_sts\n"); 1135 1136 sc = ifp->if_softc; 1137 mii = device_get_softc(sc->miibus); 1138 mii_pollstat(mii); 1139 1140 ifmr->ifm_active = mii->mii_media_active; 1141 ifmr->ifm_status = mii->mii_media_status; 1142 1143 return; 1144} 1145 1146/* miibus tick timer - maintain link status */ 1147static void 1148nve_tick(void *xsc) 1149{ 1150 struct nve_softc *sc = xsc; 1151 struct mii_data *mii; 1152 struct ifnet *ifp; 1153 1154 NVE_LOCK(sc); 1155 1156 ifp = sc->ifp; 1157 nve_update_stats(sc); 1158 1159 mii = device_get_softc(sc->miibus); 1160 mii_tick(mii); 1161 1162 if (mii->mii_media_status & IFM_ACTIVE && 1163 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1164 if (ifp->if_snd.ifq_head != NULL) 1165 nve_ifstart(ifp); 1166 } 1167 sc->stat_ch = timeout(nve_tick, sc, hz); 1168 1169 NVE_UNLOCK(sc); 1170 1171 return; 1172} 1173 1174/* Update ifnet data structure with collected interface stats from API */ 1175static void 1176nve_update_stats(struct nve_softc *sc) 1177{ 1178 struct ifnet *ifp = sc->ifp; 1179 ADAPTER_STATS stats; 1180 1181 NVE_LOCK(sc); 1182 1183 if (sc->hwapi) { 1184 sc->hwapi->pfnGetStatistics(sc->hwapi->pADCX, &stats); 1185 1186 ifp->if_ipackets = stats.ulSuccessfulReceptions; 1187 ifp->if_ierrors = stats.ulMissedFrames + 1188 stats.ulFailedReceptions + 1189 stats.ulCRCErrors + 1190 stats.ulFramingErrors + 1191 stats.ulOverFlowErrors; 1192 1193 ifp->if_opackets = stats.ulSuccessfulTransmissions; 1194 ifp->if_oerrors = sc->tx_errors + 1195 stats.ulFailedTransmissions + 1196 stats.ulRetryErrors + 1197 stats.ulUnderflowErrors + 1198 stats.ulLossOfCarrierErrors + 1199 stats.ulLateCollisionErrors; 1200 1201 ifp->if_collisions = stats.ulLateCollisionErrors; 1202 } 1203 NVE_UNLOCK(sc); 1204 1205 return; 1206} 1207 1208/* miibus Read PHY register wrapper - calls Nvidia API entry point */ 1209static int 1210nve_miibus_readreg(device_t dev, int phy, int reg) 1211{ 1212 struct nve_softc *sc = device_get_softc(dev); 1213 ULONG data; 1214 1215 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - entry\n"); 1216 1217 ADAPTER_ReadPhy(sc->hwapi->pADCX, phy, reg, &data); 1218 1219 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - exit\n"); 1220 1221 return (data); 1222} 1223 1224/* miibus Write PHY register wrapper - calls Nvidia API entry point */ 1225static void 1226nve_miibus_writereg(device_t dev, int phy, int reg, int data) 1227{ 1228 struct nve_softc *sc = device_get_softc(dev); 1229 1230 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - entry\n"); 1231 1232 ADAPTER_WritePhy(sc->hwapi->pADCX, phy, reg, (ulong)data); 1233 1234 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - exit\n"); 1235 1236 return; 1237} 1238 1239/* Watchdog timer to prevent PHY lockups */ 1240static void 1241nve_watchdog(struct ifnet *ifp) 1242{ 1243 struct nve_softc *sc = ifp->if_softc; 1244 1245 device_printf(sc->dev, "device timeout (%d)\n", sc->pending_txs); 1246 1247 sc->tx_errors++; 1248 1249 nve_stop(sc); 1250 ifp->if_flags &= ~IFF_RUNNING; 1251 nve_init(sc); 1252 1253 if (ifp->if_snd.ifq_head != NULL) 1254 nve_ifstart(ifp); 1255 1256 return; 1257} 1258 1259/* --- Start of NVOSAPI interface --- */ 1260 1261/* Allocate DMA enabled general use memory for API */ 1262static NV_SINT32 1263nve_osalloc(PNV_VOID ctx, PMEMORY_BLOCK mem) 1264{ 1265 struct nve_softc *sc; 1266 bus_addr_t mem_physical; 1267 1268 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc - %d\n", mem->uiLength); 1269 1270 sc = (struct nve_softc *)ctx; 1271 1272 mem->pLogical = (PVOID)contigmalloc(mem->uiLength, M_DEVBUF, 1273 M_NOWAIT | M_ZERO, 0, ~0, PAGE_SIZE, 0); 1274 1275 if (!mem->pLogical) { 1276 device_printf(sc->dev, "memory allocation failed\n"); 1277 return (0); 1278 } 1279 memset(mem->pLogical, 0, (ulong)mem->uiLength); 1280 mem_physical = vtophys(mem->pLogical); 1281 mem->pPhysical = (PVOID)mem_physical; 1282 1283 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc 0x%x/0x%x - %d\n", 1284 (uint)mem->pLogical, (uint)mem->pPhysical, (uint)mem->uiLength); 1285 1286 return (1); 1287} 1288 1289/* Free allocated memory */ 1290static NV_SINT32 1291nve_osfree(PNV_VOID ctx, PMEMORY_BLOCK mem) 1292{ 1293 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfree - 0x%x - %d\n", 1294 (uint)mem->pLogical, (uint) mem->uiLength); 1295 1296 contigfree(mem->pLogical, PAGE_SIZE, M_DEVBUF); 1297 return (1); 1298} 1299 1300/* Copied directly from nvnet.c */ 1301static NV_SINT32 1302nve_osallocex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex) 1303{ 1304 MEMORY_BLOCK mem_block; 1305 1306 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocex\n"); 1307 1308 mem_block_ex->pLogical = NULL; 1309 mem_block_ex->uiLengthOrig = mem_block_ex->uiLength; 1310 1311 if ((mem_block_ex->AllocFlags & ALLOC_MEMORY_ALIGNED) && 1312 (mem_block_ex->AlignmentSize > 1)) { 1313 DEBUGOUT(NVE_DEBUG_API, " aligning on %d\n", 1314 mem_block_ex->AlignmentSize); 1315 mem_block_ex->uiLengthOrig += mem_block_ex->AlignmentSize; 1316 } 1317 mem_block.uiLength = mem_block_ex->uiLengthOrig; 1318 1319 if (nve_osalloc(ctx, &mem_block) == 0) { 1320 return (0); 1321 } 1322 mem_block_ex->pLogicalOrig = mem_block.pLogical; 1323 mem_block_ex->pPhysicalOrigLow = (unsigned long)mem_block.pPhysical; 1324 mem_block_ex->pPhysicalOrigHigh = 0; 1325 1326 mem_block_ex->pPhysical = mem_block.pPhysical; 1327 mem_block_ex->pLogical = mem_block.pLogical; 1328 1329 if (mem_block_ex->uiLength != mem_block_ex->uiLengthOrig) { 1330 unsigned int offset; 1331 offset = mem_block_ex->pPhysicalOrigLow & 1332 (mem_block_ex->AlignmentSize - 1); 1333 1334 if (offset) { 1335 mem_block_ex->pPhysical = 1336 (PVOID)((ulong)mem_block_ex->pPhysical + 1337 mem_block_ex->AlignmentSize - offset); 1338 mem_block_ex->pLogical = 1339 (PVOID)((ulong)mem_block_ex->pLogical + 1340 mem_block_ex->AlignmentSize - offset); 1341 } /* if (offset) */ 1342 } /* if (mem_block_ex->uiLength != *mem_block_ex->uiLengthOrig) */ 1343 return (1); 1344} 1345 1346/* Copied directly from nvnet.c */ 1347static NV_SINT32 1348nve_osfreeex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex) 1349{ 1350 MEMORY_BLOCK mem_block; 1351 1352 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreeex\n"); 1353 1354 mem_block.pLogical = mem_block_ex->pLogicalOrig; 1355 mem_block.pPhysical = (PVOID)((ulong)mem_block_ex->pPhysicalOrigLow); 1356 mem_block.uiLength = mem_block_ex->uiLengthOrig; 1357 1358 return (nve_osfree(ctx, &mem_block)); 1359} 1360 1361/* Clear memory region */ 1362static NV_SINT32 1363nve_osclear(PNV_VOID ctx, PNV_VOID mem, NV_SINT32 length) 1364{ 1365 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osclear\n"); 1366 memset(mem, 0, length); 1367 return (1); 1368} 1369 1370/* Sleep for a tick */ 1371static NV_SINT32 1372nve_osdelay(PNV_VOID ctx, NV_UINT32 usec) 1373{ 1374 DELAY(usec); 1375 return (1); 1376} 1377 1378/* Allocate memory for rx buffer */ 1379static NV_SINT32 1380nve_osallocrxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID *id) 1381{ 1382 struct nve_softc *sc = ctx; 1383 struct nve_rx_desc *desc; 1384 struct nve_map_buffer *buf; 1385 int error; 1386 1387 NVE_LOCK(sc); 1388 1389 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocrxbuf\n"); 1390 1391 if (sc->pending_rxs == RX_RING_SIZE) { 1392 device_printf(sc->dev, "rx ring buffer is full\n"); 1393 goto fail; 1394 } 1395 desc = sc->rx_desc + sc->cur_rx; 1396 buf = &desc->buf; 1397 1398 if (buf->mbuf == NULL) { 1399 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1400 if (buf->mbuf == NULL) { 1401 device_printf(sc->dev, "failed to allocate memory\n"); 1402 goto fail; 1403 } 1404 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES; 1405 m_adj(buf->mbuf, ETHER_ALIGN); 1406 1407 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf, 1408 nve_dmamap_rx_cb, &desc->paddr, 0); 1409 if (error) { 1410 device_printf(sc->dev, "failed to dmamap mbuf\n"); 1411 m_freem(buf->mbuf); 1412 buf->mbuf = NULL; 1413 goto fail; 1414 } 1415 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD); 1416 desc->buflength = buf->mbuf->m_len; 1417 desc->vaddr = mtod(buf->mbuf, caddr_t); 1418 } 1419 sc->pending_rxs++; 1420 sc->cur_rx = (sc->cur_rx + 1) % RX_RING_SIZE; 1421 1422 mem->pLogical = (void *)desc->vaddr; 1423 mem->pPhysical = (void *)desc->paddr; 1424 mem->uiLength = desc->buflength; 1425 *id = (void *)desc; 1426 1427 NVE_UNLOCK(sc); 1428 return (1); 1429 1430fail: 1431 NVE_UNLOCK(sc); 1432 return (0); 1433} 1434 1435/* Free the rx buffer */ 1436static NV_SINT32 1437nve_osfreerxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID id) 1438{ 1439 struct nve_softc *sc = ctx; 1440 struct nve_rx_desc *desc; 1441 struct nve_map_buffer *buf; 1442 1443 NVE_LOCK(sc); 1444 1445 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreerxbuf\n"); 1446 1447 desc = (struct nve_rx_desc *) id; 1448 buf = &desc->buf; 1449 1450 if (buf->mbuf) { 1451 bus_dmamap_unload(sc->mtag, buf->map); 1452 bus_dmamap_destroy(sc->mtag, buf->map); 1453 m_freem(buf->mbuf); 1454 } 1455 sc->pending_rxs--; 1456 buf->mbuf = NULL; 1457 1458 NVE_UNLOCK(sc); 1459 1460 return (1); 1461} 1462 1463/* This gets called by the Nvidia API after our TX packet has been sent */ 1464static NV_SINT32 1465nve_ospackettx(PNV_VOID ctx, PNV_VOID id, NV_UINT32 success) 1466{ 1467 struct nve_softc *sc = ctx; 1468 struct nve_map_buffer *buf; 1469 struct nve_tx_desc *desc = (struct nve_tx_desc *) id; 1470 struct ifnet *ifp; 1471 1472 NVE_LOCK(sc); 1473 1474 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospackettx\n"); 1475 1476 ifp = sc->ifp; 1477 buf = &desc->buf; 1478 sc->pending_txs--; 1479 1480 /* Unload and free mbuf cluster */ 1481 if (buf->mbuf == NULL) 1482 goto fail; 1483 1484 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE); 1485 bus_dmamap_unload(sc->mtag, buf->map); 1486 m_freem(buf->mbuf); 1487 buf->mbuf = NULL; 1488 1489 /* Send more packets if we have them */ 1490 if (sc->pending_txs < TX_RING_SIZE) 1491 sc->ifp->if_flags &= ~IFF_OACTIVE; 1492 1493 if (ifp->if_snd.ifq_head != NULL && sc->pending_txs < TX_RING_SIZE) 1494 nve_ifstart(ifp); 1495 1496fail: 1497 NVE_UNLOCK(sc); 1498 1499 return (1); 1500} 1501 1502/* This gets called by the Nvidia API when a new packet has been received */ 1503/* XXX What is newbuf used for? XXX */ 1504static NV_SINT32 1505nve_ospacketrx(PNV_VOID ctx, PNV_VOID data, NV_UINT32 success, NV_UINT8 *newbuf, 1506 NV_UINT8 priority) 1507{ 1508 struct nve_softc *sc = ctx; 1509 struct ifnet *ifp; 1510 struct nve_rx_desc *desc; 1511 struct nve_map_buffer *buf; 1512 ADAPTER_READ_DATA *readdata; 1513 1514 NVE_LOCK(sc); 1515 1516 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospacketrx\n"); 1517 1518 ifp = sc->ifp; 1519 1520 readdata = (ADAPTER_READ_DATA *) data; 1521 desc = readdata->pvID; 1522 buf = &desc->buf; 1523 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD); 1524 1525 if (success) { 1526 /* Sync DMA bounce buffer. */ 1527 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD); 1528 1529 /* First mbuf in packet holds the ethernet and packet headers */ 1530 buf->mbuf->m_pkthdr.rcvif = ifp; 1531 buf->mbuf->m_pkthdr.len = buf->mbuf->m_len = 1532 readdata->ulTotalLength; 1533 1534 bus_dmamap_unload(sc->mtag, buf->map); 1535 1536 /* Give mbuf to OS. */ 1537 (*ifp->if_input) (ifp, buf->mbuf); 1538 if (readdata->ulFilterMatch & ADREADFL_MULTICAST_MATCH) 1539 ifp->if_imcasts++; 1540 1541 /* Blat the mbuf pointer, kernel will free the mbuf cluster */ 1542 buf->mbuf = NULL; 1543 } else { 1544 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD); 1545 bus_dmamap_unload(sc->mtag, buf->map); 1546 m_freem(buf->mbuf); 1547 buf->mbuf = NULL; 1548 } 1549 1550 sc->cur_rx = desc - sc->rx_desc; 1551 sc->pending_rxs--; 1552 1553 NVE_UNLOCK(sc); 1554 1555 return (1); 1556} 1557 1558/* This gets called by NVIDIA API when the PHY link state changes */ 1559static NV_SINT32 1560nve_oslinkchg(PNV_VOID ctx, NV_SINT32 enabled) 1561{ 1562 struct nve_softc *sc = (struct nve_softc *)ctx; 1563 struct ifnet *ifp; 1564 1565 DEBUGOUT(NVE_DEBUG_API, "nve: nve_oslinkchg\n"); 1566 1567 ifp = sc->ifp; 1568 1569 if (enabled) 1570 ifp->if_flags |= IFF_UP; 1571 else 1572 ifp->if_flags &= ~IFF_UP; 1573 1574 return (1); 1575} 1576 1577/* Setup a watchdog timer */ 1578static NV_SINT32 1579nve_osalloctimer(PNV_VOID ctx, PNV_VOID *timer) 1580{ 1581 struct nve_softc *sc = (struct nve_softc *)ctx; 1582 1583 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osalloctimer\n"); 1584 1585 callout_handle_init(&sc->ostimer); 1586 *timer = &sc->ostimer; 1587 1588 return (1); 1589} 1590 1591/* Free the timer */ 1592static NV_SINT32 1593nve_osfreetimer(PNV_VOID ctx, PNV_VOID timer) 1594{ 1595 1596 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osfreetimer\n"); 1597 1598 return (1); 1599} 1600 1601/* Setup timer parameters */ 1602static NV_SINT32 1603nve_osinittimer(PNV_VOID ctx, PNV_VOID timer, PTIMER_FUNC func, PNV_VOID parameters) 1604{ 1605 struct nve_softc *sc = (struct nve_softc *)ctx; 1606 1607 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osinittimer\n"); 1608 1609 sc->ostimer_func = func; 1610 sc->ostimer_params = parameters; 1611 1612 return (1); 1613} 1614 1615/* Set the timer to go off */ 1616static NV_SINT32 1617nve_ossettimer(PNV_VOID ctx, PNV_VOID timer, NV_UINT32 delay) 1618{ 1619 struct nve_softc *sc = ctx; 1620 1621 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ossettimer\n"); 1622 1623 *(struct callout_handle *)timer = timeout(sc->ostimer_func, 1624 sc->ostimer_params, delay); 1625 1626 return (1); 1627} 1628 1629/* Cancel the timer */ 1630static NV_SINT32 1631nve_oscanceltimer(PNV_VOID ctx, PNV_VOID timer) 1632{ 1633 struct nve_softc *sc = ctx; 1634 1635 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_oscanceltimer\n"); 1636 1637 untimeout(sc->ostimer_func, sc->ostimer_params, 1638 *(struct callout_handle *)timer); 1639 1640 return (1); 1641} 1642 1643static NV_SINT32 1644nve_ospreprocpkt(PNV_VOID ctx, PNV_VOID readdata, PNV_VOID *id, 1645 NV_UINT8 *newbuffer, NV_UINT8 priority) 1646{ 1647 1648 /* Not implemented */ 1649 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n"); 1650 1651 return (1); 1652} 1653 1654static PNV_VOID 1655nve_ospreprocpktnopq(PNV_VOID ctx, PNV_VOID readdata) 1656{ 1657 1658 /* Not implemented */ 1659 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n"); 1660 1661 return (NULL); 1662} 1663 1664static NV_SINT32 1665nve_osindicatepkt(PNV_VOID ctx, PNV_VOID *id, NV_UINT32 pktno) 1666{ 1667 1668 /* Not implemented */ 1669 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osindicatepkt\n"); 1670 1671 return (1); 1672} 1673 1674/* Allocate mutex context (already done in nve_attach) */ 1675static NV_SINT32 1676nve_oslockalloc(PNV_VOID ctx, NV_SINT32 type, PNV_VOID *pLock) 1677{ 1678 struct nve_softc *sc = (struct nve_softc *)ctx; 1679 1680 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockalloc\n"); 1681 1682 *pLock = (void **)sc; 1683 1684 return (1); 1685} 1686 1687/* Obtain a spin lock */ 1688static NV_SINT32 1689nve_oslockacquire(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock) 1690{ 1691 1692 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockacquire\n"); 1693 1694 NVE_OSLOCK((struct nve_softc *)lock); 1695 1696 return (1); 1697} 1698 1699/* Release lock */ 1700static NV_SINT32 1701nve_oslockrelease(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock) 1702{ 1703 1704 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockrelease\n"); 1705 1706 NVE_OSUNLOCK((struct nve_softc *)lock); 1707 1708 return (1); 1709} 1710 1711/* I have no idea what this is for */ 1712static PNV_VOID 1713nve_osreturnbufvirt(PNV_VOID ctx, PNV_VOID readdata) 1714{ 1715 1716 /* Not implemented */ 1717 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_osreturnbufvirt\n"); 1718 panic("nve: nve_osreturnbufvirtual not implemented\n"); 1719 1720 return (NULL); 1721} 1722 1723/* --- End on NVOSAPI interface --- */ 1724