11573Srgrimes/*- 21573Srgrimes * Copyright (C) 2009-2012 Semihalf 31573Srgrimes * All rights reserved. 41573Srgrimes * 51573Srgrimes * Redistribution and use in source and binary forms, with or without 61573Srgrimes * modification, are permitted provided that the following conditions 71573Srgrimes * are met: 81573Srgrimes * 1. Redistributions of source code must retain the above copyright 91573Srgrimes * notice, this list of conditions and the following disclaimer. 101573Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111573Srgrimes * notice, this list of conditions and the following disclaimer in the 121573Srgrimes * documentation and/or other materials provided with the distribution. 131573Srgrimes * 141573Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 151573Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 161573Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 171573Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 181573Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 191573Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 201573Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 211573Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 221573Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 231573Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 241573Srgrimes * SUCH DAMAGE. 251573Srgrimes * 261573Srgrimes * $FreeBSD: releng/10.3/sys/dev/nand/nandsim_chip.h 235537 2012-05-17 10:11:18Z gber $ 271573Srgrimes */ 281573Srgrimes 291573Srgrimes#ifndef _NANDSIM_CHIP_H 301573Srgrimes#define _NANDSIM_CHIP_H 311573Srgrimes 321573Srgrimes#include <sys/malloc.h> 3392986Sobrien#include <sys/callout.h> 3492986Sobrien#include <dev/nand/nand.h> 351573Srgrimes#include <dev/nand/nandsim.h> 361573Srgrimes#include <dev/nand/nandsim_swap.h> 371573Srgrimes 381573SrgrimesMALLOC_DECLARE(M_NANDSIM); 391573Srgrimes 40201194Skib#define MAX_CS_NUM 4 411573Srgrimesstruct nandsim_chip; 42201194Skib 43117753Swollmantypedef void nandsim_evh_t(struct nandsim_chip *chip, uint32_t ev, void *data); 441573Srgrimes 45201194Skibenum addr_type { 46117753Swollman ADDR_NONE, 47117753Swollman ADDR_ID, 48117753Swollman ADDR_ROW, 49117753Swollman ADDR_ROWCOL 50117753Swollman}; 51117753Swollman 521573Srgrimesstruct nandsim_softc { 53 struct nand_softc nand_dev; 54 device_t dev; 55 56 struct nandsim_chip *chips[MAX_CS_NUM]; 57 struct nandsim_chip *active_chip; 58 59 uint8_t address_cycle; 60 enum addr_type address_type; 61 int log_idx; 62 char *log_buff; 63 struct alq *alq; 64}; 65 66struct nandsim_ev { 67 STAILQ_ENTRY(nandsim_ev) links; 68 struct nandsim_chip *chip; 69 uint8_t type; 70 void *data; 71}; 72 73struct nandsim_data { 74 uint8_t *data_ptr; 75 uint32_t index; 76 uint32_t size; 77}; 78 79struct nandsim_block_state { 80 int32_t wear_lev; 81 uint8_t is_bad; 82}; 83 84#define NANDSIM_CHIP_ACTIVE 0x1 85#define NANDSIM_CHIP_FROZEN 0x2 86#define NANDSIM_CHIP_GET_STATUS 0x4 87 88struct nandsim_chip { 89 struct nandsim_softc *sc; 90 struct thread *nandsim_td; 91 92 STAILQ_HEAD(, nandsim_ev) nandsim_events; 93 nandsim_evh_t *ev_handler; 94 struct mtx ns_lock; 95 struct callout ns_callout; 96 97 struct chip_geom cg; 98 struct nand_id id; 99 struct onfi_params params; 100 struct nandsim_data data; 101 struct nandsim_block_state *blk_state; 102 103 struct chip_swap *swap; 104 105 uint32_t error_ratio; 106 uint32_t wear_level; 107 uint32_t sm_state; 108 uint32_t sm_addr_cycle; 109 110 uint32_t erase_delay; 111 uint32_t prog_delay; 112 uint32_t read_delay; 113 struct timeval delay_tv; 114 115 uint8_t flags; 116 uint8_t chip_status; 117 uint8_t ctrl_num; 118 uint8_t chip_num; 119}; 120 121struct sim_ctrl_conf { 122 uint8_t num; 123 uint8_t num_cs; 124 uint8_t ecc; 125 uint8_t running; 126 uint8_t created; 127 device_t sim_ctrl_dev; 128 struct sim_chip *chips[MAX_CTRL_CS]; 129 uint16_t ecc_layout[MAX_ECC_BYTES]; 130 char filename[FILENAME_SIZE]; 131}; 132 133#define NANDSIM_STATE_IDLE 0x0 134#define NANDSIM_STATE_WAIT_ADDR_BYTE 0x1 135#define NANDSIM_STATE_WAIT_CMD 0x2 136#define NANDSIM_STATE_TIMEOUT 0x3 137#define NANDSIM_STATE_WAIT_ADDR_ROW 0x4 138#define NANDSIM_STATE_WAIT_ADDR_COL 0x5 139 140#define NANDSIM_EV_START 0x1 141#define NANDSIM_EV_CMD 0x2 142#define NANDSIM_EV_ADDR 0x3 143#define NANDSIM_EV_TIMEOUT 0x4 144#define NANDSIM_EV_EXIT 0xff 145 146struct nandsim_chip *nandsim_chip_init(struct nandsim_softc *, 147 uint8_t, struct sim_chip *); 148void nandsim_chip_destroy(struct nandsim_chip *); 149void nandsim_chip_freeze(struct nandsim_chip *); 150void nandsim_chip_timeout(struct nandsim_chip *); 151int nandsim_chip_check_bad_block(struct nandsim_chip *, int); 152 153uint8_t nandchip_get_status(struct nandsim_chip *); 154 155void destroy_event(struct nandsim_ev *); 156int send_event(struct nandsim_ev *); 157struct nandsim_ev *create_event(struct nandsim_chip *, uint8_t, uint8_t); 158 159#endif /* _NANDSIM_CHIP_H */ 160