if_mskreg.h revision 199012
1193323Sed/****************************************************************************** 2193323Sed * 3193323Sed * Name: skgehw.h 4193323Sed * Project: Gigabit Ethernet Adapters, Common Modules 5193323Sed * Version: $Revision: 2.49 $ 6193323Sed * Date: $Date: 2005/01/20 13:01:35 $ 7193323Sed * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 8193323Sed * 9193323Sed ******************************************************************************/ 10193323Sed 11193323Sed/****************************************************************************** 12193323Sed * 13194612Sed * LICENSE: 14198090Srdivacky * Copyright (C) Marvell International Ltd. and/or its affiliates 15198090Srdivacky * 16204642Srdivacky * The computer program files contained in this folder ("Files") 17198090Srdivacky * are provided to you under the BSD-type license terms provided 18198090Srdivacky * below, and any use of such Files and any derivative works 19198090Srdivacky * thereof created by you shall be governed by the following terms 20198090Srdivacky * and conditions: 21198090Srdivacky * 22198090Srdivacky * - Redistributions of source code must retain the above copyright 23198090Srdivacky * notice, this list of conditions and the following disclaimer. 24198090Srdivacky * - Redistributions in binary form must reproduce the above 25198090Srdivacky * copyright notice, this list of conditions and the following 26198090Srdivacky * disclaimer in the documentation and/or other materials provided 27198090Srdivacky * with the distribution. 28198090Srdivacky * - Neither the name of Marvell nor the names of its contributors 29194612Sed * may be used to endorse or promote products derived from this 30194612Sed * software without specific prior written permission. 31194612Sed * 32195098Sed * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33194612Sed * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34195098Sed * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35194612Sed * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36194612Sed * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37194612Sed * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38194754Sed * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39194754Sed * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40198090Srdivacky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41194612Sed * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42194612Sed * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43194754Sed * OF THE POSSIBILITY OF SUCH DAMAGE. 44194754Sed * /LICENSE 45198090Srdivacky * 46194754Sed ******************************************************************************/ 47194612Sed 48194754Sed/*- 49194754Sed * Copyright (c) 1997, 1998, 1999, 2000 50194754Sed * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51194754Sed * 52199989Srdivacky * Redistribution and use in source and binary forms, with or without 53199989Srdivacky * modification, are permitted provided that the following conditions 54194754Sed * are met: 55194754Sed * 1. Redistributions of source code must retain the above copyright 56204642Srdivacky * notice, this list of conditions and the following disclaimer. 57198090Srdivacky * 2. Redistributions in binary form must reproduce the above copyright 58194612Sed * notice, this list of conditions and the following disclaimer in the 59204642Srdivacky * documentation and/or other materials provided with the distribution. 60194754Sed * 3. All advertising materials mentioning features or use of this software 61194754Sed * must display the following acknowledgement: 62194754Sed * This product includes software developed by Bill Paul. 63198090Srdivacky * 4. Neither the name of the author nor the names of any co-contributors 64198090Srdivacky * may be used to endorse or promote products derived from this software 65194612Sed * without specific prior written permission. 66194754Sed * 67194754Sed * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68194754Sed * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69198090Srdivacky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70198090Srdivacky * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71194754Sed * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72198396Srdivacky * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73198396Srdivacky * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74198396Srdivacky * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75198396Srdivacky * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76198396Srdivacky * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77198396Srdivacky * THE POSSIBILITY OF SUCH DAMAGE. 78198396Srdivacky */ 79198396Srdivacky 80198396Srdivacky/*- 81198396Srdivacky * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 82198396Srdivacky * 83198396Srdivacky * Permission to use, copy, modify, and distribute this software for any 84198396Srdivacky * purpose with or without fee is hereby granted, provided that the above 85198396Srdivacky * copyright notice and this permission notice appear in all copies. 86198396Srdivacky * 87198396Srdivacky * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 88198396Srdivacky * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 89198396Srdivacky * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 90198396Srdivacky * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 91199989Srdivacky * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 92199989Srdivacky * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 93199989Srdivacky * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 94199989Srdivacky */ 95199989Srdivacky 96199989Srdivacky/*$FreeBSD: head/sys/dev/msk/if_mskreg.h 199012 2009-11-07 01:14:09Z yongari $*/ 97199989Srdivacky 98199989Srdivacky/* 99199989Srdivacky * SysKonnect PCI vendor ID 100199989Srdivacky */ 101199989Srdivacky#define VENDORID_SK 0x1148 102199989Srdivacky 103199989Srdivacky/* 104199989Srdivacky * Marvell PCI vendor ID 105199989Srdivacky */ 106195098Sed#define VENDORID_MARVELL 0x11AB 107195098Sed 108195098Sed/* 109195098Sed * D-Link PCI vendor ID 110195098Sed */ 111194754Sed#define VENDORID_DLINK 0x1186 112198090Srdivacky 113198090Srdivacky/* 114194754Sed * SysKonnect ethernet device IDs 115194754Sed */ 116194754Sed#define DEVICEID_SK_YUKON2 0x9000 117204642Srdivacky#define DEVICEID_SK_YUKON2_EXPR 0x9e00 118204642Srdivacky 119204642Srdivacky/* 120194612Sed * Marvell gigabit ethernet device IDs 121198090Srdivacky */ 122198090Srdivacky#define DEVICEID_MRVL_8021CU 0x4340 123204642Srdivacky#define DEVICEID_MRVL_8022CU 0x4341 124194612Sed#define DEVICEID_MRVL_8061CU 0x4342 125195340Sed#define DEVICEID_MRVL_8062CU 0x4343 126195340Sed#define DEVICEID_MRVL_8021X 0x4344 127195340Sed#define DEVICEID_MRVL_8022X 0x4345 128195340Sed#define DEVICEID_MRVL_8061X 0x4346 129195340Sed#define DEVICEID_MRVL_8062X 0x4347 130195340Sed#define DEVICEID_MRVL_8035 0x4350 131195340Sed#define DEVICEID_MRVL_8036 0x4351 132195340Sed#define DEVICEID_MRVL_8038 0x4352 133195340Sed#define DEVICEID_MRVL_8039 0x4353 134204792Srdivacky#define DEVICEID_MRVL_8040 0x4354 135195340Sed#define DEVICEID_MRVL_8040T 0x4355 136195340Sed#define DEVICEID_MRVL_8042 0x4357 137195340Sed#define DEVICEID_MRVL_8048 0x435A 138195340Sed#define DEVICEID_MRVL_4360 0x4360 139195340Sed#define DEVICEID_MRVL_4361 0x4361 140195340Sed#define DEVICEID_MRVL_4362 0x4362 141195340Sed#define DEVICEID_MRVL_4363 0x4363 142195340Sed#define DEVICEID_MRVL_4364 0x4364 143195340Sed#define DEVICEID_MRVL_4365 0x4365 144195340Sed#define DEVICEID_MRVL_436A 0x436A 145195340Sed#define DEVICEID_MRVL_436B 0x436B 146198090Srdivacky#define DEVICEID_MRVL_436C 0x436C 147195340Sed#define DEVICEID_MRVL_4380 0x4380 148195340Sed 149198090Srdivacky/* 150195340Sed * D-Link gigabit ethernet device ID 151195340Sed */ 152195340Sed#define DEVICEID_DLINK_DGE550SX 0x4001 153205218Srdivacky#define DEVICEID_DLINK_DGE560SX 0x4002 154205218Srdivacky#define DEVICEID_DLINK_DGE560T 0x4b00 155205218Srdivacky 156205218Srdivacky#define BIT_31 (1 << 31) 157198090Srdivacky#define BIT_30 (1 << 30) 158195340Sed#define BIT_29 (1 << 29) 159195340Sed#define BIT_28 (1 << 28) 160195340Sed#define BIT_27 (1 << 27) 161195340Sed#define BIT_26 (1 << 26) 162195340Sed#define BIT_25 (1 << 25) 163195340Sed#define BIT_24 (1 << 24) 164195340Sed#define BIT_23 (1 << 23) 165194612Sed#define BIT_22 (1 << 22) 166195098Sed#define BIT_21 (1 << 21) 167194612Sed#define BIT_20 (1 << 20) 168194612Sed#define BIT_19 (1 << 19) 169195098Sed#define BIT_18 (1 << 18) 170195098Sed#define BIT_17 (1 << 17) 171195098Sed#define BIT_16 (1 << 16) 172201360Srdivacky#define BIT_15 (1 << 15) 173201360Srdivacky#define BIT_14 (1 << 14) 174194612Sed#define BIT_13 (1 << 13) 175198090Srdivacky#define BIT_12 (1 << 12) 176198892Srdivacky#define BIT_11 (1 << 11) 177195098Sed#define BIT_10 (1 << 10) 178195098Sed#define BIT_9 (1 << 9) 179195098Sed#define BIT_8 (1 << 8) 180201360Srdivacky#define BIT_7 (1 << 7) 181201360Srdivacky#define BIT_6 (1 << 6) 182201360Srdivacky#define BIT_5 (1 << 5) 183201360Srdivacky#define BIT_4 (1 << 4) 184201360Srdivacky#define BIT_3 (1 << 3) 185201360Srdivacky#define BIT_2 (1 << 2) 186195098Sed#define BIT_1 (1 << 1) 187195098Sed#define BIT_0 (1 << 0) 188208599Srdivacky 189208599Srdivacky#define SHIFT31(x) ((x) << 31) 190201360Srdivacky#define SHIFT30(x) ((x) << 30) 191201360Srdivacky#define SHIFT29(x) ((x) << 29) 192201360Srdivacky#define SHIFT28(x) ((x) << 28) 193201360Srdivacky#define SHIFT27(x) ((x) << 27) 194201360Srdivacky#define SHIFT26(x) ((x) << 26) 195201360Srdivacky#define SHIFT25(x) ((x) << 25) 196201360Srdivacky#define SHIFT24(x) ((x) << 24) 197201360Srdivacky#define SHIFT23(x) ((x) << 23) 198201360Srdivacky#define SHIFT22(x) ((x) << 22) 199201360Srdivacky#define SHIFT21(x) ((x) << 21) 200194612Sed#define SHIFT20(x) ((x) << 20) 201208599Srdivacky#define SHIFT19(x) ((x) << 19) 202208599Srdivacky#define SHIFT18(x) ((x) << 18) 203208599Srdivacky#define SHIFT17(x) ((x) << 17) 204201360Srdivacky#define SHIFT16(x) ((x) << 16) 205201360Srdivacky#define SHIFT15(x) ((x) << 15) 206201360Srdivacky#define SHIFT14(x) ((x) << 14) 207201360Srdivacky#define SHIFT13(x) ((x) << 13) 208201360Srdivacky#define SHIFT12(x) ((x) << 12) 209201360Srdivacky#define SHIFT11(x) ((x) << 11) 210194612Sed#define SHIFT10(x) ((x) << 10) 211194612Sed#define SHIFT9(x) ((x) << 9) 212195098Sed#define SHIFT8(x) ((x) << 8) 213208599Srdivacky#define SHIFT7(x) ((x) << 7) 214195098Sed#define SHIFT6(x) ((x) << 6) 215204642Srdivacky#define SHIFT5(x) ((x) << 5) 216198090Srdivacky#define SHIFT4(x) ((x) << 4) 217195098Sed#define SHIFT3(x) ((x) << 3) 218198090Srdivacky#define SHIFT2(x) ((x) << 2) 219198892Srdivacky#define SHIFT1(x) ((x) << 1) 220201360Srdivacky#define SHIFT0(x) ((x) << 0) 221201360Srdivacky 222201360Srdivacky/* 223201360Srdivacky * PCI Configuration Space header 224201360Srdivacky */ 225201360Srdivacky#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 226201360Srdivacky#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 227195098Sed#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 228198090Srdivacky#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 229198892Srdivacky#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 230195098Sed#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 231195098Sed#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 232201360Srdivacky#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 233201360Srdivacky#define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ 234201360Srdivacky#define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ 235201360Srdivacky 236201360Srdivacky/* PCI Express Capability */ 237201360Srdivacky#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 238201360Srdivacky#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 239195098Sed#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 240195098Sed#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 241198090Srdivacky#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 242198892Srdivacky#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 243201360Srdivacky#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 244201360Srdivacky#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 245201360Srdivacky#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 246201360Srdivacky 247201360Srdivacky/* PCI Express Extended Capabilities */ 248201360Srdivacky#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 249195098Sed#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 250195098Sed#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 251198090Srdivacky#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 252198090Srdivacky#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 253201360Srdivacky#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 254201360Srdivacky#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 255201360Srdivacky#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 256198090Srdivacky 257195098Sed/* PCI_OUR_REG_1 32 bit Our Register 1 */ 258195098Sed#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 259195098Sed#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 260201360Srdivacky#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 261194754Sed#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 262208599Srdivacky#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 263208599Srdivacky#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 264208599Srdivacky#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 265201360Srdivacky#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 266201360Srdivacky#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 267201360Srdivacky /* 1 = Map Flash to memory */ 268208599Srdivacky /* 0 = Disable addr. dec */ 269201360Srdivacky#define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 270201360Srdivacky#define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 271194754Sed#define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 272208599Srdivacky#define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 273208599Srdivacky#define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 274208599Srdivacky#define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 275201360Srdivacky#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 276201360Srdivacky#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 277201360Srdivacky#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 278208599Srdivacky#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 279201360Srdivacky#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 280194754Sed#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 281194754Sed#define PCI_BURST_DIS BIT_9 /* Burst Disable */ 282195098Sed#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 283194612Sed#define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 284194612Sed#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 285201360Srdivacky#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 286201360Srdivacky 287194612Sed/* PCI_OUR_REG_2 32 bit Our Register 2 */ 288198090Srdivacky#define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 289198892Srdivacky#define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 290201360Srdivacky#define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 291201360Srdivacky /* Bit 13..12: reserved */ 292201360Srdivacky#define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 293201360Srdivacky#define PCI_PATCH_DIR_3 BIT_11 294201360Srdivacky#define PCI_PATCH_DIR_2 BIT_10 295201360Srdivacky#define PCI_PATCH_DIR_1 BIT_9 296201360Srdivacky#define PCI_PATCH_DIR_0 BIT_8 297195098Sed#define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 298198090Srdivacky#define PCI_EXT_PATCH_3 BIT_7 299198892Srdivacky#define PCI_EXT_PATCH_2 BIT_6 300195098Sed#define PCI_EXT_PATCH_1 BIT_5 301195098Sed#define PCI_EXT_PATCH_0 BIT_4 302201360Srdivacky#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 303201360Srdivacky#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 304201360Srdivacky#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 305201360Srdivacky 306201360Srdivacky/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 307201360Srdivacky#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 308201360Srdivacky#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 309195098Sed#define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 310194754Sed#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 311198090Srdivacky#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 312198892Srdivacky#define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 313201360Srdivacky#define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 314201360Srdivacky#define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 315201360Srdivacky 316201360Srdivacky#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 317201360Srdivacky/* possible values for the speed field of the register */ 318201360Srdivacky#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 319194754Sed#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 320194754Sed#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 321194612Sed#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 322195098Sed 323195098Sed/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 324201360Srdivacky#define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 325201360Srdivacky#define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 326194754Sed#define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 327198090Srdivacky#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 328198892Srdivacky#define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 329201360Srdivacky#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 330201360Srdivacky#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 331201360Srdivacky#define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 332201360Srdivacky#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 333201360Srdivacky#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 334201360Srdivacky 335201360Srdivacky/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 336201360Srdivacky /* Bit 31..27: for A3 & later */ 337195098Sed#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ 338204961Srdivacky#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ 339204961Srdivacky#define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ 340204961Srdivacky#define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ 341201360Srdivacky#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ 342201360Srdivacky#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) 343201360Srdivacky /* Bit 26..16: Release Clock on Event */ 344201360Srdivacky#define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ 345201360Srdivacky#define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ 346201360Srdivacky#define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ 347201360Srdivacky#define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ 348195098Sed#define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ 349198090Srdivacky#define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ 350198892Srdivacky#define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ 351195098Sed#define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ 352195098Sed#define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ 353201360Srdivacky#define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ 354201360Srdivacky#define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ 355201360Srdivacky /* Bit 10.. 0: Mask for Gate Clock */ 356201360Srdivacky#define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ 357201360Srdivacky#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ 358201360Srdivacky#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ 359201360Srdivacky#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ 360201360Srdivacky#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ 361195098Sed#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ 362194612Sed#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ 363198090Srdivacky#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ 364198892Srdivacky#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ 365201360Srdivacky#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ 366201360Srdivacky#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ 367202375Srdivacky 368201360Srdivacky/* PCI_CFG_REG_1 32 bit Config Register 1 */ 369201360Srdivacky#define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ 370201360Srdivacky /* Bit 23..21: Release Clock on Event */ 371201360Srdivacky#define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ 372194612Sed#define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ 373194612Sed#define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ 374199989Srdivacky /* Bit 20..18: Gate Clock on Event */ 375204642Srdivacky#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ 376199989Srdivacky#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ 377195098Sed#define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ 378204642Srdivacky#define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 379204642Srdivacky#define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ 380194754Sed 381198090Srdivacky#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ 382198892Srdivacky#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ 383195098Sed#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ 384204642Srdivacky 385201360Srdivacky/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 386201360Srdivacky#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 387201360Srdivacky#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 388201360Srdivacky#define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 389201360Srdivacky#define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 390201360Srdivacky#define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 391195098Sed#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 392198090Srdivacky#define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 393198892Srdivacky#define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 394195098Sed#define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 395204642Srdivacky#define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 396195098Sed#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 397201360Srdivacky 398201360Srdivacky#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 399201360Srdivacky 400201360Srdivacky/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 401201360Srdivacky#define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 402201360Srdivacky#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 403201360Srdivacky#define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 404195098Sed#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 405194754Sed#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 406198090Srdivacky 407198892Srdivacky/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 408195098Sed#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 409204642Srdivacky#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 410201360Srdivacky#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 411201360Srdivacky#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 412201360Srdivacky#define PEX_COMP_TO BIT_14 /* Completion Timeout */ 413201360Srdivacky#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 414201360Srdivacky#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 415204642Srdivacky#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 416204642Srdivacky 417204642Srdivacky#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 418204642Srdivacky 419204642Srdivacky/* Control Register File (Address Map) */ 420204642Srdivacky 421195098Sed/* 422204642Srdivacky * Bank 0 423204642Srdivacky */ 424204642Srdivacky#define B0_RAP 0x0000 /* 8 bit Register Address Port */ 425204642Srdivacky#define B0_CTST 0x0004 /* 16 bit Control/Status register */ 426201360Srdivacky#define B0_LED 0x0006 /* 8 Bit LED register */ 427201360Srdivacky#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 428201360Srdivacky#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 429201360Srdivacky#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 430201360Srdivacky#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 431201360Srdivacky#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 432195098Sed#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 433204642Srdivacky 434204642Srdivacky/* Special ISR registers (Yukon-2 only) */ 435204642Srdivacky#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 436204642Srdivacky#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 437201360Srdivacky#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 438201360Srdivacky#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 439201360Srdivacky#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 440201360Srdivacky 441201360Srdivacky/* 442201360Srdivacky * Bank 1 443201360Srdivacky * - completely empty (this is the RAP Block window) 444201360Srdivacky * Note: if RAP = 1 this page is reserved 445195098Sed */ 446195098Sed 447204642Srdivacky/* 448204642Srdivacky * Bank 2 449204642Srdivacky */ 450204642Srdivacky/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 451201360Srdivacky#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 452201360Srdivacky#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 453201360Srdivacky#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 454201360Srdivacky#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 455195098Sed#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 456194754Sed#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 457195098Sed#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 458204642Srdivacky#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 459194754Sed#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 460198090Srdivacky#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 461195098Sed#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 462201360Srdivacky#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 463194754Sed#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 464208599Srdivacky#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 465208599Srdivacky#define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 466208599Srdivacky#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 467201360Srdivacky#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 468201360Srdivacky#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 469201360Srdivacky#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 470201360Srdivacky#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 471201360Srdivacky#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 472201360Srdivacky#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 473194612Sed#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 474208599Srdivacky#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 475208599Srdivacky#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 476208599Srdivacky#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 477201360Srdivacky#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 478201360Srdivacky#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 479201360Srdivacky#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 480201360Srdivacky 481201360Srdivacky#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 482194612Sed#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 483194612Sed 484194612Sed/* 485195098Sed * Bank 3 486195098Sed */ 487201360Srdivacky/* RAM Random Registers */ 488195098Sed#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 489198090Srdivacky#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 490198892Srdivacky#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 491201360Srdivacky 492201360Srdivacky#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 493201360Srdivacky 494201360Srdivacky/* RAM Interface Registers */ 495201360Srdivacky/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 496201360Srdivacky/* 497195098Sed * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 498198090Srdivacky * not usable in SW. Please notice these are NOT real timeouts, these are 499198892Srdivacky * the number of qWords transferred continuously. 500201360Srdivacky */ 501201360Srdivacky#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 502201360Srdivacky#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 503201360Srdivacky#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 504201360Srdivacky#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 505201360Srdivacky#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 506201360Srdivacky#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 507195098Sed#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 508194754Sed#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 509201360Srdivacky#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 510195098Sed#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 511194754Sed#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 512198090Srdivacky#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 513201360Srdivacky#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 514194754Sed#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 515198090Srdivacky#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 516198892Srdivacky 517201360Srdivacky/* 518201360Srdivacky * Bank 4 - 5 519201360Srdivacky */ 520201360Srdivacky/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 521201360Srdivacky#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 522201360Srdivacky#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 523201360Srdivacky#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 524201360Srdivacky#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 525195098Sed#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 526198090Srdivacky#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 527198892Srdivacky#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 528201360Srdivacky 529201360Srdivacky#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 530201360Srdivacky 531201360Srdivacky/* RSS key registers for Yukon-2 Family */ 532201360Srdivacky#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 533201360Srdivacky/* RSS key register offsets */ 534201360Srdivacky#define KEY_IDX_0 0 /* offset for location of KEY 0 */ 535201360Srdivacky#define KEY_IDX_1 4 /* offset for location of KEY 1 */ 536201360Srdivacky#define KEY_IDX_2 8 /* offset for location of KEY 2 */ 537201360Srdivacky#define KEY_IDX_3 12 /* offset for location of KEY 3 */ 538194754Sed /* 0x0280 - 0x0292: MAC 2 */ 539198090Srdivacky#define RSS_KEY_ADDR(Port, KeyIndex) \ 540198892Srdivacky ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 541201360Srdivacky 542201360Srdivacky/* 543201360Srdivacky * Bank 8 - 15 544201360Srdivacky */ 545201360Srdivacky/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 546201360Srdivacky#define B8_Q_REGS 0x0400 547201360Srdivacky 548194754Sed/* Queue Register Offsets, use Q_ADDR() to access */ 549194754Sed#define Q_D 0x00 /* 8*32 bit Current Descriptor */ 550194754Sed#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 551195340Sed#define Q_DONE 0x24 /* 16 bit Done Index */ 552201360Srdivacky#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 553198090Srdivacky#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 554198892Srdivacky#define Q_BC 0x30 /* 32 bit Current Byte Counter */ 555201360Srdivacky#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 556201360Srdivacky#define Q_F 0x38 /* 32 bit Flag Register */ 557201360Srdivacky#define Q_T1 0x3c /* 32 bit Test Register 1 */ 558201360Srdivacky#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 559201360Srdivacky#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 560201360Srdivacky#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 561201360Srdivacky#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 562201360Srdivacky#define Q_WM 0x40 /* 16 bit FIFO Watermark */ 563198090Srdivacky#define Q_AL 0x42 /* 8 bit FIFO Alignment */ 564198892Srdivacky#define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 565201360Srdivacky#define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 566201360Srdivacky#define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 567201360Srdivacky#define Q_RL 0x4a /* 8 bit FIFO Read Level */ 568201360Srdivacky#define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 569201360Srdivacky#define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 570201360Srdivacky#define Q_WL 0x4e /* 8 bit FIFO Write Level */ 571201360Srdivacky#define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 572201360Srdivacky 573201360Srdivacky#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 574201360Srdivacky 575201360Srdivacky/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 576201360Srdivacky#define Y2_B8_PREF_REGS 0x0450 577198090Srdivacky 578198892Srdivacky#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 579201360Srdivacky#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 580201360Srdivacky#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 581201360Srdivacky#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 582201360Srdivacky#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 583201360Srdivacky#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 584201360Srdivacky#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 585201360Srdivacky#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 586201360Srdivacky#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 587201360Srdivacky#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 588198090Srdivacky 589198892Srdivacky#define PREF_UNIT_MASK_IDX 0x0fff 590198892Srdivacky 591198892Srdivacky#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 592201360Srdivacky 593201360Srdivacky/* 594201360Srdivacky * Bank 16 - 23 595201360Srdivacky */ 596201360Srdivacky/* RAM Buffer Registers */ 597201360Srdivacky#define B16_RAM_REGS 0x0800 598201360Srdivacky 599198892Srdivacky/* RAM Buffer Register Offsets, use RB_ADDR() to access */ 600195340Sed#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 601195340Sed#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 602195340Sed#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 603201360Srdivacky#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 604198090Srdivacky#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 605198892Srdivacky#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 606201360Srdivacky#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 607201360Srdivacky#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 608201360Srdivacky#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 609201360Srdivacky#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 610201360Srdivacky#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 611201360Srdivacky#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 612198090Srdivacky#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 613198892Srdivacky 614201360Srdivacky/* 615201360Srdivacky * Bank 24 616201360Srdivacky */ 617201360Srdivacky/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 618201360Srdivacky#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 619201360Srdivacky#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 620201360Srdivacky#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 621201360Srdivacky#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 622201360Srdivacky#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 623201360Srdivacky#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 624198090Srdivacky#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ 625198892Srdivacky#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ 626201360Srdivacky#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 627201360Srdivacky#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 628201360Srdivacky#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 629201360Srdivacky#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 630201360Srdivacky#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 631201360Srdivacky 632201360Srdivacky/* 633195340Sed * Bank 25 634195340Sed */ 635195340Sed /* 0x0c80 - 0x0cbf: MAC 2 */ 636195340Sed /* 0x0cc0 - 0x0cff: reserved */ 637201360Srdivacky 638198090Srdivacky/* 639198892Srdivacky * Bank 26 640208599Srdivacky */ 641208599Srdivacky/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 642201360Srdivacky#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 643201360Srdivacky#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 644201360Srdivacky#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 645201360Srdivacky#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 646201360Srdivacky#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 647201360Srdivacky#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 648201360Srdivacky#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 649201360Srdivacky#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 650198090Srdivacky#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 651198892Srdivacky#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 652208599Srdivacky 653208599Srdivacky/* 654201360Srdivacky * Bank 27 655201360Srdivacky */ 656201360Srdivacky /* 0x0d80 - 0x0dbf: MAC 2 */ 657201360Srdivacky /* 0x0daa - 0x0dff: reserved */ 658201360Srdivacky 659201360Srdivacky/* 660201360Srdivacky * Bank 28 661201360Srdivacky */ 662195340Sed/* Descriptor Poll Timer Registers */ 663195340Sed#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 664204792Srdivacky#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 665204792Srdivacky#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 666204792Srdivacky#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 667204792Srdivacky/* Time Stamp Timer Registers (YUKON only) */ 668208599Srdivacky#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 669208599Srdivacky#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 670204792Srdivacky#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 671204792Srdivacky/* Polling Unit Registers (Yukon-2 only) */ 672204792Srdivacky#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 673204792Srdivacky#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 674204792Srdivacky#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 675204792Srdivacky#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 676204792Srdivacky/* ASF Subsystem Registers (Yukon-2 only) */ 677204792Srdivacky#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 678204792Srdivacky#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 679204792Srdivacky#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 680208599Srdivacky#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 681208599Srdivacky#define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ 682204792Srdivacky#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 683204792Srdivacky#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 684204792Srdivacky#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 685204792Srdivacky#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 686204792Srdivacky#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 687204792Srdivacky 688204792Srdivacky/* 689204792Srdivacky * Bank 29 690204792Srdivacky */ 691204792Srdivacky 692204642Srdivacky/* Status BMU Registers (Yukon-2 only)*/ 693204642Srdivacky#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 694204642Srdivacky#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 695204642Srdivacky#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 696204642Srdivacky#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 697204642Srdivacky#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 698204642Srdivacky#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 699204642Srdivacky#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 700204642Srdivacky#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 701204642Srdivacky#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 702204642Srdivacky#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 703204642Srdivacky/* FIFO Control/Status Registers (Yukon-2 only)*/ 704204642Srdivacky#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 705204642Srdivacky#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 706204642Srdivacky#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 707204642Srdivacky#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 708204642Srdivacky#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 709204642Srdivacky#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 710204642Srdivacky#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 711204642Srdivacky/* Level and ISR Timer Registers (Yukon-2 only)*/ 712204642Srdivacky#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 713204642Srdivacky#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 714204642Srdivacky#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 715204642Srdivacky#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 716204642Srdivacky#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 717195340Sed#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 718195340Sed#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 719201360Srdivacky#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 720198090Srdivacky#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 721198892Srdivacky#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 722208599Srdivacky#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 723208599Srdivacky#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 724201360Srdivacky 725201360Srdivacky#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 726201360Srdivacky#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 727201360Srdivacky#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 728201360Srdivacky#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 729201360Srdivacky 730201360Srdivacky/* 731195340Sed * Bank 30 732198892Srdivacky */ 733195340Sed/* GMAC and GPHY Control Registers (YUKON only) */ 734208599Srdivacky#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 735208599Srdivacky#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 736201360Srdivacky#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 737201360Srdivacky#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 738201360Srdivacky#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 739201360Srdivacky 740201360Srdivacky/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 741201360Srdivacky 742201360Srdivacky#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 743195340Sed 744195340Sed#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 745204642Srdivacky#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 746204642Srdivacky#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 747204642Srdivacky#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 748204642Srdivacky#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 749204642Srdivacky#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 750204642Srdivacky#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 751204642Srdivacky#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 752204642Srdivacky 753204642Srdivacky/* WOL Pattern Length Registers (YUKON only) */ 754204642Srdivacky 755204642Srdivacky#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 756204642Srdivacky#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 757204642Srdivacky 758204642Srdivacky/* WOL Pattern Counter Registers (YUKON only) */ 759204642Srdivacky 760204642Srdivacky#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 761204642Srdivacky#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 762204642Srdivacky 763204642Srdivacky/* 764204642Srdivacky * Bank 32 - 33 765204642Srdivacky */ 766204642Srdivacky#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 767204642Srdivacky#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 768194612Sed 769195098Sed/* offset to configuration space on Yukon-2 */ 770195098Sed#define Y2_CFG_SPC 0x1c00 771195098Sed#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 772195098Sed#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 773195098Sed 774194612Sed/* 775194612Sed * Control Register Bit Definitions: 776195098Sed */ 777195098Sed/* B0_CTST 24 bit Control/Status register */ 778208599Srdivacky#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 779208599Srdivacky#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 780198090Srdivacky#define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 781201360Srdivacky#define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 782201360Srdivacky#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 783201360Srdivacky#define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 784201360Srdivacky#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 785201360Srdivacky#define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 786201360Srdivacky#define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 787201360Srdivacky#define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 788201360Srdivacky#define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 789201360Srdivacky#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 790195098Sed#define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 791198090Srdivacky#define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 792201360Srdivacky#define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 793201360Srdivacky#define CS_MRST_SET BIT_2 /* Set Master Reset */ 794201360Srdivacky#define CS_RST_CLR BIT_1 /* Clear Software Reset */ 795201360Srdivacky#define CS_RST_SET BIT_0 /* Set Software Reset */ 796201360Srdivacky 797201360Srdivacky#define LED_STAT_ON BIT_1 /* Status LED On */ 798201360Srdivacky#define LED_STAT_OFF BIT_0 /* Status LED Off */ 799201360Srdivacky 800201360Srdivacky/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 801208599Srdivacky#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 802195098Sed#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 803198090Srdivacky#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 804198090Srdivacky#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 805201360Srdivacky#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 806201360Srdivacky#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 807201360Srdivacky#define PC_VCC_ON BIT_1 /* Switch VCC On */ 808201360Srdivacky#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 809201360Srdivacky 810201360Srdivacky/* B0_ISRC 32 bit Interrupt Source Register */ 811201360Srdivacky/* B0_IMSK 32 bit Interrupt Mask Register */ 812201360Srdivacky/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 813204642Srdivacky/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 814201360Srdivacky/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 815201360Srdivacky/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 816201360Srdivacky/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 817201360Srdivacky/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 818201360Srdivacky#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 819201360Srdivacky#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 820201360Srdivacky#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 821201360Srdivacky#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 822195098Sed#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 823198090Srdivacky#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 824198090Srdivacky#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 825201360Srdivacky#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 826201360Srdivacky#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 827201360Srdivacky#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 828201360Srdivacky#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 829201360Srdivacky#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 830201360Srdivacky#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 831201360Srdivacky#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 832201360Srdivacky#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 833195098Sed#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 834198090Srdivacky#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 835198090Srdivacky#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 836201360Srdivacky 837201360Srdivacky#define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 838201360Srdivacky 839201360Srdivacky#define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 840201360Srdivacky 841201360Srdivacky#define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 842201360Srdivacky 843201360Srdivacky#define Y2_IS_PORT_A \ 844198090Srdivacky (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 845201360Srdivacky#define Y2_IS_PORT_B \ 846201360Srdivacky (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 847201360Srdivacky 848201360Srdivacky/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 849201360Srdivacky/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 850201360Srdivacky/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 851201360Srdivacky#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 852201360Srdivacky#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 853195098Sed#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 854198090Srdivacky#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 855198090Srdivacky#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 856198090Srdivacky#define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 857201360Srdivacky#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 858201360Srdivacky#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 859201360Srdivacky#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 860201360Srdivacky#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 861201360Srdivacky#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 862201360Srdivacky#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 863201360Srdivacky#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 864201360Srdivacky#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 865195098Sed#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 866208599Srdivacky#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 867204642Srdivacky#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 868208599Srdivacky#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 869208599Srdivacky 870208599Srdivacky#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 871204642Srdivacky Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 872204642Srdivacky#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 873204642Srdivacky Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 874204642Srdivacky 875204642Srdivacky#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 876204642Srdivacky Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 877204642Srdivacky Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 878204642Srdivacky 879208599Srdivacky/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 880208599Srdivacky#define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 881208599Srdivacky#define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 882204642Srdivacky#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 883204642Srdivacky 884204642Srdivacky/* B2_CHIP_ID 8 bit Chip Identification Number */ 885204642Srdivacky#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 886204642Srdivacky#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 887204642Srdivacky#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 888204642Srdivacky#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 889198090Srdivacky#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 890198892Srdivacky#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 891198090Srdivacky#define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ 892208599Srdivacky#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 893198090Srdivacky#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 894208599Srdivacky#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ 895198090Srdivacky#define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ 896208599Srdivacky#define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ 897198892Srdivacky 898198090Srdivacky#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 899198090Srdivacky#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 900194612Sed#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 901195098Sed#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 902195098Sed 903195098Sed#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 904195340Sed#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 905204642Srdivacky#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 906201360Srdivacky 907195340Sed#define CHIP_REV_YU_EC_U_A0 1 908195340Sed#define CHIP_REV_YU_EC_U_A1 2 909201360Srdivacky 910201360Srdivacky#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ 911195340Sed 912195340Sed#define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ 913201360Srdivacky#define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ 914201360Srdivacky 915195340Sed/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 916208599Srdivacky#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 917195340Sed#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 918201360Srdivacky#define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 919198090Srdivacky#define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 920198892Srdivacky#define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 921205218Srdivacky#define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 922198090Srdivacky#define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 923201360Srdivacky#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 924201360Srdivacky 925195340Sed/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 926208599Srdivacky#define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 927195340Sed#define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 928195340Sed#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 929195340Sed 930195340Sed#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 931195340Sed#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 932195340Sed 933195340Sed/* B2_E_3 8 bit lower 4 bits used for HW self test result */ 934195340Sed#define B2_E3_RES_MASK 0x0f 935195340Sed 936195340Sed/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 937195340Sed/* Yukon-EC/FE */ 938195340Sed#define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 939195340Sed#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 940195340Sed/* Yukon-2 */ 941195340Sed#define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 942195340Sed#define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 943195340Sed#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 944195340Sed#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 945195340Sed#define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 946195340Sed#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 947195340Sed 948195340Sed/* B2_TI_CTRL 8 bit Timer control */ 949195340Sed/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 950195340Sed#define TIM_START BIT_2 /* Start Timer */ 951195340Sed#define TIM_STOP BIT_1 /* Stop Timer */ 952195340Sed#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 953195340Sed 954195340Sed/* B2_TI_TEST 8 Bit Timer Test */ 955195340Sed/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 956195340Sed/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 957195340Sed#define TIM_T_ON BIT_2 /* Test mode on */ 958195340Sed#define TIM_T_OFF BIT_1 /* Test mode off */ 959195340Sed#define TIM_T_STEP BIT_0 /* Test step */ 960195340Sed 961195340Sed/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 962195340Sed/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 963195340Sed#define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 964195340Sed 965195340Sed/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 966195340Sed#define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 967195340Sed#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 968195340Sed 969208599Srdivacky/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 970201360Srdivacky#define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 971195340Sed#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 972198090Srdivacky#define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 973198892Srdivacky#define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 974195340Sed#define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 975195340Sed#define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 976201360Srdivacky#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 977195340Sed#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 978198090Srdivacky 979198892Srdivacky/* B2_GP_IO */ 980195340Sed#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ 981195340Sed#define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ 982201360Srdivacky 983195340Sed#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ 984198090Srdivacky#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ 985198892Srdivacky#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ 986195340Sed#define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ 987201360Srdivacky#define GLB_GPIO_TEST_SEL_BASE BIT_11 988195340Sed#define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ 989198090Srdivacky#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ 990198892Srdivacky 991195340Sed/* B2_I2C_CTRL 32 bit I2C HW Control Register */ 992195340Sed#define I2C_FLAG BIT_31 /* Start read/write if WR */ 993201360Srdivacky#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 994195340Sed#define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 995198090Srdivacky#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 996198892Srdivacky#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 997195340Sed#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 998201360Srdivacky#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 999195340Sed#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 1000198090Srdivacky#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 1001198892Srdivacky#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 1002195340Sed#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 1003195340Sed#define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 1004201360Srdivacky#define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 1005195340Sed#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 1006198090Srdivacky 1007198892Srdivacky/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 1008195340Sed#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 1009201360Srdivacky 1010195340Sed/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 1011198090Srdivacky#define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 1012198892Srdivacky#define I2C_DATA BIT_1 /* I2C Data Port */ 1013195340Sed#define I2C_CLK BIT_0 /* I2C Clock Port */ 1014195340Sed 1015201360Srdivacky/* I2C Address */ 1016195340Sed#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 1017198090Srdivacky 1018198892Srdivacky 1019195340Sed/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 1020201360Srdivacky#define BSC_START BIT_1 /* Start Blink Source Counter */ 1021195340Sed#define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 1022198090Srdivacky 1023198892Srdivacky/* B2_BSC_STAT 8 bit Blink Source Counter Status */ 1024195340Sed#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 1025208599Srdivacky 1026195340Sed/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 1027204792Srdivacky#define BSC_T_ON BIT_2 /* Test mode on */ 1028204792Srdivacky#define BSC_T_OFF BIT_1 /* Test mode off */ 1029204792Srdivacky#define BSC_T_STEP BIT_0 /* Test step */ 1030204792Srdivacky 1031204792Srdivacky/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 1032204792Srdivacky#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 1033204792Srdivacky#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 1034204792Srdivacky 1035204792Srdivacky/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 1036204792Srdivacky#define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 1037204792Srdivacky 1038204792Srdivacky/* RAM Interface Registers */ 1039204792Srdivacky/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 1040204792Srdivacky#define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 1041204792Srdivacky#define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 1042204792Srdivacky#define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 1043204792Srdivacky#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 1044204792Srdivacky 1045204792Srdivacky#define MSK_RI_TO_53 36 /* RAM interface timeout */ 1046204792Srdivacky 1047204792Srdivacky/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 1048204792Srdivacky/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 1049195340Sed/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 1050204642Srdivacky/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 1051204642Srdivacky/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 1052204642Srdivacky#define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 1053195340Sed 1054195340Sed/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 1055208599Srdivacky#define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 1056201360Srdivacky#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 1057198090Srdivacky#define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 1058198892Srdivacky#define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 1059195340Sed#define TXA_START_RC BIT_3 /* Start sync Rate Control */ 1060195340Sed#define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 1061201360Srdivacky#define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 1062195340Sed#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 1063198090Srdivacky 1064198892Srdivacky/* TXA_TEST 8 bit Tx Arbiter Test Register */ 1065195340Sed#define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 1066195340Sed#define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 1067195340Sed#define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 1068201360Srdivacky#define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 1069195340Sed#define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 1070198090Srdivacky#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 1071198892Srdivacky 1072195340Sed/* TXA_STAT 8 bit Tx Arbiter Status Register */ 1073199989Srdivacky#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 1074195340Sed 1075201360Srdivacky/* Q_BC 32 bit Current Byte Counter */ 1076195340Sed#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 1077198090Srdivacky 1078198892Srdivacky/* Rx BMU Control / Status Registers (Yukon-2) */ 1079195340Sed#define BMU_IDLE BIT_31 /* BMU Idle State */ 1080195340Sed#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 1081195340Sed#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 1082201360Srdivacky#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 1083195340Sed#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 1084198090Srdivacky#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 1085198892Srdivacky#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 1086195340Sed#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 1087195340Sed#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 1088195340Sed#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 1089201360Srdivacky#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 1090195340Sed#define BMU_START BIT_8 /* Start Rx/Tx Queue */ 1091198090Srdivacky#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 1092198892Srdivacky#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 1093195340Sed#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 1094195340Sed#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 1095195340Sed#define BMU_OP_ON BIT_3 /* BMU Operational On */ 1096201360Srdivacky#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 1097195340Sed#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 1098198090Srdivacky#define BMU_RST_SET BIT_0 /* Set BMU Reset */ 1099198892Srdivacky 1100195340Sed#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 1101195340Sed#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 1102195340Sed BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 1103204792Srdivacky 1104204792Srdivacky/* Tx BMU Control / Status Registers (Yukon-2) */ 1105204792Srdivacky /* Bit 31: same as for Rx */ 1106204792Srdivacky#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 1107204792Srdivacky#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 1108204792Srdivacky#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 1109204792Srdivacky /* Bit 10..0: same as for Rx */ 1110204792Srdivacky 1111204792Srdivacky/* Q_F 32 bit Flag Register */ 1112204792Srdivacky#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ 1113204792Srdivacky#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ 1114204792Srdivacky#define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ 1115204792Srdivacky#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 1116204792Srdivacky#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 1117204792Srdivacky#define F_WM_REACHED BIT_25 /* Watermark reached */ 1118195340Sed#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1119204792Srdivacky#define F_FIFO_LEVEL (0x1f<<16) 1120204792Srdivacky /* Bit 23..16: # of Qwords in FIFO */ 1121204792Srdivacky#define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ 1122204792Srdivacky 1123205218Srdivacky/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 1124205218Srdivacky/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 1125195340Sed#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 1126205218Srdivacky#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 1127205218Srdivacky#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 1128205218Srdivacky#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 1129205218Srdivacky 1130205218Srdivacky/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 1131205218Srdivacky/* RB_START 32 bit RAM Buffer Start Address */ 1132205218Srdivacky/* RB_END 32 bit RAM Buffer End Address */ 1133205218Srdivacky/* RB_WP 32 bit RAM Buffer Write Pointer */ 1134205218Srdivacky/* RB_RP 32 bit RAM Buffer Read Pointer */ 1135205218Srdivacky/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 1136205218Srdivacky/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 1137205218Srdivacky/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 1138205218Srdivacky/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 1139205218Srdivacky/* RB_PC 32 bit RAM Buffer Packet Counter */ 1140205218Srdivacky/* RB_LEV 32 bit RAM Buffer Level Register */ 1141205218Srdivacky#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 1142204792Srdivacky 1143204792Srdivacky/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 1144205218Srdivacky#define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 1145205218Srdivacky#define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 1146205218Srdivacky#define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 1147204792Srdivacky#define RB_PC_INC BIT_0 /* Packet Counter Increment */ 1148204792Srdivacky 1149205218Srdivacky/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 1150205218Srdivacky#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 1151204792Srdivacky#define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 1152204792Srdivacky#define RB_WP_INC BIT_4 /* Write Pointer Increment */ 1153204792Srdivacky#define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 1154204792Srdivacky#define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 1155204792Srdivacky#define RB_RP_INC BIT_0 /* Read Pointer Increment */ 1156204792Srdivacky 1157204792Srdivacky/* RB_CTRL 8 bit RAM Buffer Control Register */ 1158204792Srdivacky#define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 1159204792Srdivacky#define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 1160205218Srdivacky#define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 1161205218Srdivacky#define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 1162204792Srdivacky#define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 1163204792Srdivacky#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 1164204792Srdivacky 1165204792Srdivacky/* RAM Buffer High Pause Threshold values */ 1166204792Srdivacky#define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 1167204792Srdivacky#define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 1168204792Srdivacky#define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 1169204792Srdivacky 1170204792Srdivacky/* Threshold values for Yukon-EC Ultra */ 1171204792Srdivacky#define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 1172205218Srdivacky#define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1173205218Srdivacky#define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ 1174204792Srdivacky#define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1175204792Srdivacky#define MSK_ECU_JUMBO_WM 0x01 1176204792Srdivacky 1177204792Srdivacky#define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 1178204792Srdivacky#define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 1179204792Srdivacky/* performance sensitive drivers should set this define to 0x80 */ 1180204792Srdivacky#define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 1181204792Srdivacky 1182204792Srdivacky/* Receive and Transmit Queues */ 1183204792Srdivacky#define Q_R1 0x0000 /* Receive Queue 1 */ 1184204792Srdivacky#define Q_R2 0x0080 /* Receive Queue 2 */ 1185204792Srdivacky#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 1186204792Srdivacky#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 1187204792Srdivacky#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 1188204792Srdivacky#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 1189204792Srdivacky 1190204792Srdivacky#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 1191204792Srdivacky#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 1192204792Srdivacky#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 1193204792Srdivacky#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 1194204792Srdivacky 1195204792Srdivacky#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 1196204792Srdivacky 1197204792Srdivacky/* Minimum RAM Buffer Rx Queue Size */ 1198204792Srdivacky#define MSK_MIN_RXQ_SIZE 10 1199204792Srdivacky/* Minimum RAM Buffer Tx Queue Size */ 1200204792Srdivacky#define MSK_MIN_TXQ_SIZE 10 1201204792Srdivacky/* Percentage of queue size from whole memory. 80 % for receive */ 1202204792Srdivacky#define MSK_RAM_QUOTA_RX 80 1203204792Srdivacky 1204204792Srdivacky/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1205204792Srdivacky#define WOL_CTL_LINK_CHG_OCC BIT_15 1206204792Srdivacky#define WOL_CTL_MAGIC_PKT_OCC BIT_14 1207204792Srdivacky#define WOL_CTL_PATTERN_OCC BIT_13 1208204792Srdivacky#define WOL_CTL_CLEAR_RESULT BIT_12 1209204792Srdivacky#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 1210204792Srdivacky#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 1211204792Srdivacky#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 1212204792Srdivacky#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 1213204792Srdivacky#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 1214195098Sed#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 1215195340Sed#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 1216195340Sed#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 1217195340Sed#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 1218208599Srdivacky#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 1219205218Srdivacky#define WOL_CTL_ENA_PATTERN_UNIT BIT_1 1220205218Srdivacky#define WOL_CTL_DIS_PATTERN_UNIT BIT_0 1221205218Srdivacky 1222201360Srdivacky#define WOL_CTL_DEFAULT \ 1223201360Srdivacky (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1224201360Srdivacky WOL_CTL_DIS_PME_ON_PATTERN | \ 1225201360Srdivacky WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1226205218Srdivacky WOL_CTL_DIS_LINK_CHG_UNIT | \ 1227201360Srdivacky WOL_CTL_DIS_PATTERN_UNIT | \ 1228201360Srdivacky WOL_CTL_DIS_MAGIC_PKT_UNIT) 1229195340Sed 1230205218Srdivacky/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 1231205218Srdivacky#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 1232205407Srdivacky 1233205218Srdivacky/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 1234201360Srdivacky#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 1235201360Srdivacky#define WOL_PATT_MATCH_PME_ALL 0x7f 1236201360Srdivacky 1237201360Srdivacky 1238205218Srdivacky/* 1239205218Srdivacky * Marvel-PHY Registers, indirect addressed over GMAC 1240205218Srdivacky */ 1241208599Srdivacky#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 1242205218Srdivacky#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 1243208599Srdivacky#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 1244205218Srdivacky#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 1245205218Srdivacky#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 1246205218Srdivacky#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 1247205218Srdivacky#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 1248205218Srdivacky#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 1249205218Srdivacky#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 1250205218Srdivacky /* Marvel-specific registers */ 1251205218Srdivacky#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 1252201360Srdivacky#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 1253201360Srdivacky /* 0x0b - 0x0e: reserved */ 1254195340Sed#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 1255205218Srdivacky#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 1256205218Srdivacky#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 1257205218Srdivacky#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 1258205407Srdivacky#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 1259205218Srdivacky#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 1260205218Srdivacky#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 1261205218Srdivacky#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 1262205218Srdivacky#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1263205218Srdivacky#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 1264205218Srdivacky#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 1265205218Srdivacky#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1266205218Srdivacky#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1267208599Srdivacky#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 1268205218Srdivacky#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 1269195340Sed#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 1270194612Sed 1271194612Sed/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1272194612Sed#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 1273194754Sed#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 1274198090Srdivacky#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 1275201360Srdivacky#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 1276201360Srdivacky#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 1277201360Srdivacky 1278201360Srdivacky#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 1279201360Srdivacky#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 1280201360Srdivacky#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 1281201360Srdivacky#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 1282201360Srdivacky#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 1283201360Srdivacky#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 1284194612Sed#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 1285198090Srdivacky#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 1286198090Srdivacky#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 1287198090Srdivacky#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 1288198892Srdivacky 1289201360Srdivacky#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 1290201360Srdivacky#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 1291201360Srdivacky#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 1292201360Srdivacky 1293201360Srdivacky#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 1294201360Srdivacky#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 1295201360Srdivacky#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 1296201360Srdivacky#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ 1297195098Sed#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 1298195098Sed#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 1299198090Srdivacky#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 1300198892Srdivacky#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 1301201360Srdivacky 1302201360Srdivacky#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 1303201360Srdivacky#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 1304201360Srdivacky#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 1305201360Srdivacky 1306201360Srdivacky/* different Marvell PHY Ids */ 1307201360Srdivacky#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 1308194612Sed 1309194754Sed#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 1310198090Srdivacky#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 1311198892Srdivacky#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 1312198090Srdivacky#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 1313201360Srdivacky#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1314201360Srdivacky#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 1315201360Srdivacky 1316201360Srdivacky/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1317201360Srdivacky#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1318201360Srdivacky#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1319201360Srdivacky#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1320194754Sed#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 1321198396Srdivacky#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1322198396Srdivacky#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1323194612Sed#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1324195340Sed 1325195340Sed/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 1326195340Sed/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1327195340Sed#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 1328195340Sed#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1329201360Srdivacky#define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1330201360Srdivacky#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1331201360Srdivacky#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1332201360Srdivacky#define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 1333204642Srdivacky#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1334195340Sed#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1335201360Srdivacky#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 1336195340Sed#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1337201360Srdivacky#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 1338195340Sed 1339204642Srdivacky/* special defines for FIBER (88E1011S only) */ 1340195340Sed#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1341204642Srdivacky#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1342195340Sed#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1343195340Sed#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1344195340Sed 1345195340Sed/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1346201360Srdivacky#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1347201360Srdivacky#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1348201360Srdivacky#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1349201360Srdivacky#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1350204792Srdivacky 1351201360Srdivacky/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1352195340Sed#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1353195340Sed#define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 1354195340Sed#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 1355195340Sed#define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 1356195340Sed#define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 1357195340Sed#define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 1358201360Srdivacky 1359199989Srdivacky/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1360201360Srdivacky#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 1361199989Srdivacky#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 1362204642Srdivacky#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 1363195340Sed#define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 1364195340Sed#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1365195340Sed#define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 1366194612Sed#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 1367194612Sed#define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 1368194612Sed#define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 1369201360Srdivacky#define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 1370201360Srdivacky#define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 1371201360Srdivacky#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 1372201360Srdivacky 1373194612Sed#define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 1374194754Sed#define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 1375201360Srdivacky 1376201360Srdivacky#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 1377201360Srdivacky 1378201360Srdivacky#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 1379194612Sed#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 1380201360Srdivacky#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1381204642Srdivacky 1382201360Srdivacky/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1383204642Srdivacky#define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 1384204642Srdivacky#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 1385204642Srdivacky#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 1386204642Srdivacky /* !!! Errata in spec. (1 = disable) */ 1387204642Srdivacky 1388194612Sed#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 1389198090Srdivacky /* 000=1x; 001=2x; 010=3x; 011=4x */ 1390201360Srdivacky /* 100=5x; 101=6x; 110=7x; 111=8x */ 1391201360Srdivacky 1392201360Srdivacky/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1393201360Srdivacky#define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 1394194612Sed#define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 1395194754Sed#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 1396198090Srdivacky#define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 1397198090Srdivacky#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 1398198090Srdivacky#define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 1399195098Sed#define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 1400195098Sed#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 1401195098Sed#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 1402195098Sed 1403194612Sed/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1404204642Srdivacky#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 1405194754Sed#define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 1406204642Srdivacky#define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 1407204642Srdivacky#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1408204642Srdivacky#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 1409204642Srdivacky#define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 1410204642Srdivacky#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 1411204642Srdivacky#define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 1412204642Srdivacky#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 1413204642Srdivacky#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 1414204642Srdivacky#define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 1415204642Srdivacky#define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 1416204642Srdivacky#define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 1417204642Srdivacky#define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 1418204642Srdivacky#define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 1419204642Srdivacky#define PHY_M_PS_JABBER BIT_0 /* Jabber */ 1420204642Srdivacky 1421204642Srdivacky#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1422204642Srdivacky 1423204642Srdivacky/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1424204642Srdivacky#define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 1425204642Srdivacky#define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1426204642Srdivacky 1427204642Srdivacky/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 1428204642Srdivacky/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 1429204642Srdivacky#define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 1430204642Srdivacky#define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 1431204642Srdivacky#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 1432204642Srdivacky#define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 1433204642Srdivacky#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 1434204642Srdivacky#define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 1435204642Srdivacky#define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 1436204642Srdivacky#define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 1437204642Srdivacky#define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 1438204642Srdivacky#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 1439204642Srdivacky#define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 1440204642Srdivacky#define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 1441204642Srdivacky#define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 1442204642Srdivacky#define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 1443204642Srdivacky#define PHY_M_IS_JABBER BIT_0 /* Jabber */ 1444204642Srdivacky 1445204642Srdivacky#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 1446204642Srdivacky PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 1447204642Srdivacky 1448204642Srdivacky/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1449204642Srdivacky#define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 1450204642Srdivacky#define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 1451204642Srdivacky#define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 1452204642Srdivacky#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 1453204642Srdivacky /* (88E1011 only) */ 1454204642Srdivacky#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 1455204642Srdivacky /* (88E1011 only) */ 1456204642Srdivacky#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 1457204642Srdivacky /* (88E1111 only) */ 1458204642Srdivacky#define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 1459204642Srdivacky /* !!! Errata in spec. (1 = disable) */ 1460204642Srdivacky#define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 1461204642Srdivacky#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1462204642Srdivacky#define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 1463204642Srdivacky#define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 1464204642Srdivacky#define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 1465204642Srdivacky#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 1466204642Srdivacky 1467204642Srdivacky#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 1468204642Srdivacky /* 00=1x; 01=2x; 10=3x; 11=4x */ 1469204642Srdivacky#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 1470204642Srdivacky /* 00=dis; 01=1x; 10=2x; 11=3x */ 1471204642Srdivacky#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 1472204642Srdivacky /* 01X=0; 110=2.5; 111=25 (MHz) */ 1473204642Srdivacky 1474204642Srdivacky#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 1475204642Srdivacky /* 000=1x; 001=2x; 010=3x; 011=4x */ 1476204642Srdivacky /* 100=5x; 101=6x; 110=7x; 111=8x */ 1477204642Srdivacky#define MAC_TX_CLK_0_MHZ 2 1478204642Srdivacky#define MAC_TX_CLK_2_5_MHZ 6 1479204642Srdivacky#define MAC_TX_CLK_25_MHZ 7 1480204642Srdivacky 1481204642Srdivacky/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1482204642Srdivacky#define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 1483204642Srdivacky#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 1484204642Srdivacky#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 1485204642Srdivacky#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 1486204642Srdivacky#define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 1487204642Srdivacky#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 1488204642Srdivacky#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 1489204642Srdivacky /* (88E1111 only) */ 1490204642Srdivacky#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1491204642Srdivacky /* (88E1011 only) */ 1492204642Srdivacky#define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 1493204642Srdivacky#define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 1494204642Srdivacky#define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 1495204642Srdivacky#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 1496204642Srdivacky#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 1497204642Srdivacky 1498204642Srdivacky#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 1499204642Srdivacky 1500204642Srdivacky#define PULS_NO_STR 0 /* no pulse stretching */ 1501204642Srdivacky#define PULS_21MS 1 /* 21 ms to 42 ms */ 1502204642Srdivacky#define PULS_42MS 2 /* 42 ms to 84 ms */ 1503204642Srdivacky#define PULS_84MS 3 /* 84 ms to 170 ms */ 1504204642Srdivacky#define PULS_170MS 4 /* 170 ms to 340 ms */ 1505204642Srdivacky#define PULS_340MS 5 /* 340 ms to 670 ms */ 1506204642Srdivacky#define PULS_670MS 6 /* 670 ms to 1.3 s */ 1507204642Srdivacky#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 1508204642Srdivacky 1509204642Srdivacky#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 1510204642Srdivacky 1511204642Srdivacky#define BLINK_42MS 0 /* 42 ms */ 1512204642Srdivacky#define BLINK_84MS 1 /* 84 ms */ 1513204642Srdivacky#define BLINK_170MS 2 /* 170 ms */ 1514204642Srdivacky#define BLINK_340MS 3 /* 340 ms */ 1515204642Srdivacky#define BLINK_670MS 4 /* 670 ms */ 1516204642Srdivacky 1517204642Srdivacky/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1518204642Srdivacky#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 1519204642Srdivacky#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 1520204642Srdivacky#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1521204642Srdivacky#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 1522204642Srdivacky#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 1523204642Srdivacky#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 1524204642Srdivacky#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1525204642Srdivacky 1526204642Srdivacky#define MO_LED_NORM 0 1527204642Srdivacky#define MO_LED_BLINK 1 1528204642Srdivacky#define MO_LED_OFF 2 1529204642Srdivacky#define MO_LED_ON 3 1530204642Srdivacky 1531204642Srdivacky/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1532204642Srdivacky#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 1533204642Srdivacky#define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 1534204642Srdivacky#define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 1535204642Srdivacky#define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 1536204642Srdivacky#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 1537204642Srdivacky 1538204642Srdivacky/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1539204642Srdivacky#define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 1540204642Srdivacky#define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 1541204642Srdivacky#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 1542204642Srdivacky#define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 1543204642Srdivacky#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 1544204642Srdivacky#define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 1545204642Srdivacky#define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 1546204642Srdivacky /* (88E1111 only) */ 1547204642Srdivacky#define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 1548204642Srdivacky#define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 1549204642Srdivacky#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1550204642Srdivacky 1551204642Srdivacky/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 1552204642Srdivacky#define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 1553204642Srdivacky#define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 1554194754Sed /* (88E1111 only) */ 1555195098Sed#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 1556195098Sed#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 1557195098Sed /* (88E1111 only) */ 1558201360Srdivacky#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 1559201360Srdivacky 1560201360Srdivacky/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 1561201360Srdivacky#define CABD_STAT_NORMAL 0 1562195098Sed#define CABD_STAT_SHORT 1 1563198090Srdivacky#define CABD_STAT_OPEN 2 1564198090Srdivacky#define CABD_STAT_FAIL 3 1565198892Srdivacky 1566201360Srdivacky/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1567201360Srdivacky/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1568201360Srdivacky#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 1569201360Srdivacky#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 1570201360Srdivacky#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 1571201360Srdivacky 1572201360Srdivacky#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 1573201360Srdivacky#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 1574198090Srdivacky#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 1575201360Srdivacky 1576195098Sed#define LED_PAR_CTRL_COLX 0x00 1577198090Srdivacky#define LED_PAR_CTRL_ERROR 0x01 1578208599Srdivacky#define LED_PAR_CTRL_DUPLEX 0x02 1579208599Srdivacky#define LED_PAR_CTRL_DP_COL 0x03 1580208599Srdivacky#define LED_PAR_CTRL_SPEED 0x04 1581201360Srdivacky#define LED_PAR_CTRL_LINK 0x05 1582201360Srdivacky#define LED_PAR_CTRL_TX 0x06 1583201360Srdivacky#define LED_PAR_CTRL_RX 0x07 1584201360Srdivacky#define LED_PAR_CTRL_ACT 0x08 1585201360Srdivacky#define LED_PAR_CTRL_LNK_RX 0x09 1586201360Srdivacky#define LED_PAR_CTRL_LNK_AC 0x0a 1587201360Srdivacky#define LED_PAR_CTRL_ACT_BL 0x0b 1588201360Srdivacky#define LED_PAR_CTRL_TX_BL 0x0c 1589201360Srdivacky#define LED_PAR_CTRL_RX_BL 0x0d 1590201360Srdivacky#define LED_PAR_CTRL_COL_BL 0x0e 1591208599Srdivacky#define LED_PAR_CTRL_INACT 0x0f 1592208599Srdivacky 1593208599Srdivacky/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1594201360Srdivacky#define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 1595201360Srdivacky#define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 1596201360Srdivacky#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 1597201360Srdivacky 1598201360Srdivacky/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1599201360Srdivacky/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1600201360Srdivacky#define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 1601201360Srdivacky#define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 1602201360Srdivacky#define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 1603198090Srdivacky 1604201360Srdivacky/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1605198090Srdivacky#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 1606195098Sed#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 1607194754Sed#define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 1608194754Sed#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 1609194754Sed#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 1610201360Srdivacky 1611201360Srdivacky/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1612201360Srdivacky#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 1613201360Srdivacky#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1614201360Srdivacky#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1615201360Srdivacky#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1616194754Sed 1617201360Srdivacky#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 1618201360Srdivacky#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 1619194754Sed#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 1620198090Srdivacky#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 1621198090Srdivacky 1622198892Srdivacky/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 1623201360Srdivacky#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1624201360Srdivacky#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1625201360Srdivacky#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1626201360Srdivacky#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1627201360Srdivacky#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1628201360Srdivacky#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1629201360Srdivacky 1630194754Sed#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 1631198090Srdivacky#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 1632201360Srdivacky#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 1633201360Srdivacky#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 1634201360Srdivacky#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 1635201360Srdivacky#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 1636201360Srdivacky 1637201360Srdivacky/* 1638198090Srdivacky * GMAC registers 1639198090Srdivacky * 1640201360Srdivacky * The GMAC registers are 16 or 32 bits wide. 1641201360Srdivacky * The GMACs host processor interface is 16 bits wide, 1642201360Srdivacky * therefore ALL registers will be addressed with 16 bit accesses. 1643201360Srdivacky * 1644201360Srdivacky * Note: NA reg = Network Address e.g DA, SA etc. 1645201360Srdivacky */ 1646198090Srdivacky 1647203954Srdivacky/* Port Registers */ 1648203954Srdivacky#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 1649203954Srdivacky#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1650203954Srdivacky#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1651203954Srdivacky#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1652203954Srdivacky#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1653203954Srdivacky#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1654203954Srdivacky#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1655203954Srdivacky 1656203954Srdivacky/* Source Address Registers */ 1657198090Srdivacky#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1658201360Srdivacky#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 1659201360Srdivacky#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 1660194754Sed#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 1661195098Sed#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 1662195098Sed#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 1663201360Srdivacky 1664194754Sed/* Multicast Address Hash Registers */ 1665198090Srdivacky#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 1666198090Srdivacky#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 1667198090Srdivacky#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 1668198090Srdivacky#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 1669198090Srdivacky 1670198090Srdivacky/* Interrupt Source Registers */ 1671198090Srdivacky#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 1672198090Srdivacky#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 1673198090Srdivacky#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1674195098Sed 1675195098Sed/* Interrupt Mask Registers */ 1676194754Sed#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 1677194754Sed#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 1678194754Sed#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1679194754Sed 1680195098Sed/* Serial Management Interface (SMI) Registers */ 1681198090Srdivacky#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1682198892Srdivacky#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1683201360Srdivacky#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1684201360Srdivacky 1685201360Srdivacky/* MIB Counters */ 1686201360Srdivacky#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1687201360Srdivacky#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1688201360Srdivacky 1689201360Srdivacky/* 1690194754Sed * MIB Counters base address definitions (low word) - 1691198090Srdivacky * use offset 4 for access to high word (32 bit r/o) 1692198892Srdivacky */ 1693201360Srdivacky#define GM_RXF_UC_OK \ 1694201360Srdivacky (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1695201360Srdivacky#define GM_RXF_BC_OK \ 1696201360Srdivacky (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1697201360Srdivacky#define GM_RXF_MPAUSE \ 1698201360Srdivacky (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1699201360Srdivacky#define GM_RXF_MC_OK \ 1700194754Sed (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 1701198090Srdivacky#define GM_RXF_FCS_ERR \ 1702198892Srdivacky (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 1703201360Srdivacky#define GM_RXF_SPARE1 \ 1704201360Srdivacky (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ 1705201360Srdivacky#define GM_RXO_OK_LO \ 1706201360Srdivacky (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1707201360Srdivacky#define GM_RXO_OK_HI \ 1708201360Srdivacky (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 1709201360Srdivacky#define GM_RXO_ERR_LO \ 1710194754Sed (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 1711198090Srdivacky#define GM_RXO_ERR_HI \ 1712198090Srdivacky (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 1713198090Srdivacky#define GM_RXF_SHT \ 1714198090Srdivacky (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 1715201360Srdivacky#define GM_RXE_FRAG \ 1716201360Srdivacky (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 1717201360Srdivacky#define GM_RXF_64B \ 1718201360Srdivacky (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 1719201360Srdivacky#define GM_RXF_127B \ 1720201360Srdivacky (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 1721194754Sed#define GM_RXF_255B \ 1722198090Srdivacky (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 1723201360Srdivacky#define GM_RXF_511B \ 1724201360Srdivacky (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 1725201360Srdivacky#define GM_RXF_1023B \ 1726201360Srdivacky (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1727201360Srdivacky#define GM_RXF_1518B \ 1728198090Srdivacky (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 1729201360Srdivacky#define GM_RXF_MAX_SZ \ 1730198090Srdivacky (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1731198090Srdivacky#define GM_RXF_LNG_ERR \ 1732198090Srdivacky (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 1733201360Srdivacky#define GM_RXF_JAB_PKT \ 1734201360Srdivacky (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 1735201360Srdivacky#define GM_RXF_SPARE2 \ 1736201360Srdivacky (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ 1737201360Srdivacky#define GM_RXE_FIFO_OV \ 1738201360Srdivacky (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1739198090Srdivacky#define GM_RXF_SPARE3 \ 1740198090Srdivacky (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ 1741201360Srdivacky#define GM_TXF_UC_OK \ 1742201360Srdivacky (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1743201360Srdivacky#define GM_TXF_BC_OK \ 1744201360Srdivacky (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1745201360Srdivacky#define GM_TXF_MPAUSE \ 1746201360Srdivacky (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1747198090Srdivacky#define GM_TXF_MC_OK \ 1748198090Srdivacky (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1749201360Srdivacky#define GM_TXO_OK_LO \ 1750201360Srdivacky (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1751201360Srdivacky#define GM_TXO_OK_HI \ 1752201360Srdivacky (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1753201360Srdivacky#define GM_TXF_64B \ 1754201360Srdivacky (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1755198090Srdivacky#define GM_TXF_127B \ 1756198090Srdivacky (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1757204642Srdivacky#define GM_TXF_255B \ 1758204642Srdivacky (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1759198090Srdivacky#define GM_TXF_511B \ 1760198090Srdivacky (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1761198892Srdivacky#define GM_TXF_1023B \ 1762201360Srdivacky (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1763201360Srdivacky#define GM_TXF_1518B \ 1764201360Srdivacky (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1765201360Srdivacky#define GM_TXF_MAX_SZ \ 1766201360Srdivacky (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1767201360Srdivacky#define GM_TXF_SPARE1 \ 1768201360Srdivacky (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ 1769198090Srdivacky#define GM_TXF_COL \ 1770204642Srdivacky (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1771204642Srdivacky#define GM_TXF_LAT_COL \ 1772204642Srdivacky (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1773204642Srdivacky#define GM_TXF_ABO_COL \ 1774204642Srdivacky (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1775204642Srdivacky#define GM_TXF_MUL_COL \ 1776204642Srdivacky (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1777204642Srdivacky#define GM_TXF_SNG_COL \ 1778204642Srdivacky (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1779198090Srdivacky#define GM_TXE_FIFO_UR \ 1780198892Srdivacky (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1781201360Srdivacky 1782201360Srdivacky/*----------------------------------------------------------------------------*/ 1783201360Srdivacky/* 1784201360Srdivacky * GMAC Bit Definitions 1785201360Srdivacky * 1786201360Srdivacky * If the bit access behaviour differs from the register access behaviour 1787201360Srdivacky * (r/w, r/o) this is documented after the bit number. 1788198090Srdivacky * The following bit access behaviours are used: 1789204642Srdivacky * (sc) self clearing 1790204642Srdivacky * (r/o) read only 1791204642Srdivacky */ 1792204642Srdivacky 1793204642Srdivacky/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1794204642Srdivacky#define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 1795204642Srdivacky#define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 1796204642Srdivacky#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 1797198090Srdivacky#define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 1798198090Srdivacky#define GM_GPSR_PAUSE BIT_11 /* Pause State */ 1799198892Srdivacky#define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1800201360Srdivacky#define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occured */ 1801201360Srdivacky#define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occured */ 1802201360Srdivacky#define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 1803201360Srdivacky#define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 1804201360Srdivacky#define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 1805201360Srdivacky#define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 1806201360Srdivacky 1807198090Srdivacky/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1808204642Srdivacky#define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 1809204642Srdivacky#define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 1810204642Srdivacky#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 1811204642Srdivacky#define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 1812204642Srdivacky#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 1813204642Srdivacky#define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 1814204642Srdivacky#define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 1815204642Srdivacky#define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 1816204642Srdivacky#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 1817198090Srdivacky#define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 1818198090Srdivacky#define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 1819198892Srdivacky#define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 1820198090Srdivacky#define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 1821201360Srdivacky#define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 1822201360Srdivacky#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 1823201360Srdivacky 1824201360Srdivacky#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1825201360Srdivacky#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1826201360Srdivacky GM_GPCR_AU_SPD_DIS) 1827201360Srdivacky 1828201360Srdivacky/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1829198090Srdivacky#define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 1830198090Srdivacky#define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 1831198892Srdivacky#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 1832198090Srdivacky#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 1833201360Srdivacky#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 1834201360Srdivacky /* (Yukon-2 only) */ 1835201360Srdivacky 1836201360Srdivacky#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1837201360Srdivacky#define TX_COL_DEF 0x04 1838201360Srdivacky 1839201360Srdivacky/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1840201360Srdivacky#define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 1841198090Srdivacky#define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 1842198090Srdivacky#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 1843198892Srdivacky#define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 1844198090Srdivacky 1845201360Srdivacky/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1846201360Srdivacky#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 1847201360Srdivacky#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 1848201360Srdivacky#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 1849201360Srdivacky#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 1850201360Srdivacky /* (Yukon-2 only) */ 1851201360Srdivacky 1852201360Srdivacky#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1853198090Srdivacky#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1854198090Srdivacky#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1855198892Srdivacky#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1856198090Srdivacky 1857201360Srdivacky#define TX_JAM_LEN_DEF 0x03 1858201360Srdivacky#define TX_JAM_IPG_DEF 0x0b 1859201360Srdivacky#define TX_IPG_JAM_DEF 0x1c 1860201360Srdivacky#define TX_BOF_LIM_DEF 0x04 1861201360Srdivacky 1862201360Srdivacky/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1863201360Srdivacky#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 1864201360Srdivacky /* r/o on Yukon, r/w on Yukon-EC */ 1865198090Srdivacky#define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 1866198090Srdivacky#define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 1867198892Srdivacky#define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 1868198090Srdivacky#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 1869201360Srdivacky 1870201360Srdivacky#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1871201360Srdivacky#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 1872201360Srdivacky 1873201360Srdivacky#define DATA_BLIND_DEF 0x04 1874201360Srdivacky#define IPG_DATA_DEF 0x1e 1875201360Srdivacky 1876201360Srdivacky/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1877198090Srdivacky#define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1878198090Srdivacky#define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1879198892Srdivacky#define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 1880198090Srdivacky#define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 1881201360Srdivacky#define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 1882201360Srdivacky 1883201360Srdivacky#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1884201360Srdivacky#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1885201360Srdivacky 1886201360Srdivacky/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1887201360Srdivacky#define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 1888201360Srdivacky#define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 1889198090Srdivacky 1890198090Srdivacky/* Receive Frame Status Encoding */ 1891198090Srdivacky#define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 1892198090Srdivacky#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 1893198090Srdivacky#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 1894198892Srdivacky#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 1895198090Srdivacky#define GMR_FS_MC BIT_10 /* Multicast Packet */ 1896198090Srdivacky#define GMR_FS_BC BIT_9 /* Broadcast Packet */ 1897201360Srdivacky#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 1898201360Srdivacky#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 1899201360Srdivacky#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 1900201360Srdivacky#define GMR_FS_MII_ERR BIT_5 /* MII Error */ 1901201360Srdivacky#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 1902201360Srdivacky#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 1903201360Srdivacky#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 1904201360Srdivacky#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 1905198090Srdivacky 1906198090Srdivacky#define GMR_FS_LEN_SHIFT 16 1907198892Srdivacky 1908198090Srdivacky#define GMR_FS_ANY_ERR ( \ 1909204642Srdivacky GMR_FS_RX_FF_OV | \ 1910201360Srdivacky GMR_FS_CRC_ERR | \ 1911201360Srdivacky GMR_FS_FRAGMENT | \ 1912201360Srdivacky GMR_FS_LONG_ERR | \ 1913201360Srdivacky GMR_FS_MII_ERR | \ 1914201360Srdivacky GMR_FS_BAD_FC | \ 1915201360Srdivacky GMR_FS_GOOD_FC | \ 1916201360Srdivacky GMR_FS_UN_SIZE | \ 1917198090Srdivacky GMR_FS_JABBER) 1918198090Srdivacky 1919198892Srdivacky/* Rx GMAC FIFO Flush Mask (default) */ 1920198090Srdivacky#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 1921201360Srdivacky 1922201360Srdivacky/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 1923201360Srdivacky 1924201360Srdivacky/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 1925201360Srdivacky/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 1926201360Srdivacky/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 1927201360Srdivacky/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 1928201360Srdivacky/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 1929198090Srdivacky/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 1930198090Srdivacky/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 1931198892Srdivacky/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 1932198090Srdivacky/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 1933204642Srdivacky/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 1934201360Srdivacky/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 1935201360Srdivacky/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 1936201360Srdivacky/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 1937201360Srdivacky/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 1938201360Srdivacky 1939201360Srdivacky/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1940201360Srdivacky#define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 1941198090Srdivacky#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 1942198090Srdivacky#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 1943198892Srdivacky#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 1944198090Srdivacky#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ 1945204642Srdivacky#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ 1946201360Srdivacky#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ 1947201360Srdivacky#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ 1948201360Srdivacky#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 1949201360Srdivacky#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 1950201360Srdivacky#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 1951201360Srdivacky#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 1952201360Srdivacky#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 1953198090Srdivacky#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 1954198090Srdivacky#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 1955198892Srdivacky#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 1956198090Srdivacky#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 1957204642Srdivacky#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 1958201360Srdivacky#define GMF_OPER_ON BIT_3 /* Operational Mode On */ 1959201360Srdivacky#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 1960201360Srdivacky#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 1961201360Srdivacky#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 1962201360Srdivacky 1963201360Srdivacky/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 1964201360Srdivacky#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 1965198090Srdivacky#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 1966198090Srdivacky#define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 1967198090Srdivacky#define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1968198090Srdivacky#define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ 1969198090Srdivacky#define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ 1970204642Srdivacky#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 1971204642Srdivacky#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 1972204642Srdivacky#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 1973204642Srdivacky /* Bits 15..8: same as for RX_GMF_CTRL_T */ 1974204642Srdivacky#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 1975204642Srdivacky#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 1976204642Srdivacky#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 1977204642Srdivacky /* Bits 3..0: same as for RX_GMF_CTRL_T */ 1978204642Srdivacky 1979204642Srdivacky#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 1980204642Srdivacky#define GMF_TX_CTRL_DEF GMF_OPER_ON 1981204642Srdivacky 1982204642Srdivacky#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 1983198090Srdivacky#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 1984204642Srdivacky 1985204642Srdivacky/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1986198090Srdivacky#define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 1987204642Srdivacky#define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 1988204642Srdivacky#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 1989204642Srdivacky 1990204642Srdivacky/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 1991204642Srdivacky#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 1992204642Srdivacky#define PC_POLL_RQ BIT_4 /* Poll Request Start */ 1993204642Srdivacky#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 1994204642Srdivacky#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 1995204642Srdivacky#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 1996204642Srdivacky#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 1997204642Srdivacky 1998204642Srdivacky/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1999204642Srdivacky/* This register is used by the host driver software */ 2000204642Srdivacky#define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 2001204642Srdivacky#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 2002204642Srdivacky#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 2003204642Srdivacky#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 2004204642Srdivacky#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 2005204642Srdivacky 2006204642Srdivacky#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 2007204642Srdivacky#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 2008204642Srdivacky 2009204642Srdivacky/* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */ 2010204642Srdivacky#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ 2011204642Srdivacky#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ 2012204642Srdivacky#define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ 2013204642Srdivacky#define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ 2014204642Srdivacky#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ 2015204642Srdivacky#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ 2016204642Srdivacky#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ 2017204642Srdivacky#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ 2018204642Srdivacky#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 2019204642Srdivacky#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 2020204642Srdivacky#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 2021204642Srdivacky#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ 2022204642Srdivacky#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 2023204642Srdivacky#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ 2024204642Srdivacky /* Microcontroller State */ 2025204642Srdivacky#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 2026204642Srdivacky#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 2027204642Srdivacky#define Y2_ASF_HCU_CCSR_ASF_RESET 0 2028194754Sed#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 2029194754Sed#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 2030194754Sed 2031194754Sed/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 2032204642Srdivacky/* This register is used by the ASF firmware */ 2033204642Srdivacky#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 2034201360Srdivacky#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 2035201360Srdivacky 2036201360Srdivacky/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 2037201360Srdivacky#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 2038201360Srdivacky#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 2039201360Srdivacky#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 2040201360Srdivacky#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 2041201360Srdivacky#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 2042194754Sed 2043201360Srdivacky/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2044201360Srdivacky#define GMC_SEC_RST BIT_15 /* MAC SEC RST */ 2045194754Sed#define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ 2046202878Srdivacky#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ 2047202878Srdivacky#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ 2048202878Srdivacky#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ 2049202878Srdivacky#define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ 2050201360Srdivacky#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ 2051201360Srdivacky#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ 2052201360Srdivacky#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 2053201360Srdivacky#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 2054201360Srdivacky#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 2055194754Sed#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 2056194754Sed#define GMC_PAUSE_ON BIT_3 /* Pause On */ 2057194754Sed#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 2058194754Sed#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 2059194754Sed#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 2060194754Sed 2061201360Srdivacky/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 2062201360Srdivacky#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 2063194754Sed#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 2064194754Sed#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 2065198090Srdivacky#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 2066194754Sed#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 2067194754Sed#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 2068198090Srdivacky#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 2069204642Srdivacky#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 2070198090Srdivacky#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 2071198090Srdivacky#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 2072208599Srdivacky#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 2073208599Srdivacky#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 2074201360Srdivacky#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 2075201360Srdivacky#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 2076201360Srdivacky#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 2077201360Srdivacky#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 2078201360Srdivacky#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 2079201360Srdivacky#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 2080194754Sed#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 2081198090Srdivacky#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 2082198090Srdivacky#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 2083208599Srdivacky#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 2084208599Srdivacky#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 2085198090Srdivacky 2086208599Srdivacky/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 2087208599Srdivacky/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 2088198090Srdivacky#define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 2089198090Srdivacky#define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 2090204642Srdivacky#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 2091198090Srdivacky#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 2092198090Srdivacky#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 2093208599Srdivacky#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 2094208599Srdivacky 2095201360Srdivacky#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 2096201360Srdivacky 2097201360Srdivacky/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 2098201360Srdivacky#define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 2099201360Srdivacky#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 2100201360Srdivacky 2101198090Srdivacky#define MSK_PORT_A 0 2102198090Srdivacky#define MSK_PORT_B 1 2103198090Srdivacky 2104198090Srdivacky/* Register access macros */ 2105208599Srdivacky#define CSR_WRITE_4(sc, reg, val) \ 2106208599Srdivacky bus_write_4((sc)->msk_res[0], (reg), (val)) 2107198090Srdivacky#define CSR_WRITE_2(sc, reg, val) \ 2108198090Srdivacky bus_write_2((sc)->msk_res[0], (reg), (val)) 2109208599Srdivacky#define CSR_WRITE_1(sc, reg, val) \ 2110208599Srdivacky bus_write_1((sc)->msk_res[0], (reg), (val)) 2111198090Srdivacky 2112194754Sed#define CSR_READ_4(sc, reg) \ 2113194754Sed bus_read_4((sc)->msk_res[0], (reg)) 2114194754Sed#define CSR_READ_2(sc, reg) \ 2115194754Sed bus_read_2((sc)->msk_res[0], (reg)) 2116201360Srdivacky#define CSR_READ_1(sc, reg) \ 2117201360Srdivacky bus_read_1((sc)->msk_res[0], (reg)) 2118201360Srdivacky 2119201360Srdivacky#define CSR_PCI_WRITE_4(sc, reg, val) \ 2120194754Sed bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2121202878Srdivacky#define CSR_PCI_WRITE_2(sc, reg, val) \ 2122202878Srdivacky bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2123202878Srdivacky#define CSR_PCI_WRITE_1(sc, reg, val) \ 2124202878Srdivacky bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2125201360Srdivacky 2126201360Srdivacky#define CSR_PCI_READ_4(sc, reg) \ 2127194754Sed bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2128202878Srdivacky#define CSR_PCI_READ_2(sc, reg) \ 2129202878Srdivacky bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2130194754Sed#define CSR_PCI_READ_1(sc, reg) \ 2131195340Sed bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2132202878Srdivacky 2133194754Sed#define MSK_IF_READ_4(sc_if, reg) \ 2134201360Srdivacky CSR_READ_4((sc_if)->msk_softc, (reg)) 2135201360Srdivacky#define MSK_IF_READ_2(sc_if, reg) \ 2136201360Srdivacky CSR_READ_2((sc_if)->msk_softc, (reg)) 2137201360Srdivacky#define MSK_IF_READ_1(sc_if, reg) \ 2138194754Sed CSR_READ_1((sc_if)->msk_softc, (reg)) 2139194754Sed 2140194754Sed#define MSK_IF_WRITE_4(sc_if, reg, val) \ 2141194754Sed CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 2142194754Sed#define MSK_IF_WRITE_2(sc_if, reg, val) \ 2143194754Sed CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 2144198090Srdivacky#define MSK_IF_WRITE_1(sc_if, reg, val) \ 2145198090Srdivacky CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 2146204642Srdivacky 2147208599Srdivacky#define GMAC_REG(port, reg) \ 2148198090Srdivacky ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 2149198892Srdivacky#define GMAC_WRITE_2(sc, port, reg, val) \ 2150198090Srdivacky CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 2151201360Srdivacky#define GMAC_READ_2(sc, port, reg) \ 2152201360Srdivacky CSR_READ_2((sc), GMAC_REG((port), (reg))) 2153201360Srdivacky 2154201360Srdivacky/* GPHY address (bits 15..11 of SMI control reg) */ 2155201360Srdivacky#define PHY_ADDR_MARV 0 2156201360Srdivacky 2157201360Srdivacky#define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 2158201360Srdivacky#define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 2159201360Srdivacky 2160198090Srdivacky/* 2161198090Srdivacky * At first I guessed 8 bytes, the size of a single descriptor, would be 2162198892Srdivacky * required alignment constraints. But, it seems that Yukon II have 4096 2163198090Srdivacky * bytes boundary alignment constraints. 2164201360Srdivacky */ 2165201360Srdivacky#define MSK_RING_ALIGN 4096 2166201360Srdivacky#define MSK_STAT_ALIGN 4096 2167201360Srdivacky 2168201360Srdivacky/* Rx descriptor data structure */ 2169201360Srdivackystruct msk_rx_desc { 2170201360Srdivacky uint32_t msk_addr; 2171201360Srdivacky uint32_t msk_control; 2172198090Srdivacky}; 2173201360Srdivacky 2174201360Srdivacky/* Tx descriptor data structure */ 2175201360Srdivackystruct msk_tx_desc { 2176201360Srdivacky uint32_t msk_addr; 2177201360Srdivacky uint32_t msk_control; 2178201360Srdivacky}; 2179201360Srdivacky 2180201360Srdivacky/* Status descriptor data structure */ 2181201360Srdivackystruct msk_stat_desc { 2182201360Srdivacky uint32_t msk_status; 2183201360Srdivacky uint32_t msk_control; 2184201360Srdivacky}; 2185201360Srdivacky 2186201360Srdivacky/* mask and shift value to get Tx async queue status for port 1 */ 2187201360Srdivacky#define STLE_TXA1_MSKL 0x00000fff 2188201360Srdivacky#define STLE_TXA1_SHIFTL 0 2189201360Srdivacky 2190201360Srdivacky/* mask and shift value to get Tx sync queue status for port 1 */ 2191201360Srdivacky#define STLE_TXS1_MSKL 0x00fff000 2192201360Srdivacky#define STLE_TXS1_SHIFTL 12 2193201360Srdivacky 2194201360Srdivacky/* mask and shift value to get Tx async queue status for port 2 */ 2195201360Srdivacky#define STLE_TXA2_MSKL 0xff000000 2196201360Srdivacky#define STLE_TXA2_SHIFTL 24 2197201360Srdivacky#define STLE_TXA2_MSKH 0x000f 2198201360Srdivacky/* this one shifts up */ 2199208599Srdivacky#define STLE_TXA2_SHIFTH 8 2200198090Srdivacky 2201195340Sed/* mask and shift value to get Tx sync queue status for port 2 */ 2202200581Srdivacky#define STLE_TXS2_MSKL 0x00000000 2203200581Srdivacky#define STLE_TXS2_SHIFTL 0 2204200581Srdivacky#define STLE_TXS2_MSKH 0xfff0 2205200581Srdivacky#define STLE_TXS2_SHIFTH 4 2206200581Srdivacky 2207200581Srdivacky/* YUKON-2 bit values */ 2208205218Srdivacky#define HW_OWNER 0x80000000 2209200581Srdivacky#define SW_OWNER 0x00000000 2210200581Srdivacky 2211200581Srdivacky#define PU_PUTIDX_VALID 0x10000000 2212201360Srdivacky 2213200581Srdivacky/* YUKON-2 Control flags */ 2214201360Srdivacky#define UDPTCP 0x00010000 2215200581Srdivacky#define CALSUM 0x00020000 2216200581Srdivacky#define WR_SUM 0x00040000 2217200581Srdivacky#define INIT_SUM 0x00080000 2218205218Srdivacky#define LOCK_SUM 0x00100000 2219200581Srdivacky#define INS_VLAN 0x00200000 2220200581Srdivacky#define FRC_STAT 0x00400000 2221200581Srdivacky#define EOP 0x00800000 2222201360Srdivacky 2223200581Srdivacky#define TX_LOCK 0x01000000 2224201360Srdivacky#define BUF_SEND 0x02000000 2225200581Srdivacky#define PACKET_SEND 0x04000000 2226200581Srdivacky 2227200581Srdivacky#define NO_WARNING 0x40000000 2228204642Srdivacky#define NO_UPDATE 0x80000000 2229204642Srdivacky 2230204642Srdivacky/* YUKON-2 Rx/Tx opcodes defines */ 2231204642Srdivacky#define OP_TCPWRITE 0x11000000 2232204642Srdivacky#define OP_TCPSTART 0x12000000 2233204642Srdivacky#define OP_TCPINIT 0x14000000 2234204642Srdivacky#define OP_TCPLCK 0x18000000 2235204642Srdivacky#define OP_TCPCHKSUM OP_TCPSTART 2236204642Srdivacky#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 2237204642Srdivacky#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 2238204642Srdivacky#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 2239204642Srdivacky#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 2240204642Srdivacky#define OP_ADDR64 0x21000000 2241204642Srdivacky#define OP_VLAN 0x22000000 2242204642Srdivacky#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 2243204642Srdivacky#define OP_LRGLEN 0x24000000 2244204642Srdivacky#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2245204642Srdivacky#define OP_MSS 0x28000000 2246204642Srdivacky#define OP_MSSVLAN (OP_MSS | OP_VLAN) 2247204642Srdivacky#define OP_BUFFER 0x40000000 2248204642Srdivacky#define OP_PACKET 0x41000000 2249204642Srdivacky#define OP_LARGESEND 0x43000000 2250204642Srdivacky 2251204642Srdivacky/* YUKON-2 STATUS opcodes defines */ 2252204642Srdivacky#define OP_RXSTAT 0x60000000 2253204642Srdivacky#define OP_RXTIMESTAMP 0x61000000 2254204642Srdivacky#define OP_RXVLAN 0x62000000 2255204642Srdivacky#define OP_RXCHKS 0x64000000 2256204642Srdivacky#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 2257204642Srdivacky#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 2258204642Srdivacky#define OP_RSS_HASH 0x65000000 2259204642Srdivacky#define OP_TXINDEXLE 0x68000000 2260204642Srdivacky 2261204642Srdivacky/* YUKON-2 SPECIAL opcodes defines */ 2262204642Srdivacky#define OP_PUTIDX 0x70000000 2263204642Srdivacky 2264204642Srdivacky#define STLE_OP_MASK 0xff000000 2265204642Srdivacky#define STLE_CSS_MASK 0x00ff0000 2266204642Srdivacky#define STLE_LEN_MASK 0x0000ffff 2267204642Srdivacky 2268204642Srdivacky/* CSS defined in status LE(valid for descriptor V2 format). */ 2269204642Srdivacky#define CSS_TCPUDP_CSUM_OK 0x00800000 2270204642Srdivacky#define CSS_UDP 0x00400000 2271204642Srdivacky#define CSS_TCP 0x00200000 2272204642Srdivacky#define CSS_IPFRAG 0x00100000 2273204642Srdivacky#define CSS_IPV6 0x00080000 2274204642Srdivacky#define CSS_IPV4_CSUM_OK 0x00040000 2275204642Srdivacky#define CSS_IPV4 0x00020000 2276204642Srdivacky#define CSS_PORT 0x00010000 2277204642Srdivacky 2278204642Srdivacky/* Descriptor Bit Definition */ 2279204642Srdivacky/* TxCtrl Transmit Buffer Control Field */ 2280204642Srdivacky/* RxCtrl Receive Buffer Control Field */ 2281204642Srdivacky#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 2282204642Srdivacky#define BMU_STF BIT_30 /* Start of Frame */ 2283204642Srdivacky#define BMU_EOF BIT_29 /* End of Frame */ 2284204642Srdivacky#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 2285204642Srdivacky#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 2286204642Srdivacky/* TxCtrl specific bits */ 2287204642Srdivacky#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 2288201360Srdivacky#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 2289201360Srdivacky#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 2290201360Srdivacky/* RxCtrl specific bits */ 2291201360Srdivacky#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 2292201360Srdivacky#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 2293201360Srdivacky#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 2294201360Srdivacky /* Bit 23..16: BMU Check Opcodes */ 2295201360Srdivacky#define BMU_CHECK (0x55<<16) /* Default BMU check */ 2296201360Srdivacky#define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 2297201360Srdivacky#define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 2298201360Srdivacky#define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 2299201360Srdivacky 2300201360Srdivacky#define MSK_TX_RING_CNT 256 2301201360Srdivacky#define MSK_RX_RING_CNT 256 2302201360Srdivacky#define MSK_RX_BUF_ALIGN 8 2303201360Srdivacky#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 2304201360Srdivacky#define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT)) 2305201360Srdivacky#define MSK_MAXTXSEGS 32 2306201360Srdivacky#define MSK_TSO_MAXSGSIZE 4096 2307201360Srdivacky#define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 2308201360Srdivacky 2309201360Srdivacky/* 2310200581Srdivacky * It seems that the hardware requires extra decriptors(LEs) to offload 2311201360Srdivacky * TCP/UDP checksum, VLAN hardware tag inserstion and TSO. 2312201360Srdivacky * 2313201360Srdivacky * 1 descriptor for TCP/UDP checksum offload. 2314201360Srdivacky * 1 descriptor VLAN hardware tag insertion. 2315201360Srdivacky * 1 descriptor for TSO(TCP Segmentation Offload) 2316201360Srdivacky * 1 descriptor for 64bits DMA : Not applicatable due to the use of 2317200581Srdivacky * BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation. 2318201360Srdivacky */ 2319201360Srdivacky#define MSK_RESERVED_TX_DESC_CNT 3 2320201360Srdivacky 2321201360Srdivacky/* 2322201360Srdivacky * Jumbo buffer stuff. Note that we must allocate more jumbo 2323201360Srdivacky * buffers than there are descriptors in the receive ring. This 2324201360Srdivacky * is because we don't know how long it will take for a packet 2325200581Srdivacky * to be released after we hand it off to the upper protocol 2326201360Srdivacky * layers. To be safe, we allocate 1.5 times the number of 2327201360Srdivacky * receive descriptors. 2328201360Srdivacky */ 2329201360Srdivacky#define MSK_JUMBO_FRAMELEN 9022 2330201360Srdivacky#define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2331200581Srdivacky#define MSK_MAX_FRAMELEN \ 2332201360Srdivacky (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 2333201360Srdivacky#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 2334201360Srdivacky 2335201360Srdivackystruct msk_txdesc { 2336201360Srdivacky struct mbuf *tx_m; 2337201360Srdivacky bus_dmamap_t tx_dmamap; 2338201360Srdivacky struct msk_tx_desc *tx_le; 2339200581Srdivacky}; 2340201360Srdivacky 2341201360Srdivackystruct msk_rxdesc { 2342201360Srdivacky struct mbuf *rx_m; 2343201360Srdivacky bus_dmamap_t rx_dmamap; 2344201360Srdivacky struct msk_rx_desc *rx_le; 2345201360Srdivacky}; 2346200581Srdivacky 2347201360Srdivackystruct msk_chain_data { 2348201360Srdivacky bus_dma_tag_t msk_parent_tag; 2349201360Srdivacky bus_dma_tag_t msk_tx_tag; 2350201360Srdivacky struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 2351201360Srdivacky bus_dma_tag_t msk_rx_tag; 2352201360Srdivacky struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 2353200581Srdivacky bus_dma_tag_t msk_tx_ring_tag; 2354204642Srdivacky bus_dma_tag_t msk_rx_ring_tag; 2355204642Srdivacky bus_dmamap_t msk_tx_ring_map; 2356204642Srdivacky bus_dmamap_t msk_rx_ring_map; 2357204642Srdivacky bus_dmamap_t msk_rx_sparemap; 2358204642Srdivacky bus_dma_tag_t msk_jumbo_rx_tag; 2359204642Srdivacky struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 2360204642Srdivacky bus_dma_tag_t msk_jumbo_rx_ring_tag; 2361204642Srdivacky bus_dmamap_t msk_jumbo_rx_ring_map; 2362204642Srdivacky bus_dmamap_t msk_jumbo_rx_sparemap; 2363204642Srdivacky uint16_t msk_tso_mtu; 2364200581Srdivacky int msk_tx_prod; 2365198090Srdivacky int msk_tx_cons; 2366198090Srdivacky int msk_tx_cnt; 2367198090Srdivacky int msk_tx_put; 2368198090Srdivacky int msk_rx_cons; 2369198090Srdivacky int msk_rx_prod; 2370198090Srdivacky int msk_rx_putwm; 2371198090Srdivacky}; 2372198892Srdivacky 2373201360Srdivackystruct msk_ring_data { 2374201360Srdivacky struct msk_tx_desc *msk_tx_ring; 2375201360Srdivacky bus_addr_t msk_tx_ring_paddr; 2376201360Srdivacky struct msk_rx_desc *msk_rx_ring; 2377201360Srdivacky bus_addr_t msk_rx_ring_paddr; 2378198090Srdivacky struct msk_rx_desc *msk_jumbo_rx_ring; 2379198090Srdivacky bus_addr_t msk_jumbo_rx_ring_paddr; 2380198090Srdivacky}; 2381198090Srdivacky 2382198090Srdivacky#define MSK_TX_RING_ADDR(sc, i) \ 2383198090Srdivacky ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 2384198090Srdivacky#define MSK_RX_RING_ADDR(sc, i) \ 2385198090Srdivacky ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2386198090Srdivacky#define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 2387198090Srdivacky ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2388198090Srdivacky 2389198090Srdivacky#define MSK_TX_RING_SZ \ 2390198090Srdivacky (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 2391198090Srdivacky#define MSK_RX_RING_SZ \ 2392203954Srdivacky (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 2393203954Srdivacky#define MSK_JUMBO_RX_RING_SZ \ 2394198090Srdivacky (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 2395198090Srdivacky#define MSK_STAT_RING_SZ \ 2396198090Srdivacky (sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT) 2397198090Srdivacky 2398203954Srdivacky#define MSK_INC(x, y) (x) = (x + 1) % y 2399198090Srdivacky 2400208599Srdivacky#define MSK_PCI_BUS 0 2401203954Srdivacky#define MSK_PCIX_BUS 1 2402208599Srdivacky#define MSK_PEX_BUS 2 2403203954Srdivacky 2404198892Srdivacky#define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 2405198892Srdivacky#define MSK_PROC_MIN 30 2406208599Srdivacky#define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 2407198090Srdivacky 2408207618Srdivacky#define MSK_TX_TIMEOUT 5 2409207618Srdivacky#define MSK_PUT_WM 10 2410198090Srdivacky 2411198090Srdivackystruct msk_mii_data { 2412207618Srdivacky int port; 2413207618Srdivacky uint32_t pmd; 2414207618Srdivacky int mii_flags; 2415207618Srdivacky}; 2416208599Srdivacky 2417207618Srdivacky/* Forward decl. */ 2418208599Srdivackystruct msk_if_softc; 2419207618Srdivacky 2420207618Srdivackystruct msk_hw_stats { 2421207618Srdivacky /* Rx stats. */ 2422208599Srdivacky uint32_t rx_ucast_frames; 2423207618Srdivacky uint32_t rx_bcast_frames; 2424207618Srdivacky uint32_t rx_pause_frames; 2425207618Srdivacky uint32_t rx_mcast_frames; 2426207618Srdivacky uint32_t rx_crc_errs; 2427198090Srdivacky uint32_t rx_spare1; 2428198090Srdivacky uint64_t rx_good_octets; 2429198090Srdivacky uint64_t rx_bad_octets; 2430195340Sed uint32_t rx_runts; 2431195340Sed uint32_t rx_runt_errs; 2432194754Sed uint32_t rx_pkts_64; 2433198090Srdivacky uint32_t rx_pkts_65_127; 2434198090Srdivacky uint32_t rx_pkts_128_255; 2435198090Srdivacky uint32_t rx_pkts_256_511; 2436198090Srdivacky uint32_t rx_pkts_512_1023; 2437198090Srdivacky uint32_t rx_pkts_1024_1518; 2438198090Srdivacky uint32_t rx_pkts_1519_max; 2439205218Srdivacky uint32_t rx_pkts_too_long; 2440205218Srdivacky uint32_t rx_pkts_jabbers; 2441205218Srdivacky uint32_t rx_spare2; 2442205218Srdivacky uint32_t rx_fifo_oflows; 2443201360Srdivacky uint32_t rx_spare3; 2444201360Srdivacky /* Tx stats. */ 2445201360Srdivacky uint32_t tx_ucast_frames; 2446201360Srdivacky uint32_t tx_bcast_frames; 2447205218Srdivacky uint32_t tx_pause_frames; 2448201360Srdivacky uint32_t tx_mcast_frames; 2449201360Srdivacky uint64_t tx_octets; 2450198090Srdivacky uint32_t tx_pkts_64; 2451195340Sed uint32_t tx_pkts_65_127; 2452195340Sed uint32_t tx_pkts_128_255; 2453198090Srdivacky uint32_t tx_pkts_256_511; 2454198892Srdivacky uint32_t tx_pkts_512_1023; 2455201360Srdivacky uint32_t tx_pkts_1024_1518; 2456201360Srdivacky uint32_t tx_pkts_1519_max; 2457201360Srdivacky uint32_t tx_spare1; 2458201360Srdivacky uint32_t tx_colls; 2459201360Srdivacky uint32_t tx_late_colls; 2460195340Sed uint32_t tx_excess_colls; 2461195340Sed uint32_t tx_multi_colls; 2462198090Srdivacky uint32_t tx_single_colls; 2463198090Srdivacky uint32_t tx_underflows; 2464198090Srdivacky}; 2465198892Srdivacky 2466201360Srdivacky/* Softc for the Marvell Yukon II controller. */ 2467201360Srdivackystruct msk_softc { 2468201360Srdivacky struct resource *msk_res[1]; /* I/O resource */ 2469201360Srdivacky struct resource_spec *msk_res_spec; 2470201360Srdivacky struct resource *msk_irq[2]; /* IRQ resources */ 2471201360Srdivacky struct resource_spec *msk_irq_spec; 2472201360Srdivacky void *msk_intrhand[2]; /* irq handler handle */ 2473201360Srdivacky device_t msk_dev; 2474195340Sed uint8_t msk_hw_id; 2475198090Srdivacky uint8_t msk_hw_rev; 2476198090Srdivacky uint8_t msk_bustype; 2477195340Sed uint8_t msk_num_port; 2478198090Srdivacky int msk_ramsize; /* amount of SRAM on NIC */ 2479201360Srdivacky uint32_t msk_pmd; /* physical media type */ 2480201360Srdivacky uint32_t msk_intrmask; 2481201360Srdivacky uint32_t msk_intrhwemask; 2482201360Srdivacky uint32_t msk_pflags; 2483201360Srdivacky int msk_clock; 2484201360Srdivacky struct msk_if_softc *msk_if[2]; 2485201360Srdivacky device_t msk_devs[2]; 2486195340Sed int msk_txqsize; 2487198090Srdivacky int msk_rxqsize; 2488195340Sed int msk_txqstart[2]; 2489198090Srdivacky int msk_txqend[2]; 2490201360Srdivacky int msk_rxqstart[2]; 2491201360Srdivacky int msk_rxqend[2]; 2492201360Srdivacky bus_dma_tag_t msk_stat_tag; 2493201360Srdivacky bus_dmamap_t msk_stat_map; 2494201360Srdivacky struct msk_stat_desc *msk_stat_ring; 2495201360Srdivacky bus_addr_t msk_stat_ring_paddr; 2496201360Srdivacky int msk_process_limit; 2497204642Srdivacky int msk_stat_cons; 2498204642Srdivacky struct taskqueue *msk_tq; 2499204642Srdivacky struct task msk_int_task; 2500204642Srdivacky struct mtx msk_mtx; 2501204642Srdivacky}; 2502204642Srdivacky 2503204642Srdivacky#define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 2504204642Srdivacky#define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 2505204642Srdivacky#define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 2506204642Srdivacky#define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 2507204642Srdivacky#define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 2508204642Srdivacky#define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 2509204642Srdivacky 2510204642Srdivacky#define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 2511204642Srdivacky 2512204642Srdivacky/* Softc for each logical interface. */ 2513204642Srdivackystruct msk_if_softc { 2514204642Srdivacky struct ifnet *msk_ifp; /* interface info */ 2515198090Srdivacky device_t msk_miibus; 2516198090Srdivacky device_t msk_if_dev; 2517195340Sed int32_t msk_port; /* port # on controller */ 2518195340Sed int msk_framesize; 2519195340Sed int msk_phytype; 2520195340Sed int msk_phyaddr; 2521195340Sed uint32_t msk_flags; 2522198090Srdivacky#define MSK_FLAG_MSI 0x0001 2523198892Srdivacky#define MSK_FLAG_FASTETHER 0x0004 2524201360Srdivacky#define MSK_FLAG_JUMBO 0x0008 2525201360Srdivacky#define MSK_FLAG_JUMBO_NOCSUM 0x0010 2526201360Srdivacky#define MSK_FLAG_RAMBUF 0x0020 2527201360Srdivacky#define MSK_FLAG_DESCV2 0x0040 2528201360Srdivacky#define MSK_FLAG_AUTOTX_CSUM 0x0080 2529195340Sed#define MSK_FLAG_NOHWVLAN 0x0100 2530198090Srdivacky#define MSK_FLAG_NORXCHK 0x0200 2531198090Srdivacky#define MSK_FLAG_NORX_CSUM 0x0400 2532198090Srdivacky#define MSK_FLAG_SUSPEND 0x2000 2533198090Srdivacky#define MSK_FLAG_DETACH 0x4000 2534201360Srdivacky#define MSK_FLAG_LINK 0x8000 2535201360Srdivacky struct callout msk_tick_ch; 2536201360Srdivacky int msk_watchdog_timer; 2537201360Srdivacky uint32_t msk_txq; /* Tx. Async Queue offset */ 2538201360Srdivacky uint32_t msk_txsq; /* Tx. Syn Queue offset */ 2539198090Srdivacky uint32_t msk_rxq; /* Rx. Qeueue offset */ 2540204642Srdivacky struct msk_chain_data msk_cdata; 2541204642Srdivacky struct msk_ring_data msk_rdata; 2542204642Srdivacky struct msk_softc *msk_softc; /* parent controller */ 2543204642Srdivacky struct msk_hw_stats msk_stats; 2544204642Srdivacky struct task msk_tx_task; 2545204642Srdivacky int msk_if_flags; 2546204642Srdivacky uint16_t msk_vtag; /* VLAN tag id. */ 2547204642Srdivacky}; 2548204642Srdivacky 2549204642Srdivacky#define MSK_TIMEOUT 1000 2550204642Srdivacky#define MSK_PHY_POWERUP 1 2551204642Srdivacky#define MSK_PHY_POWERDOWN 0 2552204642Srdivacky