mpi2_cnfg.h revision 212420
1/* $FreeBSD: head/sys/dev/mps/mpi/mpi2_cnfg.h 212420 2010-09-10 15:03:56Z ken $ */ 2/* 3 * Copyright (c) 2000-2009 LSI Corporation. 4 * 5 * 6 * Name: mpi2_cnfg.h 7 * Title: MPI Configuration messages and pages 8 * Creation Date: November 10, 2006 9 * 10 * mpi2_cnfg.h Version: 02.00.13 11 * 12 * Version History 13 * --------------- 14 * 15 * Date Version Description 16 * -------- -------- ------------------------------------------------------ 17 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 18 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 19 * Added Manufacturing Page 11. 20 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 21 * define. 22 * 06-26-07 02.00.02 Adding generic structure for product-specific 23 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 24 * Rework of BIOS Page 2 configuration page. 25 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 26 * forms. 27 * Added configuration pages IOC Page 8 and Driver 28 * Persistent Mapping Page 0. 29 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 30 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 31 * RAID Physical Disk Pages 0 and 1, RAID Configuration 32 * Page 0). 33 * Added new value for AccessStatus field of SAS Device 34 * Page 0 (_SATA_NEEDS_INITIALIZATION). 35 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 36 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 37 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 38 * NVDATA. 39 * Modified IOC Page 7 to use masks and added field for 40 * SASBroadcastPrimitiveMasks. 41 * Added MPI2_CONFIG_PAGE_BIOS_4. 42 * Added MPI2_CONFIG_PAGE_LOG_0. 43 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 44 * Added SAS Device IDs. 45 * Updated Integrated RAID configuration pages including 46 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 47 * Page 0. 48 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 49 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 50 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 51 * Added missing MaxNumRoutedSasAddresses field to 52 * MPI2_CONFIG_PAGE_EXPANDER_0. 53 * Added SAS Port Page 0. 54 * Modified structure layout for 55 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 56 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 57 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 58 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 59 * to 0x000000FF. 60 * Added two new values for the Physical Disk Coercion Size 61 * bits in the Flags field of Manufacturing Page 4. 62 * Added product-specific Manufacturing pages 16 to 31. 63 * Modified Flags bits for controlling write cache on SATA 64 * drives in IO Unit Page 1. 65 * Added new bit to AdditionalControlFlags of SAS IO Unit 66 * Page 1 to control Invalid Topology Correction. 67 * Added additional defines for RAID Volume Page 0 68 * VolumeStatusFlags field. 69 * Modified meaning of RAID Volume Page 0 VolumeSettings 70 * define for auto-configure of hot-swap drives. 71 * Added SupportedPhysDisks field to RAID Volume Page 1 and 72 * added related defines. 73 * Added PhysDiskAttributes field (and related defines) to 74 * RAID Physical Disk Page 0. 75 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 76 * Added three new DiscoveryStatus bits for SAS IO Unit 77 * Page 0 and SAS Expander Page 0. 78 * Removed multiplexing information from SAS IO Unit pages. 79 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 80 * Removed Zone Address Resolved bit from PhyInfo and from 81 * Expander Page 0 Flags field. 82 * Added two new AccessStatus values to SAS Device Page 0 83 * for indicating routing problems. Added 3 reserved words 84 * to this page. 85 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 86 * Inserted missing reserved field into structure for IOC 87 * Page 6. 88 * Added more pending task bits to RAID Volume Page 0 89 * VolumeStatusFlags defines. 90 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 91 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 92 * and SAS Expander Page 0 to flag a downstream initiator 93 * when in simplified routing mode. 94 * Removed SATA Init Failure defines for DiscoveryStatus 95 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 96 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 97 * Added PortGroups, DmaGroup, and ControlGroup fields to 98 * SAS Device Page 0. 99 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 100 * Unit Page 6. 101 * Added expander reduced functionality data to SAS 102 * Expander Page 0. 103 * Added SAS PHY Page 2 and SAS PHY Page 3. 104 * 07-30-09 02.00.12 Added IO Unit Page 7. 105 * Added new device ids. 106 * Added SAS IO Unit Page 5. 107 * Added partial and slumber power management capable flags 108 * to SAS Device Page 0 Flags field. 109 * Added PhyInfo defines for power condition. 110 * Added Ethernet configuration pages. 111 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 112 * Added SAS PHY Page 4 structure and defines. 113 * -------------------------------------------------------------------------- 114 */ 115 116#ifndef MPI2_CNFG_H 117#define MPI2_CNFG_H 118 119/***************************************************************************** 120* Configuration Page Header and defines 121*****************************************************************************/ 122 123/* Config Page Header */ 124typedef struct _MPI2_CONFIG_PAGE_HEADER 125{ 126 U8 PageVersion; /* 0x00 */ 127 U8 PageLength; /* 0x01 */ 128 U8 PageNumber; /* 0x02 */ 129 U8 PageType; /* 0x03 */ 130} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 131 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 132 133typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 134{ 135 MPI2_CONFIG_PAGE_HEADER Struct; 136 U8 Bytes[4]; 137 U16 Word16[2]; 138 U32 Word32; 139} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 140 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 141 142/* Extended Config Page Header */ 143typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 144{ 145 U8 PageVersion; /* 0x00 */ 146 U8 Reserved1; /* 0x01 */ 147 U8 PageNumber; /* 0x02 */ 148 U8 PageType; /* 0x03 */ 149 U16 ExtPageLength; /* 0x04 */ 150 U8 ExtPageType; /* 0x06 */ 151 U8 Reserved2; /* 0x07 */ 152} MPI2_CONFIG_EXTENDED_PAGE_HEADER, 153 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 154 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 155 156typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 157{ 158 MPI2_CONFIG_PAGE_HEADER Struct; 159 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 160 U8 Bytes[8]; 161 U16 Word16[4]; 162 U32 Word32[2]; 163} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 164 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 165 166 167/* PageType field values */ 168#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 169#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 170#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 171#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 172 173#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 174#define MPI2_CONFIG_PAGETYPE_IOC (0x01) 175#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 176#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 177#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 178#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 179#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 180#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 181 182#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 183 184 185/* ExtPageType field values */ 186#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 187#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 188#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 189#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 190#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 191#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 192#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 193#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 194#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 195#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 196 197 198/***************************************************************************** 199* PageAddress defines 200*****************************************************************************/ 201 202/* RAID Volume PageAddress format */ 203#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 204#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 205#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 206 207#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 208 209 210/* RAID Physical Disk PageAddress format */ 211#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 212#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 213#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 214#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 215 216#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 217#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 218 219 220/* SAS Expander PageAddress format */ 221#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 222#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 223#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 224#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 225 226#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 227#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 228#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 229 230 231/* SAS Device PageAddress format */ 232#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 233#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 234#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 235 236#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 237 238 239/* SAS PHY PageAddress format */ 240#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 241#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 242#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 243 244#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 245#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 246 247 248/* SAS Port PageAddress format */ 249#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 250#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 251#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 252 253#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 254 255 256/* SAS Enclosure PageAddress format */ 257#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 258#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 259#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 260 261#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 262 263 264/* RAID Configuration PageAddress format */ 265#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 266#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 267#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 268#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 269 270#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 271 272 273/* Driver Persistent Mapping PageAddress format */ 274#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 275#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 276 277#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 278#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 279#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 280 281 282/* Ethernet PageAddress format */ 283#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 284#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 285 286#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 287 288 289 290/**************************************************************************** 291* Configuration messages 292****************************************************************************/ 293 294/* Configuration Request Message */ 295typedef struct _MPI2_CONFIG_REQUEST 296{ 297 U8 Action; /* 0x00 */ 298 U8 SGLFlags; /* 0x01 */ 299 U8 ChainOffset; /* 0x02 */ 300 U8 Function; /* 0x03 */ 301 U16 ExtPageLength; /* 0x04 */ 302 U8 ExtPageType; /* 0x06 */ 303 U8 MsgFlags; /* 0x07 */ 304 U8 VP_ID; /* 0x08 */ 305 U8 VF_ID; /* 0x09 */ 306 U16 Reserved1; /* 0x0A */ 307 U32 Reserved2; /* 0x0C */ 308 U32 Reserved3; /* 0x10 */ 309 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 310 U32 PageAddress; /* 0x18 */ 311 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 312} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 313 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 314 315/* values for the Action field */ 316#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 317#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 318#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 319#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 320#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 321#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 322#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 323#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 324 325/* values for SGLFlags field are in the SGL section of mpi2.h */ 326 327 328/* Config Reply Message */ 329typedef struct _MPI2_CONFIG_REPLY 330{ 331 U8 Action; /* 0x00 */ 332 U8 SGLFlags; /* 0x01 */ 333 U8 MsgLength; /* 0x02 */ 334 U8 Function; /* 0x03 */ 335 U16 ExtPageLength; /* 0x04 */ 336 U8 ExtPageType; /* 0x06 */ 337 U8 MsgFlags; /* 0x07 */ 338 U8 VP_ID; /* 0x08 */ 339 U8 VF_ID; /* 0x09 */ 340 U16 Reserved1; /* 0x0A */ 341 U16 Reserved2; /* 0x0C */ 342 U16 IOCStatus; /* 0x0E */ 343 U32 IOCLogInfo; /* 0x10 */ 344 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 345} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 346 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 347 348 349 350/***************************************************************************** 351* 352* C o n f i g u r a t i o n P a g e s 353* 354*****************************************************************************/ 355 356/**************************************************************************** 357* Manufacturing Config pages 358****************************************************************************/ 359 360#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 361 362/* SAS */ 363#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 364#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 365#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 366#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 367#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 368#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 369#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 370 371#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 372#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 373#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 374#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 375#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 376#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 377#define MPI2_MFGPAGE_DEVID_SAS2208_7 (0x0086) 378#define MPI2_MFGPAGE_DEVID_SAS2208_8 (0x0087) 379 380 381/* Manufacturing Page 0 */ 382 383typedef struct _MPI2_CONFIG_PAGE_MAN_0 384{ 385 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 386 U8 ChipName[16]; /* 0x04 */ 387 U8 ChipRevision[8]; /* 0x14 */ 388 U8 BoardName[16]; /* 0x1C */ 389 U8 BoardAssembly[16]; /* 0x2C */ 390 U8 BoardTracerNumber[16]; /* 0x3C */ 391} MPI2_CONFIG_PAGE_MAN_0, 392 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 393 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 394 395#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 396 397 398/* Manufacturing Page 1 */ 399 400typedef struct _MPI2_CONFIG_PAGE_MAN_1 401{ 402 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 403 U8 VPD[256]; /* 0x04 */ 404} MPI2_CONFIG_PAGE_MAN_1, 405 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 406 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 407 408#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 409 410 411typedef struct _MPI2_CHIP_REVISION_ID 412{ 413 U16 DeviceID; /* 0x00 */ 414 U8 PCIRevisionID; /* 0x02 */ 415 U8 Reserved; /* 0x03 */ 416} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 417 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 418 419 420/* Manufacturing Page 2 */ 421 422/* 423 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 424 * one and check Header.PageLength at runtime. 425 */ 426#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 427#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 428#endif 429 430typedef struct _MPI2_CONFIG_PAGE_MAN_2 431{ 432 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 433 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 434 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 435} MPI2_CONFIG_PAGE_MAN_2, 436 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 437 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 438 439#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 440 441 442/* Manufacturing Page 3 */ 443 444/* 445 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 446 * one and check Header.PageLength at runtime. 447 */ 448#ifndef MPI2_MAN_PAGE_3_INFO_WORDS 449#define MPI2_MAN_PAGE_3_INFO_WORDS (1) 450#endif 451 452typedef struct _MPI2_CONFIG_PAGE_MAN_3 453{ 454 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 455 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 456 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 457} MPI2_CONFIG_PAGE_MAN_3, 458 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 459 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 460 461#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 462 463 464/* Manufacturing Page 4 */ 465 466typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 467{ 468 U8 PowerSaveFlags; /* 0x00 */ 469 U8 InternalOperationsSleepTime; /* 0x01 */ 470 U8 InternalOperationsRunTime; /* 0x02 */ 471 U8 HostIdleTime; /* 0x03 */ 472} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 473 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 474 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 475 476/* defines for the PowerSaveFlags field */ 477#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 478#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 479#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 480#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 481 482typedef struct _MPI2_CONFIG_PAGE_MAN_4 483{ 484 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 485 U32 Reserved1; /* 0x04 */ 486 U32 Flags; /* 0x08 */ 487 U8 InquirySize; /* 0x0C */ 488 U8 Reserved2; /* 0x0D */ 489 U16 Reserved3; /* 0x0E */ 490 U8 InquiryData[56]; /* 0x10 */ 491 U32 RAID0VolumeSettings; /* 0x48 */ 492 U32 RAID1EVolumeSettings; /* 0x4C */ 493 U32 RAID1VolumeSettings; /* 0x50 */ 494 U32 RAID10VolumeSettings; /* 0x54 */ 495 U32 Reserved4; /* 0x58 */ 496 U32 Reserved5; /* 0x5C */ 497 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 498 U8 MaxOCEDisks; /* 0x64 */ 499 U8 ResyncRate; /* 0x65 */ 500 U16 DataScrubDuration; /* 0x66 */ 501 U8 MaxHotSpares; /* 0x68 */ 502 U8 MaxPhysDisksPerVol; /* 0x69 */ 503 U8 MaxPhysDisks; /* 0x6A */ 504 U8 MaxVolumes; /* 0x6B */ 505} MPI2_CONFIG_PAGE_MAN_4, 506 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 507 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 508 509#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 510 511/* Manufacturing Page 4 Flags field */ 512#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 513#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 514 515#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 516#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 517#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 518 519#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 520#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 521#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 522#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 523#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 524 525#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 526#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 527#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 528#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 529 530#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 531#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 532#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 533#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 534#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 535#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 536#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 537#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 538 539 540/* Manufacturing Page 5 */ 541 542/* 543 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 544 * one and check Header.PageLength or NumPhys at runtime. 545 */ 546#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 547#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 548#endif 549 550typedef struct _MPI2_MANUFACTURING5_ENTRY 551{ 552 U64 WWID; /* 0x00 */ 553 U64 DeviceName; /* 0x08 */ 554} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 555 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 556 557typedef struct _MPI2_CONFIG_PAGE_MAN_5 558{ 559 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 560 U8 NumPhys; /* 0x04 */ 561 U8 Reserved1; /* 0x05 */ 562 U16 Reserved2; /* 0x06 */ 563 U32 Reserved3; /* 0x08 */ 564 U32 Reserved4; /* 0x0C */ 565 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 566} MPI2_CONFIG_PAGE_MAN_5, 567 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 568 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 569 570#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 571 572 573/* Manufacturing Page 6 */ 574 575typedef struct _MPI2_CONFIG_PAGE_MAN_6 576{ 577 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 578 U32 ProductSpecificInfo;/* 0x04 */ 579} MPI2_CONFIG_PAGE_MAN_6, 580 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 581 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 582 583#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 584 585 586/* Manufacturing Page 7 */ 587 588typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 589{ 590 U32 Pinout; /* 0x00 */ 591 U8 Connector[16]; /* 0x04 */ 592 U8 Location; /* 0x14 */ 593 U8 Reserved1; /* 0x15 */ 594 U16 Slot; /* 0x16 */ 595 U32 Reserved2; /* 0x18 */ 596} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 597 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 598 599/* defines for the Pinout field */ 600#define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 601#define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 602#define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 603#define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 604#define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 605#define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 606#define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 607#define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 608#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 609#define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 610 611/* defines for the Location field */ 612#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 613#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 614#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 615#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 616#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 617#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 618#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 619 620/* 621 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 622 * one and check NumPhys at runtime. 623 */ 624#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 625#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 626#endif 627 628typedef struct _MPI2_CONFIG_PAGE_MAN_7 629{ 630 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 631 U32 Reserved1; /* 0x04 */ 632 U32 Reserved2; /* 0x08 */ 633 U32 Flags; /* 0x0C */ 634 U8 EnclosureName[16]; /* 0x10 */ 635 U8 NumPhys; /* 0x20 */ 636 U8 Reserved3; /* 0x21 */ 637 U16 Reserved4; /* 0x22 */ 638 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 639} MPI2_CONFIG_PAGE_MAN_7, 640 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 641 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 642 643#define MPI2_MANUFACTURING7_PAGEVERSION (0x00) 644 645/* defines for the Flags field */ 646#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 647 648 649/* 650 * Generic structure to use for product-specific manufacturing pages 651 * (currently Manufacturing Page 8 through Manufacturing Page 31). 652 */ 653 654typedef struct _MPI2_CONFIG_PAGE_MAN_PS 655{ 656 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 657 U32 ProductSpecificInfo;/* 0x04 */ 658} MPI2_CONFIG_PAGE_MAN_PS, 659 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 660 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 661 662#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 663#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 664#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 665#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 666#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 667#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 668#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 669#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 670#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 671#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 672#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 673#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 674#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 675#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 676#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 677#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 678#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 679#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 680#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 681#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 682#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 683#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 684#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 685#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 686 687 688/**************************************************************************** 689* IO Unit Config Pages 690****************************************************************************/ 691 692/* IO Unit Page 0 */ 693 694typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 695{ 696 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 697 U64 UniqueValue; /* 0x04 */ 698 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 699 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 700} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 701 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 702 703#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 704 705 706/* IO Unit Page 1 */ 707 708typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 709{ 710 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 711 U32 Flags; /* 0x04 */ 712} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 713 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 714 715#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 716 717/* IO Unit Page 1 Flags defines */ 718#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 719#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 720#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 721#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 722#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 723#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 724#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 725#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 726#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 727#define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002) 728#define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 729 730 731/* IO Unit Page 3 */ 732 733/* 734 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 735 * one and check Header.PageLength at runtime. 736 */ 737#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 738#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 739#endif 740 741typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 742{ 743 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 744 U8 GPIOCount; /* 0x04 */ 745 U8 Reserved1; /* 0x05 */ 746 U16 Reserved2; /* 0x06 */ 747 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 748} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 749 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 750 751#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 752 753/* defines for IO Unit Page 3 GPIOVal field */ 754#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 755#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 756#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 757#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 758 759 760/* IO Unit Page 5 */ 761 762/* 763 * Upper layer code (drivers, utilities, etc.) should leave this define set to 764 * one and check Header.PageLength or NumDmaEngines at runtime. 765 */ 766#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 767#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 768#endif 769 770typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 771{ 772 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 773 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 774 U64 RaidAcceleratorBufferSize; /* 0x0C */ 775 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 776 U8 RAControlSize; /* 0x1C */ 777 U8 NumDmaEngines; /* 0x1D */ 778 U8 RAMinControlSize; /* 0x1E */ 779 U8 RAMaxControlSize; /* 0x1F */ 780 U32 Reserved1; /* 0x20 */ 781 U32 Reserved2; /* 0x24 */ 782 U32 Reserved3; /* 0x28 */ 783 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 784} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 785 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 786 787#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 788 789/* defines for IO Unit Page 5 DmaEngineCapabilities field */ 790#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 791#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 792 793#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 794#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 795#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 796#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 797 798 799/* IO Unit Page 6 */ 800 801typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 802{ 803 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 804 U16 Flags; /* 0x04 */ 805 U8 RAHostControlSize; /* 0x06 */ 806 U8 Reserved0; /* 0x07 */ 807 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 808 U32 Reserved1; /* 0x10 */ 809 U32 Reserved2; /* 0x14 */ 810 U32 Reserved3; /* 0x18 */ 811} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 812 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 813 814#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 815 816/* defines for IO Unit Page 6 Flags field */ 817#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 818 819 820/* IO Unit Page 7 */ 821 822typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 823{ 824 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 825 U16 Reserved1; /* 0x04 */ 826 U8 PCIeWidth; /* 0x06 */ 827 U8 PCIeSpeed; /* 0x07 */ 828 U32 ProcessorState; /* 0x08 */ 829 U32 Reserved2; /* 0x0C */ 830 U16 IOCTemperature; /* 0x10 */ 831 U8 IOCTemperatureUnits; /* 0x12 */ 832 U8 IOCSpeed; /* 0x13 */ 833 U32 Reserved3; /* 0x14 */ 834} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 835 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 836 837#define MPI2_IOUNITPAGE7_PAGEVERSION (0x00) 838 839/* defines for IO Unit Page 7 PCIeWidth field */ 840#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 841#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 842#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 843#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 844 845/* defines for IO Unit Page 7 PCIeSpeed field */ 846#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 847#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 848#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 849 850/* defines for IO Unit Page 7 ProcessorState field */ 851#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 852#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 853 854#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 855#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 856#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 857 858/* defines for IO Unit Page 7 IOCTemperatureUnits field */ 859#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 860#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 861#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 862 863/* defines for IO Unit Page 7 IOCSpeed field */ 864#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 865#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 866#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 867#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 868 869 870 871/**************************************************************************** 872* IOC Config Pages 873****************************************************************************/ 874 875/* IOC Page 0 */ 876 877typedef struct _MPI2_CONFIG_PAGE_IOC_0 878{ 879 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 880 U32 Reserved1; /* 0x04 */ 881 U32 Reserved2; /* 0x08 */ 882 U16 VendorID; /* 0x0C */ 883 U16 DeviceID; /* 0x0E */ 884 U8 RevisionID; /* 0x10 */ 885 U8 Reserved3; /* 0x11 */ 886 U16 Reserved4; /* 0x12 */ 887 U32 ClassCode; /* 0x14 */ 888 U16 SubsystemVendorID; /* 0x18 */ 889 U16 SubsystemID; /* 0x1A */ 890} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 891 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 892 893#define MPI2_IOCPAGE0_PAGEVERSION (0x02) 894 895 896/* IOC Page 1 */ 897 898typedef struct _MPI2_CONFIG_PAGE_IOC_1 899{ 900 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 901 U32 Flags; /* 0x04 */ 902 U32 CoalescingTimeout; /* 0x08 */ 903 U8 CoalescingDepth; /* 0x0C */ 904 U8 PCISlotNum; /* 0x0D */ 905 U8 PCIBusNum; /* 0x0E */ 906 U8 PCIDomainSegment; /* 0x0F */ 907 U32 Reserved1; /* 0x10 */ 908 U32 Reserved2; /* 0x14 */ 909} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 910 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 911 912#define MPI2_IOCPAGE1_PAGEVERSION (0x05) 913 914/* defines for IOC Page 1 Flags field */ 915#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 916 917#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 918#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 919#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 920 921/* IOC Page 6 */ 922 923typedef struct _MPI2_CONFIG_PAGE_IOC_6 924{ 925 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 926 U32 CapabilitiesFlags; /* 0x04 */ 927 U8 MaxDrivesRAID0; /* 0x08 */ 928 U8 MaxDrivesRAID1; /* 0x09 */ 929 U8 MaxDrivesRAID1E; /* 0x0A */ 930 U8 MaxDrivesRAID10; /* 0x0B */ 931 U8 MinDrivesRAID0; /* 0x0C */ 932 U8 MinDrivesRAID1; /* 0x0D */ 933 U8 MinDrivesRAID1E; /* 0x0E */ 934 U8 MinDrivesRAID10; /* 0x0F */ 935 U32 Reserved1; /* 0x10 */ 936 U8 MaxGlobalHotSpares; /* 0x14 */ 937 U8 MaxPhysDisks; /* 0x15 */ 938 U8 MaxVolumes; /* 0x16 */ 939 U8 MaxConfigs; /* 0x17 */ 940 U8 MaxOCEDisks; /* 0x18 */ 941 U8 Reserved2; /* 0x19 */ 942 U16 Reserved3; /* 0x1A */ 943 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 944 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 945 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 946 U32 Reserved4; /* 0x28 */ 947 U32 Reserved5; /* 0x2C */ 948 U16 DefaultMetadataSize; /* 0x30 */ 949 U16 Reserved6; /* 0x32 */ 950 U16 MaxBadBlockTableEntries; /* 0x34 */ 951 U16 Reserved7; /* 0x36 */ 952 U32 IRNvsramVersion; /* 0x38 */ 953} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 954 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 955 956#define MPI2_IOCPAGE6_PAGEVERSION (0x04) 957 958/* defines for IOC Page 6 CapabilitiesFlags */ 959#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 960#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 961#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 962#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 963#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 964 965 966/* IOC Page 7 */ 967 968#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 969 970typedef struct _MPI2_CONFIG_PAGE_IOC_7 971{ 972 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 973 U32 Reserved1; /* 0x04 */ 974 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 975 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 976 U16 Reserved2; /* 0x1A */ 977 U32 Reserved3; /* 0x1C */ 978} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 979 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 980 981#define MPI2_IOCPAGE7_PAGEVERSION (0x01) 982 983 984/* IOC Page 8 */ 985 986typedef struct _MPI2_CONFIG_PAGE_IOC_8 987{ 988 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 989 U8 NumDevsPerEnclosure; /* 0x04 */ 990 U8 Reserved1; /* 0x05 */ 991 U16 Reserved2; /* 0x06 */ 992 U16 MaxPersistentEntries; /* 0x08 */ 993 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 994 U16 Flags; /* 0x0C */ 995 U16 Reserved3; /* 0x0E */ 996 U16 IRVolumeMappingFlags; /* 0x10 */ 997 U16 Reserved4; /* 0x12 */ 998 U32 Reserved5; /* 0x14 */ 999} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1000 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1001 1002#define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1003 1004/* defines for IOC Page 8 Flags field */ 1005#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1006#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1007 1008#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1009#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1010#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1011 1012#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1013#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1014 1015/* defines for IOC Page 8 IRVolumeMappingFlags */ 1016#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1017#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1018#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1019 1020 1021/**************************************************************************** 1022* BIOS Config Pages 1023****************************************************************************/ 1024 1025/* BIOS Page 1 */ 1026 1027typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1028{ 1029 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1030 U32 BiosOptions; /* 0x04 */ 1031 U32 IOCSettings; /* 0x08 */ 1032 U32 Reserved1; /* 0x0C */ 1033 U32 DeviceSettings; /* 0x10 */ 1034 U16 NumberOfDevices; /* 0x14 */ 1035 U16 Reserved2; /* 0x16 */ 1036 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1037 U16 IOTimeoutSequential; /* 0x1A */ 1038 U16 IOTimeoutOther; /* 0x1C */ 1039 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1040} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1041 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1042 1043#define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1044 1045/* values for BIOS Page 1 BiosOptions field */ 1046#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1047 1048/* values for BIOS Page 1 IOCSettings field */ 1049#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1050#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1051#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1052 1053#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1054#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1055#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1056#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1057 1058#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1059#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1060#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1061#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1062#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1063 1064#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1065 1066/* values for BIOS Page 1 DeviceSettings field */ 1067#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1068#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1069#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1070#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1071#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1072 1073 1074/* BIOS Page 2 */ 1075 1076typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1077{ 1078 U32 Reserved1; /* 0x00 */ 1079 U32 Reserved2; /* 0x04 */ 1080 U32 Reserved3; /* 0x08 */ 1081 U32 Reserved4; /* 0x0C */ 1082 U32 Reserved5; /* 0x10 */ 1083 U32 Reserved6; /* 0x14 */ 1084} MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1085 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1086 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1087 1088typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1089{ 1090 U64 SASAddress; /* 0x00 */ 1091 U8 LUN[8]; /* 0x08 */ 1092 U32 Reserved1; /* 0x10 */ 1093 U32 Reserved2; /* 0x14 */ 1094} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1095 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1096 1097typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1098{ 1099 U64 EnclosureLogicalID; /* 0x00 */ 1100 U32 Reserved1; /* 0x08 */ 1101 U32 Reserved2; /* 0x0C */ 1102 U16 SlotNumber; /* 0x10 */ 1103 U16 Reserved3; /* 0x12 */ 1104 U32 Reserved4; /* 0x14 */ 1105} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1106 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1107 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1108 1109typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1110{ 1111 U64 DeviceName; /* 0x00 */ 1112 U8 LUN[8]; /* 0x08 */ 1113 U32 Reserved1; /* 0x10 */ 1114 U32 Reserved2; /* 0x14 */ 1115} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1116 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1117 1118typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1119{ 1120 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1121 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1122 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1123 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1124} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1125 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1126 1127typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1128{ 1129 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1130 U32 Reserved1; /* 0x04 */ 1131 U32 Reserved2; /* 0x08 */ 1132 U32 Reserved3; /* 0x0C */ 1133 U32 Reserved4; /* 0x10 */ 1134 U32 Reserved5; /* 0x14 */ 1135 U32 Reserved6; /* 0x18 */ 1136 U8 ReqBootDeviceForm; /* 0x1C */ 1137 U8 Reserved7; /* 0x1D */ 1138 U16 Reserved8; /* 0x1E */ 1139 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1140 U8 ReqAltBootDeviceForm; /* 0x38 */ 1141 U8 Reserved9; /* 0x39 */ 1142 U16 Reserved10; /* 0x3A */ 1143 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1144 U8 CurrentBootDeviceForm; /* 0x58 */ 1145 U8 Reserved11; /* 0x59 */ 1146 U16 Reserved12; /* 0x5A */ 1147 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1148} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1149 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1150 1151#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1152 1153/* values for BIOS Page 2 BootDeviceForm fields */ 1154#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1155#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1156#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1157#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1158#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1159 1160 1161/* BIOS Page 3 */ 1162 1163typedef struct _MPI2_ADAPTER_INFO 1164{ 1165 U8 PciBusNumber; /* 0x00 */ 1166 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1167 U16 AdapterFlags; /* 0x02 */ 1168} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1169 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1170 1171#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1172#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1173 1174typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1175{ 1176 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1177 U32 GlobalFlags; /* 0x04 */ 1178 U32 BiosVersion; /* 0x08 */ 1179 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1180 U32 Reserved1; /* 0x1C */ 1181} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1182 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1183 1184#define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1185 1186/* values for BIOS Page 3 GlobalFlags */ 1187#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1188#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1189#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1190 1191#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1192#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1193#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1194#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1195 1196 1197/* BIOS Page 4 */ 1198 1199/* 1200 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1201 * one and check Header.PageLength or NumPhys at runtime. 1202 */ 1203#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1204#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1205#endif 1206 1207typedef struct _MPI2_BIOS4_ENTRY 1208{ 1209 U64 ReassignmentWWID; /* 0x00 */ 1210 U64 ReassignmentDeviceName; /* 0x08 */ 1211} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1212 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1213 1214typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1215{ 1216 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1217 U8 NumPhys; /* 0x04 */ 1218 U8 Reserved1; /* 0x05 */ 1219 U16 Reserved2; /* 0x06 */ 1220 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1221} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1222 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1223 1224#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1225 1226 1227/**************************************************************************** 1228* RAID Volume Config Pages 1229****************************************************************************/ 1230 1231/* RAID Volume Page 0 */ 1232 1233typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1234{ 1235 U8 RAIDSetNum; /* 0x00 */ 1236 U8 PhysDiskMap; /* 0x01 */ 1237 U8 PhysDiskNum; /* 0x02 */ 1238 U8 Reserved; /* 0x03 */ 1239} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1240 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1241 1242/* defines for the PhysDiskMap field */ 1243#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1244#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1245 1246typedef struct _MPI2_RAIDVOL0_SETTINGS 1247{ 1248 U16 Settings; /* 0x00 */ 1249 U8 HotSparePool; /* 0x01 */ 1250 U8 Reserved; /* 0x02 */ 1251} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1252 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1253 1254/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1255#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1256#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1257#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1258#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1259#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1260#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1261#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1262#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1263 1264/* RAID Volume Page 0 VolumeSettings defines */ 1265#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1266#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1267 1268#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1269#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1270#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1271#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1272 1273/* 1274 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1275 * one and check Header.PageLength at runtime. 1276 */ 1277#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1278#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1279#endif 1280 1281typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1282{ 1283 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1284 U16 DevHandle; /* 0x04 */ 1285 U8 VolumeState; /* 0x06 */ 1286 U8 VolumeType; /* 0x07 */ 1287 U32 VolumeStatusFlags; /* 0x08 */ 1288 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1289 U64 MaxLBA; /* 0x10 */ 1290 U32 StripeSize; /* 0x18 */ 1291 U16 BlockSize; /* 0x1C */ 1292 U16 Reserved1; /* 0x1E */ 1293 U8 SupportedPhysDisks; /* 0x20 */ 1294 U8 ResyncRate; /* 0x21 */ 1295 U16 DataScrubDuration; /* 0x22 */ 1296 U8 NumPhysDisks; /* 0x24 */ 1297 U8 Reserved2; /* 0x25 */ 1298 U8 Reserved3; /* 0x26 */ 1299 U8 InactiveStatus; /* 0x27 */ 1300 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1301} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1302 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1303 1304#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1305 1306/* values for RAID VolumeState */ 1307#define MPI2_RAID_VOL_STATE_MISSING (0x00) 1308#define MPI2_RAID_VOL_STATE_FAILED (0x01) 1309#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1310#define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1311#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1312#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1313 1314/* values for RAID VolumeType */ 1315#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1316#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1317#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1318#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1319#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1320 1321/* values for RAID Volume Page 0 VolumeStatusFlags field */ 1322#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1323#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1324#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1325#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1326#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1327#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1328#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1329#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1330#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1331#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1332#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1333#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1334#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1335#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1336#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1337#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1338#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1339#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1340 1341/* values for RAID Volume Page 0 SupportedPhysDisks field */ 1342#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1343#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1344#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1345#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1346 1347/* values for RAID Volume Page 0 InactiveStatus field */ 1348#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1349#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1350#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1351#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1352#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1353#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1354#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1355 1356 1357/* RAID Volume Page 1 */ 1358 1359typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1360{ 1361 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1362 U16 DevHandle; /* 0x04 */ 1363 U16 Reserved0; /* 0x06 */ 1364 U8 GUID[24]; /* 0x08 */ 1365 U8 Name[16]; /* 0x20 */ 1366 U64 WWID; /* 0x30 */ 1367 U32 Reserved1; /* 0x38 */ 1368 U32 Reserved2; /* 0x3C */ 1369} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1370 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1371 1372#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1373 1374 1375/**************************************************************************** 1376* RAID Physical Disk Config Pages 1377****************************************************************************/ 1378 1379/* RAID Physical Disk Page 0 */ 1380 1381typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1382{ 1383 U16 Reserved1; /* 0x00 */ 1384 U8 HotSparePool; /* 0x02 */ 1385 U8 Reserved2; /* 0x03 */ 1386} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1387 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1388 1389/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1390 1391typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1392{ 1393 U8 VendorID[8]; /* 0x00 */ 1394 U8 ProductID[16]; /* 0x08 */ 1395 U8 ProductRevLevel[4]; /* 0x18 */ 1396 U8 SerialNum[32]; /* 0x1C */ 1397} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1398 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1399 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1400 1401typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1402{ 1403 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1404 U16 DevHandle; /* 0x04 */ 1405 U8 Reserved1; /* 0x06 */ 1406 U8 PhysDiskNum; /* 0x07 */ 1407 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1408 U32 Reserved2; /* 0x0C */ 1409 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1410 U32 Reserved3; /* 0x4C */ 1411 U8 PhysDiskState; /* 0x50 */ 1412 U8 OfflineReason; /* 0x51 */ 1413 U8 IncompatibleReason; /* 0x52 */ 1414 U8 PhysDiskAttributes; /* 0x53 */ 1415 U32 PhysDiskStatusFlags; /* 0x54 */ 1416 U64 DeviceMaxLBA; /* 0x58 */ 1417 U64 HostMaxLBA; /* 0x60 */ 1418 U64 CoercedMaxLBA; /* 0x68 */ 1419 U16 BlockSize; /* 0x70 */ 1420 U16 Reserved5; /* 0x72 */ 1421 U32 Reserved6; /* 0x74 */ 1422} MPI2_CONFIG_PAGE_RD_PDISK_0, 1423 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1424 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1425 1426#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1427 1428/* PhysDiskState defines */ 1429#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1430#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1431#define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1432#define MPI2_RAID_PD_STATE_ONLINE (0x03) 1433#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1434#define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1435#define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1436#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1437 1438/* OfflineReason defines */ 1439#define MPI2_PHYSDISK0_ONLINE (0x00) 1440#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1441#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1442#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1443#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1444#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1445#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1446 1447/* IncompatibleReason defines */ 1448#define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1449#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1450#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1451#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1452#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1453#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1454#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1455 1456/* PhysDiskAttributes defines */ 1457#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1458#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1459#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1460#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1461 1462/* PhysDiskStatusFlags defines */ 1463#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1464#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1465#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1466#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1467#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1468#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1469#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1470#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1471 1472 1473/* RAID Physical Disk Page 1 */ 1474 1475/* 1476 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1477 * one and check Header.PageLength or NumPhysDiskPaths at runtime. 1478 */ 1479#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1480#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1481#endif 1482 1483typedef struct _MPI2_RAIDPHYSDISK1_PATH 1484{ 1485 U16 DevHandle; /* 0x00 */ 1486 U16 Reserved1; /* 0x02 */ 1487 U64 WWID; /* 0x04 */ 1488 U64 OwnerWWID; /* 0x0C */ 1489 U8 OwnerIdentifier; /* 0x14 */ 1490 U8 Reserved2; /* 0x15 */ 1491 U16 Flags; /* 0x16 */ 1492} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1493 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1494 1495/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1496#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1497#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1498#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1499 1500typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1501{ 1502 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1503 U8 NumPhysDiskPaths; /* 0x04 */ 1504 U8 PhysDiskNum; /* 0x05 */ 1505 U16 Reserved1; /* 0x06 */ 1506 U32 Reserved2; /* 0x08 */ 1507 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1508} MPI2_CONFIG_PAGE_RD_PDISK_1, 1509 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1510 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1511 1512#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1513 1514 1515/**************************************************************************** 1516* values for fields used by several types of SAS Config Pages 1517****************************************************************************/ 1518 1519/* values for NegotiatedLinkRates fields */ 1520#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1521#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1522#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1523/* link rates used for Negotiated Physical and Logical Link Rate */ 1524#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1525#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1526#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1527#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1528#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1529#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1530#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1531#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1532#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1533 1534 1535/* values for AttachedPhyInfo fields */ 1536#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1537#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1538#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1539 1540#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1541#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1542#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1543#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1544#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1545#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1546#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1547#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1548#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1549#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1550 1551 1552/* values for PhyInfo fields */ 1553#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1554 1555#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1556#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1557#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1558#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1559 1560#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1561#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1562#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1563#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1564#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1565#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1566 1567#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1568#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1569#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1570#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1571#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1572#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1573#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1574#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1575#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1576#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1577 1578#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1579#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1580#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1581#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1582 1583#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1584#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1585 1586#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1587#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1588#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1589#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1590 1591 1592/* values for SAS ProgrammedLinkRate fields */ 1593#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1594#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1595#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1596#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1597#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1598#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1599#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1600#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1601#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1602#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1603 1604 1605/* values for SAS HwLinkRate fields */ 1606#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1607#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1608#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1609#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1610#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1611#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1612#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1613#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1614 1615 1616 1617/**************************************************************************** 1618* SAS IO Unit Config Pages 1619****************************************************************************/ 1620 1621/* SAS IO Unit Page 0 */ 1622 1623typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1624{ 1625 U8 Port; /* 0x00 */ 1626 U8 PortFlags; /* 0x01 */ 1627 U8 PhyFlags; /* 0x02 */ 1628 U8 NegotiatedLinkRate; /* 0x03 */ 1629 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1630 U16 AttachedDevHandle; /* 0x08 */ 1631 U16 ControllerDevHandle; /* 0x0A */ 1632 U32 DiscoveryStatus; /* 0x0C */ 1633 U32 Reserved; /* 0x10 */ 1634} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1635 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1636 1637/* 1638 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1639 * one and check Header.ExtPageLength or NumPhys at runtime. 1640 */ 1641#ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1642#define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1643#endif 1644 1645typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1646{ 1647 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1648 U32 Reserved1; /* 0x08 */ 1649 U8 NumPhys; /* 0x0C */ 1650 U8 Reserved2; /* 0x0D */ 1651 U16 Reserved3; /* 0x0E */ 1652 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1653} MPI2_CONFIG_PAGE_SASIOUNIT_0, 1654 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1655 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1656 1657#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1658 1659/* values for SAS IO Unit Page 0 PortFlags */ 1660#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1661#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1662 1663/* values for SAS IO Unit Page 0 PhyFlags */ 1664#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1665#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1666 1667/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1668 1669/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1670 1671/* values for SAS IO Unit Page 0 DiscoveryStatus */ 1672#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1673#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1674#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1675#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1676#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1677#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1678#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1679#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1680#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1681#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1682#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1683#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1684#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1685#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1686#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1687#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1688#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1689#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1690#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1691#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1692 1693 1694/* SAS IO Unit Page 1 */ 1695 1696typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1697{ 1698 U8 Port; /* 0x00 */ 1699 U8 PortFlags; /* 0x01 */ 1700 U8 PhyFlags; /* 0x02 */ 1701 U8 MaxMinLinkRate; /* 0x03 */ 1702 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1703 U16 MaxTargetPortConnectTime; /* 0x08 */ 1704 U16 Reserved1; /* 0x0A */ 1705} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1706 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1707 1708/* 1709 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1710 * one and check Header.ExtPageLength or NumPhys at runtime. 1711 */ 1712#ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1713#define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1714#endif 1715 1716typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1717{ 1718 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1719 U16 ControlFlags; /* 0x08 */ 1720 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1721 U16 AdditionalControlFlags; /* 0x0C */ 1722 U16 SASWideMaxQueueDepth; /* 0x0E */ 1723 U8 NumPhys; /* 0x10 */ 1724 U8 SATAMaxQDepth; /* 0x11 */ 1725 U8 ReportDeviceMissingDelay; /* 0x12 */ 1726 U8 IODeviceMissingDelay; /* 0x13 */ 1727 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1728} MPI2_CONFIG_PAGE_SASIOUNIT_1, 1729 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1730 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1731 1732#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1733 1734/* values for SAS IO Unit Page 1 ControlFlags */ 1735#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1736#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1737#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1738#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1739 1740#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1741#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1742#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1743#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1744#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1745 1746#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1747#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1748#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1749#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1750#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1751#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1752#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1753#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1754 1755/* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1756#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1757#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1758#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1759#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1760#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1761#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1762#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1763#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1764 1765/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1766#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1767#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1768 1769/* values for SAS IO Unit Page 1 PortFlags */ 1770#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1771 1772/* values for SAS IO Unit Page 1 PhyFlags */ 1773#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1774#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1775 1776/* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1777#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1778#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1779#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1780#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1781#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1782#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1783#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1784#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1785 1786/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1787 1788 1789/* SAS IO Unit Page 4 */ 1790 1791typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1792{ 1793 U8 MaxTargetSpinup; /* 0x00 */ 1794 U8 SpinupDelay; /* 0x01 */ 1795 U16 Reserved1; /* 0x02 */ 1796} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1797 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1798 1799/* 1800 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1801 * four and check Header.ExtPageLength or NumPhys at runtime. 1802 */ 1803#ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1804#define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1805#endif 1806 1807typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1808{ 1809 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1810 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1811 U32 Reserved1; /* 0x18 */ 1812 U32 Reserved2; /* 0x1C */ 1813 U32 Reserved3; /* 0x20 */ 1814 U8 BootDeviceWaitTime; /* 0x24 */ 1815 U8 Reserved4; /* 0x25 */ 1816 U16 Reserved5; /* 0x26 */ 1817 U8 NumPhys; /* 0x28 */ 1818 U8 PEInitialSpinupDelay; /* 0x29 */ 1819 U8 PEReplyDelay; /* 0x2A */ 1820 U8 Flags; /* 0x2B */ 1821 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1822} MPI2_CONFIG_PAGE_SASIOUNIT_4, 1823 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1824 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1825 1826#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1827 1828/* defines for Flags field */ 1829#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1830 1831/* defines for PHY field */ 1832#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1833 1834 1835/* SAS IO Unit Page 5 */ 1836 1837typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 1838{ 1839 U8 ControlFlags; /* 0x00 */ 1840 U8 Reserved1; /* 0x01 */ 1841 U16 InactivityTimerExponent; /* 0x02 */ 1842 U8 SATAPartialTimeout; /* 0x04 */ 1843 U8 Reserved2; /* 0x05 */ 1844 U8 SATASlumberTimeout; /* 0x06 */ 1845 U8 Reserved3; /* 0x07 */ 1846 U8 SASPartialTimeout; /* 0x08 */ 1847 U8 Reserved4; /* 0x09 */ 1848 U8 SASSlumberTimeout; /* 0x0A */ 1849 U8 Reserved5; /* 0x0B */ 1850} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1851 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1852 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1853 1854/* defines for ControlFlags field */ 1855#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1856#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1857#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1858#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1859 1860/* defines for InactivityTimerExponent field */ 1861#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1862#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1863#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1864#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1865#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1866#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1867#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1868#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1869 1870#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1871#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1872#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1873#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1874#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1875#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1876#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1877#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1878 1879/* 1880 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1881 * one and check Header.ExtPageLength or NumPhys at runtime. 1882 */ 1883#ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1884#define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1885#endif 1886 1887typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 1888{ 1889 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1890 U8 NumPhys; /* 0x08 */ 1891 U8 Reserved1; /* 0x09 */ 1892 U16 Reserved2; /* 0x0A */ 1893 U32 Reserved3; /* 0x0C */ 1894 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1895} MPI2_CONFIG_PAGE_SASIOUNIT_5, 1896 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1897 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1898 1899#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x00) 1900 1901 1902 1903 1904/**************************************************************************** 1905* SAS Expander Config Pages 1906****************************************************************************/ 1907 1908/* SAS Expander Page 0 */ 1909 1910typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 1911{ 1912 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1913 U8 PhysicalPort; /* 0x08 */ 1914 U8 ReportGenLength; /* 0x09 */ 1915 U16 EnclosureHandle; /* 0x0A */ 1916 U64 SASAddress; /* 0x0C */ 1917 U32 DiscoveryStatus; /* 0x14 */ 1918 U16 DevHandle; /* 0x18 */ 1919 U16 ParentDevHandle; /* 0x1A */ 1920 U16 ExpanderChangeCount; /* 0x1C */ 1921 U16 ExpanderRouteIndexes; /* 0x1E */ 1922 U8 NumPhys; /* 0x20 */ 1923 U8 SASLevel; /* 0x21 */ 1924 U16 Flags; /* 0x22 */ 1925 U16 STPBusInactivityTimeLimit; /* 0x24 */ 1926 U16 STPMaxConnectTimeLimit; /* 0x26 */ 1927 U16 STP_SMP_NexusLossTime; /* 0x28 */ 1928 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 1929 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 1930 U16 ZoneLockInactivityLimit; /* 0x34 */ 1931 U16 Reserved1; /* 0x36 */ 1932 U8 TimeToReducedFunc; /* 0x38 */ 1933 U8 InitialTimeToReducedFunc; /* 0x39 */ 1934 U8 MaxReducedFuncTime; /* 0x3A */ 1935 U8 Reserved2; /* 0x3B */ 1936} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 1937 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 1938 1939#define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 1940 1941/* values for SAS Expander Page 0 DiscoveryStatus field */ 1942#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1943#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1944#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 1945#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1946#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1947#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1948#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1949#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 1950#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1951#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 1952#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 1953#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 1954#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 1955#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 1956#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 1957#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1958#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 1959#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 1960#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1961#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 1962 1963/* values for SAS Expander Page 0 Flags field */ 1964#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 1965#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 1966#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 1967#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 1968#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 1969#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 1970#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 1971#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 1972#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 1973#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 1974#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 1975 1976 1977/* SAS Expander Page 1 */ 1978 1979typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 1980{ 1981 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1982 U8 PhysicalPort; /* 0x08 */ 1983 U8 Reserved1; /* 0x09 */ 1984 U16 Reserved2; /* 0x0A */ 1985 U8 NumPhys; /* 0x0C */ 1986 U8 Phy; /* 0x0D */ 1987 U16 NumTableEntriesProgrammed; /* 0x0E */ 1988 U8 ProgrammedLinkRate; /* 0x10 */ 1989 U8 HwLinkRate; /* 0x11 */ 1990 U16 AttachedDevHandle; /* 0x12 */ 1991 U32 PhyInfo; /* 0x14 */ 1992 U32 AttachedDeviceInfo; /* 0x18 */ 1993 U16 ExpanderDevHandle; /* 0x1C */ 1994 U8 ChangeCount; /* 0x1E */ 1995 U8 NegotiatedLinkRate; /* 0x1F */ 1996 U8 PhyIdentifier; /* 0x20 */ 1997 U8 AttachedPhyIdentifier; /* 0x21 */ 1998 U8 Reserved3; /* 0x22 */ 1999 U8 DiscoveryInfo; /* 0x23 */ 2000 U32 AttachedPhyInfo; /* 0x24 */ 2001 U8 ZoneGroup; /* 0x28 */ 2002 U8 SelfConfigStatus; /* 0x29 */ 2003 U16 Reserved4; /* 0x2A */ 2004} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2005 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2006 2007#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2008 2009/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2010 2011/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2012 2013/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2014 2015/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2016 2017/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2018 2019/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2020 2021/* values for SAS Expander Page 1 DiscoveryInfo field */ 2022#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2023#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2024#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2025 2026 2027/**************************************************************************** 2028* SAS Device Config Pages 2029****************************************************************************/ 2030 2031/* SAS Device Page 0 */ 2032 2033typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2034{ 2035 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2036 U16 Slot; /* 0x08 */ 2037 U16 EnclosureHandle; /* 0x0A */ 2038 U64 SASAddress; /* 0x0C */ 2039 U16 ParentDevHandle; /* 0x14 */ 2040 U8 PhyNum; /* 0x16 */ 2041 U8 AccessStatus; /* 0x17 */ 2042 U16 DevHandle; /* 0x18 */ 2043 U8 AttachedPhyIdentifier; /* 0x1A */ 2044 U8 ZoneGroup; /* 0x1B */ 2045 U32 DeviceInfo; /* 0x1C */ 2046 U16 Flags; /* 0x20 */ 2047 U8 PhysicalPort; /* 0x22 */ 2048 U8 MaxPortConnections; /* 0x23 */ 2049 U64 DeviceName; /* 0x24 */ 2050 U8 PortGroups; /* 0x2C */ 2051 U8 DmaGroup; /* 0x2D */ 2052 U8 ControlGroup; /* 0x2E */ 2053 U8 Reserved1; /* 0x2F */ 2054 U32 Reserved2; /* 0x30 */ 2055 U32 Reserved3; /* 0x34 */ 2056} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2057 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2058 2059#define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2060 2061/* values for SAS Device Page 0 AccessStatus field */ 2062#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2063#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2064#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2065#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2066#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2067#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2068#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2069#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2070/* specific values for SATA Init failures */ 2071#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2072#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2073#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2074#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2075#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2076#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2077#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2078#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2079#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2080#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2081#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2082 2083/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2084 2085/* values for SAS Device Page 0 Flags field */ 2086#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2087#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2088#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2089#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2090#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2091#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2092#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2093#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2094#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2095#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2096#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2097 2098 2099/* SAS Device Page 1 */ 2100 2101typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2102{ 2103 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2104 U32 Reserved1; /* 0x08 */ 2105 U64 SASAddress; /* 0x0C */ 2106 U32 Reserved2; /* 0x14 */ 2107 U16 DevHandle; /* 0x18 */ 2108 U16 Reserved3; /* 0x1A */ 2109 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2110} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2111 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2112 2113#define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2114 2115 2116/**************************************************************************** 2117* SAS PHY Config Pages 2118****************************************************************************/ 2119 2120/* SAS PHY Page 0 */ 2121 2122typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2123{ 2124 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2125 U16 OwnerDevHandle; /* 0x08 */ 2126 U16 Reserved1; /* 0x0A */ 2127 U16 AttachedDevHandle; /* 0x0C */ 2128 U8 AttachedPhyIdentifier; /* 0x0E */ 2129 U8 Reserved2; /* 0x0F */ 2130 U32 AttachedPhyInfo; /* 0x10 */ 2131 U8 ProgrammedLinkRate; /* 0x14 */ 2132 U8 HwLinkRate; /* 0x15 */ 2133 U8 ChangeCount; /* 0x16 */ 2134 U8 Flags; /* 0x17 */ 2135 U32 PhyInfo; /* 0x18 */ 2136 U8 NegotiatedLinkRate; /* 0x1C */ 2137 U8 Reserved3; /* 0x1D */ 2138 U16 Reserved4; /* 0x1E */ 2139} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2140 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2141 2142#define MPI2_SASPHY0_PAGEVERSION (0x03) 2143 2144/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2145 2146/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2147 2148/* values for SAS PHY Page 0 Flags field */ 2149#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2150 2151/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2152 2153/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2154 2155/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2156 2157 2158/* SAS PHY Page 1 */ 2159 2160typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2161{ 2162 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2163 U32 Reserved1; /* 0x08 */ 2164 U32 InvalidDwordCount; /* 0x0C */ 2165 U32 RunningDisparityErrorCount; /* 0x10 */ 2166 U32 LossDwordSynchCount; /* 0x14 */ 2167 U32 PhyResetProblemCount; /* 0x18 */ 2168} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2169 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2170 2171#define MPI2_SASPHY1_PAGEVERSION (0x01) 2172 2173 2174/* SAS PHY Page 2 */ 2175 2176typedef struct _MPI2_SASPHY2_PHY_EVENT 2177{ 2178 U8 PhyEventCode; /* 0x00 */ 2179 U8 Reserved1; /* 0x01 */ 2180 U16 Reserved2; /* 0x02 */ 2181 U32 PhyEventInfo; /* 0x04 */ 2182} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2183 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2184 2185/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2186 2187 2188/* 2189 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2190 * one and check Header.ExtPageLength or NumPhyEvents at runtime. 2191 */ 2192#ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2193#define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2194#endif 2195 2196typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2197{ 2198 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2199 U32 Reserved1; /* 0x08 */ 2200 U8 NumPhyEvents; /* 0x0C */ 2201 U8 Reserved2; /* 0x0D */ 2202 U16 Reserved3; /* 0x0E */ 2203 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2204} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2205 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2206 2207#define MPI2_SASPHY2_PAGEVERSION (0x00) 2208 2209 2210/* SAS PHY Page 3 */ 2211 2212typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2213{ 2214 U8 PhyEventCode; /* 0x00 */ 2215 U8 Reserved1; /* 0x01 */ 2216 U16 Reserved2; /* 0x02 */ 2217 U8 CounterType; /* 0x04 */ 2218 U8 ThresholdWindow; /* 0x05 */ 2219 U8 TimeUnits; /* 0x06 */ 2220 U8 Reserved3; /* 0x07 */ 2221 U32 EventThreshold; /* 0x08 */ 2222 U16 ThresholdFlags; /* 0x0C */ 2223 U16 Reserved4; /* 0x0E */ 2224} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2225 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2226 2227/* values for PhyEventCode field */ 2228#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2229#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2230#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2231#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2232#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2233#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2234#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2235#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2236#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2237#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2238#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2239#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2240#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2241#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2242#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2243#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2244#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2245#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2246#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2247#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2248#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2249#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2250#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2251#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2252#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2253#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2254#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2255#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2256#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2257#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2258#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2259#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2260#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2261#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2262#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2263#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2264#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2265 2266/* values for the CounterType field */ 2267#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2268#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2269#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2270 2271/* values for the TimeUnits field */ 2272#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2273#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2274#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2275#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2276 2277/* values for the ThresholdFlags field */ 2278#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2279#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2280 2281/* 2282 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2283 * one and check Header.ExtPageLength or NumPhyEvents at runtime. 2284 */ 2285#ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2286#define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2287#endif 2288 2289typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2290{ 2291 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2292 U32 Reserved1; /* 0x08 */ 2293 U8 NumPhyEvents; /* 0x0C */ 2294 U8 Reserved2; /* 0x0D */ 2295 U16 Reserved3; /* 0x0E */ 2296 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2297} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2298 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2299 2300#define MPI2_SASPHY3_PAGEVERSION (0x00) 2301 2302 2303/* SAS PHY Page 4 */ 2304 2305typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2306{ 2307 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2308 U16 Reserved1; /* 0x08 */ 2309 U8 Reserved2; /* 0x0A */ 2310 U8 Flags; /* 0x0B */ 2311 U8 InitialFrame[28]; /* 0x0C */ 2312} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2313 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2314 2315#define MPI2_SASPHY4_PAGEVERSION (0x00) 2316 2317/* values for the Flags field */ 2318#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2319#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2320 2321 2322 2323 2324/**************************************************************************** 2325* SAS Port Config Pages 2326****************************************************************************/ 2327 2328/* SAS Port Page 0 */ 2329 2330typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2331{ 2332 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2333 U8 PortNumber; /* 0x08 */ 2334 U8 PhysicalPort; /* 0x09 */ 2335 U8 PortWidth; /* 0x0A */ 2336 U8 PhysicalPortWidth; /* 0x0B */ 2337 U8 ZoneGroup; /* 0x0C */ 2338 U8 Reserved1; /* 0x0D */ 2339 U16 Reserved2; /* 0x0E */ 2340 U64 SASAddress; /* 0x10 */ 2341 U32 DeviceInfo; /* 0x18 */ 2342 U32 Reserved3; /* 0x1C */ 2343 U32 Reserved4; /* 0x20 */ 2344} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2345 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2346 2347#define MPI2_SASPORT0_PAGEVERSION (0x00) 2348 2349/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2350 2351 2352/**************************************************************************** 2353* SAS Enclosure Config Pages 2354****************************************************************************/ 2355 2356/* SAS Enclosure Page 0 */ 2357 2358typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2359{ 2360 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2361 U32 Reserved1; /* 0x08 */ 2362 U64 EnclosureLogicalID; /* 0x0C */ 2363 U16 Flags; /* 0x14 */ 2364 U16 EnclosureHandle; /* 0x16 */ 2365 U16 NumSlots; /* 0x18 */ 2366 U16 StartSlot; /* 0x1A */ 2367 U16 Reserved2; /* 0x1C */ 2368 U16 SEPDevHandle; /* 0x1E */ 2369 U32 Reserved3; /* 0x20 */ 2370 U32 Reserved4; /* 0x24 */ 2371} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2372 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2373 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2374 2375#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2376 2377/* values for SAS Enclosure Page 0 Flags field */ 2378#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2379#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2380#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2381#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2382#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2383#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2384#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2385 2386 2387/**************************************************************************** 2388* Log Config Page 2389****************************************************************************/ 2390 2391/* Log Page 0 */ 2392 2393/* 2394 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2395 * one and check Header.ExtPageLength or NumPhys at runtime. 2396 */ 2397#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2398#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2399#endif 2400 2401#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2402 2403typedef struct _MPI2_LOG_0_ENTRY 2404{ 2405 U64 TimeStamp; /* 0x00 */ 2406 U32 Reserved1; /* 0x08 */ 2407 U16 LogSequence; /* 0x0C */ 2408 U16 LogEntryQualifier; /* 0x0E */ 2409 U8 VP_ID; /* 0x10 */ 2410 U8 VF_ID; /* 0x11 */ 2411 U16 Reserved2; /* 0x12 */ 2412 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2413} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2414 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2415 2416/* values for Log Page 0 LogEntry LogEntryQualifier field */ 2417#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2418#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2419#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2420#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2421#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2422 2423typedef struct _MPI2_CONFIG_PAGE_LOG_0 2424{ 2425 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2426 U32 Reserved1; /* 0x08 */ 2427 U32 Reserved2; /* 0x0C */ 2428 U16 NumLogEntries; /* 0x10 */ 2429 U16 Reserved3; /* 0x12 */ 2430 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2431} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2432 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2433 2434#define MPI2_LOG_0_PAGEVERSION (0x02) 2435 2436 2437/**************************************************************************** 2438* RAID Config Page 2439****************************************************************************/ 2440 2441/* RAID Page 0 */ 2442 2443/* 2444 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2445 * one and check Header.ExtPageLength or NumPhys at runtime. 2446 */ 2447#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2448#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2449#endif 2450 2451typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2452{ 2453 U16 ElementFlags; /* 0x00 */ 2454 U16 VolDevHandle; /* 0x02 */ 2455 U8 HotSparePool; /* 0x04 */ 2456 U8 PhysDiskNum; /* 0x05 */ 2457 U16 PhysDiskDevHandle; /* 0x06 */ 2458} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2459 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2460 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2461 2462/* values for the ElementFlags field */ 2463#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2464#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2465#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2466#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2467#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2468 2469 2470typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2471{ 2472 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2473 U8 NumHotSpares; /* 0x08 */ 2474 U8 NumPhysDisks; /* 0x09 */ 2475 U8 NumVolumes; /* 0x0A */ 2476 U8 ConfigNum; /* 0x0B */ 2477 U32 Flags; /* 0x0C */ 2478 U8 ConfigGUID[24]; /* 0x10 */ 2479 U32 Reserved1; /* 0x28 */ 2480 U8 NumElements; /* 0x2C */ 2481 U8 Reserved2; /* 0x2D */ 2482 U16 Reserved3; /* 0x2E */ 2483 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2484} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2485 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2486 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2487 2488#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2489 2490/* values for RAID Configuration Page 0 Flags field */ 2491#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2492 2493 2494/**************************************************************************** 2495* Driver Persistent Mapping Config Pages 2496****************************************************************************/ 2497 2498/* Driver Persistent Mapping Page 0 */ 2499 2500typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2501{ 2502 U64 PhysicalIdentifier; /* 0x00 */ 2503 U16 MappingInformation; /* 0x08 */ 2504 U16 DeviceIndex; /* 0x0A */ 2505 U32 PhysicalBitsMapping; /* 0x0C */ 2506 U32 Reserved1; /* 0x10 */ 2507} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2508 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2509 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2510 2511typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2512{ 2513 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2514 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2515} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2516 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2517 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2518 2519#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2520 2521/* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2522#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2523#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2524#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2525 2526 2527/**************************************************************************** 2528* Ethernet Config Pages 2529****************************************************************************/ 2530 2531/* Ethernet Page 0 */ 2532 2533/* IP address (union of IPv4 and IPv6) */ 2534typedef union _MPI2_ETHERNET_IP_ADDR 2535{ 2536 U32 IPv4Addr; 2537 U32 IPv6Addr[4]; 2538} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2539 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2540 2541#define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2542 2543typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 2544{ 2545 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2546 U8 NumInterfaces; /* 0x08 */ 2547 U8 Reserved0; /* 0x09 */ 2548 U16 Reserved1; /* 0x0A */ 2549 U32 Status; /* 0x0C */ 2550 U8 MediaState; /* 0x10 */ 2551 U8 Reserved2; /* 0x11 */ 2552 U16 Reserved3; /* 0x12 */ 2553 U8 MacAddress[6]; /* 0x14 */ 2554 U8 Reserved4; /* 0x1A */ 2555 U8 Reserved5; /* 0x1B */ 2556 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2557 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2558 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2559 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2560 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2561 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2562 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2563} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2564 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2565 2566#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2567 2568/* values for Ethernet Page 0 Status field */ 2569#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2570#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2571#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2572#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2573#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2574#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2575#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2576#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2577#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2578#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2579#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2580#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2581 2582/* values for Ethernet Page 0 MediaState field */ 2583#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2584#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2585#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2586 2587#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2588#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2589#define MPI2_ETHPG0_MS_10MBIT (0x01) 2590#define MPI2_ETHPG0_MS_100MBIT (0x02) 2591#define MPI2_ETHPG0_MS_1GBIT (0x03) 2592 2593 2594/* Ethernet Page 1 */ 2595 2596typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 2597{ 2598 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2599 U32 Reserved0; /* 0x08 */ 2600 U32 Flags; /* 0x0C */ 2601 U8 MediaState; /* 0x10 */ 2602 U8 Reserved1; /* 0x11 */ 2603 U16 Reserved2; /* 0x12 */ 2604 U8 MacAddress[6]; /* 0x14 */ 2605 U8 Reserved3; /* 0x1A */ 2606 U8 Reserved4; /* 0x1B */ 2607 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2608 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2609 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2610 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2611 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2612 U32 Reserved5; /* 0x6C */ 2613 U32 Reserved6; /* 0x70 */ 2614 U32 Reserved7; /* 0x74 */ 2615 U32 Reserved8; /* 0x78 */ 2616 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2617} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2618 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2619 2620#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2621 2622/* values for Ethernet Page 1 Flags field */ 2623#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2624#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2625#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2626#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2627#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2628#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2629#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2630#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2631#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2632 2633/* values for Ethernet Page 1 MediaState field */ 2634#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2635#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2636#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2637 2638#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2639#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2640#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2641#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2642#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2643 2644 2645#endif 2646 2647