1/*-
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: releng/10.3/sys/dev/mlx5/mlx5_ifc.h 290650 2015-11-10 12:20:22Z hselasky $
26
27   Autogenerated file.
28   Date: 2015-04-13 14:59
29   Source Document Name: Mellanox <Doc Name>
30   Source Document Version: 0.28
31   Generated by adb_to_c.py (EAT.ME Version: 1.0.70)
32*/
33#ifndef MLX5_IFC_H
34#define MLX5_IFC_H
35
36enum {
37	MLX5_EVENT_TYPE_COMP                                       = 0x0,
38	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
39	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
40	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
41	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
42	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
43	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
44	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
45	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
46	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
47	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
48	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
49	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
50	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
51	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
52	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
53	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
54	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
55	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
56	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
57	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
58	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
59	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
60	MLX5_EVENT_TYPE_CMD                                        = 0xa,
61	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
62	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd
63};
64
65enum {
66	MLX5_MODIFY_TIR_BITMASK_LRO                                                                                                         = 0x0,
67	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                                                                                              = 0x1,
68	MLX5_MODIFY_TIR_BITMASK_HASH                                                                                                        = 0x2,
69	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                                                                                         = 0x3
70};
71
72enum {
73	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
74};
75
76enum {
77	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
78	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
79	MLX5_CMD_OP_INIT_HCA                      = 0x102,
80	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
81	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
82	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
83	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
84	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
85	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
86	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
87	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
88	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
89	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
90	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
91	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
92	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
93	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
94	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
95	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
96	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
97	MLX5_CMD_OP_GEN_EQE                       = 0x304,
98	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
99	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
100	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
101	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
102	MLX5_CMD_OP_CREATE_QP                     = 0x500,
103	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
104	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
105	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
106	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
107	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
108	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
109	MLX5_CMD_OP_2ERR_QP                       = 0x507,
110	MLX5_CMD_OP_2RST_QP                       = 0x50a,
111	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
112	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
113	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
114	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
115	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
116	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
117	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
118	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
119	MLX5_CMD_OP_ARM_RQ                        = 0x703,
120	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
121	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
122	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
123	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
124	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
125	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
126	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
127	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
128	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
129	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
130	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
131	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
132	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
133	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
134	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
135	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
136	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
137	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
138	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
139	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
140	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
141	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
142	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
143	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
144	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
145	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
146	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
147	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
148	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
149	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
150	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
151	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
152	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
153	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
154	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
155	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
156	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
157	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
158	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
159	MLX5_CMD_OP_NOP                           = 0x80d,
160	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
161	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
162	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
163	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
164	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
165	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
166	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
167	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
168	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
169	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
170	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
171	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
172	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
173	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
174	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
175	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
176	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
177	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
178	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
179	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
180	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
181	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
182	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
183	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
184	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
185	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
186	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
187	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
188	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
189	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
190	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
191	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
192	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
193	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
194	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
195	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
196	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
197	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
198	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
199	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
200	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
201	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
202	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
203	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
204	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
205	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
206	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
207	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
208	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
209	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
210	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
211	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
212	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
213	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
214	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
215	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
216	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b
217};
218
219enum {
220	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
221	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
222	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
223	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
224	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
225	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
226	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
227	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
228	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
229	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
230	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
231	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
232};
233
234struct mlx5_ifc_flow_table_fields_supported_bits {
235	u8         outer_dmac[0x1];
236	u8         outer_smac[0x1];
237	u8         outer_ether_type[0x1];
238	u8         reserved_0[0x1];
239	u8         outer_first_prio[0x1];
240	u8         outer_first_cfi[0x1];
241	u8         outer_first_vid[0x1];
242	u8         reserved_1[0x1];
243	u8         outer_second_prio[0x1];
244	u8         outer_second_cfi[0x1];
245	u8         outer_second_vid[0x1];
246	u8         outer_ipv6_flow_label[0x1];
247	u8         outer_sip[0x1];
248	u8         outer_dip[0x1];
249	u8         outer_frag[0x1];
250	u8         outer_ip_protocol[0x1];
251	u8         outer_ip_ecn[0x1];
252	u8         outer_ip_dscp[0x1];
253	u8         outer_udp_sport[0x1];
254	u8         outer_udp_dport[0x1];
255	u8         outer_tcp_sport[0x1];
256	u8         outer_tcp_dport[0x1];
257	u8         outer_tcp_flags[0x1];
258	u8         outer_gre_protocol[0x1];
259	u8         outer_gre_key[0x1];
260	u8         outer_vxlan_vni[0x1];
261	u8         reserved_2[0x5];
262	u8         source_eswitch_port[0x1];
263
264	u8         inner_dmac[0x1];
265	u8         inner_smac[0x1];
266	u8         inner_ether_type[0x1];
267	u8         reserved_3[0x1];
268	u8         inner_first_prio[0x1];
269	u8         inner_first_cfi[0x1];
270	u8         inner_first_vid[0x1];
271	u8         reserved_4[0x1];
272	u8         inner_second_prio[0x1];
273	u8         inner_second_cfi[0x1];
274	u8         inner_second_vid[0x1];
275	u8         inner_ipv6_flow_label[0x1];
276	u8         inner_sip[0x1];
277	u8         inner_dip[0x1];
278	u8         inner_frag[0x1];
279	u8         inner_ip_protocol[0x1];
280	u8         inner_ip_ecn[0x1];
281	u8         inner_ip_dscp[0x1];
282	u8         inner_udp_sport[0x1];
283	u8         inner_udp_dport[0x1];
284	u8         inner_tcp_sport[0x1];
285	u8         inner_tcp_dport[0x1];
286	u8         inner_tcp_flags[0x1];
287	u8         reserved_5[0x9];
288
289	u8         reserved_6[0x1f];
290	u8         source_sqn[0x1];
291
292	u8         reserved_7[0x20];
293};
294
295struct mlx5_ifc_flow_table_prop_layout_bits {
296	u8         ft_support[0x1];
297	u8         flow_tag[0x1];
298	u8         flow_counter[0x1];
299	u8         flow_modify_en[0x1];
300	u8         modify_root[0x1];
301	u8         reserved_0[0x1b];
302
303	u8         reserved_1[0x2];
304	u8         log_max_ft_size[0x6];
305	u8         reserved_2[0x10];
306	u8         max_ft_level[0x8];
307
308	u8         reserved_3[0x20];
309
310	u8         reserved_4[0x18];
311	u8         log_max_ft_num[0x8];
312
313	u8         reserved_5[0x10];
314	u8         log_max_flow_counter[0x8];
315	u8         log_max_destination[0x8];
316
317	u8         reserved_6[0x18];
318	u8         log_max_flow[0x8];
319
320	u8         reserved_7[0x40];
321
322	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
323
324	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
325};
326
327struct mlx5_ifc_odp_per_transport_service_cap_bits {
328	u8         send[0x1];
329	u8         receive[0x1];
330	u8         write[0x1];
331	u8         read[0x1];
332	u8         atomic[0x1];
333	u8         srq_receive[0x1];
334	u8         reserved_0[0x1a];
335};
336
337struct mlx5_ifc_flow_counter_list_bits {
338	u8         reserved_0[0x10];
339	u8         flow_counter_id[0x10];
340
341	u8         reserved_1[0x20];
342};
343
344enum {
345	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
346	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
347	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
348};
349
350struct mlx5_ifc_dest_format_struct_bits {
351	u8         destination_type[0x8];
352	u8         destination_id[0x18];
353
354	u8         reserved_0[0x20];
355};
356
357struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
358	u8         smac_47_16[0x20];
359
360	u8         smac_15_0[0x10];
361	u8         ethertype[0x10];
362
363	u8         dmac_47_16[0x20];
364
365	u8         dmac_15_0[0x10];
366	u8         first_prio[0x3];
367	u8         first_cfi[0x1];
368	u8         first_vid[0xc];
369
370	u8         ip_protocol[0x8];
371	u8         ip_dscp[0x6];
372	u8         ip_ecn[0x2];
373	u8         vlan_tag[0x1];
374	u8         reserved_0[0x1];
375	u8         frag[0x1];
376	u8         reserved_1[0x4];
377	u8         tcp_flags[0x9];
378
379	u8         tcp_sport[0x10];
380	u8         tcp_dport[0x10];
381
382	u8         reserved_2[0x20];
383
384	u8         udp_sport[0x10];
385	u8         udp_dport[0x10];
386
387	u8         src_ip[4][0x20];
388
389	u8         dst_ip[4][0x20];
390};
391
392struct mlx5_ifc_fte_match_set_misc_bits {
393	u8         reserved_0[0x8];
394	u8         source_sqn[0x18];
395
396	u8         reserved_1[0x10];
397	u8         source_port[0x10];
398
399	u8         outer_second_prio[0x3];
400	u8         outer_second_cfi[0x1];
401	u8         outer_second_vid[0xc];
402	u8         inner_second_prio[0x3];
403	u8         inner_second_cfi[0x1];
404	u8         inner_second_vid[0xc];
405
406	u8         outer_second_vlan_tag[0x1];
407	u8         inner_second_vlan_tag[0x1];
408	u8         reserved_2[0xe];
409	u8         gre_protocol[0x10];
410
411	u8         gre_key_h[0x18];
412	u8         gre_key_l[0x8];
413
414	u8         vxlan_vni[0x18];
415	u8         reserved_3[0x8];
416
417	u8         reserved_4[0x20];
418
419	u8         reserved_5[0xc];
420	u8         outer_ipv6_flow_label[0x14];
421
422	u8         reserved_6[0xc];
423	u8         inner_ipv6_flow_label[0x14];
424
425	u8         reserved_7[0xe0];
426};
427
428struct mlx5_ifc_cmd_pas_bits {
429	u8         pa_h[0x20];
430
431	u8         pa_l[0x14];
432	u8         reserved_0[0xc];
433};
434
435struct mlx5_ifc_uint64_bits {
436	u8         hi[0x20];
437
438	u8         lo[0x20];
439};
440
441struct mlx5_ifc_nodnic_ring_doorbell_bits {
442	u8         reserved_0[0x8];
443	u8         ring_pi[0x10];
444	u8         reserved_1[0x8];
445};
446
447enum {
448	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
449	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
450	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
451	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
452	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
453	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
454	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
455	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
456	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
457	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
458};
459
460struct mlx5_ifc_ads_bits {
461	u8         fl[0x1];
462	u8         free_ar[0x1];
463	u8         reserved_0[0xe];
464	u8         pkey_index[0x10];
465
466	u8         reserved_1[0x8];
467	u8         grh[0x1];
468	u8         mlid[0x7];
469	u8         rlid[0x10];
470
471	u8         ack_timeout[0x5];
472	u8         reserved_2[0x3];
473	u8         src_addr_index[0x8];
474	u8         log_rtm[0x4];
475	u8         stat_rate[0x4];
476	u8         hop_limit[0x8];
477
478	u8         reserved_3[0x4];
479	u8         tclass[0x8];
480	u8         flow_label[0x14];
481
482	u8         rgid_rip[16][0x8];
483
484	u8         reserved_4[0x4];
485	u8         f_dscp[0x1];
486	u8         f_ecn[0x1];
487	u8         reserved_5[0x1];
488	u8         f_eth_prio[0x1];
489	u8         ecn[0x2];
490	u8         dscp[0x6];
491	u8         udp_sport[0x10];
492
493	u8         dei_cfi[0x1];
494	u8         eth_prio[0x3];
495	u8         sl[0x4];
496	u8         port[0x8];
497	u8         rmac_47_32[0x10];
498
499	u8         rmac_31_0[0x20];
500};
501
502struct mlx5_ifc_e_switch_cap_bits {
503	u8         vport_svlan_strip[0x1];
504	u8         vport_cvlan_strip[0x1];
505	u8         vport_svlan_insert[0x1];
506	u8         vport_cvlan_insert_if_not_exist[0x1];
507	u8         vport_cvlan_insert_overwrite[0x1];
508	u8         reserved_0[0x1b];
509
510	u8         reserved_1[0x7e0];
511};
512
513struct mlx5_ifc_flow_table_eswitch_cap_bits {
514	u8         reserved_0[0x200];
515
516	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
517
518	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
519
520	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
521
522	u8         reserved_1[0x7800];
523};
524
525struct mlx5_ifc_flow_table_nic_cap_bits {
526	u8         reserved_0[0x200];
527
528	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
529
530	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
531
532	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
533
534	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
535
536	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
537
538	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
539
540	u8         reserved_1[0x7200];
541};
542
543struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
544	u8         csum_cap[0x1];
545	u8         vlan_cap[0x1];
546	u8         lro_cap[0x1];
547	u8         lro_psh_flag[0x1];
548	u8         lro_time_stamp[0x1];
549	u8         lro_max_msg_sz_mode[0x2];
550	u8         reserved_0[0x2];
551	u8         self_lb_mc[0x1];
552	u8         self_lb_uc[0x1];
553	u8         max_lso_cap[0x5];
554	u8         multi_pkt_send_wqe[0x2];
555	u8         wqe_inline_mode[0x2];
556	u8         rss_ind_tbl_cap[0x4];
557	u8         reserved_1[0x3];
558	u8         tunnel_lso_const_out_ip_id[0x1];
559	u8         tunnel_lro_gre[0x1];
560	u8         tunnel_lro_vxlan[0x1];
561	u8         tunnel_statless_gre[0x1];
562	u8         tunnel_stateless_vxlan[0x1];
563
564	u8         reserved_2[0x20];
565
566	u8         reserved_3[0x10];
567	u8         lro_min_mss_size[0x10];
568
569	u8         reserved_4[0x120];
570
571	u8         lro_timer_supported_periods[4][0x20];
572
573	u8         reserved_5[0x600];
574};
575
576enum {
577	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
578	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
579	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
580};
581
582struct mlx5_ifc_roce_cap_bits {
583	u8         roce_apm[0x1];
584	u8         eth_prio_primary_in_rts2rts[0x1];
585	u8         reserved_0[0x1e];
586
587	u8         reserved_1[0x60];
588
589	u8         reserved_2[0xc];
590	u8         l3_type[0x4];
591	u8         reserved_3[0x8];
592	u8         roce_version[0x8];
593
594	u8         reserved_4[0x10];
595	u8         r_roce_dest_udp_port[0x10];
596
597	u8         r_roce_max_src_udp_port[0x10];
598	u8         r_roce_min_src_udp_port[0x10];
599
600	u8         reserved_5[0x10];
601	u8         roce_address_table_size[0x10];
602
603	u8         reserved_6[0x700];
604};
605
606enum {
607	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
608	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
609	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
610	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
611	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
612	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
613	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
614	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
615	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
616};
617
618enum {
619	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
620	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
621	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
622	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
623	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
624	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
625	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
626	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
627	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
628};
629
630struct mlx5_ifc_atomic_caps_bits {
631	u8         reserved_0[0x40];
632
633	u8         atomic_req_endianess[0x1];
634	u8         reserved_1[0x1f];
635
636	u8         reserved_2[0x20];
637
638	u8         reserved_3[0x10];
639	u8         atomic_operations[0x10];
640
641	u8         reserved_4[0x10];
642	u8         atomic_size_qp[0x10];
643
644	u8         reserved_5[0x10];
645	u8         atomic_size_dc[0x10];
646
647	u8         reserved_6[0x720];
648};
649
650struct mlx5_ifc_odp_cap_bits {
651	u8         reserved_0[0x40];
652
653	u8         sig[0x1];
654	u8         reserved_1[0x1f];
655
656	u8         reserved_2[0x20];
657
658	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
659
660	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
661
662	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
663
664	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
665
666	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
667
668	u8         reserved_3[0x6e0];
669};
670
671enum {
672	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
673	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
674	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
675	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
676	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
677};
678
679enum {
680	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
681	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
682	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
683	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
684	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
685	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
686};
687
688enum {
689	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
690	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
691};
692
693enum {
694	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
695	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
696	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
697};
698
699struct mlx5_ifc_cmd_hca_cap_bits {
700	u8         reserved_0[0x80];
701
702	u8         log_max_srq_sz[0x8];
703	u8         log_max_qp_sz[0x8];
704	u8         reserved_1[0xb];
705	u8         log_max_qp[0x5];
706
707	u8         reserved_2[0xb];
708	u8         log_max_srq[0x5];
709	u8         reserved_3[0x10];
710
711	u8         reserved_4[0x8];
712	u8         log_max_cq_sz[0x8];
713	u8         reserved_5[0xb];
714	u8         log_max_cq[0x5];
715
716	u8         log_max_eq_sz[0x8];
717	u8         reserved_6[0x2];
718	u8         log_max_mkey[0x6];
719	u8         reserved_7[0xc];
720	u8         log_max_eq[0x4];
721
722	u8         max_indirection[0x8];
723	u8         reserved_8[0x1];
724	u8         log_max_mrw_sz[0x7];
725	u8         reserved_9[0x2];
726	u8         log_max_bsf_list_size[0x6];
727	u8         reserved_10[0x2];
728	u8         log_max_klm_list_size[0x6];
729
730	u8         reserved_11[0xa];
731	u8         log_max_ra_req_dc[0x6];
732	u8         reserved_12[0xa];
733	u8         log_max_ra_res_dc[0x6];
734
735	u8         reserved_13[0xa];
736	u8         log_max_ra_req_qp[0x6];
737	u8         reserved_14[0xa];
738	u8         log_max_ra_res_qp[0x6];
739
740	u8         pad_cap[0x1];
741	u8         cc_query_allowed[0x1];
742	u8         cc_modify_allowed[0x1];
743	u8         reserved_15[0xd];
744	u8         gid_table_size[0x10];
745
746	u8         out_of_seq_cnt[0x1];
747	u8         vport_counters[0x1];
748	u8         reserved_16[0x4];
749	u8         max_qp_cnt[0xa];
750	u8         pkey_table_size[0x10];
751
752	u8         vport_group_manager[0x1];
753	u8         vhca_group_manager[0x1];
754	u8         ib_virt[0x1];
755	u8         eth_virt[0x1];
756	u8         reserved_17[0x1];
757	u8         ets[0x1];
758	u8         nic_flow_table[0x1];
759	u8         eswitch_flow_table[0x1];
760	u8         reserved_18[0x3];
761	u8         local_ca_ack_delay[0x5];
762	u8         port_module_event[0x1];
763	u8         reserved_19[0x5];
764	u8         port_type[0x2];
765	u8         num_ports[0x8];
766
767	u8         snapshot[0x1];
768	u8         reserved_20[0x2];
769	u8         log_max_msg[0x5];
770	u8         reserved_21[0x4];
771	u8         max_tc[0x4];
772	u8         reserved_22[0x6];
773	u8         rol_s[0x1];
774	u8         rol_g[0x1];
775	u8         reserved_23[0x1];
776	u8         wol_s[0x1];
777	u8         wol_g[0x1];
778	u8         wol_a[0x1];
779	u8         wol_b[0x1];
780	u8         wol_m[0x1];
781	u8         wol_u[0x1];
782	u8         wol_p[0x1];
783
784	u8         stat_rate_support[0x10];
785	u8         reserved_24[0xc];
786	u8         cqe_version[0x4];
787
788	u8         compact_address_vector[0x1];
789	u8         striding_rq[0x1];
790	u8         reserved_25[0xc];
791	u8         dc_cnak_trace[0x1];
792	u8         drain_sigerr[0x1];
793	u8         cmdif_checksum[0x2];
794	u8         sigerr_cqe[0x1];
795	u8         reserved_26[0x1];
796	u8         wq_signature[0x1];
797	u8         sctr_data_cqe[0x1];
798	u8         reserved_27[0x1];
799	u8         sho[0x1];
800	u8         tph[0x1];
801	u8         rf[0x1];
802	u8         dct[0x1];
803	u8         reserved_28[0x1];
804	u8         eth_net_offloads[0x1];
805	u8         roce[0x1];
806	u8         atomic[0x1];
807	u8         reserved_29[0x1];
808
809	u8         cq_oi[0x1];
810	u8         cq_resize[0x1];
811	u8         cq_moderation[0x1];
812	u8         reserved_30[0x3];
813	u8         cq_eq_remap[0x1];
814	u8         pg[0x1];
815	u8         block_lb_mc[0x1];
816	u8         exponential_backoff[0x1];
817	u8         scqe_break_moderation[0x1];
818	u8         cq_period_start_from_cqe[0x1];
819	u8         cd[0x1];
820	u8         atm[0x1];
821	u8         apm[0x1];
822	u8         reserved_31[0x7];
823	u8         qkv[0x1];
824	u8         pkv[0x1];
825	u8         reserved_32[0x4];
826	u8         xrc[0x1];
827	u8         ud[0x1];
828	u8         uc[0x1];
829	u8         rc[0x1];
830
831	u8         reserved_33[0xa];
832	u8         uar_sz[0x6];
833	u8         reserved_34[0x8];
834	u8         log_pg_sz[0x8];
835
836	u8         bf[0x1];
837	u8         driver_version[0x1];
838	u8         pad_tx_eth_packet[0x1];
839	u8         reserved_35[0x8];
840	u8         log_bf_reg_size[0x5];
841	u8         reserved_36[0x10];
842
843	u8         reserved_37[0x10];
844	u8         max_wqe_sz_sq[0x10];
845
846	u8         reserved_38[0x10];
847	u8         max_wqe_sz_rq[0x10];
848
849	u8         reserved_39[0x10];
850	u8         max_wqe_sz_sq_dc[0x10];
851
852	u8         reserved_40[0x7];
853	u8         max_qp_mcg[0x19];
854
855	u8         reserved_41[0x18];
856	u8         log_max_mcg[0x8];
857
858	u8         reserved_42[0x3];
859	u8         log_max_transport_domain[0x5];
860	u8         reserved_43[0x3];
861	u8         log_max_pd[0x5];
862	u8         reserved_44[0xb];
863	u8         log_max_xrcd[0x5];
864
865	u8         reserved_45[0x10];
866	u8         max_flow_counter[0x10];
867
868	u8         reserved_46[0x3];
869	u8         log_max_rq[0x5];
870	u8         reserved_47[0x3];
871	u8         log_max_sq[0x5];
872	u8         reserved_48[0x3];
873	u8         log_max_tir[0x5];
874	u8         reserved_49[0x3];
875	u8         log_max_tis[0x5];
876
877	u8         basic_cyclic_rcv_wqe[0x1];
878	u8         reserved_50[0x2];
879	u8         log_max_rmp[0x5];
880	u8         reserved_51[0x3];
881	u8         log_max_rqt[0x5];
882	u8         reserved_52[0x3];
883	u8         log_max_rqt_size[0x5];
884	u8         reserved_53[0x3];
885	u8         log_max_tis_per_sq[0x5];
886
887	u8         reserved_54[0x3];
888	u8         log_max_stride_sz_rq[0x5];
889	u8         reserved_55[0x3];
890	u8         log_min_stride_sz_rq[0x5];
891	u8         reserved_56[0x3];
892	u8         log_max_stride_sz_sq[0x5];
893	u8         reserved_57[0x3];
894	u8         log_min_stride_sz_sq[0x5];
895
896	u8         reserved_58[0x1b];
897	u8         log_max_wq_sz[0x5];
898
899	u8         nic_vport_change_event[0x1];
900	u8         reserved_59[0xa];
901	u8         log_max_vlan_list[0x5];
902	u8         reserved_60[0x3];
903	u8         log_max_current_mc_list[0x5];
904	u8         reserved_61[0x3];
905	u8         log_max_current_uc_list[0x5];
906
907	u8         reserved_62[0x80];
908
909	u8         reserved_63[0x3];
910	u8         log_max_l2_table[0x5];
911	u8         reserved_64[0x8];
912	u8         log_uar_page_sz[0x10];
913
914	u8         reserved_65[0x20];
915
916	u8         device_frequency[0x20];
917
918	u8         reserved_66[0xa0];
919
920	u8         log_max_atomic_size_qp[0x8];
921	u8         reserved_67[0x10];
922	u8         log_max_atomic_size_dc[0x8];
923
924	u8         reserved_68[0x1f];
925	u8         cqe_compression[0x1];
926
927	u8         cqe_compression_timeout[0x10];
928	u8         cqe_compression_max_num[0x10];
929
930	u8         reserved_69[0x220];
931};
932
933union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
934	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
935	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
936	u8         reserved_0[0x40];
937};
938
939struct mlx5_ifc_fte_match_param_bits {
940	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
941
942	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
943
944	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
945
946	u8         reserved_0[0xa00];
947};
948
949enum {
950	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
951	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
952	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
953	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
954	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
955};
956
957struct mlx5_ifc_rx_hash_field_select_bits {
958	u8         l3_prot_type[0x1];
959	u8         l4_prot_type[0x1];
960	u8         selected_fields[0x1e];
961};
962
963enum {
964	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
965	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
966	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
967	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
968};
969
970enum {
971	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
972	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
973};
974
975struct mlx5_ifc_wq_bits {
976	u8         wq_type[0x4];
977	u8         wq_signature[0x1];
978	u8         end_padding_mode[0x2];
979	u8         cd_slave[0x1];
980	u8         reserved_0[0x18];
981
982	u8         hds_skip_first_sge[0x1];
983	u8         log2_hds_buf_size[0x3];
984	u8         reserved_1[0x7];
985	u8         page_offset[0x5];
986	u8         lwm[0x10];
987
988	u8         reserved_2[0x8];
989	u8         pd[0x18];
990
991	u8         reserved_3[0x8];
992	u8         uar_page[0x18];
993
994	u8         dbr_addr[0x40];
995
996	u8         hw_counter[0x20];
997
998	u8         sw_counter[0x20];
999
1000	u8         reserved_4[0xc];
1001	u8         log_wq_stride[0x4];
1002	u8         reserved_5[0x3];
1003	u8         log_wq_pg_sz[0x5];
1004	u8         reserved_6[0x3];
1005	u8         log_wq_sz[0x5];
1006
1007	u8         reserved_7[0x15];
1008	u8         single_wqe_log_num_of_strides[0x3];
1009	u8         two_byte_shift_en[0x1];
1010	u8         reserved_8[0x4];
1011	u8         single_stride_log_num_of_bytes[0x3];
1012
1013	u8         reserved_9[0x4c0];
1014
1015	struct mlx5_ifc_cmd_pas_bits pas[0];
1016};
1017
1018struct mlx5_ifc_rq_num_bits {
1019	u8         reserved_0[0x8];
1020	u8         rq_num[0x18];
1021};
1022
1023struct mlx5_ifc_mac_address_layout_bits {
1024	u8         reserved_0[0x10];
1025	u8         mac_addr_47_32[0x10];
1026
1027	u8         mac_addr_31_0[0x20];
1028};
1029
1030struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1031	u8         reserved_0[0xa0];
1032
1033	u8         min_time_between_cnps[0x20];
1034
1035	u8         reserved_1[0x12];
1036	u8         cnp_dscp[0x6];
1037	u8         reserved_2[0x4];
1038	u8         cnp_prio_mode[0x1];
1039	u8         cnp_802p_prio[0x3];
1040
1041	u8         reserved_3[0x720];
1042};
1043
1044struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1045	u8         reserved_0[0x60];
1046
1047	u8         reserved_1[0x4];
1048	u8         clamp_tgt_rate[0x1];
1049	u8         reserved_2[0x3];
1050	u8         clamp_tgt_rate_after_time_inc[0x1];
1051	u8         reserved_3[0x17];
1052
1053	u8         reserved_4[0x20];
1054
1055	u8         rpg_time_reset[0x20];
1056
1057	u8         rpg_byte_reset[0x20];
1058
1059	u8         rpg_threshold[0x20];
1060
1061	u8         rpg_max_rate[0x20];
1062
1063	u8         rpg_ai_rate[0x20];
1064
1065	u8         rpg_hai_rate[0x20];
1066
1067	u8         rpg_gd[0x20];
1068
1069	u8         rpg_min_dec_fac[0x20];
1070
1071	u8         rpg_min_rate[0x20];
1072
1073	u8         reserved_5[0xe0];
1074
1075	u8         rate_to_set_on_first_cnp[0x20];
1076
1077	u8         dce_tcp_g[0x20];
1078
1079	u8         dce_tcp_rtt[0x20];
1080
1081	u8         rate_reduce_monitor_period[0x20];
1082
1083	u8         reserved_6[0x20];
1084
1085	u8         initial_alpha_value[0x20];
1086
1087	u8         reserved_7[0x4a0];
1088};
1089
1090struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1091	u8         reserved_0[0x80];
1092
1093	u8         rppp_max_rps[0x20];
1094
1095	u8         rpg_time_reset[0x20];
1096
1097	u8         rpg_byte_reset[0x20];
1098
1099	u8         rpg_threshold[0x20];
1100
1101	u8         rpg_max_rate[0x20];
1102
1103	u8         rpg_ai_rate[0x20];
1104
1105	u8         rpg_hai_rate[0x20];
1106
1107	u8         rpg_gd[0x20];
1108
1109	u8         rpg_min_dec_fac[0x20];
1110
1111	u8         rpg_min_rate[0x20];
1112
1113	u8         reserved_1[0x640];
1114};
1115
1116enum {
1117	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1118	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1119	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1120};
1121
1122struct mlx5_ifc_resize_field_select_bits {
1123	u8         resize_field_select[0x20];
1124};
1125
1126enum {
1127	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1128	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1129	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1130	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1131};
1132
1133struct mlx5_ifc_modify_field_select_bits {
1134	u8         modify_field_select[0x20];
1135};
1136
1137struct mlx5_ifc_field_select_r_roce_np_bits {
1138	u8         field_select_r_roce_np[0x20];
1139};
1140
1141enum {
1142	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
1143	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
1144	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
1145	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
1146	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
1147	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
1148	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
1149	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
1150	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
1151	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
1152	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
1153	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
1154	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
1155	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
1156	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
1157};
1158
1159struct mlx5_ifc_field_select_r_roce_rp_bits {
1160	u8         field_select_r_roce_rp[0x20];
1161};
1162
1163enum {
1164	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1165	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1166	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1167	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1168	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1169	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1170	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1171	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1172	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1173	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1174};
1175
1176struct mlx5_ifc_field_select_802_1qau_rp_bits {
1177	u8         field_select_8021qaurp[0x20];
1178};
1179
1180struct mlx5_ifc_nodnic_ring_config_reg_bits {
1181	u8         queue_address_63_32[0x20];
1182
1183	u8         queue_address_31_12[0x14];
1184	u8         reserved_0[0x6];
1185	u8         log_size[0x6];
1186
1187	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
1188
1189	u8         reserved_1[0x8];
1190	u8         queue_number[0x18];
1191
1192	u8         q_key[0x20];
1193
1194	u8         reserved_2[0x10];
1195	u8         pkey_index[0x10];
1196
1197	u8         reserved_3[0x40];
1198};
1199
1200struct mlx5_ifc_nodnic_cq_arming_word_bits {
1201	u8         reserved_0[0x8];
1202	u8         cq_ci[0x10];
1203	u8         reserved_1[0x8];
1204};
1205
1206enum {
1207	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
1208	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
1209};
1210
1211enum {
1212	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
1213	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
1214	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
1215	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
1216};
1217
1218struct mlx5_ifc_nodnic_event_word_bits {
1219	u8         driver_reset_needed[0x1];
1220	u8         port_management_change_event[0x1];
1221	u8         reserved_0[0x19];
1222	u8         link_type[0x1];
1223	u8         port_state[0x4];
1224};
1225
1226struct mlx5_ifc_nic_vport_change_event_bits {
1227	u8         reserved_0[0x10];
1228	u8         vport_num[0x10];
1229
1230	u8         reserved_1[0xc0];
1231};
1232
1233struct mlx5_ifc_pages_req_event_bits {
1234	u8         reserved_0[0x10];
1235	u8         function_id[0x10];
1236
1237	u8         num_pages[0x20];
1238
1239	u8         reserved_1[0xa0];
1240};
1241
1242struct mlx5_ifc_cmd_inter_comp_event_bits {
1243	u8         command_completion_vector[0x20];
1244
1245	u8         reserved_0[0xc0];
1246};
1247
1248struct mlx5_ifc_stall_vl_event_bits {
1249	u8         reserved_0[0x18];
1250	u8         port_num[0x1];
1251	u8         reserved_1[0x3];
1252	u8         vl[0x4];
1253
1254	u8         reserved_2[0xa0];
1255};
1256
1257struct mlx5_ifc_db_bf_congestion_event_bits {
1258	u8         event_subtype[0x8];
1259	u8         reserved_0[0x8];
1260	u8         congestion_level[0x8];
1261	u8         reserved_1[0x8];
1262
1263	u8         reserved_2[0xa0];
1264};
1265
1266struct mlx5_ifc_gpio_event_bits {
1267	u8         reserved_0[0x60];
1268
1269	u8         gpio_event_hi[0x20];
1270
1271	u8         gpio_event_lo[0x20];
1272
1273	u8         reserved_1[0x40];
1274};
1275
1276struct mlx5_ifc_port_state_change_event_bits {
1277	u8         reserved_0[0x40];
1278
1279	u8         port_num[0x4];
1280	u8         reserved_1[0x1c];
1281
1282	u8         reserved_2[0x80];
1283};
1284
1285struct mlx5_ifc_dropped_packet_logged_bits {
1286	u8         reserved_0[0xe0];
1287};
1288
1289enum {
1290	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1291	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1292};
1293
1294struct mlx5_ifc_cq_error_bits {
1295	u8         reserved_0[0x8];
1296	u8         cqn[0x18];
1297
1298	u8         reserved_1[0x20];
1299
1300	u8         reserved_2[0x18];
1301	u8         syndrome[0x8];
1302
1303	u8         reserved_3[0x80];
1304};
1305
1306struct mlx5_ifc_rdma_page_fault_event_bits {
1307	u8         bytes_commited[0x20];
1308
1309	u8         r_key[0x20];
1310
1311	u8         reserved_0[0x10];
1312	u8         packet_len[0x10];
1313
1314	u8         rdma_op_len[0x20];
1315
1316	u8         rdma_va[0x40];
1317
1318	u8         reserved_1[0x5];
1319	u8         rdma[0x1];
1320	u8         write[0x1];
1321	u8         requestor[0x1];
1322	u8         qp_number[0x18];
1323};
1324
1325struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1326	u8         bytes_committed[0x20];
1327
1328	u8         reserved_0[0x10];
1329	u8         wqe_index[0x10];
1330
1331	u8         reserved_1[0x10];
1332	u8         len[0x10];
1333
1334	u8         reserved_2[0x60];
1335
1336	u8         reserved_3[0x5];
1337	u8         rdma[0x1];
1338	u8         write_read[0x1];
1339	u8         requestor[0x1];
1340	u8         qpn[0x18];
1341};
1342
1343enum {
1344	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
1345	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
1346	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
1347};
1348
1349struct mlx5_ifc_qp_events_bits {
1350	u8         reserved_0[0xa0];
1351
1352	u8         type[0x8];
1353	u8         reserved_1[0x18];
1354
1355	u8         reserved_2[0x8];
1356	u8         qpn_rqn_sqn[0x18];
1357};
1358
1359struct mlx5_ifc_dct_events_bits {
1360	u8         reserved_0[0xc0];
1361
1362	u8         reserved_1[0x8];
1363	u8         dct_number[0x18];
1364};
1365
1366struct mlx5_ifc_comp_event_bits {
1367	u8         reserved_0[0xc0];
1368
1369	u8         reserved_1[0x8];
1370	u8         cq_number[0x18];
1371};
1372
1373struct mlx5_ifc_fw_version_bits {
1374	u8         major[0x10];
1375	u8         reserved_0[0x10];
1376
1377	u8         minor[0x10];
1378	u8         subminor[0x10];
1379
1380	u8         second[0x8];
1381	u8         minute[0x8];
1382	u8         hour[0x8];
1383	u8         reserved_1[0x8];
1384
1385	u8         year[0x10];
1386	u8         month[0x8];
1387	u8         day[0x8];
1388};
1389
1390enum {
1391	MLX5_QPC_STATE_RST        = 0x0,
1392	MLX5_QPC_STATE_INIT       = 0x1,
1393	MLX5_QPC_STATE_RTR        = 0x2,
1394	MLX5_QPC_STATE_RTS        = 0x3,
1395	MLX5_QPC_STATE_SQER       = 0x4,
1396	MLX5_QPC_STATE_SQD        = 0x5,
1397	MLX5_QPC_STATE_ERR        = 0x6,
1398	MLX5_QPC_STATE_SUSPENDED  = 0x9,
1399};
1400
1401enum {
1402	MLX5_QPC_ST_RC            = 0x0,
1403	MLX5_QPC_ST_UC            = 0x1,
1404	MLX5_QPC_ST_UD            = 0x2,
1405	MLX5_QPC_ST_XRC           = 0x3,
1406	MLX5_QPC_ST_DCI           = 0x5,
1407	MLX5_QPC_ST_QP0           = 0x7,
1408	MLX5_QPC_ST_QP1           = 0x8,
1409	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1410	MLX5_QPC_ST_REG_UMR       = 0xc,
1411};
1412
1413enum {
1414	MLX5_QP_PM_ARMED            = 0x0,
1415	MLX5_QP_PM_REARM            = 0x1,
1416	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1417	MLX5_QP_PM_MIGRATED         = 0x3,
1418};
1419
1420enum {
1421	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1422	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1423};
1424
1425enum {
1426	MLX5_QPC_MTU_256_BYTES        = 0x1,
1427	MLX5_QPC_MTU_512_BYTES        = 0x2,
1428	MLX5_QPC_MTU_1K_BYTES         = 0x3,
1429	MLX5_QPC_MTU_2K_BYTES         = 0x4,
1430	MLX5_QPC_MTU_4K_BYTES         = 0x5,
1431	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1432};
1433
1434enum {
1435	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1436	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1437	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1438	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1439	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1440	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1441	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1442	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1443};
1444
1445enum {
1446	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1447	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1448	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1449};
1450
1451enum {
1452	MLX5_QPC_CS_RES_DISABLE    = 0x0,
1453	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1454	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1455};
1456
1457struct mlx5_ifc_qpc_bits {
1458	u8         state[0x4];
1459	u8         reserved_0[0x4];
1460	u8         st[0x8];
1461	u8         reserved_1[0x3];
1462	u8         pm_state[0x2];
1463	u8         reserved_2[0x7];
1464	u8         end_padding_mode[0x2];
1465	u8         reserved_3[0x2];
1466
1467	u8         wq_signature[0x1];
1468	u8         block_lb_mc[0x1];
1469	u8         atomic_like_write_en[0x1];
1470	u8         latency_sensitive[0x1];
1471	u8         reserved_4[0x1];
1472	u8         drain_sigerr[0x1];
1473	u8         reserved_5[0x2];
1474	u8         pd[0x18];
1475
1476	u8         mtu[0x3];
1477	u8         log_msg_max[0x5];
1478	u8         reserved_6[0x1];
1479	u8         log_rq_size[0x4];
1480	u8         log_rq_stride[0x3];
1481	u8         no_sq[0x1];
1482	u8         log_sq_size[0x4];
1483	u8         reserved_7[0x6];
1484	u8         rlky[0x1];
1485	u8         reserved_8[0x4];
1486
1487	u8         counter_set_id[0x8];
1488	u8         uar_page[0x18];
1489
1490	u8         reserved_9[0x8];
1491	u8         user_index[0x18];
1492
1493	u8         reserved_10[0x3];
1494	u8         log_page_size[0x5];
1495	u8         remote_qpn[0x18];
1496
1497	struct mlx5_ifc_ads_bits primary_address_path;
1498
1499	struct mlx5_ifc_ads_bits secondary_address_path;
1500
1501	u8         log_ack_req_freq[0x4];
1502	u8         reserved_11[0x4];
1503	u8         log_sra_max[0x3];
1504	u8         reserved_12[0x2];
1505	u8         retry_count[0x3];
1506	u8         rnr_retry[0x3];
1507	u8         reserved_13[0x1];
1508	u8         fre[0x1];
1509	u8         cur_rnr_retry[0x3];
1510	u8         cur_retry_count[0x3];
1511	u8         reserved_14[0x5];
1512
1513	u8         reserved_15[0x20];
1514
1515	u8         reserved_16[0x8];
1516	u8         next_send_psn[0x18];
1517
1518	u8         reserved_17[0x8];
1519	u8         cqn_snd[0x18];
1520
1521	u8         reserved_18[0x40];
1522
1523	u8         reserved_19[0x8];
1524	u8         last_acked_psn[0x18];
1525
1526	u8         reserved_20[0x8];
1527	u8         ssn[0x18];
1528
1529	u8         reserved_21[0x8];
1530	u8         log_rra_max[0x3];
1531	u8         reserved_22[0x1];
1532	u8         atomic_mode[0x4];
1533	u8         rre[0x1];
1534	u8         rwe[0x1];
1535	u8         rae[0x1];
1536	u8         reserved_23[0x1];
1537	u8         page_offset[0x6];
1538	u8         reserved_24[0x3];
1539	u8         cd_slave_receive[0x1];
1540	u8         cd_slave_send[0x1];
1541	u8         cd_master[0x1];
1542
1543	u8         reserved_25[0x3];
1544	u8         min_rnr_nak[0x5];
1545	u8         next_rcv_psn[0x18];
1546
1547	u8         reserved_26[0x8];
1548	u8         xrcd[0x18];
1549
1550	u8         reserved_27[0x8];
1551	u8         cqn_rcv[0x18];
1552
1553	u8         dbr_addr[0x40];
1554
1555	u8         q_key[0x20];
1556
1557	u8         reserved_28[0x5];
1558	u8         rq_type[0x3];
1559	u8         srqn_rmpn[0x18];
1560
1561	u8         reserved_29[0x8];
1562	u8         rmsn[0x18];
1563
1564	u8         hw_sq_wqebb_counter[0x10];
1565	u8         sw_sq_wqebb_counter[0x10];
1566
1567	u8         hw_rq_counter[0x20];
1568
1569	u8         sw_rq_counter[0x20];
1570
1571	u8         reserved_30[0x20];
1572
1573	u8         reserved_31[0xf];
1574	u8         cgs[0x1];
1575	u8         cs_req[0x8];
1576	u8         cs_res[0x8];
1577
1578	u8         dc_access_key[0x40];
1579
1580	u8         rdma_active[0x1];
1581	u8         comm_est[0x1];
1582	u8         suspended[0x1];
1583	u8         reserved_32[0x5];
1584	u8         send_msg_psn[0x18];
1585
1586	u8         reserved_33[0x8];
1587	u8         rcv_msg_psn[0x18];
1588
1589	u8         rdma_va[0x40];
1590
1591	u8         rdma_key[0x20];
1592
1593	u8         reserved_34[0x20];
1594};
1595
1596struct mlx5_ifc_roce_addr_layout_bits {
1597	u8         source_l3_address[16][0x8];
1598
1599	u8         reserved_0[0x3];
1600	u8         vlan_valid[0x1];
1601	u8         vlan_id[0xc];
1602	u8         source_mac_47_32[0x10];
1603
1604	u8         source_mac_31_0[0x20];
1605
1606	u8         reserved_1[0x14];
1607	u8         roce_l3_type[0x4];
1608	u8         roce_version[0x8];
1609
1610	u8         reserved_2[0x20];
1611};
1612
1613struct mlx5_ifc_rdbc_bits {
1614	u8         reserved_0[0x1c];
1615	u8         type[0x4];
1616
1617	u8         reserved_1[0x20];
1618
1619	u8         reserved_2[0x8];
1620	u8         psn[0x18];
1621
1622	u8         rkey[0x20];
1623
1624	u8         address[0x40];
1625
1626	u8         byte_count[0x20];
1627
1628	u8         reserved_3[0x20];
1629
1630	u8         atomic_resp[32][0x8];
1631};
1632
1633enum {
1634	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1635	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1636	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1637	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
1638};
1639
1640struct mlx5_ifc_flow_context_bits {
1641	u8         reserved_0[0x20];
1642
1643	u8         group_id[0x20];
1644
1645	u8         reserved_1[0x8];
1646	u8         flow_tag[0x18];
1647
1648	u8         reserved_2[0x10];
1649	u8         action[0x10];
1650
1651	u8         reserved_3[0x8];
1652	u8         destination_list_size[0x18];
1653
1654	u8         reserved_4[0x8];
1655	u8         flow_counter_list_size[0x18];
1656
1657	u8         reserved_5[0x140];
1658
1659	struct mlx5_ifc_fte_match_param_bits match_value;
1660
1661	u8         reserved_6[0x600];
1662
1663	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
1664};
1665
1666enum {
1667	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1668	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1669};
1670
1671struct mlx5_ifc_xrc_srqc_bits {
1672	u8         state[0x4];
1673	u8         log_xrc_srq_size[0x4];
1674	u8         reserved_0[0x18];
1675
1676	u8         wq_signature[0x1];
1677	u8         cont_srq[0x1];
1678	u8         reserved_1[0x1];
1679	u8         rlky[0x1];
1680	u8         basic_cyclic_rcv_wqe[0x1];
1681	u8         log_rq_stride[0x3];
1682	u8         xrcd[0x18];
1683
1684	u8         page_offset[0x6];
1685	u8         reserved_2[0x2];
1686	u8         cqn[0x18];
1687
1688	u8         reserved_3[0x20];
1689
1690	u8         reserved_4[0x2];
1691	u8         log_page_size[0x6];
1692	u8         user_index[0x18];
1693
1694	u8         reserved_5[0x20];
1695
1696	u8         reserved_6[0x8];
1697	u8         pd[0x18];
1698
1699	u8         lwm[0x10];
1700	u8         wqe_cnt[0x10];
1701
1702	u8         reserved_7[0x40];
1703
1704	u8         db_record_addr_h[0x20];
1705
1706	u8         db_record_addr_l[0x1e];
1707	u8         reserved_8[0x2];
1708
1709	u8         reserved_9[0x80];
1710};
1711
1712struct mlx5_ifc_traffic_counter_bits {
1713	u8         packets[0x40];
1714
1715	u8         octets[0x40];
1716};
1717
1718struct mlx5_ifc_tisc_bits {
1719	u8         reserved_0[0xc];
1720	u8         prio[0x4];
1721	u8         reserved_1[0x10];
1722
1723	u8         reserved_2[0x100];
1724
1725	u8         reserved_3[0x8];
1726	u8         transport_domain[0x18];
1727
1728	u8         reserved_4[0x3c0];
1729};
1730
1731enum {
1732	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1733	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1734};
1735
1736enum {
1737	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1738	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1739};
1740
1741enum {
1742	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
1743	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
1744	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
1745};
1746
1747enum {
1748	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
1749	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
1750};
1751
1752struct mlx5_ifc_tirc_bits {
1753	u8         reserved_0[0x20];
1754
1755	u8         disp_type[0x4];
1756	u8         reserved_1[0x1c];
1757
1758	u8         reserved_2[0x40];
1759
1760	u8         reserved_3[0x4];
1761	u8         lro_timeout_period_usecs[0x10];
1762	u8         lro_enable_mask[0x4];
1763	u8         lro_max_msg_sz[0x8];
1764
1765	u8         reserved_4[0x40];
1766
1767	u8         reserved_5[0x8];
1768	u8         inline_rqn[0x18];
1769
1770	u8         rx_hash_symmetric[0x1];
1771	u8         reserved_6[0x1];
1772	u8         tunneled_offload_en[0x1];
1773	u8         reserved_7[0x5];
1774	u8         indirect_table[0x18];
1775
1776	u8         rx_hash_fn[0x4];
1777	u8         reserved_8[0x2];
1778	u8         self_lb_en[0x2];
1779	u8         transport_domain[0x18];
1780
1781	u8         rx_hash_toeplitz_key[10][0x20];
1782
1783	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1784
1785	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1786
1787	u8         reserved_9[0x4c0];
1788};
1789
1790enum {
1791	MLX5_SRQC_STATE_GOOD   = 0x0,
1792	MLX5_SRQC_STATE_ERROR  = 0x1,
1793};
1794
1795struct mlx5_ifc_srqc_bits {
1796	u8         state[0x4];
1797	u8         log_srq_size[0x4];
1798	u8         reserved_0[0x18];
1799
1800	u8         wq_signature[0x1];
1801	u8         cont_srq[0x1];
1802	u8         reserved_1[0x1];
1803	u8         rlky[0x1];
1804	u8         reserved_2[0x1];
1805	u8         log_rq_stride[0x3];
1806	u8         xrcd[0x18];
1807
1808	u8         page_offset[0x6];
1809	u8         reserved_3[0x2];
1810	u8         cqn[0x18];
1811
1812	u8         reserved_4[0x20];
1813
1814	u8         reserved_5[0x2];
1815	u8         log_page_size[0x6];
1816	u8         reserved_6[0x18];
1817
1818	u8         reserved_7[0x20];
1819
1820	u8         reserved_8[0x8];
1821	u8         pd[0x18];
1822
1823	u8         lwm[0x10];
1824	u8         wqe_cnt[0x10];
1825
1826	u8         reserved_9[0x40];
1827
1828	u8         db_record_addr_h[0x20];
1829
1830	u8         db_record_addr_l[0x1e];
1831	u8         reserved_10[0x2];
1832
1833	u8         reserved_11[0x80];
1834};
1835
1836enum {
1837	MLX5_SQC_STATE_RST  = 0x0,
1838	MLX5_SQC_STATE_RDY  = 0x1,
1839	MLX5_SQC_STATE_ERR  = 0x3,
1840};
1841
1842struct mlx5_ifc_sqc_bits {
1843	u8         rlky[0x1];
1844	u8         cd_master[0x1];
1845	u8         fre[0x1];
1846	u8         flush_in_error_en[0x1];
1847	u8         allow_multi_pkt_send_wqe[0x1];
1848	u8         min_wqe_inline_mode[0x3];
1849	u8         state[0x4];
1850	u8         reserved_0[0x14];
1851
1852	u8         reserved_1[0x8];
1853	u8         user_index[0x18];
1854
1855	u8         reserved_2[0x8];
1856	u8         cqn[0x18];
1857
1858	u8         reserved_3[0xa0];
1859
1860	u8         tis_lst_sz[0x10];
1861	u8         reserved_4[0x10];
1862
1863	u8         reserved_5[0x40];
1864
1865	u8         reserved_6[0x8];
1866	u8         tis_num_0[0x18];
1867
1868	struct mlx5_ifc_wq_bits wq;
1869};
1870
1871struct mlx5_ifc_rqtc_bits {
1872	u8         reserved_0[0xa0];
1873
1874	u8         reserved_1[0x10];
1875	u8         rqt_max_size[0x10];
1876
1877	u8         reserved_2[0x10];
1878	u8         rqt_actual_size[0x10];
1879
1880	u8         reserved_3[0x6a0];
1881
1882	struct mlx5_ifc_rq_num_bits rq_num[0];
1883};
1884
1885enum {
1886	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
1887	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
1888};
1889
1890enum {
1891	MLX5_RQC_STATE_RST  = 0x0,
1892	MLX5_RQC_STATE_RDY  = 0x1,
1893	MLX5_RQC_STATE_ERR  = 0x3,
1894};
1895
1896struct mlx5_ifc_rqc_bits {
1897	u8         rlky[0x1];
1898	u8         reserved_0[0x2];
1899	u8         vlan_strip_disable[0x1];
1900	u8         mem_rq_type[0x4];
1901	u8         state[0x4];
1902	u8         reserved_1[0x1];
1903	u8         flush_in_error_en[0x1];
1904	u8         reserved_2[0x12];
1905
1906	u8         reserved_3[0x8];
1907	u8         user_index[0x18];
1908
1909	u8         reserved_4[0x8];
1910	u8         cqn[0x18];
1911
1912	u8         counter_set_id[0x8];
1913	u8         reserved_5[0x18];
1914
1915	u8         reserved_6[0x8];
1916	u8         rmpn[0x18];
1917
1918	u8         reserved_7[0xe0];
1919
1920	struct mlx5_ifc_wq_bits wq;
1921};
1922
1923enum {
1924	MLX5_RMPC_STATE_RDY  = 0x1,
1925	MLX5_RMPC_STATE_ERR  = 0x3,
1926};
1927
1928struct mlx5_ifc_rmpc_bits {
1929	u8         reserved_0[0x8];
1930	u8         state[0x4];
1931	u8         reserved_1[0x14];
1932
1933	u8         basic_cyclic_rcv_wqe[0x1];
1934	u8         reserved_2[0x1f];
1935
1936	u8         reserved_3[0x140];
1937
1938	struct mlx5_ifc_wq_bits wq;
1939};
1940
1941enum {
1942	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
1943	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
1944	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
1945};
1946
1947struct mlx5_ifc_nic_vport_context_bits {
1948	u8         reserved_0[0x5];
1949	u8         min_wqe_inline_mode[0x3];
1950	u8         reserved_1[0x17];
1951	u8         roce_en[0x1];
1952
1953	u8         arm_change_event[0x1];
1954	u8         reserved_2[0x1a];
1955	u8         event_on_mtu[0x1];
1956	u8         event_on_promisc_change[0x1];
1957	u8         event_on_vlan_change[0x1];
1958	u8         event_on_mc_address_change[0x1];
1959	u8         event_on_uc_address_change[0x1];
1960
1961	u8         reserved_3[0xe0];
1962
1963	u8         reserved_4[0x10];
1964	u8         mtu[0x10];
1965
1966	u8         system_image_guid[0x40];
1967
1968	u8         port_guid[0x40];
1969
1970	u8         node_guid[0x40];
1971
1972	u8         reserved_5[0x140];
1973
1974	u8         qkey_violation_counter[0x10];
1975	u8         reserved_6[0x10];
1976
1977	u8         reserved_7[0x420];
1978
1979	u8         promisc_uc[0x1];
1980	u8         promisc_mc[0x1];
1981	u8         promisc_all[0x1];
1982	u8         reserved_8[0x2];
1983	u8         allowed_list_type[0x3];
1984	u8         reserved_9[0xc];
1985	u8         allowed_list_size[0xc];
1986
1987	struct mlx5_ifc_mac_address_layout_bits permanent_address;
1988
1989	u8         reserved_10[0x20];
1990
1991	u8         current_uc_mac_address[0][0x40];
1992};
1993
1994enum {
1995	MLX5_ACCESS_MODE_PA        = 0x0,
1996	MLX5_ACCESS_MODE_MTT       = 0x1,
1997	MLX5_ACCESS_MODE_KLM       = 0x2,
1998};
1999
2000struct mlx5_ifc_mkc_bits {
2001	u8         reserved_0[0x1];
2002	u8         free[0x1];
2003	u8         reserved_1[0xd];
2004	u8         small_fence_on_rdma_read_response[0x1];
2005	u8         umr_en[0x1];
2006	u8         a[0x1];
2007	u8         rw[0x1];
2008	u8         rr[0x1];
2009	u8         lw[0x1];
2010	u8         lr[0x1];
2011	u8         access_mode[0x2];
2012	u8         reserved_2[0x8];
2013
2014	u8         qpn[0x18];
2015	u8         mkey_7_0[0x8];
2016
2017	u8         reserved_3[0x20];
2018
2019	u8         length64[0x1];
2020	u8         bsf_en[0x1];
2021	u8         sync_umr[0x1];
2022	u8         reserved_4[0x2];
2023	u8         expected_sigerr_count[0x1];
2024	u8         reserved_5[0x1];
2025	u8         en_rinval[0x1];
2026	u8         pd[0x18];
2027
2028	u8         start_addr[0x40];
2029
2030	u8         len[0x40];
2031
2032	u8         bsf_octword_size[0x20];
2033
2034	u8         reserved_6[0x80];
2035
2036	u8         translations_octword_size[0x20];
2037
2038	u8         reserved_7[0x1b];
2039	u8         log_page_size[0x5];
2040
2041	u8         reserved_8[0x20];
2042};
2043
2044struct mlx5_ifc_pkey_bits {
2045	u8         reserved_0[0x10];
2046	u8         pkey[0x10];
2047};
2048
2049struct mlx5_ifc_array128_auto_bits {
2050	u8         array128_auto[16][0x8];
2051};
2052
2053enum {
2054	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
2055	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
2056	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
2057};
2058
2059enum {
2060	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
2061	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
2062	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
2063	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
2064	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
2065	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
2066	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
2067};
2068
2069enum {
2070	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
2071	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
2072	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
2073};
2074
2075enum {
2076	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
2077	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
2078	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
2079	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
2080};
2081
2082enum {
2083	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
2084	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
2085	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
2086	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
2087};
2088
2089struct mlx5_ifc_hca_vport_context_bits {
2090	u8         field_select[0x20];
2091
2092	u8         reserved_0[0xe0];
2093
2094	u8         sm_virt_aware[0x1];
2095	u8         has_smi[0x1];
2096	u8         has_raw[0x1];
2097	u8         grh_required[0x1];
2098	u8         reserved_1[0xc];
2099	u8         port_physical_state[0x4];
2100	u8         vport_state_policy[0x4];
2101	u8         port_state[0x4];
2102	u8         vport_state[0x4];
2103
2104	u8         reserved_2[0x20];
2105
2106	u8         system_image_guid[0x40];
2107
2108	u8         port_guid[0x40];
2109
2110	u8         node_guid[0x40];
2111
2112	u8         cap_mask1[0x20];
2113
2114	u8         cap_mask1_field_select[0x20];
2115
2116	u8         cap_mask2[0x20];
2117
2118	u8         cap_mask2_field_select[0x20];
2119
2120	u8         reserved_3[0x80];
2121
2122	u8         lid[0x10];
2123	u8         reserved_4[0x4];
2124	u8         init_type_reply[0x4];
2125	u8         lmc[0x3];
2126	u8         subnet_timeout[0x5];
2127
2128	u8         sm_lid[0x10];
2129	u8         sm_sl[0x4];
2130	u8         reserved_5[0xc];
2131
2132	u8         qkey_violation_counter[0x10];
2133	u8         pkey_violation_counter[0x10];
2134
2135	u8         reserved_6[0xca0];
2136};
2137
2138union mlx5_ifc_hca_cap_union_bits {
2139	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2140	struct mlx5_ifc_odp_cap_bits odp_cap;
2141	struct mlx5_ifc_atomic_caps_bits atomic_caps;
2142	struct mlx5_ifc_roce_cap_bits roce_cap;
2143	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2144	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2145	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2146	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2147	u8         reserved_0[0x8000];
2148};
2149
2150struct mlx5_ifc_esw_vport_context_bits {
2151	u8         reserved_0[0x3];
2152	u8         vport_svlan_strip[0x1];
2153	u8         vport_cvlan_strip[0x1];
2154	u8         vport_svlan_insert[0x1];
2155	u8         vport_cvlan_insert[0x2];
2156	u8         reserved_1[0x18];
2157
2158	u8         reserved_2[0x20];
2159
2160	u8         svlan_cfi[0x1];
2161	u8         svlan_pcp[0x3];
2162	u8         svlan_id[0xc];
2163	u8         cvlan_cfi[0x1];
2164	u8         cvlan_pcp[0x3];
2165	u8         cvlan_id[0xc];
2166
2167	u8         reserved_3[0x7a0];
2168};
2169
2170enum {
2171	MLX5_EQC_STATUS_OK                = 0x0,
2172	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2173};
2174
2175enum {
2176	MLX5_EQ_STATE_ARMED = 0x9,
2177	MLX5_EQ_STATE_FIRED = 0xa,
2178};
2179
2180struct mlx5_ifc_eqc_bits {
2181	u8         status[0x4];
2182	u8         reserved_0[0x9];
2183	u8         ec[0x1];
2184	u8         oi[0x1];
2185	u8         reserved_1[0x5];
2186	u8         st[0x4];
2187	u8         reserved_2[0x8];
2188
2189	u8         reserved_3[0x20];
2190
2191	u8         reserved_4[0x14];
2192	u8         page_offset[0x6];
2193	u8         reserved_5[0x6];
2194
2195	u8         reserved_6[0x3];
2196	u8         log_eq_size[0x5];
2197	u8         uar_page[0x18];
2198
2199	u8         reserved_7[0x20];
2200
2201	u8         reserved_8[0x18];
2202	u8         intr[0x8];
2203
2204	u8         reserved_9[0x3];
2205	u8         log_page_size[0x5];
2206	u8         reserved_10[0x18];
2207
2208	u8         reserved_11[0x60];
2209
2210	u8         reserved_12[0x8];
2211	u8         consumer_counter[0x18];
2212
2213	u8         reserved_13[0x8];
2214	u8         producer_counter[0x18];
2215
2216	u8         reserved_14[0x80];
2217};
2218
2219enum {
2220	MLX5_DCTC_STATE_ACTIVE    = 0x0,
2221	MLX5_DCTC_STATE_DRAINING  = 0x1,
2222	MLX5_DCTC_STATE_DRAINED   = 0x2,
2223};
2224
2225enum {
2226	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2227	MLX5_DCTC_CS_RES_NA         = 0x1,
2228	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2229};
2230
2231enum {
2232	MLX5_DCTC_MTU_256_BYTES  = 0x1,
2233	MLX5_DCTC_MTU_512_BYTES  = 0x2,
2234	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2235	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2236	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2237};
2238
2239struct mlx5_ifc_dctc_bits {
2240	u8         reserved_0[0x4];
2241	u8         state[0x4];
2242	u8         reserved_1[0x18];
2243
2244	u8         reserved_2[0x8];
2245	u8         user_index[0x18];
2246
2247	u8         reserved_3[0x8];
2248	u8         cqn[0x18];
2249
2250	u8         counter_set_id[0x8];
2251	u8         atomic_mode[0x4];
2252	u8         rre[0x1];
2253	u8         rwe[0x1];
2254	u8         rae[0x1];
2255	u8         atomic_like_write_en[0x1];
2256	u8         latency_sensitive[0x1];
2257	u8         rlky[0x1];
2258	u8         reserved_4[0xe];
2259
2260	u8         reserved_5[0x8];
2261	u8         cs_res[0x8];
2262	u8         reserved_6[0x3];
2263	u8         min_rnr_nak[0x5];
2264	u8         reserved_7[0x8];
2265
2266	u8         reserved_8[0x8];
2267	u8         srqn[0x18];
2268
2269	u8         reserved_9[0x8];
2270	u8         pd[0x18];
2271
2272	u8         tclass[0x8];
2273	u8         reserved_10[0x4];
2274	u8         flow_label[0x14];
2275
2276	u8         dc_access_key[0x40];
2277
2278	u8         reserved_11[0x5];
2279	u8         mtu[0x3];
2280	u8         port[0x8];
2281	u8         pkey_index[0x10];
2282
2283	u8         reserved_12[0x8];
2284	u8         my_addr_index[0x8];
2285	u8         reserved_13[0x8];
2286	u8         hop_limit[0x8];
2287
2288	u8         dc_access_key_violation_count[0x20];
2289
2290	u8         reserved_14[0x14];
2291	u8         dei_cfi[0x1];
2292	u8         eth_prio[0x3];
2293	u8         ecn[0x2];
2294	u8         dscp[0x6];
2295
2296	u8         reserved_15[0x40];
2297};
2298
2299enum {
2300	MLX5_CQC_STATUS_OK             = 0x0,
2301	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2302	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2303};
2304
2305enum {
2306	CQE_SIZE_64                = 0x0,
2307	CQE_SIZE_128               = 0x1,
2308};
2309
2310enum {
2311	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
2312	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
2313};
2314
2315enum {
2316	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
2317	MLX5_CQ_STATE_ARMED                               = 0x9,
2318	MLX5_CQ_STATE_FIRED                               = 0xa,
2319};
2320
2321struct mlx5_ifc_cqc_bits {
2322	u8         status[0x4];
2323	u8         reserved_0[0x4];
2324	u8         cqe_sz[0x3];
2325	u8         cc[0x1];
2326	u8         reserved_1[0x1];
2327	u8         scqe_break_moderation_en[0x1];
2328	u8         oi[0x1];
2329	u8         cq_period_mode[0x2];
2330	u8         cqe_compression_en[0x1];
2331	u8         mini_cqe_res_format[0x2];
2332	u8         st[0x4];
2333	u8         reserved_2[0x8];
2334
2335	u8         reserved_3[0x20];
2336
2337	u8         reserved_4[0x14];
2338	u8         page_offset[0x6];
2339	u8         reserved_5[0x6];
2340
2341	u8         reserved_6[0x3];
2342	u8         log_cq_size[0x5];
2343	u8         uar_page[0x18];
2344
2345	u8         reserved_7[0x4];
2346	u8         cq_period[0xc];
2347	u8         cq_max_count[0x10];
2348
2349	u8         reserved_8[0x18];
2350	u8         c_eqn[0x8];
2351
2352	u8         reserved_9[0x3];
2353	u8         log_page_size[0x5];
2354	u8         reserved_10[0x18];
2355
2356	u8         reserved_11[0x20];
2357
2358	u8         reserved_12[0x8];
2359	u8         last_notified_index[0x18];
2360
2361	u8         reserved_13[0x8];
2362	u8         last_solicit_index[0x18];
2363
2364	u8         reserved_14[0x8];
2365	u8         consumer_counter[0x18];
2366
2367	u8         reserved_15[0x8];
2368	u8         producer_counter[0x18];
2369
2370	u8         reserved_16[0x40];
2371
2372	u8         dbr_addr[0x40];
2373};
2374
2375union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2376	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2377	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2378	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2379	u8         reserved_0[0x800];
2380};
2381
2382struct mlx5_ifc_query_adapter_param_block_bits {
2383	u8         reserved_0[0xc0];
2384
2385	u8         reserved_1[0x8];
2386	u8         ieee_vendor_id[0x18];
2387
2388	u8         reserved_2[0x10];
2389	u8         vsd_vendor_id[0x10];
2390
2391	u8         vsd[208][0x8];
2392
2393	u8         vsd_contd_psid[16][0x8];
2394};
2395
2396union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2397	struct mlx5_ifc_modify_field_select_bits modify_field_select;
2398	struct mlx5_ifc_resize_field_select_bits resize_field_select;
2399	u8         reserved_0[0x20];
2400};
2401
2402union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2403	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2404	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2405	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2406	u8         reserved_0[0x20];
2407};
2408
2409struct mlx5_ifc_bufferx_reg_bits {
2410	u8         reserved_0[0x6];
2411	u8         lossy[0x1];
2412	u8         epsb[0x1];
2413	u8         reserved_1[0xc];
2414	u8         size[0xc];
2415
2416	u8         xoff_threshold[0x10];
2417	u8         xon_threshold[0x10];
2418};
2419
2420struct mlx5_ifc_config_item_bits {
2421	u8         valid[0x2];
2422	u8         reserved_0[0x2];
2423	u8         header_type[0x2];
2424	u8         reserved_1[0x2];
2425	u8         default_location[0x1];
2426	u8         reserved_2[0x7];
2427	u8         version[0x4];
2428	u8         reserved_3[0x3];
2429	u8         length[0x9];
2430
2431	u8         type[0x20];
2432
2433	u8         reserved_4[0x10];
2434	u8         crc16[0x10];
2435};
2436
2437struct mlx5_ifc_nodnic_port_config_reg_bits {
2438	struct mlx5_ifc_nodnic_event_word_bits event;
2439
2440	u8         network_en[0x1];
2441	u8         dma_en[0x1];
2442	u8         promisc_en[0x1];
2443	u8         promisc_multicast_en[0x1];
2444	u8         reserved_0[0x17];
2445	u8         receive_filter_en[0x5];
2446
2447	u8         reserved_1[0x10];
2448	u8         mac_47_32[0x10];
2449
2450	u8         mac_31_0[0x20];
2451
2452	u8         receive_filters_mgid_mac[64][0x8];
2453
2454	u8         gid[16][0x8];
2455
2456	u8         reserved_2[0x10];
2457	u8         lid[0x10];
2458
2459	u8         reserved_3[0xc];
2460	u8         sm_sl[0x4];
2461	u8         sm_lid[0x10];
2462
2463	u8         completion_address_63_32[0x20];
2464
2465	u8         completion_address_31_12[0x14];
2466	u8         reserved_4[0x6];
2467	u8         log_cq_size[0x6];
2468
2469	u8         working_buffer_address_63_32[0x20];
2470
2471	u8         working_buffer_address_31_12[0x14];
2472	u8         reserved_5[0xc];
2473
2474	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
2475
2476	u8         pkey_index[0x10];
2477	u8         pkey[0x10];
2478
2479	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
2480
2481	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
2482
2483	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
2484
2485	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
2486
2487	u8         reserved_6[0x400];
2488};
2489
2490union mlx5_ifc_event_auto_bits {
2491	struct mlx5_ifc_comp_event_bits comp_event;
2492	struct mlx5_ifc_dct_events_bits dct_events;
2493	struct mlx5_ifc_qp_events_bits qp_events;
2494	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2495	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2496	struct mlx5_ifc_cq_error_bits cq_error;
2497	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2498	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2499	struct mlx5_ifc_gpio_event_bits gpio_event;
2500	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2501	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2502	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2503	struct mlx5_ifc_pages_req_event_bits pages_req_event;
2504	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
2505	u8         reserved_0[0xe0];
2506};
2507
2508struct mlx5_ifc_health_buffer_bits {
2509	u8         reserved_0[0x100];
2510
2511	u8         assert_existptr[0x20];
2512
2513	u8         assert_callra[0x20];
2514
2515	u8         reserved_1[0x40];
2516
2517	u8         fw_version[0x20];
2518
2519	u8         hw_id[0x20];
2520
2521	u8         reserved_2[0x20];
2522
2523	u8         irisc_index[0x8];
2524	u8         synd[0x8];
2525	u8         ext_synd[0x10];
2526};
2527
2528struct mlx5_ifc_register_loopback_control_bits {
2529	u8         no_lb[0x1];
2530	u8         reserved_0[0x7];
2531	u8         port[0x8];
2532	u8         reserved_1[0x10];
2533
2534	u8         reserved_2[0x60];
2535};
2536
2537struct mlx5_ifc_icmd_set_wol_rol_out_bits {
2538	u8         reserved_0[0x40];
2539
2540	u8         reserved_1[0x10];
2541	u8         rol_mode[0x8];
2542	u8         wol_mode[0x8];
2543};
2544
2545struct mlx5_ifc_icmd_set_wol_rol_in_bits {
2546	u8         reserved_0[0x40];
2547
2548	u8         rol_mode_valid[0x1];
2549	u8         wol_mode_valid[0x1];
2550	u8         reserved_1[0xe];
2551	u8         rol_mode[0x8];
2552	u8         wol_mode[0x8];
2553
2554	u8         reserved_2[0x7a0];
2555};
2556
2557struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
2558	u8         virtual_mac_en[0x1];
2559	u8         mac_aux_v[0x1];
2560	u8         reserved_0[0x1e];
2561
2562	u8         reserved_1[0x40];
2563
2564	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2565
2566	u8         reserved_2[0x760];
2567};
2568
2569struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
2570	u8         virtual_mac_en[0x1];
2571	u8         mac_aux_v[0x1];
2572	u8         reserved_0[0x1e];
2573
2574	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
2575
2576	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
2577
2578	u8         reserved_1[0x760];
2579};
2580
2581struct mlx5_ifc_icmd_query_fw_info_out_bits {
2582	struct mlx5_ifc_fw_version_bits fw_version;
2583
2584	u8         reserved_0[0x10];
2585	u8         hash_signature[0x10];
2586
2587	u8         psid[16][0x8];
2588
2589	u8         reserved_1[0x6e0];
2590};
2591
2592struct mlx5_ifc_icmd_query_cap_in_bits {
2593	u8         reserved_0[0x10];
2594	u8         capability_group[0x10];
2595};
2596
2597struct mlx5_ifc_icmd_query_cap_general_bits {
2598	u8         nv_access[0x1];
2599	u8         fw_info_psid[0x1];
2600	u8         reserved_0[0x1e];
2601
2602	u8         reserved_1[0x16];
2603	u8         rol_s[0x1];
2604	u8         rol_g[0x1];
2605	u8         reserved_2[0x1];
2606	u8         wol_s[0x1];
2607	u8         wol_g[0x1];
2608	u8         wol_a[0x1];
2609	u8         wol_b[0x1];
2610	u8         wol_m[0x1];
2611	u8         wol_u[0x1];
2612	u8         wol_p[0x1];
2613};
2614
2615struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
2616	u8         status[0x8];
2617	u8         reserved_0[0x18];
2618
2619	u8         reserved_1[0x7e0];
2620};
2621
2622struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
2623	u8         status[0x8];
2624	u8         reserved_0[0x18];
2625
2626	u8         reserved_1[0x7e0];
2627};
2628
2629struct mlx5_ifc_icmd_ocbb_init_in_bits {
2630	u8         address_hi[0x20];
2631
2632	u8         address_lo[0x20];
2633
2634	u8         reserved_0[0x7c0];
2635};
2636
2637struct mlx5_ifc_icmd_init_ocsd_in_bits {
2638	u8         reserved_0[0x20];
2639
2640	u8         address_hi[0x20];
2641
2642	u8         address_lo[0x20];
2643
2644	u8         reserved_1[0x7a0];
2645};
2646
2647struct mlx5_ifc_icmd_access_reg_out_bits {
2648	u8         reserved_0[0x11];
2649	u8         status[0x7];
2650	u8         reserved_1[0x8];
2651
2652	u8         register_id[0x10];
2653	u8         reserved_2[0x10];
2654
2655	u8         reserved_3[0x40];
2656
2657	u8         reserved_4[0x5];
2658	u8         len[0xb];
2659	u8         reserved_5[0x10];
2660
2661	u8         register_data[0][0x20];
2662};
2663
2664enum {
2665	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
2666	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
2667};
2668
2669struct mlx5_ifc_icmd_access_reg_in_bits {
2670	u8         constant_1[0x5];
2671	u8         constant_2[0xb];
2672	u8         reserved_0[0x10];
2673
2674	u8         register_id[0x10];
2675	u8         reserved_1[0x1];
2676	u8         method[0x7];
2677	u8         constant_3[0x8];
2678
2679	u8         reserved_2[0x40];
2680
2681	u8         constant_4[0x5];
2682	u8         len[0xb];
2683	u8         reserved_3[0x10];
2684
2685	u8         register_data[0][0x20];
2686};
2687
2688struct mlx5_ifc_teardown_hca_out_bits {
2689	u8         status[0x8];
2690	u8         reserved_0[0x18];
2691
2692	u8         syndrome[0x20];
2693
2694	u8         reserved_1[0x40];
2695};
2696
2697enum {
2698	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2699	MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2700};
2701
2702struct mlx5_ifc_teardown_hca_in_bits {
2703	u8         opcode[0x10];
2704	u8         reserved_0[0x10];
2705
2706	u8         reserved_1[0x10];
2707	u8         op_mod[0x10];
2708
2709	u8         reserved_2[0x10];
2710	u8         profile[0x10];
2711
2712	u8         reserved_3[0x20];
2713};
2714
2715struct mlx5_ifc_suspend_qp_out_bits {
2716	u8         status[0x8];
2717	u8         reserved_0[0x18];
2718
2719	u8         syndrome[0x20];
2720
2721	u8         reserved_1[0x40];
2722};
2723
2724struct mlx5_ifc_suspend_qp_in_bits {
2725	u8         opcode[0x10];
2726	u8         reserved_0[0x10];
2727
2728	u8         reserved_1[0x10];
2729	u8         op_mod[0x10];
2730
2731	u8         reserved_2[0x8];
2732	u8         qpn[0x18];
2733
2734	u8         reserved_3[0x20];
2735};
2736
2737struct mlx5_ifc_sqerr2rts_qp_out_bits {
2738	u8         status[0x8];
2739	u8         reserved_0[0x18];
2740
2741	u8         syndrome[0x20];
2742
2743	u8         reserved_1[0x40];
2744};
2745
2746struct mlx5_ifc_sqerr2rts_qp_in_bits {
2747	u8         opcode[0x10];
2748	u8         reserved_0[0x10];
2749
2750	u8         reserved_1[0x10];
2751	u8         op_mod[0x10];
2752
2753	u8         reserved_2[0x8];
2754	u8         qpn[0x18];
2755
2756	u8         reserved_3[0x20];
2757
2758	u8         opt_param_mask[0x20];
2759
2760	u8         reserved_4[0x20];
2761
2762	struct mlx5_ifc_qpc_bits qpc;
2763
2764	u8         reserved_5[0x80];
2765};
2766
2767struct mlx5_ifc_sqd2rts_qp_out_bits {
2768	u8         status[0x8];
2769	u8         reserved_0[0x18];
2770
2771	u8         syndrome[0x20];
2772
2773	u8         reserved_1[0x40];
2774};
2775
2776struct mlx5_ifc_sqd2rts_qp_in_bits {
2777	u8         opcode[0x10];
2778	u8         reserved_0[0x10];
2779
2780	u8         reserved_1[0x10];
2781	u8         op_mod[0x10];
2782
2783	u8         reserved_2[0x8];
2784	u8         qpn[0x18];
2785
2786	u8         reserved_3[0x20];
2787
2788	u8         opt_param_mask[0x20];
2789
2790	u8         reserved_4[0x20];
2791
2792	struct mlx5_ifc_qpc_bits qpc;
2793
2794	u8         reserved_5[0x80];
2795};
2796
2797struct mlx5_ifc_snapshot_cap_bits {
2798	u8         reserved_0[0x1d];
2799	u8         suspend_qp_uc[0x1];
2800	u8         suspend_qp_ud[0x1];
2801	u8         suspend_qp_rc[0x1];
2802
2803	u8         reserved_1[0x1c];
2804	u8         restore_pd[0x1];
2805	u8         restore_uar[0x1];
2806	u8         restore_mkey[0x1];
2807	u8         restore_qp[0x1];
2808
2809	u8         reserved_2[0x1e];
2810	u8         named_mkey[0x1];
2811	u8         named_qp[0x1];
2812
2813	u8         reserved_3[0x7a0];
2814};
2815
2816struct mlx5_ifc_set_wol_rol_out_bits {
2817	u8         status[0x8];
2818	u8         reserved_0[0x18];
2819
2820	u8         syndrome[0x20];
2821
2822	u8         reserved_1[0x40];
2823};
2824
2825struct mlx5_ifc_set_wol_rol_in_bits {
2826	u8         opcode[0x10];
2827	u8         reserved_0[0x10];
2828
2829	u8         reserved_1[0x10];
2830	u8         op_mod[0x10];
2831
2832	u8         rol_mode_valid[0x1];
2833	u8         wol_mode_valid[0x1];
2834	u8         reserved_2[0xe];
2835	u8         rol_mode[0x8];
2836	u8         wol_mode[0x8];
2837
2838	u8         reserved_3[0x20];
2839};
2840
2841struct mlx5_ifc_set_roce_address_out_bits {
2842	u8         status[0x8];
2843	u8         reserved_0[0x18];
2844
2845	u8         syndrome[0x20];
2846
2847	u8         reserved_1[0x40];
2848};
2849
2850struct mlx5_ifc_set_roce_address_in_bits {
2851	u8         opcode[0x10];
2852	u8         reserved_0[0x10];
2853
2854	u8         reserved_1[0x10];
2855	u8         op_mod[0x10];
2856
2857	u8         roce_address_index[0x10];
2858	u8         reserved_2[0x10];
2859
2860	u8         reserved_3[0x20];
2861
2862	struct mlx5_ifc_roce_addr_layout_bits roce_address;
2863};
2864
2865struct mlx5_ifc_set_rdb_out_bits {
2866	u8         status[0x8];
2867	u8         reserved_0[0x18];
2868
2869	u8         syndrome[0x20];
2870
2871	u8         reserved_1[0x40];
2872};
2873
2874struct mlx5_ifc_set_rdb_in_bits {
2875	u8         opcode[0x10];
2876	u8         reserved_0[0x10];
2877
2878	u8         reserved_1[0x10];
2879	u8         op_mod[0x10];
2880
2881	u8         reserved_2[0x8];
2882	u8         qpn[0x18];
2883
2884	u8         reserved_3[0x18];
2885	u8         rdb_list_size[0x8];
2886
2887	struct mlx5_ifc_rdbc_bits rdb_context[0];
2888};
2889
2890struct mlx5_ifc_set_mad_demux_out_bits {
2891	u8         status[0x8];
2892	u8         reserved_0[0x18];
2893
2894	u8         syndrome[0x20];
2895
2896	u8         reserved_1[0x40];
2897};
2898
2899enum {
2900	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2901	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2902};
2903
2904struct mlx5_ifc_set_mad_demux_in_bits {
2905	u8         opcode[0x10];
2906	u8         reserved_0[0x10];
2907
2908	u8         reserved_1[0x10];
2909	u8         op_mod[0x10];
2910
2911	u8         reserved_2[0x20];
2912
2913	u8         reserved_3[0x6];
2914	u8         demux_mode[0x2];
2915	u8         reserved_4[0x18];
2916};
2917
2918struct mlx5_ifc_set_l2_table_entry_out_bits {
2919	u8         status[0x8];
2920	u8         reserved_0[0x18];
2921
2922	u8         syndrome[0x20];
2923
2924	u8         reserved_1[0x40];
2925};
2926
2927struct mlx5_ifc_set_l2_table_entry_in_bits {
2928	u8         opcode[0x10];
2929	u8         reserved_0[0x10];
2930
2931	u8         reserved_1[0x10];
2932	u8         op_mod[0x10];
2933
2934	u8         reserved_2[0x60];
2935
2936	u8         reserved_3[0x8];
2937	u8         table_index[0x18];
2938
2939	u8         reserved_4[0x20];
2940
2941	u8         reserved_5[0x13];
2942	u8         vlan_valid[0x1];
2943	u8         vlan[0xc];
2944
2945	struct mlx5_ifc_mac_address_layout_bits mac_address;
2946
2947	u8         reserved_6[0xc0];
2948};
2949
2950struct mlx5_ifc_set_issi_out_bits {
2951	u8         status[0x8];
2952	u8         reserved_0[0x18];
2953
2954	u8         syndrome[0x20];
2955
2956	u8         reserved_1[0x40];
2957};
2958
2959struct mlx5_ifc_set_issi_in_bits {
2960	u8         opcode[0x10];
2961	u8         reserved_0[0x10];
2962
2963	u8         reserved_1[0x10];
2964	u8         op_mod[0x10];
2965
2966	u8         reserved_2[0x10];
2967	u8         current_issi[0x10];
2968
2969	u8         reserved_3[0x20];
2970};
2971
2972struct mlx5_ifc_set_hca_cap_out_bits {
2973	u8         status[0x8];
2974	u8         reserved_0[0x18];
2975
2976	u8         syndrome[0x20];
2977
2978	u8         reserved_1[0x40];
2979};
2980
2981struct mlx5_ifc_set_hca_cap_in_bits {
2982	u8         opcode[0x10];
2983	u8         reserved_0[0x10];
2984
2985	u8         reserved_1[0x10];
2986	u8         op_mod[0x10];
2987
2988	u8         reserved_2[0x40];
2989
2990	union mlx5_ifc_hca_cap_union_bits capability;
2991};
2992
2993struct mlx5_ifc_set_flow_table_root_out_bits {
2994	u8         status[0x8];
2995	u8         reserved_0[0x18];
2996
2997	u8         syndrome[0x20];
2998
2999	u8         reserved_1[0x40];
3000};
3001
3002struct mlx5_ifc_set_flow_table_root_in_bits {
3003	u8         opcode[0x10];
3004	u8         reserved_0[0x10];
3005
3006	u8         reserved_1[0x10];
3007	u8         op_mod[0x10];
3008
3009	u8         other_vport[0x1];
3010	u8         reserved_2[0xf];
3011	u8         vport_number[0x10];
3012
3013	u8         reserved_3[0x20];
3014
3015	u8         table_type[0x8];
3016	u8         reserved_4[0x18];
3017
3018	u8         reserved_5[0x8];
3019	u8         table_id[0x18];
3020
3021	u8         reserved_6[0x140];
3022};
3023
3024struct mlx5_ifc_set_fte_out_bits {
3025	u8         status[0x8];
3026	u8         reserved_0[0x18];
3027
3028	u8         syndrome[0x20];
3029
3030	u8         reserved_1[0x40];
3031};
3032
3033struct mlx5_ifc_set_fte_in_bits {
3034	u8         opcode[0x10];
3035	u8         reserved_0[0x10];
3036
3037	u8         reserved_1[0x10];
3038	u8         op_mod[0x10];
3039
3040	u8         other_vport[0x1];
3041	u8         reserved_2[0xf];
3042	u8         vport_number[0x10];
3043
3044	u8         reserved_3[0x20];
3045
3046	u8         table_type[0x8];
3047	u8         reserved_4[0x18];
3048
3049	u8         reserved_5[0x8];
3050	u8         table_id[0x18];
3051
3052	u8         reserved_6[0x18];
3053	u8         modify_enable_mask[0x8];
3054
3055	u8         reserved_7[0x20];
3056
3057	u8         flow_index[0x20];
3058
3059	u8         reserved_8[0xe0];
3060
3061	struct mlx5_ifc_flow_context_bits flow_context;
3062};
3063
3064struct mlx5_ifc_set_driver_version_out_bits {
3065	u8         status[0x8];
3066	u8         reserved_0[0x18];
3067
3068	u8         syndrome[0x20];
3069
3070	u8         reserved_1[0x40];
3071};
3072
3073struct mlx5_ifc_set_driver_version_in_bits {
3074	u8         opcode[0x10];
3075	u8         reserved_0[0x10];
3076
3077	u8         reserved_1[0x10];
3078	u8         op_mod[0x10];
3079
3080	u8         reserved_2[0x40];
3081
3082	u8         driver_version[64][0x8];
3083};
3084
3085struct mlx5_ifc_set_dc_cnak_trace_out_bits {
3086	u8         status[0x8];
3087	u8         reserved_0[0x18];
3088
3089	u8         syndrome[0x20];
3090
3091	u8         reserved_1[0x40];
3092};
3093
3094struct mlx5_ifc_set_dc_cnak_trace_in_bits {
3095	u8         opcode[0x10];
3096	u8         reserved_0[0x10];
3097
3098	u8         reserved_1[0x10];
3099	u8         op_mod[0x10];
3100
3101	u8         enable[0x1];
3102	u8         reserved_2[0x1f];
3103
3104	u8         reserved_3[0x160];
3105
3106	struct mlx5_ifc_cmd_pas_bits pas;
3107};
3108
3109struct mlx5_ifc_set_burst_size_out_bits {
3110	u8         status[0x8];
3111	u8         reserved_0[0x18];
3112
3113	u8         syndrome[0x20];
3114
3115	u8         reserved_1[0x40];
3116};
3117
3118struct mlx5_ifc_set_burst_size_in_bits {
3119	u8         opcode[0x10];
3120	u8         reserved_0[0x10];
3121
3122	u8         reserved_1[0x10];
3123	u8         op_mod[0x10];
3124
3125	u8         reserved_2[0x20];
3126
3127	u8         reserved_3[0x9];
3128	u8         device_burst_size[0x17];
3129};
3130
3131struct mlx5_ifc_rts2rts_qp_out_bits {
3132	u8         status[0x8];
3133	u8         reserved_0[0x18];
3134
3135	u8         syndrome[0x20];
3136
3137	u8         reserved_1[0x40];
3138};
3139
3140struct mlx5_ifc_rts2rts_qp_in_bits {
3141	u8         opcode[0x10];
3142	u8         reserved_0[0x10];
3143
3144	u8         reserved_1[0x10];
3145	u8         op_mod[0x10];
3146
3147	u8         reserved_2[0x8];
3148	u8         qpn[0x18];
3149
3150	u8         reserved_3[0x20];
3151
3152	u8         opt_param_mask[0x20];
3153
3154	u8         reserved_4[0x20];
3155
3156	struct mlx5_ifc_qpc_bits qpc;
3157
3158	u8         reserved_5[0x80];
3159};
3160
3161struct mlx5_ifc_rtr2rts_qp_out_bits {
3162	u8         status[0x8];
3163	u8         reserved_0[0x18];
3164
3165	u8         syndrome[0x20];
3166
3167	u8         reserved_1[0x40];
3168};
3169
3170struct mlx5_ifc_rtr2rts_qp_in_bits {
3171	u8         opcode[0x10];
3172	u8         reserved_0[0x10];
3173
3174	u8         reserved_1[0x10];
3175	u8         op_mod[0x10];
3176
3177	u8         reserved_2[0x8];
3178	u8         qpn[0x18];
3179
3180	u8         reserved_3[0x20];
3181
3182	u8         opt_param_mask[0x20];
3183
3184	u8         reserved_4[0x20];
3185
3186	struct mlx5_ifc_qpc_bits qpc;
3187
3188	u8         reserved_5[0x80];
3189};
3190
3191struct mlx5_ifc_rst2init_qp_out_bits {
3192	u8         status[0x8];
3193	u8         reserved_0[0x18];
3194
3195	u8         syndrome[0x20];
3196
3197	u8         reserved_1[0x40];
3198};
3199
3200struct mlx5_ifc_rst2init_qp_in_bits {
3201	u8         opcode[0x10];
3202	u8         reserved_0[0x10];
3203
3204	u8         reserved_1[0x10];
3205	u8         op_mod[0x10];
3206
3207	u8         reserved_2[0x8];
3208	u8         qpn[0x18];
3209
3210	u8         reserved_3[0x20];
3211
3212	u8         opt_param_mask[0x20];
3213
3214	u8         reserved_4[0x20];
3215
3216	struct mlx5_ifc_qpc_bits qpc;
3217
3218	u8         reserved_5[0x80];
3219};
3220
3221struct mlx5_ifc_resume_qp_out_bits {
3222	u8         status[0x8];
3223	u8         reserved_0[0x18];
3224
3225	u8         syndrome[0x20];
3226
3227	u8         reserved_1[0x40];
3228};
3229
3230struct mlx5_ifc_resume_qp_in_bits {
3231	u8         opcode[0x10];
3232	u8         reserved_0[0x10];
3233
3234	u8         reserved_1[0x10];
3235	u8         op_mod[0x10];
3236
3237	u8         reserved_2[0x8];
3238	u8         qpn[0x18];
3239
3240	u8         reserved_3[0x20];
3241};
3242
3243struct mlx5_ifc_query_xrc_srq_out_bits {
3244	u8         status[0x8];
3245	u8         reserved_0[0x18];
3246
3247	u8         syndrome[0x20];
3248
3249	u8         reserved_1[0x40];
3250
3251	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3252
3253	u8         reserved_2[0x600];
3254
3255	u8         pas[0][0x40];
3256};
3257
3258struct mlx5_ifc_query_xrc_srq_in_bits {
3259	u8         opcode[0x10];
3260	u8         reserved_0[0x10];
3261
3262	u8         reserved_1[0x10];
3263	u8         op_mod[0x10];
3264
3265	u8         reserved_2[0x8];
3266	u8         xrc_srqn[0x18];
3267
3268	u8         reserved_3[0x20];
3269};
3270
3271struct mlx5_ifc_query_wol_rol_out_bits {
3272	u8         status[0x8];
3273	u8         reserved_0[0x18];
3274
3275	u8         syndrome[0x20];
3276
3277	u8         reserved_1[0x10];
3278	u8         rol_mode[0x8];
3279	u8         wol_mode[0x8];
3280
3281	u8         reserved_2[0x20];
3282};
3283
3284struct mlx5_ifc_query_wol_rol_in_bits {
3285	u8         opcode[0x10];
3286	u8         reserved_0[0x10];
3287
3288	u8         reserved_1[0x10];
3289	u8         op_mod[0x10];
3290
3291	u8         reserved_2[0x40];
3292};
3293
3294enum {
3295	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3296	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3297};
3298
3299struct mlx5_ifc_query_vport_state_out_bits {
3300	u8         status[0x8];
3301	u8         reserved_0[0x18];
3302
3303	u8         syndrome[0x20];
3304
3305	u8         reserved_1[0x20];
3306
3307	u8         reserved_2[0x18];
3308	u8         admin_state[0x4];
3309	u8         state[0x4];
3310};
3311
3312enum {
3313	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3314	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3315	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
3316};
3317
3318struct mlx5_ifc_query_vport_state_in_bits {
3319	u8         opcode[0x10];
3320	u8         reserved_0[0x10];
3321
3322	u8         reserved_1[0x10];
3323	u8         op_mod[0x10];
3324
3325	u8         other_vport[0x1];
3326	u8         reserved_2[0xf];
3327	u8         vport_number[0x10];
3328
3329	u8         reserved_3[0x20];
3330};
3331
3332struct mlx5_ifc_query_vport_counter_out_bits {
3333	u8         status[0x8];
3334	u8         reserved_0[0x18];
3335
3336	u8         syndrome[0x20];
3337
3338	u8         reserved_1[0x40];
3339
3340	struct mlx5_ifc_traffic_counter_bits received_errors;
3341
3342	struct mlx5_ifc_traffic_counter_bits transmit_errors;
3343
3344	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3345
3346	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3347
3348	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3349
3350	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3351
3352	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3353
3354	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3355
3356	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3357
3358	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3359
3360	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3361
3362	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3363
3364	u8         reserved_2[0xa00];
3365};
3366
3367enum {
3368	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3369};
3370
3371struct mlx5_ifc_query_vport_counter_in_bits {
3372	u8         opcode[0x10];
3373	u8         reserved_0[0x10];
3374
3375	u8         reserved_1[0x10];
3376	u8         op_mod[0x10];
3377
3378	u8         other_vport[0x1];
3379	u8         reserved_2[0xb];
3380	u8         port_num[0x4];
3381	u8         vport_number[0x10];
3382
3383	u8         reserved_3[0x60];
3384
3385	u8         clear[0x1];
3386	u8         reserved_4[0x1f];
3387
3388	u8         reserved_5[0x20];
3389};
3390
3391struct mlx5_ifc_query_tis_out_bits {
3392	u8         status[0x8];
3393	u8         reserved_0[0x18];
3394
3395	u8         syndrome[0x20];
3396
3397	u8         reserved_1[0x40];
3398
3399	struct mlx5_ifc_tisc_bits tis_context;
3400};
3401
3402struct mlx5_ifc_query_tis_in_bits {
3403	u8         opcode[0x10];
3404	u8         reserved_0[0x10];
3405
3406	u8         reserved_1[0x10];
3407	u8         op_mod[0x10];
3408
3409	u8         reserved_2[0x8];
3410	u8         tisn[0x18];
3411
3412	u8         reserved_3[0x20];
3413};
3414
3415struct mlx5_ifc_query_tir_out_bits {
3416	u8         status[0x8];
3417	u8         reserved_0[0x18];
3418
3419	u8         syndrome[0x20];
3420
3421	u8         reserved_1[0xc0];
3422
3423	struct mlx5_ifc_tirc_bits tir_context;
3424};
3425
3426struct mlx5_ifc_query_tir_in_bits {
3427	u8         opcode[0x10];
3428	u8         reserved_0[0x10];
3429
3430	u8         reserved_1[0x10];
3431	u8         op_mod[0x10];
3432
3433	u8         reserved_2[0x8];
3434	u8         tirn[0x18];
3435
3436	u8         reserved_3[0x20];
3437};
3438
3439struct mlx5_ifc_query_srq_out_bits {
3440	u8         status[0x8];
3441	u8         reserved_0[0x18];
3442
3443	u8         syndrome[0x20];
3444
3445	u8         reserved_1[0x40];
3446
3447	struct mlx5_ifc_srqc_bits srq_context_entry;
3448
3449	u8         reserved_2[0x600];
3450
3451	u8         pas[0][0x40];
3452};
3453
3454struct mlx5_ifc_query_srq_in_bits {
3455	u8         opcode[0x10];
3456	u8         reserved_0[0x10];
3457
3458	u8         reserved_1[0x10];
3459	u8         op_mod[0x10];
3460
3461	u8         reserved_2[0x8];
3462	u8         srqn[0x18];
3463
3464	u8         reserved_3[0x20];
3465};
3466
3467struct mlx5_ifc_query_sq_out_bits {
3468	u8         status[0x8];
3469	u8         reserved_0[0x18];
3470
3471	u8         syndrome[0x20];
3472
3473	u8         reserved_1[0xc0];
3474
3475	struct mlx5_ifc_sqc_bits sq_context;
3476};
3477
3478struct mlx5_ifc_query_sq_in_bits {
3479	u8         opcode[0x10];
3480	u8         reserved_0[0x10];
3481
3482	u8         reserved_1[0x10];
3483	u8         op_mod[0x10];
3484
3485	u8         reserved_2[0x8];
3486	u8         sqn[0x18];
3487
3488	u8         reserved_3[0x20];
3489};
3490
3491struct mlx5_ifc_query_special_contexts_out_bits {
3492	u8         status[0x8];
3493	u8         reserved_0[0x18];
3494
3495	u8         syndrome[0x20];
3496
3497	u8         reserved_1[0x20];
3498
3499	u8         resd_lkey[0x20];
3500};
3501
3502struct mlx5_ifc_query_special_contexts_in_bits {
3503	u8         opcode[0x10];
3504	u8         reserved_0[0x10];
3505
3506	u8         reserved_1[0x10];
3507	u8         op_mod[0x10];
3508
3509	u8         reserved_2[0x40];
3510};
3511
3512struct mlx5_ifc_query_rqt_out_bits {
3513	u8         status[0x8];
3514	u8         reserved_0[0x18];
3515
3516	u8         syndrome[0x20];
3517
3518	u8         reserved_1[0xc0];
3519
3520	struct mlx5_ifc_rqtc_bits rqt_context;
3521};
3522
3523struct mlx5_ifc_query_rqt_in_bits {
3524	u8         opcode[0x10];
3525	u8         reserved_0[0x10];
3526
3527	u8         reserved_1[0x10];
3528	u8         op_mod[0x10];
3529
3530	u8         reserved_2[0x8];
3531	u8         rqtn[0x18];
3532
3533	u8         reserved_3[0x20];
3534};
3535
3536struct mlx5_ifc_query_rq_out_bits {
3537	u8         status[0x8];
3538	u8         reserved_0[0x18];
3539
3540	u8         syndrome[0x20];
3541
3542	u8         reserved_1[0xc0];
3543
3544	struct mlx5_ifc_rqc_bits rq_context;
3545};
3546
3547struct mlx5_ifc_query_rq_in_bits {
3548	u8         opcode[0x10];
3549	u8         reserved_0[0x10];
3550
3551	u8         reserved_1[0x10];
3552	u8         op_mod[0x10];
3553
3554	u8         reserved_2[0x8];
3555	u8         rqn[0x18];
3556
3557	u8         reserved_3[0x20];
3558};
3559
3560struct mlx5_ifc_query_roce_address_out_bits {
3561	u8         status[0x8];
3562	u8         reserved_0[0x18];
3563
3564	u8         syndrome[0x20];
3565
3566	u8         reserved_1[0x40];
3567
3568	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3569};
3570
3571struct mlx5_ifc_query_roce_address_in_bits {
3572	u8         opcode[0x10];
3573	u8         reserved_0[0x10];
3574
3575	u8         reserved_1[0x10];
3576	u8         op_mod[0x10];
3577
3578	u8         roce_address_index[0x10];
3579	u8         reserved_2[0x10];
3580
3581	u8         reserved_3[0x20];
3582};
3583
3584struct mlx5_ifc_query_rmp_out_bits {
3585	u8         status[0x8];
3586	u8         reserved_0[0x18];
3587
3588	u8         syndrome[0x20];
3589
3590	u8         reserved_1[0xc0];
3591
3592	struct mlx5_ifc_rmpc_bits rmp_context;
3593};
3594
3595struct mlx5_ifc_query_rmp_in_bits {
3596	u8         opcode[0x10];
3597	u8         reserved_0[0x10];
3598
3599	u8         reserved_1[0x10];
3600	u8         op_mod[0x10];
3601
3602	u8         reserved_2[0x8];
3603	u8         rmpn[0x18];
3604
3605	u8         reserved_3[0x20];
3606};
3607
3608struct mlx5_ifc_query_rdb_out_bits {
3609	u8         status[0x8];
3610	u8         reserved_0[0x18];
3611
3612	u8         syndrome[0x20];
3613
3614	u8         reserved_1[0x20];
3615
3616	u8         reserved_2[0x18];
3617	u8         rdb_list_size[0x8];
3618
3619	struct mlx5_ifc_rdbc_bits rdb_context[0];
3620};
3621
3622struct mlx5_ifc_query_rdb_in_bits {
3623	u8         opcode[0x10];
3624	u8         reserved_0[0x10];
3625
3626	u8         reserved_1[0x10];
3627	u8         op_mod[0x10];
3628
3629	u8         reserved_2[0x8];
3630	u8         qpn[0x18];
3631
3632	u8         reserved_3[0x20];
3633};
3634
3635struct mlx5_ifc_query_qp_out_bits {
3636	u8         status[0x8];
3637	u8         reserved_0[0x18];
3638
3639	u8         syndrome[0x20];
3640
3641	u8         reserved_1[0x40];
3642
3643	u8         opt_param_mask[0x20];
3644
3645	u8         reserved_2[0x20];
3646
3647	struct mlx5_ifc_qpc_bits qpc;
3648
3649	u8         reserved_3[0x80];
3650
3651	u8         pas[0][0x40];
3652};
3653
3654struct mlx5_ifc_query_qp_in_bits {
3655	u8         opcode[0x10];
3656	u8         reserved_0[0x10];
3657
3658	u8         reserved_1[0x10];
3659	u8         op_mod[0x10];
3660
3661	u8         reserved_2[0x8];
3662	u8         qpn[0x18];
3663
3664	u8         reserved_3[0x20];
3665};
3666
3667struct mlx5_ifc_query_q_counter_out_bits {
3668	u8         status[0x8];
3669	u8         reserved_0[0x18];
3670
3671	u8         syndrome[0x20];
3672
3673	u8         reserved_1[0x40];
3674
3675	u8         rx_write_requests[0x20];
3676
3677	u8         reserved_2[0x20];
3678
3679	u8         rx_read_requests[0x20];
3680
3681	u8         reserved_3[0x20];
3682
3683	u8         rx_atomic_requests[0x20];
3684
3685	u8         reserved_4[0x20];
3686
3687	u8         rx_dct_connect[0x20];
3688
3689	u8         reserved_5[0x20];
3690
3691	u8         out_of_buffer[0x20];
3692
3693	u8         reserved_6[0x20];
3694
3695	u8         out_of_sequence[0x20];
3696
3697	u8         reserved_7[0x620];
3698};
3699
3700struct mlx5_ifc_query_q_counter_in_bits {
3701	u8         opcode[0x10];
3702	u8         reserved_0[0x10];
3703
3704	u8         reserved_1[0x10];
3705	u8         op_mod[0x10];
3706
3707	u8         reserved_2[0x80];
3708
3709	u8         clear[0x1];
3710	u8         reserved_3[0x1f];
3711
3712	u8         reserved_4[0x18];
3713	u8         counter_set_id[0x8];
3714};
3715
3716struct mlx5_ifc_query_pages_out_bits {
3717	u8         status[0x8];
3718	u8         reserved_0[0x18];
3719
3720	u8         syndrome[0x20];
3721
3722	u8         reserved_1[0x10];
3723	u8         function_id[0x10];
3724
3725	u8         num_pages[0x20];
3726};
3727
3728enum {
3729	MLX5_BOOT_PAGES                           = 0x1,
3730	MLX5_INIT_PAGES                           = 0x2,
3731	MLX5_POST_INIT_PAGES                      = 0x3,
3732};
3733
3734struct mlx5_ifc_query_pages_in_bits {
3735	u8         opcode[0x10];
3736	u8         reserved_0[0x10];
3737
3738	u8         reserved_1[0x10];
3739	u8         op_mod[0x10];
3740
3741	u8         reserved_2[0x10];
3742	u8         function_id[0x10];
3743
3744	u8         reserved_3[0x20];
3745};
3746
3747struct mlx5_ifc_query_nic_vport_context_out_bits {
3748	u8         status[0x8];
3749	u8         reserved_0[0x18];
3750
3751	u8         syndrome[0x20];
3752
3753	u8         reserved_1[0x40];
3754
3755	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3756};
3757
3758struct mlx5_ifc_query_nic_vport_context_in_bits {
3759	u8         opcode[0x10];
3760	u8         reserved_0[0x10];
3761
3762	u8         reserved_1[0x10];
3763	u8         op_mod[0x10];
3764
3765	u8         other_vport[0x1];
3766	u8         reserved_2[0xf];
3767	u8         vport_number[0x10];
3768
3769	u8         reserved_3[0x5];
3770	u8         allowed_list_type[0x3];
3771	u8         reserved_4[0x18];
3772};
3773
3774struct mlx5_ifc_query_mkey_out_bits {
3775	u8         status[0x8];
3776	u8         reserved_0[0x18];
3777
3778	u8         syndrome[0x20];
3779
3780	u8         reserved_1[0x40];
3781
3782	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3783
3784	u8         reserved_2[0x600];
3785
3786	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3787
3788	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3789};
3790
3791struct mlx5_ifc_query_mkey_in_bits {
3792	u8         opcode[0x10];
3793	u8         reserved_0[0x10];
3794
3795	u8         reserved_1[0x10];
3796	u8         op_mod[0x10];
3797
3798	u8         reserved_2[0x8];
3799	u8         mkey_index[0x18];
3800
3801	u8         pg_access[0x1];
3802	u8         reserved_3[0x1f];
3803};
3804
3805struct mlx5_ifc_query_mad_demux_out_bits {
3806	u8         status[0x8];
3807	u8         reserved_0[0x18];
3808
3809	u8         syndrome[0x20];
3810
3811	u8         reserved_1[0x40];
3812
3813	u8         mad_dumux_parameters_block[0x20];
3814};
3815
3816struct mlx5_ifc_query_mad_demux_in_bits {
3817	u8         opcode[0x10];
3818	u8         reserved_0[0x10];
3819
3820	u8         reserved_1[0x10];
3821	u8         op_mod[0x10];
3822
3823	u8         reserved_2[0x40];
3824};
3825
3826struct mlx5_ifc_query_l2_table_entry_out_bits {
3827	u8         status[0x8];
3828	u8         reserved_0[0x18];
3829
3830	u8         syndrome[0x20];
3831
3832	u8         reserved_1[0xa0];
3833
3834	u8         reserved_2[0x13];
3835	u8         vlan_valid[0x1];
3836	u8         vlan[0xc];
3837
3838	struct mlx5_ifc_mac_address_layout_bits mac_address;
3839
3840	u8         reserved_3[0xc0];
3841};
3842
3843struct mlx5_ifc_query_l2_table_entry_in_bits {
3844	u8         opcode[0x10];
3845	u8         reserved_0[0x10];
3846
3847	u8         reserved_1[0x10];
3848	u8         op_mod[0x10];
3849
3850	u8         reserved_2[0x60];
3851
3852	u8         reserved_3[0x8];
3853	u8         table_index[0x18];
3854
3855	u8         reserved_4[0x140];
3856};
3857
3858struct mlx5_ifc_query_issi_out_bits {
3859	u8         status[0x8];
3860	u8         reserved_0[0x18];
3861
3862	u8         syndrome[0x20];
3863
3864	u8         reserved_1[0x10];
3865	u8         current_issi[0x10];
3866
3867	u8         reserved_2[0xa0];
3868
3869	u8         supported_issi_reserved[76][0x8];
3870	u8         supported_issi_dw0[0x20];
3871};
3872
3873struct mlx5_ifc_query_issi_in_bits {
3874	u8         opcode[0x10];
3875	u8         reserved_0[0x10];
3876
3877	u8         reserved_1[0x10];
3878	u8         op_mod[0x10];
3879
3880	u8         reserved_2[0x40];
3881};
3882
3883struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3884	u8         status[0x8];
3885	u8         reserved_0[0x18];
3886
3887	u8         syndrome[0x20];
3888
3889	u8         reserved_1[0x40];
3890
3891	struct mlx5_ifc_pkey_bits pkey[0];
3892};
3893
3894struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3895	u8         opcode[0x10];
3896	u8         reserved_0[0x10];
3897
3898	u8         reserved_1[0x10];
3899	u8         op_mod[0x10];
3900
3901	u8         other_vport[0x1];
3902	u8         reserved_2[0xb];
3903	u8         port_num[0x4];
3904	u8         vport_number[0x10];
3905
3906	u8         reserved_3[0x10];
3907	u8         pkey_index[0x10];
3908};
3909
3910struct mlx5_ifc_query_hca_vport_gid_out_bits {
3911	u8         status[0x8];
3912	u8         reserved_0[0x18];
3913
3914	u8         syndrome[0x20];
3915
3916	u8         reserved_1[0x20];
3917
3918	u8         gids_num[0x10];
3919	u8         reserved_2[0x10];
3920
3921	struct mlx5_ifc_array128_auto_bits gid[0];
3922};
3923
3924struct mlx5_ifc_query_hca_vport_gid_in_bits {
3925	u8         opcode[0x10];
3926	u8         reserved_0[0x10];
3927
3928	u8         reserved_1[0x10];
3929	u8         op_mod[0x10];
3930
3931	u8         other_vport[0x1];
3932	u8         reserved_2[0xb];
3933	u8         port_num[0x4];
3934	u8         vport_number[0x10];
3935
3936	u8         reserved_3[0x10];
3937	u8         gid_index[0x10];
3938};
3939
3940struct mlx5_ifc_query_hca_vport_context_out_bits {
3941	u8         status[0x8];
3942	u8         reserved_0[0x18];
3943
3944	u8         syndrome[0x20];
3945
3946	u8         reserved_1[0x40];
3947
3948	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3949};
3950
3951struct mlx5_ifc_query_hca_vport_context_in_bits {
3952	u8         opcode[0x10];
3953	u8         reserved_0[0x10];
3954
3955	u8         reserved_1[0x10];
3956	u8         op_mod[0x10];
3957
3958	u8         other_vport[0x1];
3959	u8         reserved_2[0xb];
3960	u8         port_num[0x4];
3961	u8         vport_number[0x10];
3962
3963	u8         reserved_3[0x20];
3964};
3965
3966struct mlx5_ifc_query_hca_cap_out_bits {
3967	u8         status[0x8];
3968	u8         reserved_0[0x18];
3969
3970	u8         syndrome[0x20];
3971
3972	u8         reserved_1[0x40];
3973
3974	union mlx5_ifc_hca_cap_union_bits capability;
3975};
3976
3977struct mlx5_ifc_query_hca_cap_in_bits {
3978	u8         opcode[0x10];
3979	u8         reserved_0[0x10];
3980
3981	u8         reserved_1[0x10];
3982	u8         op_mod[0x10];
3983
3984	u8         reserved_2[0x40];
3985};
3986
3987struct mlx5_ifc_query_flow_table_out_bits {
3988	u8         status[0x8];
3989	u8         reserved_0[0x18];
3990
3991	u8         syndrome[0x20];
3992
3993	u8         reserved_1[0x80];
3994
3995	u8         reserved_2[0x8];
3996	u8         level[0x8];
3997	u8         reserved_3[0x8];
3998	u8         log_size[0x8];
3999
4000	u8         reserved_4[0x120];
4001};
4002
4003struct mlx5_ifc_query_flow_table_in_bits {
4004	u8         opcode[0x10];
4005	u8         reserved_0[0x10];
4006
4007	u8         reserved_1[0x10];
4008	u8         op_mod[0x10];
4009
4010	u8         other_vport[0x1];
4011	u8         reserved_2[0xf];
4012	u8         vport_number[0x10];
4013
4014	u8         reserved_3[0x20];
4015
4016	u8         table_type[0x8];
4017	u8         reserved_4[0x18];
4018
4019	u8         reserved_5[0x8];
4020	u8         table_id[0x18];
4021
4022	u8         reserved_6[0x140];
4023};
4024
4025struct mlx5_ifc_query_fte_out_bits {
4026	u8         status[0x8];
4027	u8         reserved_0[0x18];
4028
4029	u8         syndrome[0x20];
4030
4031	u8         reserved_1[0x1c0];
4032
4033	struct mlx5_ifc_flow_context_bits flow_context;
4034};
4035
4036struct mlx5_ifc_query_fte_in_bits {
4037	u8         opcode[0x10];
4038	u8         reserved_0[0x10];
4039
4040	u8         reserved_1[0x10];
4041	u8         op_mod[0x10];
4042
4043	u8         other_vport[0x1];
4044	u8         reserved_2[0xf];
4045	u8         vport_number[0x10];
4046
4047	u8         reserved_3[0x20];
4048
4049	u8         table_type[0x8];
4050	u8         reserved_4[0x18];
4051
4052	u8         reserved_5[0x8];
4053	u8         table_id[0x18];
4054
4055	u8         reserved_6[0x40];
4056
4057	u8         flow_index[0x20];
4058
4059	u8         reserved_7[0xe0];
4060};
4061
4062enum {
4063	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4064	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4065	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4066};
4067
4068struct mlx5_ifc_query_flow_group_out_bits {
4069	u8         status[0x8];
4070	u8         reserved_0[0x18];
4071
4072	u8         syndrome[0x20];
4073
4074	u8         reserved_1[0xa0];
4075
4076	u8         start_flow_index[0x20];
4077
4078	u8         reserved_2[0x20];
4079
4080	u8         end_flow_index[0x20];
4081
4082	u8         reserved_3[0xa0];
4083
4084	u8         reserved_4[0x18];
4085	u8         match_criteria_enable[0x8];
4086
4087	struct mlx5_ifc_fte_match_param_bits match_criteria;
4088
4089	u8         reserved_5[0xe00];
4090};
4091
4092struct mlx5_ifc_query_flow_group_in_bits {
4093	u8         opcode[0x10];
4094	u8         reserved_0[0x10];
4095
4096	u8         reserved_1[0x10];
4097	u8         op_mod[0x10];
4098
4099	u8         other_vport[0x1];
4100	u8         reserved_2[0xf];
4101	u8         vport_number[0x10];
4102
4103	u8         reserved_3[0x20];
4104
4105	u8         table_type[0x8];
4106	u8         reserved_4[0x18];
4107
4108	u8         reserved_5[0x8];
4109	u8         table_id[0x18];
4110
4111	u8         group_id[0x20];
4112
4113	u8         reserved_6[0x120];
4114};
4115
4116struct mlx5_ifc_query_flow_counter_out_bits {
4117	u8         status[0x8];
4118	u8         reserved_0[0x18];
4119
4120	u8         syndrome[0x20];
4121
4122	u8         reserved_1[0x40];
4123
4124	struct mlx5_ifc_traffic_counter_bits flow_statistics;
4125
4126	u8         reserved_2[0x700];
4127};
4128
4129struct mlx5_ifc_query_flow_counter_in_bits {
4130	u8         opcode[0x10];
4131	u8         reserved_0[0x10];
4132
4133	u8         reserved_1[0x10];
4134	u8         op_mod[0x10];
4135
4136	u8         reserved_2[0x80];
4137
4138	u8         clear[0x1];
4139	u8         reserved_3[0x1f];
4140
4141	u8         reserved_4[0x10];
4142	u8         flow_counter_id[0x10];
4143};
4144
4145struct mlx5_ifc_query_esw_vport_context_out_bits {
4146	u8         status[0x8];
4147	u8         reserved_0[0x18];
4148
4149	u8         syndrome[0x20];
4150
4151	u8         reserved_1[0x40];
4152
4153	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4154};
4155
4156struct mlx5_ifc_query_esw_vport_context_in_bits {
4157	u8         opcode[0x10];
4158	u8         reserved_0[0x10];
4159
4160	u8         reserved_1[0x10];
4161	u8         op_mod[0x10];
4162
4163	u8         other_vport[0x1];
4164	u8         reserved_2[0xf];
4165	u8         vport_number[0x10];
4166
4167	u8         reserved_3[0x20];
4168};
4169
4170struct mlx5_ifc_query_eq_out_bits {
4171	u8         status[0x8];
4172	u8         reserved_0[0x18];
4173
4174	u8         syndrome[0x20];
4175
4176	u8         reserved_1[0x40];
4177
4178	struct mlx5_ifc_eqc_bits eq_context_entry;
4179
4180	u8         reserved_2[0x40];
4181
4182	u8         event_bitmask[0x40];
4183
4184	u8         reserved_3[0x580];
4185
4186	u8         pas[0][0x40];
4187};
4188
4189struct mlx5_ifc_query_eq_in_bits {
4190	u8         opcode[0x10];
4191	u8         reserved_0[0x10];
4192
4193	u8         reserved_1[0x10];
4194	u8         op_mod[0x10];
4195
4196	u8         reserved_2[0x18];
4197	u8         eq_number[0x8];
4198
4199	u8         reserved_3[0x20];
4200};
4201
4202struct mlx5_ifc_query_dct_out_bits {
4203	u8         status[0x8];
4204	u8         reserved_0[0x18];
4205
4206	u8         syndrome[0x20];
4207
4208	u8         reserved_1[0x40];
4209
4210	struct mlx5_ifc_dctc_bits dct_context_entry;
4211
4212	u8         reserved_2[0x180];
4213};
4214
4215struct mlx5_ifc_query_dct_in_bits {
4216	u8         opcode[0x10];
4217	u8         reserved_0[0x10];
4218
4219	u8         reserved_1[0x10];
4220	u8         op_mod[0x10];
4221
4222	u8         reserved_2[0x8];
4223	u8         dctn[0x18];
4224
4225	u8         reserved_3[0x20];
4226};
4227
4228struct mlx5_ifc_query_dc_cnak_trace_out_bits {
4229	u8         status[0x8];
4230	u8         reserved_0[0x18];
4231
4232	u8         syndrome[0x20];
4233
4234	u8         enable[0x1];
4235	u8         reserved_1[0x1f];
4236
4237	u8         reserved_2[0x160];
4238
4239	struct mlx5_ifc_cmd_pas_bits pas;
4240};
4241
4242struct mlx5_ifc_query_dc_cnak_trace_in_bits {
4243	u8         opcode[0x10];
4244	u8         reserved_0[0x10];
4245
4246	u8         reserved_1[0x10];
4247	u8         op_mod[0x10];
4248
4249	u8         reserved_2[0x40];
4250};
4251
4252struct mlx5_ifc_query_cq_out_bits {
4253	u8         status[0x8];
4254	u8         reserved_0[0x18];
4255
4256	u8         syndrome[0x20];
4257
4258	u8         reserved_1[0x40];
4259
4260	struct mlx5_ifc_cqc_bits cq_context;
4261
4262	u8         reserved_2[0x600];
4263
4264	u8         pas[0][0x40];
4265};
4266
4267struct mlx5_ifc_query_cq_in_bits {
4268	u8         opcode[0x10];
4269	u8         reserved_0[0x10];
4270
4271	u8         reserved_1[0x10];
4272	u8         op_mod[0x10];
4273
4274	u8         reserved_2[0x8];
4275	u8         cqn[0x18];
4276
4277	u8         reserved_3[0x20];
4278};
4279
4280struct mlx5_ifc_query_cong_status_out_bits {
4281	u8         status[0x8];
4282	u8         reserved_0[0x18];
4283
4284	u8         syndrome[0x20];
4285
4286	u8         reserved_1[0x20];
4287
4288	u8         enable[0x1];
4289	u8         tag_enable[0x1];
4290	u8         reserved_2[0x1e];
4291};
4292
4293struct mlx5_ifc_query_cong_status_in_bits {
4294	u8         opcode[0x10];
4295	u8         reserved_0[0x10];
4296
4297	u8         reserved_1[0x10];
4298	u8         op_mod[0x10];
4299
4300	u8         reserved_2[0x18];
4301	u8         priority[0x4];
4302	u8         cong_protocol[0x4];
4303
4304	u8         reserved_3[0x20];
4305};
4306
4307struct mlx5_ifc_query_cong_statistics_out_bits {
4308	u8         status[0x8];
4309	u8         reserved_0[0x18];
4310
4311	u8         syndrome[0x20];
4312
4313	u8         reserved_1[0x40];
4314
4315	u8         cur_flows[0x20];
4316
4317	u8         sum_flows[0x20];
4318
4319	u8         cnp_ignored_high[0x20];
4320
4321	u8         cnp_ignored_low[0x20];
4322
4323	u8         cnp_handled_high[0x20];
4324
4325	u8         cnp_handled_low[0x20];
4326
4327	u8         reserved_2[0x100];
4328
4329	u8         time_stamp_high[0x20];
4330
4331	u8         time_stamp_low[0x20];
4332
4333	u8         accumulators_period[0x20];
4334
4335	u8         ecn_marked_roce_packets_high[0x20];
4336
4337	u8         ecn_marked_roce_packets_low[0x20];
4338
4339	u8         cnps_sent_high[0x20];
4340
4341	u8         cnps_sent_low[0x20];
4342
4343	u8         reserved_3[0x560];
4344};
4345
4346struct mlx5_ifc_query_cong_statistics_in_bits {
4347	u8         opcode[0x10];
4348	u8         reserved_0[0x10];
4349
4350	u8         reserved_1[0x10];
4351	u8         op_mod[0x10];
4352
4353	u8         clear[0x1];
4354	u8         reserved_2[0x1f];
4355
4356	u8         reserved_3[0x20];
4357};
4358
4359struct mlx5_ifc_query_cong_params_out_bits {
4360	u8         status[0x8];
4361	u8         reserved_0[0x18];
4362
4363	u8         syndrome[0x20];
4364
4365	u8         reserved_1[0x40];
4366
4367	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4368};
4369
4370struct mlx5_ifc_query_cong_params_in_bits {
4371	u8         opcode[0x10];
4372	u8         reserved_0[0x10];
4373
4374	u8         reserved_1[0x10];
4375	u8         op_mod[0x10];
4376
4377	u8         reserved_2[0x1c];
4378	u8         cong_protocol[0x4];
4379
4380	u8         reserved_3[0x20];
4381};
4382
4383struct mlx5_ifc_query_burst_size_out_bits {
4384	u8         status[0x8];
4385	u8         reserved_0[0x18];
4386
4387	u8         syndrome[0x20];
4388
4389	u8         reserved_1[0x20];
4390
4391	u8         reserved_2[0x9];
4392	u8         device_burst_size[0x17];
4393};
4394
4395struct mlx5_ifc_query_burst_size_in_bits {
4396	u8         opcode[0x10];
4397	u8         reserved_0[0x10];
4398
4399	u8         reserved_1[0x10];
4400	u8         op_mod[0x10];
4401
4402	u8         reserved_2[0x40];
4403};
4404
4405struct mlx5_ifc_query_adapter_out_bits {
4406	u8         status[0x8];
4407	u8         reserved_0[0x18];
4408
4409	u8         syndrome[0x20];
4410
4411	u8         reserved_1[0x40];
4412
4413	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4414};
4415
4416struct mlx5_ifc_query_adapter_in_bits {
4417	u8         opcode[0x10];
4418	u8         reserved_0[0x10];
4419
4420	u8         reserved_1[0x10];
4421	u8         op_mod[0x10];
4422
4423	u8         reserved_2[0x40];
4424};
4425
4426struct mlx5_ifc_qp_2rst_out_bits {
4427	u8         status[0x8];
4428	u8         reserved_0[0x18];
4429
4430	u8         syndrome[0x20];
4431
4432	u8         reserved_1[0x40];
4433};
4434
4435struct mlx5_ifc_qp_2rst_in_bits {
4436	u8         opcode[0x10];
4437	u8         reserved_0[0x10];
4438
4439	u8         reserved_1[0x10];
4440	u8         op_mod[0x10];
4441
4442	u8         reserved_2[0x8];
4443	u8         qpn[0x18];
4444
4445	u8         reserved_3[0x20];
4446};
4447
4448struct mlx5_ifc_qp_2err_out_bits {
4449	u8         status[0x8];
4450	u8         reserved_0[0x18];
4451
4452	u8         syndrome[0x20];
4453
4454	u8         reserved_1[0x40];
4455};
4456
4457struct mlx5_ifc_qp_2err_in_bits {
4458	u8         opcode[0x10];
4459	u8         reserved_0[0x10];
4460
4461	u8         reserved_1[0x10];
4462	u8         op_mod[0x10];
4463
4464	u8         reserved_2[0x8];
4465	u8         qpn[0x18];
4466
4467	u8         reserved_3[0x20];
4468};
4469
4470struct mlx5_ifc_page_fault_resume_out_bits {
4471	u8         status[0x8];
4472	u8         reserved_0[0x18];
4473
4474	u8         syndrome[0x20];
4475
4476	u8         reserved_1[0x40];
4477};
4478
4479struct mlx5_ifc_page_fault_resume_in_bits {
4480	u8         opcode[0x10];
4481	u8         reserved_0[0x10];
4482
4483	u8         reserved_1[0x10];
4484	u8         op_mod[0x10];
4485
4486	u8         error[0x1];
4487	u8         reserved_2[0x4];
4488	u8         rdma[0x1];
4489	u8         read_write[0x1];
4490	u8         req_res[0x1];
4491	u8         qpn[0x18];
4492
4493	u8         reserved_3[0x20];
4494};
4495
4496struct mlx5_ifc_nop_out_bits {
4497	u8         status[0x8];
4498	u8         reserved_0[0x18];
4499
4500	u8         syndrome[0x20];
4501
4502	u8         reserved_1[0x40];
4503};
4504
4505struct mlx5_ifc_nop_in_bits {
4506	u8         opcode[0x10];
4507	u8         reserved_0[0x10];
4508
4509	u8         reserved_1[0x10];
4510	u8         op_mod[0x10];
4511
4512	u8         reserved_2[0x40];
4513};
4514
4515struct mlx5_ifc_modify_vport_state_out_bits {
4516	u8         status[0x8];
4517	u8         reserved_0[0x18];
4518
4519	u8         syndrome[0x20];
4520
4521	u8         reserved_1[0x40];
4522};
4523
4524enum {
4525	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
4526	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
4527	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
4528};
4529
4530enum {
4531	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
4532	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
4533	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
4534};
4535
4536struct mlx5_ifc_modify_vport_state_in_bits {
4537	u8         opcode[0x10];
4538	u8         reserved_0[0x10];
4539
4540	u8         reserved_1[0x10];
4541	u8         op_mod[0x10];
4542
4543	u8         other_vport[0x1];
4544	u8         reserved_2[0xf];
4545	u8         vport_number[0x10];
4546
4547	u8         reserved_3[0x18];
4548	u8         admin_state[0x4];
4549	u8         reserved_4[0x4];
4550};
4551
4552struct mlx5_ifc_modify_tis_out_bits {
4553	u8         status[0x8];
4554	u8         reserved_0[0x18];
4555
4556	u8         syndrome[0x20];
4557
4558	u8         reserved_1[0x40];
4559};
4560
4561struct mlx5_ifc_modify_tis_in_bits {
4562	u8         opcode[0x10];
4563	u8         reserved_0[0x10];
4564
4565	u8         reserved_1[0x10];
4566	u8         op_mod[0x10];
4567
4568	u8         reserved_2[0x8];
4569	u8         tisn[0x18];
4570
4571	u8         reserved_3[0x20];
4572
4573	u8         modify_bitmask[0x40];
4574
4575	u8         reserved_4[0x40];
4576
4577	struct mlx5_ifc_tisc_bits ctx;
4578};
4579
4580struct mlx5_ifc_modify_tir_out_bits {
4581	u8         status[0x8];
4582	u8         reserved_0[0x18];
4583
4584	u8         syndrome[0x20];
4585
4586	u8         reserved_1[0x40];
4587};
4588
4589struct mlx5_ifc_modify_tir_in_bits {
4590	u8         opcode[0x10];
4591	u8         reserved_0[0x10];
4592
4593	u8         reserved_1[0x10];
4594	u8         op_mod[0x10];
4595
4596	u8         reserved_2[0x8];
4597	u8         tirn[0x18];
4598
4599	u8         reserved_3[0x20];
4600
4601	u8         modify_bitmask[0x40];
4602
4603	u8         reserved_4[0x40];
4604
4605	struct mlx5_ifc_tirc_bits tir_context;
4606};
4607
4608struct mlx5_ifc_modify_sq_out_bits {
4609	u8         status[0x8];
4610	u8         reserved_0[0x18];
4611
4612	u8         syndrome[0x20];
4613
4614	u8         reserved_1[0x40];
4615};
4616
4617struct mlx5_ifc_modify_sq_in_bits {
4618	u8         opcode[0x10];
4619	u8         reserved_0[0x10];
4620
4621	u8         reserved_1[0x10];
4622	u8         op_mod[0x10];
4623
4624	u8         sq_state[0x4];
4625	u8         reserved_2[0x4];
4626	u8         sqn[0x18];
4627
4628	u8         reserved_3[0x20];
4629
4630	u8         modify_bitmask[0x40];
4631
4632	u8         reserved_4[0x40];
4633
4634	struct mlx5_ifc_sqc_bits ctx;
4635};
4636
4637struct mlx5_ifc_modify_rqt_out_bits {
4638	u8         status[0x8];
4639	u8         reserved_0[0x18];
4640
4641	u8         syndrome[0x20];
4642
4643	u8         reserved_1[0x40];
4644};
4645
4646struct mlx5_ifc_modify_rqt_in_bits {
4647	u8         opcode[0x10];
4648	u8         reserved_0[0x10];
4649
4650	u8         reserved_1[0x10];
4651	u8         op_mod[0x10];
4652
4653	u8         reserved_2[0x8];
4654	u8         rqtn[0x18];
4655
4656	u8         reserved_3[0x20];
4657
4658	u8         modify_bitmask[0x40];
4659
4660	u8         reserved_4[0x40];
4661
4662	struct mlx5_ifc_rqtc_bits ctx;
4663};
4664
4665struct mlx5_ifc_modify_rq_out_bits {
4666	u8         status[0x8];
4667	u8         reserved_0[0x18];
4668
4669	u8         syndrome[0x20];
4670
4671	u8         reserved_1[0x40];
4672};
4673
4674struct mlx5_ifc_modify_rq_in_bits {
4675	u8         opcode[0x10];
4676	u8         reserved_0[0x10];
4677
4678	u8         reserved_1[0x10];
4679	u8         op_mod[0x10];
4680
4681	u8         rq_state[0x4];
4682	u8         reserved_2[0x4];
4683	u8         rqn[0x18];
4684
4685	u8         reserved_3[0x20];
4686
4687	u8         modify_bitmask[0x40];
4688
4689	u8         reserved_4[0x40];
4690
4691	struct mlx5_ifc_rqc_bits ctx;
4692};
4693
4694struct mlx5_ifc_modify_rmp_out_bits {
4695	u8         status[0x8];
4696	u8         reserved_0[0x18];
4697
4698	u8         syndrome[0x20];
4699
4700	u8         reserved_1[0x40];
4701};
4702
4703struct mlx5_ifc_rmp_bitmask_bits {
4704	u8	   reserved[0x20];
4705
4706	u8         reserved1[0x1f];
4707	u8         lwm[0x1];
4708};
4709
4710struct mlx5_ifc_modify_rmp_in_bits {
4711	u8         opcode[0x10];
4712	u8         reserved_0[0x10];
4713
4714	u8         reserved_1[0x10];
4715	u8         op_mod[0x10];
4716
4717	u8         rmp_state[0x4];
4718	u8         reserved_2[0x4];
4719	u8         rmpn[0x18];
4720
4721	u8         reserved_3[0x20];
4722
4723	struct mlx5_ifc_rmp_bitmask_bits bitmask;
4724
4725	u8         reserved_4[0x40];
4726
4727	struct mlx5_ifc_rmpc_bits ctx;
4728};
4729
4730struct mlx5_ifc_modify_nic_vport_context_out_bits {
4731	u8         status[0x8];
4732	u8         reserved_0[0x18];
4733
4734	u8         syndrome[0x20];
4735
4736	u8         reserved_1[0x40];
4737};
4738
4739struct mlx5_ifc_modify_nic_vport_field_select_bits {
4740	u8         reserved_0[0x18];
4741	u8         min_wqe_inline_mode[0x1];
4742	u8         mtu[0x1];
4743	u8         change_event[0x1];
4744	u8         promisc[0x1];
4745	u8         permanent_address[0x1];
4746	u8         addresses_list[0x1];
4747	u8         roce_en[0x1];
4748	u8         reserved_1[0x1];
4749};
4750
4751struct mlx5_ifc_modify_nic_vport_context_in_bits {
4752	u8         opcode[0x10];
4753	u8         reserved_0[0x10];
4754
4755	u8         reserved_1[0x10];
4756	u8         op_mod[0x10];
4757
4758	u8         other_vport[0x1];
4759	u8         reserved_2[0xf];
4760	u8         vport_number[0x10];
4761
4762	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4763
4764	u8         reserved_3[0x780];
4765
4766	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4767};
4768
4769struct mlx5_ifc_modify_hca_vport_context_out_bits {
4770	u8         status[0x8];
4771	u8         reserved_0[0x18];
4772
4773	u8         syndrome[0x20];
4774
4775	u8         reserved_1[0x40];
4776};
4777
4778struct mlx5_ifc_modify_hca_vport_context_in_bits {
4779	u8         opcode[0x10];
4780	u8         reserved_0[0x10];
4781
4782	u8         reserved_1[0x10];
4783	u8         op_mod[0x10];
4784
4785	u8         other_vport[0x1];
4786	u8         reserved_2[0xb];
4787	u8         port_num[0x4];
4788	u8         vport_number[0x10];
4789
4790	u8         reserved_3[0x20];
4791
4792	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4793};
4794
4795struct mlx5_ifc_modify_esw_vport_context_out_bits {
4796	u8         status[0x8];
4797	u8         reserved_0[0x18];
4798
4799	u8         syndrome[0x20];
4800
4801	u8         reserved_1[0x40];
4802};
4803
4804struct mlx5_ifc_modify_esw_vport_context_in_bits {
4805	u8         opcode[0x10];
4806	u8         reserved_0[0x10];
4807
4808	u8         reserved_1[0x10];
4809	u8         op_mod[0x10];
4810
4811	u8         other_vport[0x1];
4812	u8         reserved_2[0xf];
4813	u8         vport_number[0x10];
4814
4815	u8         field_select[0x20];
4816
4817	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4818};
4819
4820struct mlx5_ifc_modify_cq_out_bits {
4821	u8         status[0x8];
4822	u8         reserved_0[0x18];
4823
4824	u8         syndrome[0x20];
4825
4826	u8         reserved_1[0x40];
4827};
4828
4829enum {
4830	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4831	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4832};
4833
4834struct mlx5_ifc_modify_cq_in_bits {
4835	u8         opcode[0x10];
4836	u8         reserved_0[0x10];
4837
4838	u8         reserved_1[0x10];
4839	u8         op_mod[0x10];
4840
4841	u8         reserved_2[0x8];
4842	u8         cqn[0x18];
4843
4844	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4845
4846	struct mlx5_ifc_cqc_bits cq_context;
4847
4848	u8         reserved_3[0x600];
4849
4850	u8         pas[0][0x40];
4851};
4852
4853struct mlx5_ifc_modify_cong_status_out_bits {
4854	u8         status[0x8];
4855	u8         reserved_0[0x18];
4856
4857	u8         syndrome[0x20];
4858
4859	u8         reserved_1[0x40];
4860};
4861
4862struct mlx5_ifc_modify_cong_status_in_bits {
4863	u8         opcode[0x10];
4864	u8         reserved_0[0x10];
4865
4866	u8         reserved_1[0x10];
4867	u8         op_mod[0x10];
4868
4869	u8         reserved_2[0x18];
4870	u8         priority[0x4];
4871	u8         cong_protocol[0x4];
4872
4873	u8         enable[0x1];
4874	u8         tag_enable[0x1];
4875	u8         reserved_3[0x1e];
4876};
4877
4878struct mlx5_ifc_modify_cong_params_out_bits {
4879	u8         status[0x8];
4880	u8         reserved_0[0x18];
4881
4882	u8         syndrome[0x20];
4883
4884	u8         reserved_1[0x40];
4885};
4886
4887struct mlx5_ifc_modify_cong_params_in_bits {
4888	u8         opcode[0x10];
4889	u8         reserved_0[0x10];
4890
4891	u8         reserved_1[0x10];
4892	u8         op_mod[0x10];
4893
4894	u8         reserved_2[0x1c];
4895	u8         cong_protocol[0x4];
4896
4897	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4898
4899	u8         reserved_3[0x80];
4900
4901	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4902};
4903
4904struct mlx5_ifc_manage_pages_out_bits {
4905	u8         status[0x8];
4906	u8         reserved_0[0x18];
4907
4908	u8         syndrome[0x20];
4909
4910	u8         output_num_entries[0x20];
4911
4912	u8         reserved_1[0x20];
4913
4914	u8         pas[0][0x40];
4915};
4916
4917enum {
4918	MLX5_PAGES_CANT_GIVE                            = 0x0,
4919	MLX5_PAGES_GIVE                                 = 0x1,
4920	MLX5_PAGES_TAKE                                 = 0x2,
4921};
4922
4923struct mlx5_ifc_manage_pages_in_bits {
4924	u8         opcode[0x10];
4925	u8         reserved_0[0x10];
4926
4927	u8         reserved_1[0x10];
4928	u8         op_mod[0x10];
4929
4930	u8         reserved_2[0x10];
4931	u8         function_id[0x10];
4932
4933	u8         input_num_entries[0x20];
4934
4935	u8         pas[0][0x40];
4936};
4937
4938struct mlx5_ifc_mad_ifc_out_bits {
4939	u8         status[0x8];
4940	u8         reserved_0[0x18];
4941
4942	u8         syndrome[0x20];
4943
4944	u8         reserved_1[0x40];
4945
4946	u8         response_mad_packet[256][0x8];
4947};
4948
4949struct mlx5_ifc_mad_ifc_in_bits {
4950	u8         opcode[0x10];
4951	u8         reserved_0[0x10];
4952
4953	u8         reserved_1[0x10];
4954	u8         op_mod[0x10];
4955
4956	u8         remote_lid[0x10];
4957	u8         reserved_2[0x8];
4958	u8         port[0x8];
4959
4960	u8         reserved_3[0x20];
4961
4962	u8         mad[256][0x8];
4963};
4964
4965struct mlx5_ifc_init_hca_out_bits {
4966	u8         status[0x8];
4967	u8         reserved_0[0x18];
4968
4969	u8         syndrome[0x20];
4970
4971	u8         reserved_1[0x40];
4972};
4973
4974enum {
4975	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
4976	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
4977};
4978
4979struct mlx5_ifc_init_hca_in_bits {
4980	u8         opcode[0x10];
4981	u8         reserved_0[0x10];
4982
4983	u8         reserved_1[0x10];
4984	u8         op_mod[0x10];
4985
4986	u8         reserved_2[0x40];
4987};
4988
4989struct mlx5_ifc_init2rtr_qp_out_bits {
4990	u8         status[0x8];
4991	u8         reserved_0[0x18];
4992
4993	u8         syndrome[0x20];
4994
4995	u8         reserved_1[0x40];
4996};
4997
4998struct mlx5_ifc_init2rtr_qp_in_bits {
4999	u8         opcode[0x10];
5000	u8         reserved_0[0x10];
5001
5002	u8         reserved_1[0x10];
5003	u8         op_mod[0x10];
5004
5005	u8         reserved_2[0x8];
5006	u8         qpn[0x18];
5007
5008	u8         reserved_3[0x20];
5009
5010	u8         opt_param_mask[0x20];
5011
5012	u8         reserved_4[0x20];
5013
5014	struct mlx5_ifc_qpc_bits qpc;
5015
5016	u8         reserved_5[0x80];
5017};
5018
5019struct mlx5_ifc_init2init_qp_out_bits {
5020	u8         status[0x8];
5021	u8         reserved_0[0x18];
5022
5023	u8         syndrome[0x20];
5024
5025	u8         reserved_1[0x40];
5026};
5027
5028struct mlx5_ifc_init2init_qp_in_bits {
5029	u8         opcode[0x10];
5030	u8         reserved_0[0x10];
5031
5032	u8         reserved_1[0x10];
5033	u8         op_mod[0x10];
5034
5035	u8         reserved_2[0x8];
5036	u8         qpn[0x18];
5037
5038	u8         reserved_3[0x20];
5039
5040	u8         opt_param_mask[0x20];
5041
5042	u8         reserved_4[0x20];
5043
5044	struct mlx5_ifc_qpc_bits qpc;
5045
5046	u8         reserved_5[0x80];
5047};
5048
5049struct mlx5_ifc_get_dropped_packet_log_out_bits {
5050	u8         status[0x8];
5051	u8         reserved_0[0x18];
5052
5053	u8         syndrome[0x20];
5054
5055	u8         reserved_1[0x40];
5056
5057	u8         packet_headers_log[128][0x8];
5058
5059	u8         packet_syndrome[64][0x8];
5060};
5061
5062struct mlx5_ifc_get_dropped_packet_log_in_bits {
5063	u8         opcode[0x10];
5064	u8         reserved_0[0x10];
5065
5066	u8         reserved_1[0x10];
5067	u8         op_mod[0x10];
5068
5069	u8         reserved_2[0x40];
5070};
5071
5072struct mlx5_ifc_gen_eqe_in_bits {
5073	u8         opcode[0x10];
5074	u8         reserved_0[0x10];
5075
5076	u8         reserved_1[0x10];
5077	u8         op_mod[0x10];
5078
5079	u8         reserved_2[0x18];
5080	u8         eq_number[0x8];
5081
5082	u8         reserved_3[0x20];
5083
5084	u8         eqe[64][0x8];
5085};
5086
5087struct mlx5_ifc_gen_eq_out_bits {
5088	u8         status[0x8];
5089	u8         reserved_0[0x18];
5090
5091	u8         syndrome[0x20];
5092
5093	u8         reserved_1[0x40];
5094};
5095
5096struct mlx5_ifc_enable_hca_out_bits {
5097	u8         status[0x8];
5098	u8         reserved_0[0x18];
5099
5100	u8         syndrome[0x20];
5101
5102	u8         reserved_1[0x20];
5103};
5104
5105struct mlx5_ifc_enable_hca_in_bits {
5106	u8         opcode[0x10];
5107	u8         reserved_0[0x10];
5108
5109	u8         reserved_1[0x10];
5110	u8         op_mod[0x10];
5111
5112	u8         reserved_2[0x10];
5113	u8         function_id[0x10];
5114
5115	u8         reserved_3[0x20];
5116};
5117
5118struct mlx5_ifc_drain_dct_out_bits {
5119	u8         status[0x8];
5120	u8         reserved_0[0x18];
5121
5122	u8         syndrome[0x20];
5123
5124	u8         reserved_1[0x40];
5125};
5126
5127struct mlx5_ifc_drain_dct_in_bits {
5128	u8         opcode[0x10];
5129	u8         reserved_0[0x10];
5130
5131	u8         reserved_1[0x10];
5132	u8         op_mod[0x10];
5133
5134	u8         reserved_2[0x8];
5135	u8         dctn[0x18];
5136
5137	u8         reserved_3[0x20];
5138};
5139
5140struct mlx5_ifc_disable_hca_out_bits {
5141	u8         status[0x8];
5142	u8         reserved_0[0x18];
5143
5144	u8         syndrome[0x20];
5145
5146	u8         reserved_1[0x20];
5147};
5148
5149struct mlx5_ifc_disable_hca_in_bits {
5150	u8         opcode[0x10];
5151	u8         reserved_0[0x10];
5152
5153	u8         reserved_1[0x10];
5154	u8         op_mod[0x10];
5155
5156	u8         reserved_2[0x10];
5157	u8         function_id[0x10];
5158
5159	u8         reserved_3[0x20];
5160};
5161
5162struct mlx5_ifc_detach_from_mcg_out_bits {
5163	u8         status[0x8];
5164	u8         reserved_0[0x18];
5165
5166	u8         syndrome[0x20];
5167
5168	u8         reserved_1[0x40];
5169};
5170
5171struct mlx5_ifc_detach_from_mcg_in_bits {
5172	u8         opcode[0x10];
5173	u8         reserved_0[0x10];
5174
5175	u8         reserved_1[0x10];
5176	u8         op_mod[0x10];
5177
5178	u8         reserved_2[0x8];
5179	u8         qpn[0x18];
5180
5181	u8         reserved_3[0x20];
5182
5183	u8         multicast_gid[16][0x8];
5184};
5185
5186struct mlx5_ifc_destroy_xrc_srq_out_bits {
5187	u8         status[0x8];
5188	u8         reserved_0[0x18];
5189
5190	u8         syndrome[0x20];
5191
5192	u8         reserved_1[0x40];
5193};
5194
5195struct mlx5_ifc_destroy_xrc_srq_in_bits {
5196	u8         opcode[0x10];
5197	u8         reserved_0[0x10];
5198
5199	u8         reserved_1[0x10];
5200	u8         op_mod[0x10];
5201
5202	u8         reserved_2[0x8];
5203	u8         xrc_srqn[0x18];
5204
5205	u8         reserved_3[0x20];
5206};
5207
5208struct mlx5_ifc_destroy_tis_out_bits {
5209	u8         status[0x8];
5210	u8         reserved_0[0x18];
5211
5212	u8         syndrome[0x20];
5213
5214	u8         reserved_1[0x40];
5215};
5216
5217struct mlx5_ifc_destroy_tis_in_bits {
5218	u8         opcode[0x10];
5219	u8         reserved_0[0x10];
5220
5221	u8         reserved_1[0x10];
5222	u8         op_mod[0x10];
5223
5224	u8         reserved_2[0x8];
5225	u8         tisn[0x18];
5226
5227	u8         reserved_3[0x20];
5228};
5229
5230struct mlx5_ifc_destroy_tir_out_bits {
5231	u8         status[0x8];
5232	u8         reserved_0[0x18];
5233
5234	u8         syndrome[0x20];
5235
5236	u8         reserved_1[0x40];
5237};
5238
5239struct mlx5_ifc_destroy_tir_in_bits {
5240	u8         opcode[0x10];
5241	u8         reserved_0[0x10];
5242
5243	u8         reserved_1[0x10];
5244	u8         op_mod[0x10];
5245
5246	u8         reserved_2[0x8];
5247	u8         tirn[0x18];
5248
5249	u8         reserved_3[0x20];
5250};
5251
5252struct mlx5_ifc_destroy_srq_out_bits {
5253	u8         status[0x8];
5254	u8         reserved_0[0x18];
5255
5256	u8         syndrome[0x20];
5257
5258	u8         reserved_1[0x40];
5259};
5260
5261struct mlx5_ifc_destroy_srq_in_bits {
5262	u8         opcode[0x10];
5263	u8         reserved_0[0x10];
5264
5265	u8         reserved_1[0x10];
5266	u8         op_mod[0x10];
5267
5268	u8         reserved_2[0x8];
5269	u8         srqn[0x18];
5270
5271	u8         reserved_3[0x20];
5272};
5273
5274struct mlx5_ifc_destroy_sq_out_bits {
5275	u8         status[0x8];
5276	u8         reserved_0[0x18];
5277
5278	u8         syndrome[0x20];
5279
5280	u8         reserved_1[0x40];
5281};
5282
5283struct mlx5_ifc_destroy_sq_in_bits {
5284	u8         opcode[0x10];
5285	u8         reserved_0[0x10];
5286
5287	u8         reserved_1[0x10];
5288	u8         op_mod[0x10];
5289
5290	u8         reserved_2[0x8];
5291	u8         sqn[0x18];
5292
5293	u8         reserved_3[0x20];
5294};
5295
5296struct mlx5_ifc_destroy_rqt_out_bits {
5297	u8         status[0x8];
5298	u8         reserved_0[0x18];
5299
5300	u8         syndrome[0x20];
5301
5302	u8         reserved_1[0x40];
5303};
5304
5305struct mlx5_ifc_destroy_rqt_in_bits {
5306	u8         opcode[0x10];
5307	u8         reserved_0[0x10];
5308
5309	u8         reserved_1[0x10];
5310	u8         op_mod[0x10];
5311
5312	u8         reserved_2[0x8];
5313	u8         rqtn[0x18];
5314
5315	u8         reserved_3[0x20];
5316};
5317
5318struct mlx5_ifc_destroy_rq_out_bits {
5319	u8         status[0x8];
5320	u8         reserved_0[0x18];
5321
5322	u8         syndrome[0x20];
5323
5324	u8         reserved_1[0x40];
5325};
5326
5327struct mlx5_ifc_destroy_rq_in_bits {
5328	u8         opcode[0x10];
5329	u8         reserved_0[0x10];
5330
5331	u8         reserved_1[0x10];
5332	u8         op_mod[0x10];
5333
5334	u8         reserved_2[0x8];
5335	u8         rqn[0x18];
5336
5337	u8         reserved_3[0x20];
5338};
5339
5340struct mlx5_ifc_destroy_rmp_out_bits {
5341	u8         status[0x8];
5342	u8         reserved_0[0x18];
5343
5344	u8         syndrome[0x20];
5345
5346	u8         reserved_1[0x40];
5347};
5348
5349struct mlx5_ifc_destroy_rmp_in_bits {
5350	u8         opcode[0x10];
5351	u8         reserved_0[0x10];
5352
5353	u8         reserved_1[0x10];
5354	u8         op_mod[0x10];
5355
5356	u8         reserved_2[0x8];
5357	u8         rmpn[0x18];
5358
5359	u8         reserved_3[0x20];
5360};
5361
5362struct mlx5_ifc_destroy_qp_out_bits {
5363	u8         status[0x8];
5364	u8         reserved_0[0x18];
5365
5366	u8         syndrome[0x20];
5367
5368	u8         reserved_1[0x40];
5369};
5370
5371struct mlx5_ifc_destroy_qp_in_bits {
5372	u8         opcode[0x10];
5373	u8         reserved_0[0x10];
5374
5375	u8         reserved_1[0x10];
5376	u8         op_mod[0x10];
5377
5378	u8         reserved_2[0x8];
5379	u8         qpn[0x18];
5380
5381	u8         reserved_3[0x20];
5382};
5383
5384struct mlx5_ifc_destroy_psv_out_bits {
5385	u8         status[0x8];
5386	u8         reserved_0[0x18];
5387
5388	u8         syndrome[0x20];
5389
5390	u8         reserved_1[0x40];
5391};
5392
5393struct mlx5_ifc_destroy_psv_in_bits {
5394	u8         opcode[0x10];
5395	u8         reserved_0[0x10];
5396
5397	u8         reserved_1[0x10];
5398	u8         op_mod[0x10];
5399
5400	u8         reserved_2[0x8];
5401	u8         psvn[0x18];
5402
5403	u8         reserved_3[0x20];
5404};
5405
5406struct mlx5_ifc_destroy_mkey_out_bits {
5407	u8         status[0x8];
5408	u8         reserved_0[0x18];
5409
5410	u8         syndrome[0x20];
5411
5412	u8         reserved_1[0x40];
5413};
5414
5415struct mlx5_ifc_destroy_mkey_in_bits {
5416	u8         opcode[0x10];
5417	u8         reserved_0[0x10];
5418
5419	u8         reserved_1[0x10];
5420	u8         op_mod[0x10];
5421
5422	u8         reserved_2[0x8];
5423	u8         mkey_index[0x18];
5424
5425	u8         reserved_3[0x20];
5426};
5427
5428struct mlx5_ifc_destroy_flow_table_out_bits {
5429	u8         status[0x8];
5430	u8         reserved_0[0x18];
5431
5432	u8         syndrome[0x20];
5433
5434	u8         reserved_1[0x40];
5435};
5436
5437struct mlx5_ifc_destroy_flow_table_in_bits {
5438	u8         opcode[0x10];
5439	u8         reserved_0[0x10];
5440
5441	u8         reserved_1[0x10];
5442	u8         op_mod[0x10];
5443
5444	u8         other_vport[0x1];
5445	u8         reserved_2[0xf];
5446	u8         vport_number[0x10];
5447
5448	u8         reserved_3[0x20];
5449
5450	u8         table_type[0x8];
5451	u8         reserved_4[0x18];
5452
5453	u8         reserved_5[0x8];
5454	u8         table_id[0x18];
5455
5456	u8         reserved_6[0x140];
5457};
5458
5459struct mlx5_ifc_destroy_flow_group_out_bits {
5460	u8         status[0x8];
5461	u8         reserved_0[0x18];
5462
5463	u8         syndrome[0x20];
5464
5465	u8         reserved_1[0x40];
5466};
5467
5468struct mlx5_ifc_destroy_flow_group_in_bits {
5469	u8         opcode[0x10];
5470	u8         reserved_0[0x10];
5471
5472	u8         reserved_1[0x10];
5473	u8         op_mod[0x10];
5474
5475	u8         other_vport[0x1];
5476	u8         reserved_2[0xf];
5477	u8         vport_number[0x10];
5478
5479	u8         reserved_3[0x20];
5480
5481	u8         table_type[0x8];
5482	u8         reserved_4[0x18];
5483
5484	u8         reserved_5[0x8];
5485	u8         table_id[0x18];
5486
5487	u8         group_id[0x20];
5488
5489	u8         reserved_6[0x120];
5490};
5491
5492struct mlx5_ifc_destroy_eq_out_bits {
5493	u8         status[0x8];
5494	u8         reserved_0[0x18];
5495
5496	u8         syndrome[0x20];
5497
5498	u8         reserved_1[0x40];
5499};
5500
5501struct mlx5_ifc_destroy_eq_in_bits {
5502	u8         opcode[0x10];
5503	u8         reserved_0[0x10];
5504
5505	u8         reserved_1[0x10];
5506	u8         op_mod[0x10];
5507
5508	u8         reserved_2[0x18];
5509	u8         eq_number[0x8];
5510
5511	u8         reserved_3[0x20];
5512};
5513
5514struct mlx5_ifc_destroy_dct_out_bits {
5515	u8         status[0x8];
5516	u8         reserved_0[0x18];
5517
5518	u8         syndrome[0x20];
5519
5520	u8         reserved_1[0x40];
5521};
5522
5523struct mlx5_ifc_destroy_dct_in_bits {
5524	u8         opcode[0x10];
5525	u8         reserved_0[0x10];
5526
5527	u8         reserved_1[0x10];
5528	u8         op_mod[0x10];
5529
5530	u8         reserved_2[0x8];
5531	u8         dctn[0x18];
5532
5533	u8         reserved_3[0x20];
5534};
5535
5536struct mlx5_ifc_destroy_cq_out_bits {
5537	u8         status[0x8];
5538	u8         reserved_0[0x18];
5539
5540	u8         syndrome[0x20];
5541
5542	u8         reserved_1[0x40];
5543};
5544
5545struct mlx5_ifc_destroy_cq_in_bits {
5546	u8         opcode[0x10];
5547	u8         reserved_0[0x10];
5548
5549	u8         reserved_1[0x10];
5550	u8         op_mod[0x10];
5551
5552	u8         reserved_2[0x8];
5553	u8         cqn[0x18];
5554
5555	u8         reserved_3[0x20];
5556};
5557
5558struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5559	u8         status[0x8];
5560	u8         reserved_0[0x18];
5561
5562	u8         syndrome[0x20];
5563
5564	u8         reserved_1[0x40];
5565};
5566
5567struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5568	u8         opcode[0x10];
5569	u8         reserved_0[0x10];
5570
5571	u8         reserved_1[0x10];
5572	u8         op_mod[0x10];
5573
5574	u8         reserved_2[0x20];
5575
5576	u8         reserved_3[0x10];
5577	u8         vxlan_udp_port[0x10];
5578};
5579
5580struct mlx5_ifc_delete_l2_table_entry_out_bits {
5581	u8         status[0x8];
5582	u8         reserved_0[0x18];
5583
5584	u8         syndrome[0x20];
5585
5586	u8         reserved_1[0x40];
5587};
5588
5589struct mlx5_ifc_delete_l2_table_entry_in_bits {
5590	u8         opcode[0x10];
5591	u8         reserved_0[0x10];
5592
5593	u8         reserved_1[0x10];
5594	u8         op_mod[0x10];
5595
5596	u8         reserved_2[0x60];
5597
5598	u8         reserved_3[0x8];
5599	u8         table_index[0x18];
5600
5601	u8         reserved_4[0x140];
5602};
5603
5604struct mlx5_ifc_delete_fte_out_bits {
5605	u8         status[0x8];
5606	u8         reserved_0[0x18];
5607
5608	u8         syndrome[0x20];
5609
5610	u8         reserved_1[0x40];
5611};
5612
5613struct mlx5_ifc_delete_fte_in_bits {
5614	u8         opcode[0x10];
5615	u8         reserved_0[0x10];
5616
5617	u8         reserved_1[0x10];
5618	u8         op_mod[0x10];
5619
5620	u8         other_vport[0x1];
5621	u8         reserved_2[0xf];
5622	u8         vport_number[0x10];
5623
5624	u8         reserved_3[0x20];
5625
5626	u8         table_type[0x8];
5627	u8         reserved_4[0x18];
5628
5629	u8         reserved_5[0x8];
5630	u8         table_id[0x18];
5631
5632	u8         reserved_6[0x40];
5633
5634	u8         flow_index[0x20];
5635
5636	u8         reserved_7[0xe0];
5637};
5638
5639struct mlx5_ifc_dealloc_xrcd_out_bits {
5640	u8         status[0x8];
5641	u8         reserved_0[0x18];
5642
5643	u8         syndrome[0x20];
5644
5645	u8         reserved_1[0x40];
5646};
5647
5648struct mlx5_ifc_dealloc_xrcd_in_bits {
5649	u8         opcode[0x10];
5650	u8         reserved_0[0x10];
5651
5652	u8         reserved_1[0x10];
5653	u8         op_mod[0x10];
5654
5655	u8         reserved_2[0x8];
5656	u8         xrcd[0x18];
5657
5658	u8         reserved_3[0x20];
5659};
5660
5661struct mlx5_ifc_dealloc_uar_out_bits {
5662	u8         status[0x8];
5663	u8         reserved_0[0x18];
5664
5665	u8         syndrome[0x20];
5666
5667	u8         reserved_1[0x40];
5668};
5669
5670struct mlx5_ifc_dealloc_uar_in_bits {
5671	u8         opcode[0x10];
5672	u8         reserved_0[0x10];
5673
5674	u8         reserved_1[0x10];
5675	u8         op_mod[0x10];
5676
5677	u8         reserved_2[0x8];
5678	u8         uar[0x18];
5679
5680	u8         reserved_3[0x20];
5681};
5682
5683struct mlx5_ifc_dealloc_transport_domain_out_bits {
5684	u8         status[0x8];
5685	u8         reserved_0[0x18];
5686
5687	u8         syndrome[0x20];
5688
5689	u8         reserved_1[0x40];
5690};
5691
5692struct mlx5_ifc_dealloc_transport_domain_in_bits {
5693	u8         opcode[0x10];
5694	u8         reserved_0[0x10];
5695
5696	u8         reserved_1[0x10];
5697	u8         op_mod[0x10];
5698
5699	u8         reserved_2[0x8];
5700	u8         transport_domain[0x18];
5701
5702	u8         reserved_3[0x20];
5703};
5704
5705struct mlx5_ifc_dealloc_q_counter_out_bits {
5706	u8         status[0x8];
5707	u8         reserved_0[0x18];
5708
5709	u8         syndrome[0x20];
5710
5711	u8         reserved_1[0x40];
5712};
5713
5714struct mlx5_ifc_dealloc_q_counter_in_bits {
5715	u8         opcode[0x10];
5716	u8         reserved_0[0x10];
5717
5718	u8         reserved_1[0x10];
5719	u8         op_mod[0x10];
5720
5721	u8         reserved_2[0x18];
5722	u8         counter_set_id[0x8];
5723
5724	u8         reserved_3[0x20];
5725};
5726
5727struct mlx5_ifc_dealloc_pd_out_bits {
5728	u8         status[0x8];
5729	u8         reserved_0[0x18];
5730
5731	u8         syndrome[0x20];
5732
5733	u8         reserved_1[0x40];
5734};
5735
5736struct mlx5_ifc_dealloc_pd_in_bits {
5737	u8         opcode[0x10];
5738	u8         reserved_0[0x10];
5739
5740	u8         reserved_1[0x10];
5741	u8         op_mod[0x10];
5742
5743	u8         reserved_2[0x8];
5744	u8         pd[0x18];
5745
5746	u8         reserved_3[0x20];
5747};
5748
5749struct mlx5_ifc_dealloc_flow_counter_out_bits {
5750	u8         status[0x8];
5751	u8         reserved_0[0x18];
5752
5753	u8         syndrome[0x20];
5754
5755	u8         reserved_1[0x40];
5756};
5757
5758struct mlx5_ifc_dealloc_flow_counter_in_bits {
5759	u8         opcode[0x10];
5760	u8         reserved_0[0x10];
5761
5762	u8         reserved_1[0x10];
5763	u8         op_mod[0x10];
5764
5765	u8         reserved_2[0x10];
5766	u8         flow_counter_id[0x10];
5767
5768	u8         reserved_3[0x20];
5769};
5770
5771struct mlx5_ifc_deactivate_tracer_out_bits {
5772	u8         status[0x8];
5773	u8         reserved_0[0x18];
5774
5775	u8         syndrome[0x20];
5776
5777	u8         reserved_1[0x40];
5778};
5779
5780struct mlx5_ifc_deactivate_tracer_in_bits {
5781	u8         opcode[0x10];
5782	u8         reserved_0[0x10];
5783
5784	u8         reserved_1[0x10];
5785	u8         op_mod[0x10];
5786
5787	u8         mkey[0x20];
5788
5789	u8         reserved_2[0x20];
5790};
5791
5792struct mlx5_ifc_create_xrc_srq_out_bits {
5793	u8         status[0x8];
5794	u8         reserved_0[0x18];
5795
5796	u8         syndrome[0x20];
5797
5798	u8         reserved_1[0x8];
5799	u8         xrc_srqn[0x18];
5800
5801	u8         reserved_2[0x20];
5802};
5803
5804struct mlx5_ifc_create_xrc_srq_in_bits {
5805	u8         opcode[0x10];
5806	u8         reserved_0[0x10];
5807
5808	u8         reserved_1[0x10];
5809	u8         op_mod[0x10];
5810
5811	u8         reserved_2[0x40];
5812
5813	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5814
5815	u8         reserved_3[0x600];
5816
5817	u8         pas[0][0x40];
5818};
5819
5820struct mlx5_ifc_create_tis_out_bits {
5821	u8         status[0x8];
5822	u8         reserved_0[0x18];
5823
5824	u8         syndrome[0x20];
5825
5826	u8         reserved_1[0x8];
5827	u8         tisn[0x18];
5828
5829	u8         reserved_2[0x20];
5830};
5831
5832struct mlx5_ifc_create_tis_in_bits {
5833	u8         opcode[0x10];
5834	u8         reserved_0[0x10];
5835
5836	u8         reserved_1[0x10];
5837	u8         op_mod[0x10];
5838
5839	u8         reserved_2[0xc0];
5840
5841	struct mlx5_ifc_tisc_bits ctx;
5842};
5843
5844struct mlx5_ifc_create_tir_out_bits {
5845	u8         status[0x8];
5846	u8         reserved_0[0x18];
5847
5848	u8         syndrome[0x20];
5849
5850	u8         reserved_1[0x8];
5851	u8         tirn[0x18];
5852
5853	u8         reserved_2[0x20];
5854};
5855
5856struct mlx5_ifc_create_tir_in_bits {
5857	u8         opcode[0x10];
5858	u8         reserved_0[0x10];
5859
5860	u8         reserved_1[0x10];
5861	u8         op_mod[0x10];
5862
5863	u8         reserved_2[0xc0];
5864
5865	struct mlx5_ifc_tirc_bits tir_context;
5866};
5867
5868struct mlx5_ifc_create_srq_out_bits {
5869	u8         status[0x8];
5870	u8         reserved_0[0x18];
5871
5872	u8         syndrome[0x20];
5873
5874	u8         reserved_1[0x8];
5875	u8         srqn[0x18];
5876
5877	u8         reserved_2[0x20];
5878};
5879
5880struct mlx5_ifc_create_srq_in_bits {
5881	u8         opcode[0x10];
5882	u8         reserved_0[0x10];
5883
5884	u8         reserved_1[0x10];
5885	u8         op_mod[0x10];
5886
5887	u8         reserved_2[0x40];
5888
5889	struct mlx5_ifc_srqc_bits srq_context_entry;
5890
5891	u8         reserved_3[0x600];
5892
5893	u8         pas[0][0x40];
5894};
5895
5896struct mlx5_ifc_create_sq_out_bits {
5897	u8         status[0x8];
5898	u8         reserved_0[0x18];
5899
5900	u8         syndrome[0x20];
5901
5902	u8         reserved_1[0x8];
5903	u8         sqn[0x18];
5904
5905	u8         reserved_2[0x20];
5906};
5907
5908struct mlx5_ifc_create_sq_in_bits {
5909	u8         opcode[0x10];
5910	u8         reserved_0[0x10];
5911
5912	u8         reserved_1[0x10];
5913	u8         op_mod[0x10];
5914
5915	u8         reserved_2[0xc0];
5916
5917	struct mlx5_ifc_sqc_bits ctx;
5918};
5919
5920struct mlx5_ifc_create_rqt_out_bits {
5921	u8         status[0x8];
5922	u8         reserved_0[0x18];
5923
5924	u8         syndrome[0x20];
5925
5926	u8         reserved_1[0x8];
5927	u8         rqtn[0x18];
5928
5929	u8         reserved_2[0x20];
5930};
5931
5932struct mlx5_ifc_create_rqt_in_bits {
5933	u8         opcode[0x10];
5934	u8         reserved_0[0x10];
5935
5936	u8         reserved_1[0x10];
5937	u8         op_mod[0x10];
5938
5939	u8         reserved_2[0xc0];
5940
5941	struct mlx5_ifc_rqtc_bits rqt_context;
5942};
5943
5944struct mlx5_ifc_create_rq_out_bits {
5945	u8         status[0x8];
5946	u8         reserved_0[0x18];
5947
5948	u8         syndrome[0x20];
5949
5950	u8         reserved_1[0x8];
5951	u8         rqn[0x18];
5952
5953	u8         reserved_2[0x20];
5954};
5955
5956struct mlx5_ifc_create_rq_in_bits {
5957	u8         opcode[0x10];
5958	u8         reserved_0[0x10];
5959
5960	u8         reserved_1[0x10];
5961	u8         op_mod[0x10];
5962
5963	u8         reserved_2[0xc0];
5964
5965	struct mlx5_ifc_rqc_bits ctx;
5966};
5967
5968struct mlx5_ifc_create_rmp_out_bits {
5969	u8         status[0x8];
5970	u8         reserved_0[0x18];
5971
5972	u8         syndrome[0x20];
5973
5974	u8         reserved_1[0x8];
5975	u8         rmpn[0x18];
5976
5977	u8         reserved_2[0x20];
5978};
5979
5980struct mlx5_ifc_create_rmp_in_bits {
5981	u8         opcode[0x10];
5982	u8         reserved_0[0x10];
5983
5984	u8         reserved_1[0x10];
5985	u8         op_mod[0x10];
5986
5987	u8         reserved_2[0xc0];
5988
5989	struct mlx5_ifc_rmpc_bits ctx;
5990};
5991
5992struct mlx5_ifc_create_qp_out_bits {
5993	u8         status[0x8];
5994	u8         reserved_0[0x18];
5995
5996	u8         syndrome[0x20];
5997
5998	u8         reserved_1[0x8];
5999	u8         qpn[0x18];
6000
6001	u8         reserved_2[0x20];
6002};
6003
6004struct mlx5_ifc_create_qp_in_bits {
6005	u8         opcode[0x10];
6006	u8         reserved_0[0x10];
6007
6008	u8         reserved_1[0x10];
6009	u8         op_mod[0x10];
6010
6011	u8         reserved_2[0x40];
6012
6013	u8         opt_param_mask[0x20];
6014
6015	u8         reserved_3[0x20];
6016
6017	struct mlx5_ifc_qpc_bits qpc;
6018
6019	u8         reserved_4[0x80];
6020
6021	u8         pas[0][0x40];
6022};
6023
6024struct mlx5_ifc_create_psv_out_bits {
6025	u8         status[0x8];
6026	u8         reserved_0[0x18];
6027
6028	u8         syndrome[0x20];
6029
6030	u8         reserved_1[0x40];
6031
6032	u8         reserved_2[0x8];
6033	u8         psv0_index[0x18];
6034
6035	u8         reserved_3[0x8];
6036	u8         psv1_index[0x18];
6037
6038	u8         reserved_4[0x8];
6039	u8         psv2_index[0x18];
6040
6041	u8         reserved_5[0x8];
6042	u8         psv3_index[0x18];
6043};
6044
6045struct mlx5_ifc_create_psv_in_bits {
6046	u8         opcode[0x10];
6047	u8         reserved_0[0x10];
6048
6049	u8         reserved_1[0x10];
6050	u8         op_mod[0x10];
6051
6052	u8         num_psv[0x4];
6053	u8         reserved_2[0x4];
6054	u8         pd[0x18];
6055
6056	u8         reserved_3[0x20];
6057};
6058
6059struct mlx5_ifc_create_mkey_out_bits {
6060	u8         status[0x8];
6061	u8         reserved_0[0x18];
6062
6063	u8         syndrome[0x20];
6064
6065	u8         reserved_1[0x8];
6066	u8         mkey_index[0x18];
6067
6068	u8         reserved_2[0x20];
6069};
6070
6071struct mlx5_ifc_create_mkey_in_bits {
6072	u8         opcode[0x10];
6073	u8         reserved_0[0x10];
6074
6075	u8         reserved_1[0x10];
6076	u8         op_mod[0x10];
6077
6078	u8         reserved_2[0x20];
6079
6080	u8         pg_access[0x1];
6081	u8         reserved_3[0x1f];
6082
6083	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6084
6085	u8         reserved_4[0x80];
6086
6087	u8         translations_octword_actual_size[0x20];
6088
6089	u8         reserved_5[0x560];
6090
6091	u8         klm_pas_mtt[0][0x20];
6092};
6093
6094struct mlx5_ifc_create_flow_table_out_bits {
6095	u8         status[0x8];
6096	u8         reserved_0[0x18];
6097
6098	u8         syndrome[0x20];
6099
6100	u8         reserved_1[0x8];
6101	u8         table_id[0x18];
6102
6103	u8         reserved_2[0x20];
6104};
6105
6106struct mlx5_ifc_create_flow_table_in_bits {
6107	u8         opcode[0x10];
6108	u8         reserved_0[0x10];
6109
6110	u8         reserved_1[0x10];
6111	u8         op_mod[0x10];
6112
6113	u8         other_vport[0x1];
6114	u8         reserved_2[0xf];
6115	u8         vport_number[0x10];
6116
6117	u8         reserved_3[0x20];
6118
6119	u8         table_type[0x8];
6120	u8         reserved_4[0x18];
6121
6122	u8         reserved_5[0x20];
6123
6124	u8         reserved_6[0x8];
6125	u8         level[0x8];
6126	u8         reserved_7[0x8];
6127	u8         log_size[0x8];
6128
6129	u8         reserved_8[0x120];
6130};
6131
6132struct mlx5_ifc_create_flow_group_out_bits {
6133	u8         status[0x8];
6134	u8         reserved_0[0x18];
6135
6136	u8         syndrome[0x20];
6137
6138	u8         reserved_1[0x8];
6139	u8         group_id[0x18];
6140
6141	u8         reserved_2[0x20];
6142};
6143
6144enum {
6145	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6146	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6147	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6148};
6149
6150struct mlx5_ifc_create_flow_group_in_bits {
6151	u8         opcode[0x10];
6152	u8         reserved_0[0x10];
6153
6154	u8         reserved_1[0x10];
6155	u8         op_mod[0x10];
6156
6157	u8         other_vport[0x1];
6158	u8         reserved_2[0xf];
6159	u8         vport_number[0x10];
6160
6161	u8         reserved_3[0x20];
6162
6163	u8         table_type[0x8];
6164	u8         reserved_4[0x18];
6165
6166	u8         reserved_5[0x8];
6167	u8         table_id[0x18];
6168
6169	u8         reserved_6[0x20];
6170
6171	u8         start_flow_index[0x20];
6172
6173	u8         reserved_7[0x20];
6174
6175	u8         end_flow_index[0x20];
6176
6177	u8         reserved_8[0xa0];
6178
6179	u8         reserved_9[0x18];
6180	u8         match_criteria_enable[0x8];
6181
6182	struct mlx5_ifc_fte_match_param_bits match_criteria;
6183
6184	u8         reserved_10[0xe00];
6185};
6186
6187struct mlx5_ifc_create_eq_out_bits {
6188	u8         status[0x8];
6189	u8         reserved_0[0x18];
6190
6191	u8         syndrome[0x20];
6192
6193	u8         reserved_1[0x18];
6194	u8         eq_number[0x8];
6195
6196	u8         reserved_2[0x20];
6197};
6198
6199struct mlx5_ifc_create_eq_in_bits {
6200	u8         opcode[0x10];
6201	u8         reserved_0[0x10];
6202
6203	u8         reserved_1[0x10];
6204	u8         op_mod[0x10];
6205
6206	u8         reserved_2[0x40];
6207
6208	struct mlx5_ifc_eqc_bits eq_context_entry;
6209
6210	u8         reserved_3[0x40];
6211
6212	u8         event_bitmask[0x40];
6213
6214	u8         reserved_4[0x580];
6215
6216	u8         pas[0][0x40];
6217};
6218
6219struct mlx5_ifc_create_dct_out_bits {
6220	u8         status[0x8];
6221	u8         reserved_0[0x18];
6222
6223	u8         syndrome[0x20];
6224
6225	u8         reserved_1[0x8];
6226	u8         dctn[0x18];
6227
6228	u8         reserved_2[0x20];
6229};
6230
6231struct mlx5_ifc_create_dct_in_bits {
6232	u8         opcode[0x10];
6233	u8         reserved_0[0x10];
6234
6235	u8         reserved_1[0x10];
6236	u8         op_mod[0x10];
6237
6238	u8         reserved_2[0x40];
6239
6240	struct mlx5_ifc_dctc_bits dct_context_entry;
6241
6242	u8         reserved_3[0x180];
6243};
6244
6245struct mlx5_ifc_create_cq_out_bits {
6246	u8         status[0x8];
6247	u8         reserved_0[0x18];
6248
6249	u8         syndrome[0x20];
6250
6251	u8         reserved_1[0x8];
6252	u8         cqn[0x18];
6253
6254	u8         reserved_2[0x20];
6255};
6256
6257struct mlx5_ifc_create_cq_in_bits {
6258	u8         opcode[0x10];
6259	u8         reserved_0[0x10];
6260
6261	u8         reserved_1[0x10];
6262	u8         op_mod[0x10];
6263
6264	u8         reserved_2[0x40];
6265
6266	struct mlx5_ifc_cqc_bits cq_context;
6267
6268	u8         reserved_3[0x600];
6269
6270	u8         pas[0][0x40];
6271};
6272
6273struct mlx5_ifc_config_int_moderation_out_bits {
6274	u8         status[0x8];
6275	u8         reserved_0[0x18];
6276
6277	u8         syndrome[0x20];
6278
6279	u8         reserved_1[0x4];
6280	u8         min_delay[0xc];
6281	u8         int_vector[0x10];
6282
6283	u8         reserved_2[0x20];
6284};
6285
6286enum {
6287	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6288	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6289};
6290
6291struct mlx5_ifc_config_int_moderation_in_bits {
6292	u8         opcode[0x10];
6293	u8         reserved_0[0x10];
6294
6295	u8         reserved_1[0x10];
6296	u8         op_mod[0x10];
6297
6298	u8         reserved_2[0x4];
6299	u8         min_delay[0xc];
6300	u8         int_vector[0x10];
6301
6302	u8         reserved_3[0x20];
6303};
6304
6305struct mlx5_ifc_attach_to_mcg_out_bits {
6306	u8         status[0x8];
6307	u8         reserved_0[0x18];
6308
6309	u8         syndrome[0x20];
6310
6311	u8         reserved_1[0x40];
6312};
6313
6314struct mlx5_ifc_attach_to_mcg_in_bits {
6315	u8         opcode[0x10];
6316	u8         reserved_0[0x10];
6317
6318	u8         reserved_1[0x10];
6319	u8         op_mod[0x10];
6320
6321	u8         reserved_2[0x8];
6322	u8         qpn[0x18];
6323
6324	u8         reserved_3[0x20];
6325
6326	u8         multicast_gid[16][0x8];
6327};
6328
6329struct mlx5_ifc_arm_xrc_srq_out_bits {
6330	u8         status[0x8];
6331	u8         reserved_0[0x18];
6332
6333	u8         syndrome[0x20];
6334
6335	u8         reserved_1[0x40];
6336};
6337
6338enum {
6339	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6340};
6341
6342struct mlx5_ifc_arm_xrc_srq_in_bits {
6343	u8         opcode[0x10];
6344	u8         reserved_0[0x10];
6345
6346	u8         reserved_1[0x10];
6347	u8         op_mod[0x10];
6348
6349	u8         reserved_2[0x8];
6350	u8         xrc_srqn[0x18];
6351
6352	u8         reserved_3[0x10];
6353	u8         lwm[0x10];
6354};
6355
6356struct mlx5_ifc_arm_rq_out_bits {
6357	u8         status[0x8];
6358	u8         reserved_0[0x18];
6359
6360	u8         syndrome[0x20];
6361
6362	u8         reserved_1[0x40];
6363};
6364
6365enum {
6366	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
6367};
6368
6369struct mlx5_ifc_arm_rq_in_bits {
6370	u8         opcode[0x10];
6371	u8         reserved_0[0x10];
6372
6373	u8         reserved_1[0x10];
6374	u8         op_mod[0x10];
6375
6376	u8         reserved_2[0x8];
6377	u8         srq_number[0x18];
6378
6379	u8         reserved_3[0x10];
6380	u8         lwm[0x10];
6381};
6382
6383struct mlx5_ifc_arm_dct_out_bits {
6384	u8         status[0x8];
6385	u8         reserved_0[0x18];
6386
6387	u8         syndrome[0x20];
6388
6389	u8         reserved_1[0x40];
6390};
6391
6392struct mlx5_ifc_arm_dct_in_bits {
6393	u8         opcode[0x10];
6394	u8         reserved_0[0x10];
6395
6396	u8         reserved_1[0x10];
6397	u8         op_mod[0x10];
6398
6399	u8         reserved_2[0x8];
6400	u8         dctn[0x18];
6401
6402	u8         reserved_3[0x20];
6403};
6404
6405struct mlx5_ifc_alloc_xrcd_out_bits {
6406	u8         status[0x8];
6407	u8         reserved_0[0x18];
6408
6409	u8         syndrome[0x20];
6410
6411	u8         reserved_1[0x8];
6412	u8         xrcd[0x18];
6413
6414	u8         reserved_2[0x20];
6415};
6416
6417struct mlx5_ifc_alloc_xrcd_in_bits {
6418	u8         opcode[0x10];
6419	u8         reserved_0[0x10];
6420
6421	u8         reserved_1[0x10];
6422	u8         op_mod[0x10];
6423
6424	u8         reserved_2[0x40];
6425};
6426
6427struct mlx5_ifc_alloc_uar_out_bits {
6428	u8         status[0x8];
6429	u8         reserved_0[0x18];
6430
6431	u8         syndrome[0x20];
6432
6433	u8         reserved_1[0x8];
6434	u8         uar[0x18];
6435
6436	u8         reserved_2[0x20];
6437};
6438
6439struct mlx5_ifc_alloc_uar_in_bits {
6440	u8         opcode[0x10];
6441	u8         reserved_0[0x10];
6442
6443	u8         reserved_1[0x10];
6444	u8         op_mod[0x10];
6445
6446	u8         reserved_2[0x40];
6447};
6448
6449struct mlx5_ifc_alloc_transport_domain_out_bits {
6450	u8         status[0x8];
6451	u8         reserved_0[0x18];
6452
6453	u8         syndrome[0x20];
6454
6455	u8         reserved_1[0x8];
6456	u8         transport_domain[0x18];
6457
6458	u8         reserved_2[0x20];
6459};
6460
6461struct mlx5_ifc_alloc_transport_domain_in_bits {
6462	u8         opcode[0x10];
6463	u8         reserved_0[0x10];
6464
6465	u8         reserved_1[0x10];
6466	u8         op_mod[0x10];
6467
6468	u8         reserved_2[0x40];
6469};
6470
6471struct mlx5_ifc_alloc_q_counter_out_bits {
6472	u8         status[0x8];
6473	u8         reserved_0[0x18];
6474
6475	u8         syndrome[0x20];
6476
6477	u8         reserved_1[0x18];
6478	u8         counter_set_id[0x8];
6479
6480	u8         reserved_2[0x20];
6481};
6482
6483struct mlx5_ifc_alloc_q_counter_in_bits {
6484	u8         opcode[0x10];
6485	u8         reserved_0[0x10];
6486
6487	u8         reserved_1[0x10];
6488	u8         op_mod[0x10];
6489
6490	u8         reserved_2[0x40];
6491};
6492
6493struct mlx5_ifc_alloc_pd_out_bits {
6494	u8         status[0x8];
6495	u8         reserved_0[0x18];
6496
6497	u8         syndrome[0x20];
6498
6499	u8         reserved_1[0x8];
6500	u8         pd[0x18];
6501
6502	u8         reserved_2[0x20];
6503};
6504
6505struct mlx5_ifc_alloc_pd_in_bits {
6506	u8         opcode[0x10];
6507	u8         reserved_0[0x10];
6508
6509	u8         reserved_1[0x10];
6510	u8         op_mod[0x10];
6511
6512	u8         reserved_2[0x40];
6513};
6514
6515struct mlx5_ifc_alloc_flow_counter_out_bits {
6516	u8         status[0x8];
6517	u8         reserved_0[0x18];
6518
6519	u8         syndrome[0x20];
6520
6521	u8         reserved_1[0x10];
6522	u8         flow_counter_id[0x10];
6523
6524	u8         reserved_2[0x20];
6525};
6526
6527struct mlx5_ifc_alloc_flow_counter_in_bits {
6528	u8         opcode[0x10];
6529	u8         reserved_0[0x10];
6530
6531	u8         reserved_1[0x10];
6532	u8         op_mod[0x10];
6533
6534	u8         reserved_2[0x40];
6535};
6536
6537struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6538	u8         status[0x8];
6539	u8         reserved_0[0x18];
6540
6541	u8         syndrome[0x20];
6542
6543	u8         reserved_1[0x40];
6544};
6545
6546struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6547	u8         opcode[0x10];
6548	u8         reserved_0[0x10];
6549
6550	u8         reserved_1[0x10];
6551	u8         op_mod[0x10];
6552
6553	u8         reserved_2[0x20];
6554
6555	u8         reserved_3[0x10];
6556	u8         vxlan_udp_port[0x10];
6557};
6558
6559struct mlx5_ifc_activate_tracer_out_bits {
6560	u8         status[0x8];
6561	u8         reserved_0[0x18];
6562
6563	u8         syndrome[0x20];
6564
6565	u8         reserved_1[0x40];
6566};
6567
6568struct mlx5_ifc_activate_tracer_in_bits {
6569	u8         opcode[0x10];
6570	u8         reserved_0[0x10];
6571
6572	u8         reserved_1[0x10];
6573	u8         op_mod[0x10];
6574
6575	u8         mkey[0x20];
6576
6577	u8         reserved_2[0x20];
6578};
6579
6580struct mlx5_ifc_access_register_out_bits {
6581	u8         status[0x8];
6582	u8         reserved_0[0x18];
6583
6584	u8         syndrome[0x20];
6585
6586	u8         reserved_1[0x40];
6587
6588	u8         register_data[0][0x20];
6589};
6590
6591enum {
6592	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6593	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6594};
6595
6596struct mlx5_ifc_access_register_in_bits {
6597	u8         opcode[0x10];
6598	u8         reserved_0[0x10];
6599
6600	u8         reserved_1[0x10];
6601	u8         op_mod[0x10];
6602
6603	u8         reserved_2[0x10];
6604	u8         register_id[0x10];
6605
6606	u8         argument[0x20];
6607
6608	u8         register_data[0][0x20];
6609};
6610
6611struct mlx5_ifc_sltp_reg_bits {
6612	u8         status[0x4];
6613	u8         version[0x4];
6614	u8         local_port[0x8];
6615	u8         pnat[0x2];
6616	u8         reserved_0[0x2];
6617	u8         lane[0x4];
6618	u8         reserved_1[0x8];
6619
6620	u8         reserved_2[0x20];
6621
6622	u8         reserved_3[0x7];
6623	u8         polarity[0x1];
6624	u8         ob_tap0[0x8];
6625	u8         ob_tap1[0x8];
6626	u8         ob_tap2[0x8];
6627
6628	u8         reserved_4[0xc];
6629	u8         ob_preemp_mode[0x4];
6630	u8         ob_reg[0x8];
6631	u8         ob_bias[0x8];
6632
6633	u8         reserved_5[0x20];
6634};
6635
6636struct mlx5_ifc_slrp_reg_bits {
6637	u8         status[0x4];
6638	u8         version[0x4];
6639	u8         local_port[0x8];
6640	u8         pnat[0x2];
6641	u8         reserved_0[0x2];
6642	u8         lane[0x4];
6643	u8         reserved_1[0x8];
6644
6645	u8         ib_sel[0x2];
6646	u8         reserved_2[0x11];
6647	u8         dp_sel[0x1];
6648	u8         dp90sel[0x4];
6649	u8         mix90phase[0x8];
6650
6651	u8         ffe_tap0[0x8];
6652	u8         ffe_tap1[0x8];
6653	u8         ffe_tap2[0x8];
6654	u8         ffe_tap3[0x8];
6655
6656	u8         ffe_tap4[0x8];
6657	u8         ffe_tap5[0x8];
6658	u8         ffe_tap6[0x8];
6659	u8         ffe_tap7[0x8];
6660
6661	u8         ffe_tap8[0x8];
6662	u8         mixerbias_tap_amp[0x8];
6663	u8         reserved_3[0x7];
6664	u8         ffe_tap_en[0x9];
6665
6666	u8         ffe_tap_offset0[0x8];
6667	u8         ffe_tap_offset1[0x8];
6668	u8         slicer_offset0[0x10];
6669
6670	u8         mixer_offset0[0x10];
6671	u8         mixer_offset1[0x10];
6672
6673	u8         mixerbgn_inp[0x8];
6674	u8         mixerbgn_inn[0x8];
6675	u8         mixerbgn_refp[0x8];
6676	u8         mixerbgn_refn[0x8];
6677
6678	u8         sel_slicer_lctrl_h[0x1];
6679	u8         sel_slicer_lctrl_l[0x1];
6680	u8         reserved_4[0x1];
6681	u8         ref_mixer_vreg[0x5];
6682	u8         slicer_gctrl[0x8];
6683	u8         lctrl_input[0x8];
6684	u8         mixer_offset_cm1[0x8];
6685
6686	u8         common_mode[0x6];
6687	u8         reserved_5[0x1];
6688	u8         mixer_offset_cm0[0x9];
6689	u8         reserved_6[0x7];
6690	u8         slicer_offset_cm[0x9];
6691};
6692
6693struct mlx5_ifc_slrg_reg_bits {
6694	u8         status[0x4];
6695	u8         version[0x4];
6696	u8         local_port[0x8];
6697	u8         pnat[0x2];
6698	u8         reserved_0[0x2];
6699	u8         lane[0x4];
6700	u8         reserved_1[0x8];
6701
6702	u8         time_to_link_up[0x10];
6703	u8         reserved_2[0xc];
6704	u8         grade_lane_speed[0x4];
6705
6706	u8         grade_version[0x8];
6707	u8         grade[0x18];
6708
6709	u8         reserved_3[0x4];
6710	u8         height_grade_type[0x4];
6711	u8         height_grade[0x18];
6712
6713	u8         height_dz[0x10];
6714	u8         height_dv[0x10];
6715
6716	u8         reserved_4[0x10];
6717	u8         height_sigma[0x10];
6718
6719	u8         reserved_5[0x20];
6720
6721	u8         reserved_6[0x4];
6722	u8         phase_grade_type[0x4];
6723	u8         phase_grade[0x18];
6724
6725	u8         reserved_7[0x8];
6726	u8         phase_eo_pos[0x8];
6727	u8         reserved_8[0x8];
6728	u8         phase_eo_neg[0x8];
6729
6730	u8         ffe_set_tested[0x10];
6731	u8         test_errors_per_lane[0x10];
6732};
6733
6734struct mlx5_ifc_pvlc_reg_bits {
6735	u8         reserved_0[0x8];
6736	u8         local_port[0x8];
6737	u8         reserved_1[0x10];
6738
6739	u8         reserved_2[0x1c];
6740	u8         vl_hw_cap[0x4];
6741
6742	u8         reserved_3[0x1c];
6743	u8         vl_admin[0x4];
6744
6745	u8         reserved_4[0x1c];
6746	u8         vl_operational[0x4];
6747};
6748
6749struct mlx5_ifc_pude_reg_bits {
6750	u8         swid[0x8];
6751	u8         local_port[0x8];
6752	u8         reserved_0[0x4];
6753	u8         admin_status[0x4];
6754	u8         reserved_1[0x4];
6755	u8         oper_status[0x4];
6756
6757	u8         reserved_2[0x60];
6758};
6759
6760enum {
6761	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
6762	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
6763};
6764
6765struct mlx5_ifc_ptys_reg_bits {
6766	u8         reserved_0[0x8];
6767	u8         local_port[0x8];
6768	u8         reserved_1[0xd];
6769	u8         proto_mask[0x3];
6770
6771	u8         reserved_2[0x40];
6772
6773	u8         eth_proto_capability[0x20];
6774
6775	u8         ib_link_width_capability[0x10];
6776	u8         ib_proto_capability[0x10];
6777
6778	u8         reserved_3[0x20];
6779
6780	u8         eth_proto_admin[0x20];
6781
6782	u8         ib_link_width_admin[0x10];
6783	u8         ib_proto_admin[0x10];
6784
6785	u8         reserved_4[0x20];
6786
6787	u8         eth_proto_oper[0x20];
6788
6789	u8         ib_link_width_oper[0x10];
6790	u8         ib_proto_oper[0x10];
6791
6792	u8         reserved_5[0x20];
6793
6794	u8         eth_proto_lp_advertise[0x20];
6795
6796	u8         reserved_6[0x60];
6797};
6798
6799struct mlx5_ifc_ptas_reg_bits {
6800	u8         reserved_0[0x20];
6801
6802	u8         algorithm_options[0x10];
6803	u8         reserved_1[0x4];
6804	u8         repetitions_mode[0x4];
6805	u8         num_of_repetitions[0x8];
6806
6807	u8         grade_version[0x8];
6808	u8         height_grade_type[0x4];
6809	u8         phase_grade_type[0x4];
6810	u8         height_grade_weight[0x8];
6811	u8         phase_grade_weight[0x8];
6812
6813	u8         gisim_measure_bits[0x10];
6814	u8         adaptive_tap_measure_bits[0x10];
6815
6816	u8         ber_bath_high_error_threshold[0x10];
6817	u8         ber_bath_mid_error_threshold[0x10];
6818
6819	u8         ber_bath_low_error_threshold[0x10];
6820	u8         one_ratio_high_threshold[0x10];
6821
6822	u8         one_ratio_high_mid_threshold[0x10];
6823	u8         one_ratio_low_mid_threshold[0x10];
6824
6825	u8         one_ratio_low_threshold[0x10];
6826	u8         ndeo_error_threshold[0x10];
6827
6828	u8         mixer_offset_step_size[0x10];
6829	u8         reserved_2[0x8];
6830	u8         mix90_phase_for_voltage_bath[0x8];
6831
6832	u8         mixer_offset_start[0x10];
6833	u8         mixer_offset_end[0x10];
6834
6835	u8         reserved_3[0x15];
6836	u8         ber_test_time[0xb];
6837};
6838
6839struct mlx5_ifc_pspa_reg_bits {
6840	u8         swid[0x8];
6841	u8         local_port[0x8];
6842	u8         sub_port[0x8];
6843	u8         reserved_0[0x8];
6844
6845	u8         reserved_1[0x20];
6846};
6847
6848struct mlx5_ifc_ppsc_reg_bits {
6849	u8         reserved_0[0x8];
6850	u8         local_port[0x8];
6851	u8         reserved_1[0x10];
6852
6853	u8         reserved_2[0x60];
6854
6855	u8         reserved_3[0x1c];
6856	u8         wrps_admin[0x4];
6857
6858	u8         reserved_4[0x1c];
6859	u8         wrps_status[0x4];
6860
6861	u8         up_th_vld[0x1];
6862	u8         down_th_vld[0x1];
6863	u8         reserved_5[0x6];
6864	u8         up_threshold[0x8];
6865	u8         reserved_6[0x8];
6866	u8         down_threshold[0x8];
6867
6868	u8         reserved_7[0x20];
6869
6870	u8         reserved_8[0x1c];
6871	u8         srps_admin[0x4];
6872
6873	u8         reserved_9[0x60];
6874};
6875
6876struct mlx5_ifc_pplr_reg_bits {
6877	u8         reserved_0[0x8];
6878	u8         local_port[0x8];
6879	u8         reserved_1[0x10];
6880
6881	u8         reserved_2[0x8];
6882	u8         lb_cap[0x8];
6883	u8         reserved_3[0x8];
6884	u8         lb_en[0x8];
6885};
6886
6887struct mlx5_ifc_pplm_reg_bits {
6888	u8         reserved_0[0x8];
6889	u8         local_port[0x8];
6890	u8         reserved_1[0x10];
6891
6892	u8         reserved_2[0x20];
6893
6894	u8         port_profile_mode[0x8];
6895	u8         static_port_profile[0x8];
6896	u8         active_port_profile[0x8];
6897	u8         reserved_3[0x8];
6898
6899	u8         retransmission_active[0x8];
6900	u8         fec_mode_active[0x18];
6901
6902	u8         reserved_4[0x10];
6903	u8         v_100g_fec_override_cap[0x4];
6904	u8         v_50g_fec_override_cap[0x4];
6905	u8         v_25g_fec_override_cap[0x4];
6906	u8         v_10g_40g_fec_override_cap[0x4];
6907
6908	u8         reserved_5[0x10];
6909	u8         v_100g_fec_override_admin[0x4];
6910	u8         v_50g_fec_override_admin[0x4];
6911	u8         v_25g_fec_override_admin[0x4];
6912	u8         v_10g_40g_fec_override_admin[0x4];
6913};
6914
6915struct mlx5_ifc_ppll_reg_bits {
6916	u8         num_pll_groups[0x8];
6917	u8         pll_group[0x8];
6918	u8         reserved_0[0x4];
6919	u8         num_plls[0x4];
6920	u8         reserved_1[0x8];
6921
6922	u8         reserved_2[0x1f];
6923	u8         ae[0x1];
6924
6925	u8         pll_status[4][0x40];
6926};
6927
6928struct mlx5_ifc_ppad_reg_bits {
6929	u8         reserved_0[0x3];
6930	u8         single_mac[0x1];
6931	u8         reserved_1[0x4];
6932	u8         local_port[0x8];
6933	u8         mac_47_32[0x10];
6934
6935	u8         mac_31_0[0x20];
6936
6937	u8         reserved_2[0x40];
6938};
6939
6940struct mlx5_ifc_pmtu_reg_bits {
6941	u8         reserved_0[0x8];
6942	u8         local_port[0x8];
6943	u8         reserved_1[0x10];
6944
6945	u8         max_mtu[0x10];
6946	u8         reserved_2[0x10];
6947
6948	u8         admin_mtu[0x10];
6949	u8         reserved_3[0x10];
6950
6951	u8         oper_mtu[0x10];
6952	u8         reserved_4[0x10];
6953};
6954
6955struct mlx5_ifc_pmpr_reg_bits {
6956	u8         reserved_0[0x8];
6957	u8         module[0x8];
6958	u8         reserved_1[0x10];
6959
6960	u8         reserved_2[0x18];
6961	u8         attenuation_5g[0x8];
6962
6963	u8         reserved_3[0x18];
6964	u8         attenuation_7g[0x8];
6965
6966	u8         reserved_4[0x18];
6967	u8         attenuation_12g[0x8];
6968};
6969
6970struct mlx5_ifc_pmpe_reg_bits {
6971	u8         reserved_0[0x8];
6972	u8         module[0x8];
6973	u8         reserved_1[0xc];
6974	u8         module_status[0x4];
6975
6976	u8         reserved_2[0x14];
6977	u8         error_type[0x4];
6978	u8         reserved_3[0x8];
6979
6980	u8         reserved_4[0x40];
6981};
6982
6983struct mlx5_ifc_pmpc_reg_bits {
6984	u8         module_state_updated[32][0x8];
6985};
6986
6987struct mlx5_ifc_pmlpn_reg_bits {
6988	u8         reserved_0[0x4];
6989	u8         mlpn_status[0x4];
6990	u8         local_port[0x8];
6991	u8         reserved_1[0x10];
6992
6993	u8         e[0x1];
6994	u8         reserved_2[0x1f];
6995};
6996
6997struct mlx5_ifc_pmlp_reg_bits {
6998	u8         rxtx[0x1];
6999	u8         reserved_0[0x7];
7000	u8         local_port[0x8];
7001	u8         reserved_1[0x8];
7002	u8         width[0x8];
7003
7004	u8         lane0_module_mapping[0x20];
7005
7006	u8         lane1_module_mapping[0x20];
7007
7008	u8         lane2_module_mapping[0x20];
7009
7010	u8         lane3_module_mapping[0x20];
7011
7012	u8         reserved_2[0x160];
7013};
7014
7015struct mlx5_ifc_pmaos_reg_bits {
7016	u8         reserved_0[0x8];
7017	u8         module[0x8];
7018	u8         reserved_1[0x4];
7019	u8         admin_status[0x4];
7020	u8         reserved_2[0x4];
7021	u8         oper_status[0x4];
7022
7023	u8         ase[0x1];
7024	u8         ee[0x1];
7025	u8         reserved_3[0x12];
7026	u8         error_type[0x4];
7027	u8         reserved_4[0x6];
7028	u8         e[0x2];
7029
7030	u8         reserved_5[0x40];
7031};
7032
7033struct mlx5_ifc_plpc_reg_bits {
7034	u8         reserved_0[0x4];
7035	u8         profile_id[0xc];
7036	u8         reserved_1[0x4];
7037	u8         proto_mask[0x4];
7038	u8         reserved_2[0x8];
7039
7040	u8         reserved_3[0x10];
7041	u8         lane_speed[0x10];
7042
7043	u8         reserved_4[0x17];
7044	u8         lpbf[0x1];
7045	u8         fec_mode_policy[0x8];
7046
7047	u8         retransmission_capability[0x8];
7048	u8         fec_mode_capability[0x18];
7049
7050	u8         retransmission_support_admin[0x8];
7051	u8         fec_mode_support_admin[0x18];
7052
7053	u8         retransmission_request_admin[0x8];
7054	u8         fec_mode_request_admin[0x18];
7055
7056	u8         reserved_5[0x80];
7057};
7058
7059struct mlx5_ifc_pll_status_data_bits {
7060	u8         reserved_0[0x1];
7061	u8         lock_cal[0x1];
7062	u8         lock_status[0x2];
7063	u8         reserved_1[0x2];
7064	u8         algo_f_ctrl[0xa];
7065	u8         analog_algo_num_var[0x6];
7066	u8         f_ctrl_measure[0xa];
7067
7068	u8         reserved_2[0x2];
7069	u8         analog_var[0x6];
7070	u8         reserved_3[0x2];
7071	u8         high_var[0x6];
7072	u8         reserved_4[0x2];
7073	u8         low_var[0x6];
7074	u8         reserved_5[0x2];
7075	u8         mid_val[0x6];
7076};
7077
7078struct mlx5_ifc_plib_reg_bits {
7079	u8         reserved_0[0x8];
7080	u8         local_port[0x8];
7081	u8         reserved_1[0x8];
7082	u8         ib_port[0x8];
7083
7084	u8         reserved_2[0x60];
7085};
7086
7087struct mlx5_ifc_plbf_reg_bits {
7088	u8         reserved_0[0x8];
7089	u8         local_port[0x8];
7090	u8         reserved_1[0xd];
7091	u8         lbf_mode[0x3];
7092
7093	u8         reserved_2[0x20];
7094};
7095
7096struct mlx5_ifc_pipg_reg_bits {
7097	u8         reserved_0[0x8];
7098	u8         local_port[0x8];
7099	u8         reserved_1[0x10];
7100
7101	u8         dic[0x1];
7102	u8         reserved_2[0x19];
7103	u8         ipg[0x4];
7104	u8         reserved_3[0x2];
7105};
7106
7107struct mlx5_ifc_pifr_reg_bits {
7108	u8         reserved_0[0x8];
7109	u8         local_port[0x8];
7110	u8         reserved_1[0x10];
7111
7112	u8         reserved_2[0xe0];
7113
7114	u8         port_filter[8][0x20];
7115
7116	u8         port_filter_update_en[8][0x20];
7117};
7118
7119struct mlx5_ifc_phys_layer_cntrs_bits {
7120	u8         time_since_last_clear_high[0x20];
7121
7122	u8         time_since_last_clear_low[0x20];
7123
7124	u8         symbol_errors_high[0x20];
7125
7126	u8         symbol_errors_low[0x20];
7127
7128	u8         sync_headers_errors_high[0x20];
7129
7130	u8         sync_headers_errors_low[0x20];
7131
7132	u8         edpl_bip_errors_lane0_high[0x20];
7133
7134	u8         edpl_bip_errors_lane0_low[0x20];
7135
7136	u8         edpl_bip_errors_lane1_high[0x20];
7137
7138	u8         edpl_bip_errors_lane1_low[0x20];
7139
7140	u8         edpl_bip_errors_lane2_high[0x20];
7141
7142	u8         edpl_bip_errors_lane2_low[0x20];
7143
7144	u8         edpl_bip_errors_lane3_high[0x20];
7145
7146	u8         edpl_bip_errors_lane3_low[0x20];
7147
7148	u8         fc_fec_corrected_blocks_lane0_high[0x20];
7149
7150	u8         fc_fec_corrected_blocks_lane0_low[0x20];
7151
7152	u8         fc_fec_corrected_blocks_lane1_high[0x20];
7153
7154	u8         fc_fec_corrected_blocks_lane1_low[0x20];
7155
7156	u8         fc_fec_corrected_blocks_lane2_high[0x20];
7157
7158	u8         fc_fec_corrected_blocks_lane2_low[0x20];
7159
7160	u8         fc_fec_corrected_blocks_lane3_high[0x20];
7161
7162	u8         fc_fec_corrected_blocks_lane3_low[0x20];
7163
7164	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
7165
7166	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
7167
7168	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
7169
7170	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
7171
7172	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
7173
7174	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
7175
7176	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
7177
7178	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
7179
7180	u8         rs_fec_corrected_blocks_high[0x20];
7181
7182	u8         rs_fec_corrected_blocks_low[0x20];
7183
7184	u8         rs_fec_uncorrectable_blocks_high[0x20];
7185
7186	u8         rs_fec_uncorrectable_blocks_low[0x20];
7187
7188	u8         rs_fec_no_errors_blocks_high[0x20];
7189
7190	u8         rs_fec_no_errors_blocks_low[0x20];
7191
7192	u8         rs_fec_single_error_blocks_high[0x20];
7193
7194	u8         rs_fec_single_error_blocks_low[0x20];
7195
7196	u8         rs_fec_corrected_symbols_total_high[0x20];
7197
7198	u8         rs_fec_corrected_symbols_total_low[0x20];
7199
7200	u8         rs_fec_corrected_symbols_lane0_high[0x20];
7201
7202	u8         rs_fec_corrected_symbols_lane0_low[0x20];
7203
7204	u8         rs_fec_corrected_symbols_lane1_high[0x20];
7205
7206	u8         rs_fec_corrected_symbols_lane1_low[0x20];
7207
7208	u8         rs_fec_corrected_symbols_lane2_high[0x20];
7209
7210	u8         rs_fec_corrected_symbols_lane2_low[0x20];
7211
7212	u8         rs_fec_corrected_symbols_lane3_high[0x20];
7213
7214	u8         rs_fec_corrected_symbols_lane3_low[0x20];
7215
7216	u8         link_down_events[0x20];
7217
7218	u8         successful_recovery_events[0x20];
7219
7220	u8         reserved_0[0x180];
7221};
7222
7223struct mlx5_ifc_phrr_reg_bits {
7224	u8         clr[0x1];
7225	u8         reserved_0[0x7];
7226	u8         local_port[0x8];
7227	u8         reserved_1[0x10];
7228
7229	u8         hist_group[0x8];
7230	u8         reserved_2[0x10];
7231	u8         hist_id[0x8];
7232
7233	u8         reserved_3[0x40];
7234
7235	u8         time_since_last_clear_high[0x20];
7236
7237	u8         time_since_last_clear_low[0x20];
7238
7239	u8         bin[10][0x20];
7240};
7241
7242struct mlx5_ifc_phbr_for_prio_reg_bits {
7243	u8         reserved_0[0x18];
7244	u8         prio[0x8];
7245};
7246
7247struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
7248	u8         reserved_0[0x18];
7249	u8         tclass[0x8];
7250};
7251
7252struct mlx5_ifc_phbr_binding_reg_bits {
7253	u8         opcode[0x4];
7254	u8         reserved_0[0x4];
7255	u8         local_port[0x8];
7256	u8         pnat[0x2];
7257	u8         reserved_1[0xe];
7258
7259	u8         hist_group[0x8];
7260	u8         reserved_2[0x10];
7261	u8         hist_id[0x8];
7262
7263	u8         reserved_3[0x10];
7264	u8         hist_type[0x10];
7265
7266	u8         hist_parameters[0x20];
7267
7268	u8         hist_min_value[0x20];
7269
7270	u8         hist_max_value[0x20];
7271
7272	u8         sample_time[0x20];
7273};
7274
7275enum {
7276	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
7277	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
7278};
7279
7280struct mlx5_ifc_pfcc_reg_bits {
7281	u8         reserved_0[0x8];
7282	u8         local_port[0x8];
7283	u8         pnat[0x2];
7284	u8         reserved_1[0xc];
7285	u8         shl_cap[0x1];
7286	u8         shl_opr[0x1];
7287
7288	u8         ppan[0x4];
7289	u8         reserved_2[0x4];
7290	u8         prio_mask_tx[0x8];
7291	u8         reserved_3[0x8];
7292	u8         prio_mask_rx[0x8];
7293
7294	u8         pptx[0x1];
7295	u8         aptx[0x1];
7296	u8         reserved_4[0x6];
7297	u8         pfctx[0x8];
7298	u8         reserved_5[0x10];
7299
7300	u8         pprx[0x1];
7301	u8         aprx[0x1];
7302	u8         reserved_6[0x6];
7303	u8         pfcrx[0x8];
7304	u8         reserved_7[0x10];
7305
7306	u8         reserved_8[0x80];
7307};
7308
7309struct mlx5_ifc_pelc_reg_bits {
7310	u8         op[0x4];
7311	u8         reserved_0[0x4];
7312	u8         local_port[0x8];
7313	u8         reserved_1[0x10];
7314
7315	u8         op_admin[0x8];
7316	u8         op_capability[0x8];
7317	u8         op_request[0x8];
7318	u8         op_active[0x8];
7319
7320	u8         admin[0x40];
7321
7322	u8         capability[0x40];
7323
7324	u8         request[0x40];
7325
7326	u8         active[0x40];
7327
7328	u8         reserved_2[0x80];
7329};
7330
7331struct mlx5_ifc_peir_reg_bits {
7332	u8         reserved_0[0x8];
7333	u8         local_port[0x8];
7334	u8         reserved_1[0x10];
7335
7336	u8         reserved_2[0xc];
7337	u8         error_count[0x4];
7338	u8         reserved_3[0x10];
7339
7340	u8         reserved_4[0xc];
7341	u8         lane[0x4];
7342	u8         reserved_5[0x8];
7343	u8         error_type[0x8];
7344};
7345
7346struct mlx5_ifc_pcap_reg_bits {
7347	u8         reserved_0[0x8];
7348	u8         local_port[0x8];
7349	u8         reserved_1[0x10];
7350
7351	u8         port_capability_mask[4][0x20];
7352};
7353
7354struct mlx5_ifc_pbmc_reg_bits {
7355	u8         reserved_0[0x8];
7356	u8         local_port[0x8];
7357	u8         reserved_1[0x10];
7358
7359	u8         xoff_timer_value[0x10];
7360	u8         xoff_refresh[0x10];
7361
7362	u8         reserved_2[0x10];
7363	u8         port_buffer_size[0x10];
7364
7365	struct mlx5_ifc_bufferx_reg_bits buffer[10];
7366
7367	u8         reserved_3[0x40];
7368
7369	u8         port_shared_buffer[0x40];
7370};
7371
7372struct mlx5_ifc_paos_reg_bits {
7373	u8         swid[0x8];
7374	u8         local_port[0x8];
7375	u8         reserved_0[0x4];
7376	u8         admin_status[0x4];
7377	u8         reserved_1[0x4];
7378	u8         oper_status[0x4];
7379
7380	u8         ase[0x1];
7381	u8         ee[0x1];
7382	u8         reserved_2[0x1c];
7383	u8         e[0x2];
7384
7385	u8         reserved_3[0x40];
7386};
7387
7388struct mlx5_ifc_pamp_reg_bits {
7389	u8         reserved_0[0x8];
7390	u8         opamp_group[0x8];
7391	u8         reserved_1[0xc];
7392	u8         opamp_group_type[0x4];
7393
7394	u8         start_index[0x10];
7395	u8         reserved_2[0x4];
7396	u8         num_of_indices[0xc];
7397
7398	u8         index_data[18][0x10];
7399};
7400
7401struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
7402	u8         llr_rx_cells_high[0x20];
7403
7404	u8         llr_rx_cells_low[0x20];
7405
7406	u8         llr_rx_error_high[0x20];
7407
7408	u8         llr_rx_error_low[0x20];
7409
7410	u8         llr_rx_crc_error_high[0x20];
7411
7412	u8         llr_rx_crc_error_low[0x20];
7413
7414	u8         llr_tx_cells_high[0x20];
7415
7416	u8         llr_tx_cells_low[0x20];
7417
7418	u8         llr_tx_ret_cells_high[0x20];
7419
7420	u8         llr_tx_ret_cells_low[0x20];
7421
7422	u8         llr_tx_ret_events_high[0x20];
7423
7424	u8         llr_tx_ret_events_low[0x20];
7425
7426	u8         reserved_0[0x640];
7427};
7428
7429struct mlx5_ifc_lane_2_module_mapping_bits {
7430	u8         reserved_0[0x6];
7431	u8         rx_lane[0x2];
7432	u8         reserved_1[0x6];
7433	u8         tx_lane[0x2];
7434	u8         reserved_2[0x8];
7435	u8         module[0x8];
7436};
7437
7438struct mlx5_ifc_eth_per_traffic_class_layout_bits {
7439	u8         transmit_queue_high[0x20];
7440
7441	u8         transmit_queue_low[0x20];
7442
7443	u8         reserved_0[0x780];
7444};
7445
7446struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
7447	u8         no_buffer_discard_uc_high[0x20];
7448
7449	u8         no_buffer_discard_uc_low[0x20];
7450
7451	u8         wred_discard_high[0x20];
7452
7453	u8         wred_discard_low[0x20];
7454
7455	u8         reserved_0[0x740];
7456};
7457
7458struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
7459	u8         rx_octets_high[0x20];
7460
7461	u8         rx_octets_low[0x20];
7462
7463	u8         reserved_0[0xc0];
7464
7465	u8         rx_frames_high[0x20];
7466
7467	u8         rx_frames_low[0x20];
7468
7469	u8         tx_octets_high[0x20];
7470
7471	u8         tx_octets_low[0x20];
7472
7473	u8         reserved_1[0xc0];
7474
7475	u8         tx_frames_high[0x20];
7476
7477	u8         tx_frames_low[0x20];
7478
7479	u8         rx_pause_high[0x20];
7480
7481	u8         rx_pause_low[0x20];
7482
7483	u8         rx_pause_duration_high[0x20];
7484
7485	u8         rx_pause_duration_low[0x20];
7486
7487	u8         tx_pause_high[0x20];
7488
7489	u8         tx_pause_low[0x20];
7490
7491	u8         tx_pause_duration_high[0x20];
7492
7493	u8         tx_pause_duration_low[0x20];
7494
7495	u8         rx_pause_transition_high[0x20];
7496
7497	u8         rx_pause_transition_low[0x20];
7498
7499	u8         reserved_2[0x400];
7500};
7501
7502struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
7503	u8         port_transmit_wait_high[0x20];
7504
7505	u8         port_transmit_wait_low[0x20];
7506
7507	u8         ecn_marked_high[0x20];
7508
7509	u8         ecn_marked_low[0x20];
7510
7511	u8         no_buffer_discard_mc_high[0x20];
7512
7513	u8         no_buffer_discard_mc_low[0x20];
7514
7515	u8         reserved_0[0x700];
7516};
7517
7518struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
7519	u8         a_frames_transmitted_ok_high[0x20];
7520
7521	u8         a_frames_transmitted_ok_low[0x20];
7522
7523	u8         a_frames_received_ok_high[0x20];
7524
7525	u8         a_frames_received_ok_low[0x20];
7526
7527	u8         a_frame_check_sequence_errors_high[0x20];
7528
7529	u8         a_frame_check_sequence_errors_low[0x20];
7530
7531	u8         a_alignment_errors_high[0x20];
7532
7533	u8         a_alignment_errors_low[0x20];
7534
7535	u8         a_octets_transmitted_ok_high[0x20];
7536
7537	u8         a_octets_transmitted_ok_low[0x20];
7538
7539	u8         a_octets_received_ok_high[0x20];
7540
7541	u8         a_octets_received_ok_low[0x20];
7542
7543	u8         a_multicast_frames_xmitted_ok_high[0x20];
7544
7545	u8         a_multicast_frames_xmitted_ok_low[0x20];
7546
7547	u8         a_broadcast_frames_xmitted_ok_high[0x20];
7548
7549	u8         a_broadcast_frames_xmitted_ok_low[0x20];
7550
7551	u8         a_multicast_frames_received_ok_high[0x20];
7552
7553	u8         a_multicast_frames_received_ok_low[0x20];
7554
7555	u8         a_broadcast_frames_recieved_ok_high[0x20];
7556
7557	u8         a_broadcast_frames_recieved_ok_low[0x20];
7558
7559	u8         a_in_range_length_errors_high[0x20];
7560
7561	u8         a_in_range_length_errors_low[0x20];
7562
7563	u8         a_out_of_range_length_field_high[0x20];
7564
7565	u8         a_out_of_range_length_field_low[0x20];
7566
7567	u8         a_frame_too_long_errors_high[0x20];
7568
7569	u8         a_frame_too_long_errors_low[0x20];
7570
7571	u8         a_symbol_error_during_carrier_high[0x20];
7572
7573	u8         a_symbol_error_during_carrier_low[0x20];
7574
7575	u8         a_mac_control_frames_transmitted_high[0x20];
7576
7577	u8         a_mac_control_frames_transmitted_low[0x20];
7578
7579	u8         a_mac_control_frames_received_high[0x20];
7580
7581	u8         a_mac_control_frames_received_low[0x20];
7582
7583	u8         a_unsupported_opcodes_received_high[0x20];
7584
7585	u8         a_unsupported_opcodes_received_low[0x20];
7586
7587	u8         a_pause_mac_ctrl_frames_received_high[0x20];
7588
7589	u8         a_pause_mac_ctrl_frames_received_low[0x20];
7590
7591	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
7592
7593	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
7594
7595	u8         reserved_0[0x300];
7596};
7597
7598struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
7599	u8         dot3stats_alignment_errors_high[0x20];
7600
7601	u8         dot3stats_alignment_errors_low[0x20];
7602
7603	u8         dot3stats_fcs_errors_high[0x20];
7604
7605	u8         dot3stats_fcs_errors_low[0x20];
7606
7607	u8         dot3stats_single_collision_frames_high[0x20];
7608
7609	u8         dot3stats_single_collision_frames_low[0x20];
7610
7611	u8         dot3stats_multiple_collision_frames_high[0x20];
7612
7613	u8         dot3stats_multiple_collision_frames_low[0x20];
7614
7615	u8         dot3stats_sqe_test_errors_high[0x20];
7616
7617	u8         dot3stats_sqe_test_errors_low[0x20];
7618
7619	u8         dot3stats_deferred_transmissions_high[0x20];
7620
7621	u8         dot3stats_deferred_transmissions_low[0x20];
7622
7623	u8         dot3stats_late_collisions_high[0x20];
7624
7625	u8         dot3stats_late_collisions_low[0x20];
7626
7627	u8         dot3stats_excessive_collisions_high[0x20];
7628
7629	u8         dot3stats_excessive_collisions_low[0x20];
7630
7631	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
7632
7633	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
7634
7635	u8         dot3stats_carrier_sense_errors_high[0x20];
7636
7637	u8         dot3stats_carrier_sense_errors_low[0x20];
7638
7639	u8         dot3stats_frame_too_longs_high[0x20];
7640
7641	u8         dot3stats_frame_too_longs_low[0x20];
7642
7643	u8         dot3stats_internal_mac_receive_errors_high[0x20];
7644
7645	u8         dot3stats_internal_mac_receive_errors_low[0x20];
7646
7647	u8         dot3stats_symbol_errors_high[0x20];
7648
7649	u8         dot3stats_symbol_errors_low[0x20];
7650
7651	u8         dot3control_in_unknown_opcodes_high[0x20];
7652
7653	u8         dot3control_in_unknown_opcodes_low[0x20];
7654
7655	u8         dot3in_pause_frames_high[0x20];
7656
7657	u8         dot3in_pause_frames_low[0x20];
7658
7659	u8         dot3out_pause_frames_high[0x20];
7660
7661	u8         dot3out_pause_frames_low[0x20];
7662
7663	u8         reserved_0[0x3c0];
7664};
7665
7666struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
7667	u8         if_in_octets_high[0x20];
7668
7669	u8         if_in_octets_low[0x20];
7670
7671	u8         if_in_ucast_pkts_high[0x20];
7672
7673	u8         if_in_ucast_pkts_low[0x20];
7674
7675	u8         if_in_discards_high[0x20];
7676
7677	u8         if_in_discards_low[0x20];
7678
7679	u8         if_in_errors_high[0x20];
7680
7681	u8         if_in_errors_low[0x20];
7682
7683	u8         if_in_unknown_protos_high[0x20];
7684
7685	u8         if_in_unknown_protos_low[0x20];
7686
7687	u8         if_out_octets_high[0x20];
7688
7689	u8         if_out_octets_low[0x20];
7690
7691	u8         if_out_ucast_pkts_high[0x20];
7692
7693	u8         if_out_ucast_pkts_low[0x20];
7694
7695	u8         if_out_discards_high[0x20];
7696
7697	u8         if_out_discards_low[0x20];
7698
7699	u8         if_out_errors_high[0x20];
7700
7701	u8         if_out_errors_low[0x20];
7702
7703	u8         if_in_multicast_pkts_high[0x20];
7704
7705	u8         if_in_multicast_pkts_low[0x20];
7706
7707	u8         if_in_broadcast_pkts_high[0x20];
7708
7709	u8         if_in_broadcast_pkts_low[0x20];
7710
7711	u8         if_out_multicast_pkts_high[0x20];
7712
7713	u8         if_out_multicast_pkts_low[0x20];
7714
7715	u8         if_out_broadcast_pkts_high[0x20];
7716
7717	u8         if_out_broadcast_pkts_low[0x20];
7718
7719	u8         reserved_0[0x480];
7720};
7721
7722struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
7723	u8         ether_stats_drop_events_high[0x20];
7724
7725	u8         ether_stats_drop_events_low[0x20];
7726
7727	u8         ether_stats_octets_high[0x20];
7728
7729	u8         ether_stats_octets_low[0x20];
7730
7731	u8         ether_stats_pkts_high[0x20];
7732
7733	u8         ether_stats_pkts_low[0x20];
7734
7735	u8         ether_stats_broadcast_pkts_high[0x20];
7736
7737	u8         ether_stats_broadcast_pkts_low[0x20];
7738
7739	u8         ether_stats_multicast_pkts_high[0x20];
7740
7741	u8         ether_stats_multicast_pkts_low[0x20];
7742
7743	u8         ether_stats_crc_align_errors_high[0x20];
7744
7745	u8         ether_stats_crc_align_errors_low[0x20];
7746
7747	u8         ether_stats_undersize_pkts_high[0x20];
7748
7749	u8         ether_stats_undersize_pkts_low[0x20];
7750
7751	u8         ether_stats_oversize_pkts_high[0x20];
7752
7753	u8         ether_stats_oversize_pkts_low[0x20];
7754
7755	u8         ether_stats_fragments_high[0x20];
7756
7757	u8         ether_stats_fragments_low[0x20];
7758
7759	u8         ether_stats_jabbers_high[0x20];
7760
7761	u8         ether_stats_jabbers_low[0x20];
7762
7763	u8         ether_stats_collisions_high[0x20];
7764
7765	u8         ether_stats_collisions_low[0x20];
7766
7767	u8         ether_stats_pkts64octets_high[0x20];
7768
7769	u8         ether_stats_pkts64octets_low[0x20];
7770
7771	u8         ether_stats_pkts65to127octets_high[0x20];
7772
7773	u8         ether_stats_pkts65to127octets_low[0x20];
7774
7775	u8         ether_stats_pkts128to255octets_high[0x20];
7776
7777	u8         ether_stats_pkts128to255octets_low[0x20];
7778
7779	u8         ether_stats_pkts256to511octets_high[0x20];
7780
7781	u8         ether_stats_pkts256to511octets_low[0x20];
7782
7783	u8         ether_stats_pkts512to1023octets_high[0x20];
7784
7785	u8         ether_stats_pkts512to1023octets_low[0x20];
7786
7787	u8         ether_stats_pkts1024to1518octets_high[0x20];
7788
7789	u8         ether_stats_pkts1024to1518octets_low[0x20];
7790
7791	u8         ether_stats_pkts1519to2047octets_high[0x20];
7792
7793	u8         ether_stats_pkts1519to2047octets_low[0x20];
7794
7795	u8         ether_stats_pkts2048to4095octets_high[0x20];
7796
7797	u8         ether_stats_pkts2048to4095octets_low[0x20];
7798
7799	u8         ether_stats_pkts4096to8191octets_high[0x20];
7800
7801	u8         ether_stats_pkts4096to8191octets_low[0x20];
7802
7803	u8         ether_stats_pkts8192to10239octets_high[0x20];
7804
7805	u8         ether_stats_pkts8192to10239octets_low[0x20];
7806
7807	u8         reserved_0[0x280];
7808};
7809
7810struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
7811	u8         symbol_error_counter[0x10];
7812	u8         link_error_recovery_counter[0x8];
7813	u8         link_downed_counter[0x8];
7814
7815	u8         port_rcv_errors[0x10];
7816	u8         port_rcv_remote_physical_errors[0x10];
7817
7818	u8         port_rcv_switch_relay_errors[0x10];
7819	u8         port_xmit_discards[0x10];
7820
7821	u8         port_xmit_constraint_errors[0x8];
7822	u8         port_rcv_constraint_errors[0x8];
7823	u8         reserved_0[0x8];
7824	u8         local_link_integrity_errors[0x4];
7825	u8         excessive_buffer_overrun_errors[0x4];
7826
7827	u8         reserved_1[0x10];
7828	u8         vl_15_dropped[0x10];
7829
7830	u8         port_xmit_data[0x20];
7831
7832	u8         port_rcv_data[0x20];
7833
7834	u8         port_xmit_pkts[0x20];
7835
7836	u8         port_rcv_pkts[0x20];
7837
7838	u8         port_xmit_wait[0x20];
7839
7840	u8         reserved_2[0x680];
7841};
7842
7843struct mlx5_ifc_trc_tlb_reg_bits {
7844	u8         reserved_0[0x80];
7845
7846	u8         tlb_addr[0][0x40];
7847};
7848
7849struct mlx5_ifc_trc_read_fifo_reg_bits {
7850	u8         reserved_0[0x10];
7851	u8         requested_event_num[0x10];
7852
7853	u8         reserved_1[0x20];
7854
7855	u8         reserved_2[0x10];
7856	u8         acual_event_num[0x10];
7857
7858	u8         reserved_3[0x20];
7859
7860	u8         event[0][0x40];
7861};
7862
7863struct mlx5_ifc_trc_lock_reg_bits {
7864	u8         reserved_0[0x1f];
7865	u8         lock[0x1];
7866
7867	u8         reserved_1[0x60];
7868};
7869
7870struct mlx5_ifc_trc_filter_reg_bits {
7871	u8         status[0x1];
7872	u8         reserved_0[0xf];
7873	u8         filter_index[0x10];
7874
7875	u8         reserved_1[0x20];
7876
7877	u8         filter_val[0x20];
7878
7879	u8         reserved_2[0x1a0];
7880};
7881
7882struct mlx5_ifc_trc_event_reg_bits {
7883	u8         status[0x1];
7884	u8         reserved_0[0xf];
7885	u8         event_index[0x10];
7886
7887	u8         reserved_1[0x20];
7888
7889	u8         event_id[0x20];
7890
7891	u8         event_selector_val[0x10];
7892	u8         event_selector_size[0x10];
7893
7894	u8         reserved_2[0x180];
7895};
7896
7897struct mlx5_ifc_trc_conf_reg_bits {
7898	u8         limit_en[0x1];
7899	u8         reserved_0[0x3];
7900	u8         dump_mode[0x4];
7901	u8         reserved_1[0x15];
7902	u8         state[0x3];
7903
7904	u8         reserved_2[0x20];
7905
7906	u8         limit_event_index[0x20];
7907
7908	u8         mkey[0x20];
7909
7910	u8         fifo_ready_ev_num[0x20];
7911
7912	u8         reserved_3[0x160];
7913};
7914
7915struct mlx5_ifc_trc_cap_reg_bits {
7916	u8         reserved_0[0x18];
7917	u8         dump_mode[0x8];
7918
7919	u8         reserved_1[0x20];
7920
7921	u8         num_of_events[0x10];
7922	u8         num_of_filters[0x10];
7923
7924	u8         fifo_size[0x20];
7925
7926	u8         tlb_size[0x10];
7927	u8         event_size[0x10];
7928
7929	u8         reserved_2[0x160];
7930};
7931
7932struct mlx5_ifc_set_node_in_bits {
7933	u8         node_description[64][0x8];
7934};
7935
7936struct mlx5_ifc_register_power_settings_bits {
7937	u8         reserved_0[0x18];
7938	u8         power_settings_level[0x8];
7939
7940	u8         reserved_1[0x60];
7941};
7942
7943struct mlx5_ifc_register_host_endianess_bits {
7944	u8         he[0x1];
7945	u8         reserved_0[0x1f];
7946
7947	u8         reserved_1[0x60];
7948};
7949
7950struct mlx5_ifc_register_diag_buffer_ctrl_bits {
7951	u8         physical_address[0x40];
7952};
7953
7954struct mlx5_ifc_qtct_reg_bits {
7955	u8         reserved_0[0x8];
7956	u8         port_number[0x8];
7957	u8         reserved_1[0xd];
7958	u8         prio[0x3];
7959
7960	u8         reserved_2[0x1d];
7961	u8         tclass[0x3];
7962};
7963
7964struct mlx5_ifc_qpdp_reg_bits {
7965	u8         reserved_0[0x8];
7966	u8         port_number[0x8];
7967	u8         reserved_1[0x10];
7968
7969	u8         reserved_2[0x1d];
7970	u8         pprio[0x3];
7971};
7972
7973struct mlx5_ifc_port_info_ro_fields_param_bits {
7974	u8         reserved_0[0x8];
7975	u8         port[0x8];
7976	u8         max_gid[0x10];
7977
7978	u8         reserved_1[0x20];
7979
7980	u8         port_guid[0x40];
7981};
7982
7983struct mlx5_ifc_nvqc_reg_bits {
7984	u8         type[0x20];
7985
7986	u8         reserved_0[0x18];
7987	u8         version[0x4];
7988	u8         reserved_1[0x2];
7989	u8         support_wr[0x1];
7990	u8         support_rd[0x1];
7991};
7992
7993struct mlx5_ifc_nvia_reg_bits {
7994	u8         reserved_0[0x1d];
7995	u8         target[0x3];
7996
7997	u8         reserved_1[0x20];
7998};
7999
8000struct mlx5_ifc_nvdi_reg_bits {
8001	struct mlx5_ifc_config_item_bits configuration_item_header;
8002};
8003
8004struct mlx5_ifc_nvda_reg_bits {
8005	struct mlx5_ifc_config_item_bits configuration_item_header;
8006
8007	u8         configuration_item_data[0x20];
8008};
8009
8010struct mlx5_ifc_node_info_ro_fields_param_bits {
8011	u8         system_image_guid[0x40];
8012
8013	u8         reserved_0[0x40];
8014
8015	u8         node_guid[0x40];
8016
8017	u8         reserved_1[0x10];
8018	u8         max_pkey[0x10];
8019
8020	u8         reserved_2[0x20];
8021};
8022
8023struct mlx5_ifc_ets_tcn_config_reg_bits {
8024	u8         g[0x1];
8025	u8         b[0x1];
8026	u8         r[0x1];
8027	u8         reserved_0[0x9];
8028	u8         group[0x4];
8029	u8         reserved_1[0x9];
8030	u8         bw_allocation[0x7];
8031
8032	u8         reserved_2[0xc];
8033	u8         max_bw_units[0x4];
8034	u8         reserved_3[0x8];
8035	u8         max_bw_value[0x8];
8036};
8037
8038struct mlx5_ifc_ets_global_config_reg_bits {
8039	u8         reserved_0[0x2];
8040	u8         r[0x1];
8041	u8         reserved_1[0x1d];
8042
8043	u8         reserved_2[0xc];
8044	u8         max_bw_units[0x4];
8045	u8         reserved_3[0x8];
8046	u8         max_bw_value[0x8];
8047};
8048
8049struct mlx5_ifc_nodnic_mac_filters_bits {
8050	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
8051
8052	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
8053
8054	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
8055
8056	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
8057
8058	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
8059
8060	u8         reserved_0[0xc0];
8061};
8062
8063struct mlx5_ifc_nodnic_gid_filters_bits {
8064	u8         mgid_filter0[16][0x8];
8065
8066	u8         mgid_filter1[16][0x8];
8067
8068	u8         mgid_filter2[16][0x8];
8069
8070	u8         mgid_filter3[16][0x8];
8071};
8072
8073enum {
8074	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
8075	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
8076};
8077
8078enum {
8079	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
8080	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
8081};
8082
8083struct mlx5_ifc_nodnic_config_reg_bits {
8084	u8         no_dram_nic_revision[0x8];
8085	u8         hardware_format[0x8];
8086	u8         support_receive_filter[0x1];
8087	u8         support_promisc_filter[0x1];
8088	u8         support_promisc_multicast_filter[0x1];
8089	u8         reserved_0[0x2];
8090	u8         log_working_buffer_size[0x3];
8091	u8         log_pkey_table_size[0x4];
8092	u8         reserved_1[0x3];
8093	u8         num_ports[0x1];
8094
8095	u8         reserved_2[0x2];
8096	u8         log_max_ring_size[0x6];
8097	u8         reserved_3[0x18];
8098
8099	u8         lkey[0x20];
8100
8101	u8         cqe_format[0x4];
8102	u8         reserved_4[0x1c];
8103
8104	u8         node_guid[0x40];
8105
8106	u8         reserved_5[0x740];
8107
8108	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
8109
8110	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
8111};
8112
8113struct mlx5_ifc_vlan_layout_bits {
8114	u8         reserved_0[0x14];
8115	u8         vlan[0xc];
8116
8117	u8         reserved_1[0x20];
8118};
8119
8120struct mlx5_ifc_umr_pointer_desc_argument_bits {
8121	u8         reserved_0[0x20];
8122
8123	u8         mkey[0x20];
8124
8125	u8         addressh_63_32[0x20];
8126
8127	u8         addressl_31_0[0x20];
8128};
8129
8130struct mlx5_ifc_ud_adrs_vector_bits {
8131	u8         dc_key[0x40];
8132
8133	u8         ext[0x1];
8134	u8         reserved_0[0x7];
8135	u8         destination_qp_dct[0x18];
8136
8137	u8         static_rate[0x4];
8138	u8         sl_eth_prio[0x4];
8139	u8         fl[0x1];
8140	u8         mlid[0x7];
8141	u8         rlid_udp_sport[0x10];
8142
8143	u8         reserved_1[0x20];
8144
8145	u8         rmac_47_16[0x20];
8146
8147	u8         rmac_15_0[0x10];
8148	u8         tclass[0x8];
8149	u8         hop_limit[0x8];
8150
8151	u8         reserved_2[0x1];
8152	u8         grh[0x1];
8153	u8         reserved_3[0x2];
8154	u8         src_addr_index[0x8];
8155	u8         flow_label[0x14];
8156
8157	u8         rgid_rip[16][0x8];
8158};
8159
8160struct mlx5_ifc_port_module_event_bits {
8161	u8         reserved_0[0x8];
8162	u8         module[0x8];
8163	u8         reserved_1[0xc];
8164	u8         module_status[0x4];
8165
8166	u8         reserved_2[0x14];
8167	u8         error_type[0x4];
8168	u8         reserved_3[0x8];
8169
8170	u8         reserved_4[0xa0];
8171};
8172
8173struct mlx5_ifc_icmd_control_bits {
8174	u8         opcode[0x10];
8175	u8         status[0x8];
8176	u8         reserved_0[0x7];
8177	u8         busy[0x1];
8178};
8179
8180struct mlx5_ifc_eqe_bits {
8181	u8         reserved_0[0x8];
8182	u8         event_type[0x8];
8183	u8         reserved_1[0x8];
8184	u8         event_sub_type[0x8];
8185
8186	u8         reserved_2[0xe0];
8187
8188	union mlx5_ifc_event_auto_bits event_data;
8189
8190	u8         reserved_3[0x10];
8191	u8         signature[0x8];
8192	u8         reserved_4[0x7];
8193	u8         owner[0x1];
8194};
8195
8196enum {
8197	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8198};
8199
8200struct mlx5_ifc_cmd_queue_entry_bits {
8201	u8         type[0x8];
8202	u8         reserved_0[0x18];
8203
8204	u8         input_length[0x20];
8205
8206	u8         input_mailbox_pointer_63_32[0x20];
8207
8208	u8         input_mailbox_pointer_31_9[0x17];
8209	u8         reserved_1[0x9];
8210
8211	u8         command_input_inline_data[16][0x8];
8212
8213	u8         command_output_inline_data[16][0x8];
8214
8215	u8         output_mailbox_pointer_63_32[0x20];
8216
8217	u8         output_mailbox_pointer_31_9[0x17];
8218	u8         reserved_2[0x9];
8219
8220	u8         output_length[0x20];
8221
8222	u8         token[0x8];
8223	u8         signature[0x8];
8224	u8         reserved_3[0x8];
8225	u8         status[0x7];
8226	u8         ownership[0x1];
8227};
8228
8229struct mlx5_ifc_cmd_out_bits {
8230	u8         status[0x8];
8231	u8         reserved_0[0x18];
8232
8233	u8         syndrome[0x20];
8234
8235	u8         command_output[0x20];
8236};
8237
8238struct mlx5_ifc_cmd_in_bits {
8239	u8         opcode[0x10];
8240	u8         reserved_0[0x10];
8241
8242	u8         reserved_1[0x10];
8243	u8         op_mod[0x10];
8244
8245	u8         command[0][0x20];
8246};
8247
8248struct mlx5_ifc_cmd_if_box_bits {
8249	u8         mailbox_data[512][0x8];
8250
8251	u8         reserved_0[0x180];
8252
8253	u8         next_pointer_63_32[0x20];
8254
8255	u8         next_pointer_31_10[0x16];
8256	u8         reserved_1[0xa];
8257
8258	u8         block_number[0x20];
8259
8260	u8         reserved_2[0x8];
8261	u8         token[0x8];
8262	u8         ctrl_signature[0x8];
8263	u8         signature[0x8];
8264};
8265
8266struct mlx5_ifc_mtt_bits {
8267	u8         ptag_63_32[0x20];
8268
8269	u8         ptag_31_8[0x18];
8270	u8         reserved_0[0x6];
8271	u8         wr_en[0x1];
8272	u8         rd_en[0x1];
8273};
8274
8275struct mlx5_ifc_vendor_specific_cap_bits {
8276	u8         type[0x8];
8277	u8         length[0x8];
8278	u8         next_pointer[0x8];
8279	u8         capability_id[0x8];
8280
8281	u8         status[0x3];
8282	u8         reserved_0[0xd];
8283	u8         space[0x10];
8284
8285	u8         counter[0x20];
8286
8287	u8         semaphore[0x20];
8288
8289	u8         flag[0x1];
8290	u8         reserved_1[0x1];
8291	u8         address[0x1e];
8292
8293	u8         data[0x20];
8294};
8295
8296enum {
8297	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8298	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8299	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8300};
8301
8302enum {
8303	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8304	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8305	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8306};
8307
8308enum {
8309	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
8310	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
8311	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
8312	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
8313	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
8314	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
8315	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
8316	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
8317	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
8318	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
8319	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
8320};
8321
8322struct mlx5_ifc_initial_seg_bits {
8323	u8         fw_rev_minor[0x10];
8324	u8         fw_rev_major[0x10];
8325
8326	u8         cmd_interface_rev[0x10];
8327	u8         fw_rev_subminor[0x10];
8328
8329	u8         reserved_0[0x40];
8330
8331	u8         cmdq_phy_addr_63_32[0x20];
8332
8333	u8         cmdq_phy_addr_31_12[0x14];
8334	u8         reserved_1[0x2];
8335	u8         nic_interface[0x2];
8336	u8         log_cmdq_size[0x4];
8337	u8         log_cmdq_stride[0x4];
8338
8339	u8         command_doorbell_vector[0x20];
8340
8341	u8         reserved_2[0xf00];
8342
8343	u8         initializing[0x1];
8344	u8         reserved_3[0x4];
8345	u8         nic_interface_supported[0x3];
8346	u8         reserved_4[0x18];
8347
8348	struct mlx5_ifc_health_buffer_bits health_buffer;
8349
8350	u8         no_dram_nic_offset[0x20];
8351
8352	u8         reserved_5[0x6de0];
8353
8354	u8         internal_timer_h[0x20];
8355
8356	u8         internal_timer_l[0x20];
8357
8358	u8         reserved_6[0x20];
8359
8360	u8         reserved_7[0x1f];
8361	u8         clear_int[0x1];
8362
8363	u8         health_syndrome[0x8];
8364	u8         health_counter[0x18];
8365
8366	u8         reserved_8[0x17fc0];
8367};
8368
8369union mlx5_ifc_icmd_interface_document_bits {
8370	struct mlx5_ifc_fw_version_bits fw_version;
8371	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
8372	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
8373	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
8374	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
8375	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
8376	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
8377	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
8378	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
8379	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
8380	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
8381	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
8382	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
8383	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
8384	u8         reserved_0[0x42c0];
8385};
8386
8387union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
8388	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8389	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8390	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8391	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8392	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8393	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8394	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8395	u8         reserved_0[0x7c0];
8396};
8397
8398struct mlx5_ifc_ppcnt_reg_bits {
8399	u8         swid[0x8];
8400	u8         local_port[0x8];
8401	u8         pnat[0x2];
8402	u8         reserved_0[0x8];
8403	u8         grp[0x6];
8404
8405	u8         clr[0x1];
8406	u8         reserved_1[0x1c];
8407	u8         prio_tc[0x3];
8408
8409	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8410};
8411
8412union mlx5_ifc_ports_control_registers_document_bits {
8413	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
8414	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8415	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8416	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8417	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8418	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8419	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8420	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8421	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
8422	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
8423	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8424	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
8425	struct mlx5_ifc_pamp_reg_bits pamp_reg;
8426	struct mlx5_ifc_paos_reg_bits paos_reg;
8427	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
8428	struct mlx5_ifc_pcap_reg_bits pcap_reg;
8429	struct mlx5_ifc_peir_reg_bits peir_reg;
8430	struct mlx5_ifc_pelc_reg_bits pelc_reg;
8431	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8432	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
8433	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
8434	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
8435	struct mlx5_ifc_phrr_reg_bits phrr_reg;
8436	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8437	struct mlx5_ifc_pifr_reg_bits pifr_reg;
8438	struct mlx5_ifc_pipg_reg_bits pipg_reg;
8439	struct mlx5_ifc_plbf_reg_bits plbf_reg;
8440	struct mlx5_ifc_plib_reg_bits plib_reg;
8441	struct mlx5_ifc_pll_status_data_bits pll_status_data;
8442	struct mlx5_ifc_plpc_reg_bits plpc_reg;
8443	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8444	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8445	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8446	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8447	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8448	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8449	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8450	struct mlx5_ifc_ppad_reg_bits ppad_reg;
8451	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8452	struct mlx5_ifc_ppll_reg_bits ppll_reg;
8453	struct mlx5_ifc_pplm_reg_bits pplm_reg;
8454	struct mlx5_ifc_pplr_reg_bits pplr_reg;
8455	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8456	struct mlx5_ifc_pspa_reg_bits pspa_reg;
8457	struct mlx5_ifc_ptas_reg_bits ptas_reg;
8458	struct mlx5_ifc_ptys_reg_bits ptys_reg;
8459	struct mlx5_ifc_pude_reg_bits pude_reg;
8460	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8461	struct mlx5_ifc_slrg_reg_bits slrg_reg;
8462	struct mlx5_ifc_slrp_reg_bits slrp_reg;
8463	struct mlx5_ifc_sltp_reg_bits sltp_reg;
8464	u8         reserved_0[0x7880];
8465};
8466
8467union mlx5_ifc_debug_enhancements_document_bits {
8468	struct mlx5_ifc_health_buffer_bits health_buffer;
8469	u8         reserved_0[0x200];
8470};
8471
8472union mlx5_ifc_no_dram_nic_document_bits {
8473	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
8474	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
8475	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
8476	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
8477	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
8478	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
8479	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
8480	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
8481	u8         reserved_0[0x3160];
8482};
8483
8484union mlx5_ifc_uplink_pci_interface_document_bits {
8485	struct mlx5_ifc_initial_seg_bits initial_seg;
8486	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
8487	u8         reserved_0[0x20120];
8488};
8489
8490
8491#endif /* MLX5_IFC_H */
8492