jmphyreg.h revision 179335
1179335Syongari/*- 2179335Syongari * Copyright (c) 2008, Pyun YongHyeon 3179335Syongari * All rights reserved. 4179335Syongari * 5179335Syongari * Redistribution and use in source and binary forms, with or without 6179335Syongari * modification, are permitted provided that the following conditions 7179335Syongari * are met: 8179335Syongari * 1. Redistributions of source code must retain the above copyright 9179335Syongari * notice unmodified, this list of conditions, and the following 10179335Syongari * disclaimer. 11179335Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179335Syongari * notice, this list of conditions and the following disclaimer in the 13179335Syongari * documentation and/or other materials provided with the distribution. 14179335Syongari * 15179335Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179335Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179335Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179335Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179335Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179335Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179335Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179335Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179335Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179335Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179335Syongari * SUCH DAMAGE. 26179335Syongari * 27179335Syongari * $FreeBSD: head/sys/dev/mii/jmphyreg.h 179335 2008-05-27 01:16:40Z yongari $ 28179335Syongari */ 29179335Syongari 30179335Syongari#ifndef _DEV_MII_JMPHYREG_H_ 31179335Syongari#define _DEV_MII_JMPHYREG_H_ 32179335Syongari 33179335Syongari/* 34179335Syongari * Registers for the JMicron JMC250 Gigabit PHY. 35179335Syongari */ 36179335Syongari 37179335Syongari/* PHY specific status register. */ 38179335Syongari#define JMPHY_SSR 0x11 39179335Syongari#define JMPHY_SSR_SPEED_1000 0x8000 40179335Syongari#define JMPHY_SSR_SPEED_100 0x4000 41179335Syongari#define JMPHY_SSR_SPEED_10 0x0000 42179335Syongari#define JMPHY_SSR_SPEED_MASK 0xC000 43179335Syongari#define JMPHY_SSR_DUPLEX 0x2000 44179335Syongari#define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800 45179335Syongari#define JMPHY_SSR_LINK_UP 0x0400 46179335Syongari#define JMPHY_SSR_MDI_XOVER 0x0040 47179335Syongari#define JMPHY_SSR_INV_POLARITY 0x0002 48179335Syongari 49179335Syongari/* PHY specific cable length status register. */ 50179335Syongari#define JMPHY_SCL 0x17 51179335Syongari#define JMPHY_SCL_CHAN_D_MASK 0xF000 52179335Syongari#define JMPHY_SCL_CHAN_C_MASK 0x0F00 53179335Syongari#define JMPHY_SCL_CHAN_B_MASK 0x00F0 54179335Syongari#define JMPHY_SCL_CHAN_A_MASK 0x000F 55179335Syongari#define JMPHY_SCL_LEN_35 0 56179335Syongari#define JMPHY_SCL_LEN_40 1 57179335Syongari#define JMPHY_SCL_LEN_50 2 58179335Syongari#define JMPHY_SCL_LEN_60 3 59179335Syongari#define JMPHY_SCL_LEN_70 4 60179335Syongari#define JMPHY_SCL_LEN_80 5 61179335Syongari#define JMPHY_SCL_LEN_90 6 62179335Syongari#define JMPHY_SCL_LEN_100 7 63179335Syongari#define JMPHY_SCL_LEN_110 8 64179335Syongari#define JMPHY_SCL_LEN_120 9 65179335Syongari#define JMPHY_SCL_LEN_130 10 66179335Syongari#define JMPHY_SCL_LEN_140 11 67179335Syongari#define JMPHY_SCL_LEN_150 12 68179335Syongari#define JMPHY_SCL_LEN_160 13 69179335Syongari#define JMPHY_SCL_LEN_170 14 70179335Syongari#define JMPHY_SCL_RSVD 15 71179335Syongari 72179335Syongari/* PHY specific LED control register 1. */ 73179335Syongari#define JMPHY_LED_CTL1 0x18 74179335Syongari#define JMPHY_LED_BLINK_42MS 0x0000 75179335Syongari#define JMPHY_LED_BLINK_84MS 0x2000 76179335Syongari#define JMPHY_LED_BLINK_170MS 0x4000 77179335Syongari#define JMPHY_LED_BLINK_340MS 0x6000 78179335Syongari#define JMPHY_LED_BLINK_670MS 0x8000 79179335Syongari#define JMPHY_LED_BLINK_MASK 0xE000 80179335Syongari#define JMPHY_LED_FLP_GAP_MASK 0x1F00 81179335Syongari#define JMPHY_LED_FLP_GAP_DEFULT 0x1000 82179335Syongari#define JMPHY_LED2_POLARITY_MASK 0x0030 83179335Syongari#define JMPHY_LED1_POLARITY_MASK 0x000C 84179335Syongari#define JMPHY_LED0_POLARITY_MASK 0x0003 85179335Syongari#define JMPHY_LED_ON_LO_OFF_HI 0 86179335Syongari#define JMPHY_LED_ON_HI_OFF_HI 1 87179335Syongari#define JMPHY_LED_ON_LO_OFF_TS 2 88179335Syongari#define JMPHY_LED_ON_HI_OFF_TS 3 89179335Syongari 90179335Syongari/* PHY specific LED control register 2. */ 91179335Syongari#define JMPHY_LED_CTL2 0x19 92179335Syongari#define JMPHY_LED_NO_STRETCH 0x0000 93179335Syongari#define JMPHY_LED_STRETCH_42MS 0x2000 94179335Syongari#define JMPHY_LED_STRETCH_84MS 0x4000 95179335Syongari#define JMPHY_LED_STRETCH_170MS 0x6000 96179335Syongari#define JMPHY_LED_STRETCH_340MS 0x8000 97179335Syongari#define JMPHY_LED_STRETCH_670MS 0xB000 98179335Syongari#define JMPHY_LED_STRETCH_1300MS 0xC000 99179335Syongari#define JMPHY_LED_STRETCH_2700MS 0xE000 100179335Syongari#define JMPHY_LED2_MODE_MASK 0x0F00 101179335Syongari#define JMPHY_LED1_MODE_MASK 0x00F0 102179335Syongari#define JMPHY_LED0_MODE_MASK 0x000F 103179335Syongari 104179335Syongari/* PHY specific test mode control register. */ 105179335Syongari#define JMPHY_TMCTL 0x1A 106179335Syongari#define JMPHY_TMCTL_SLEEP_ENB 0x1000 107179335Syongari 108179335Syongari#endif /* _DEV_MII_JMPHYREG_H_ */ 109