atphy.c revision 211103 
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/mii/atphy.c 211103 2010-08-09 17:22:14Z yongari $");
30
31/*
32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY.
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/socket.h>
40#include <sys/bus.h>
41
42#include <net/if.h>
43#include <net/if_media.h>
44
45#include <dev/mii/mii.h>
46#include <dev/mii/miivar.h>
47#include "miidevs.h"
48
49#include <dev/mii/atphyreg.h>
50
51#include "miibus_if.h"
52
53static int atphy_probe(device_t);
54static int atphy_attach(device_t);
55
56struct atphy_softc {
57	struct mii_softc mii_sc;
58	int mii_oui;
59	int mii_model;
60	int mii_rev;
61};
62
63static device_method_t atphy_methods[] = {
64	/* Device interface. */
65	DEVMETHOD(device_probe,		atphy_probe),
66	DEVMETHOD(device_attach,	atphy_attach),
67	DEVMETHOD(device_detach,	mii_phy_detach),
68	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
69	{ NULL, NULL }
70};
71
72static devclass_t atphy_devclass;
73static driver_t atphy_driver = {
74	"atphy",
75	atphy_methods,
76	sizeof(struct atphy_softc)
77};
78
79DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
80
81static int	atphy_service(struct mii_softc *, struct mii_data *, int);
82static void	atphy_status(struct mii_softc *);
83static void	atphy_reset(struct mii_softc *);
84static uint16_t	atphy_anar(struct ifmedia_entry *);
85static int	atphy_auto(struct mii_softc *);
86
87static const struct mii_phydesc atphys[] = {
88	MII_PHY_DESC(ATHEROS, F1),
89	MII_PHY_DESC(ATHEROS, F1_7),
90	MII_PHY_DESC(ATHEROS, F2),
91	MII_PHY_END
92};
93
94static int
95atphy_probe(device_t dev)
96{
97
98	return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
99}
100
101static int
102atphy_attach(device_t dev)
103{
104	struct atphy_softc *asc;
105	struct mii_softc *sc;
106	struct mii_attach_args *ma;
107	struct mii_data *mii;
108
109	asc = device_get_softc(dev);
110	sc = &asc->mii_sc;
111	ma = device_get_ivars(dev);
112	sc->mii_dev = device_get_parent(dev);
113	mii = device_get_softc(sc->mii_dev);
114	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
115
116	sc->mii_inst = mii->mii_instance;
117	sc->mii_phy = ma->mii_phyno;
118	sc->mii_service = atphy_service;
119	sc->mii_pdata = mii;
120	sc->mii_anegticks = MII_ANEGTICKS_GIGE;
121
122	mii->mii_instance++;
123
124	asc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
125	asc->mii_model = MII_MODEL(ma->mii_id2);
126	asc->mii_rev = MII_REV(ma->mii_id2);
127	if (bootverbose)
128		device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
129		    asc->mii_oui, asc->mii_model, asc->mii_rev);
130
131	atphy_reset(sc);
132
133	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
134	if (sc->mii_capabilities & BMSR_EXTSTAT)
135		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
136	device_printf(dev, " ");
137	mii_phy_add_media(sc);
138	printf("\n");
139
140	MIIBUS_MEDIAINIT(sc->mii_dev);
141	return(0);
142}
143
144static int
145atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
146{
147	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
148	uint16_t anar, bmcr, bmsr;
149
150	switch (cmd) {
151	case MII_POLLSTAT:
152		/*
153		 * If we're not polling our PHY instance, just return.
154		 */
155		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
156			return (0);
157		break;
158
159	case MII_MEDIACHG:
160		/*
161		 * If the media indicates a different PHY instance,
162		 * isolate ourselves.
163		 */
164		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
165			bmcr = PHY_READ(sc, MII_BMCR);
166			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
167			return (0);
168		}
169
170		/*
171		 * If the interface is not up, don't do anything.
172		 */
173		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
174			break;
175
176		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
177		    IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
178			atphy_auto(sc);
179			break;
180		}
181
182		bmcr = 0;
183		switch (IFM_SUBTYPE(ife->ifm_media)) {
184		case IFM_100_TX:
185			bmcr = BMCR_S100;
186			break;
187		case IFM_10_T:
188			bmcr = BMCR_S10;
189			break;
190		case IFM_NONE:
191			bmcr = PHY_READ(sc, MII_BMCR);
192			/*
193			 * XXX
194			 * Due to an unknown reason powering down PHY resulted
195			 * in unexpected results such as inaccessbility of
196			 * hardware of freshly rebooted system. Disable
197			 * powering down PHY until I got more information for
198			 * Attansic/Atheros PHY hardwares.
199			 */
200			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
201			goto done;
202		default:
203			return (EINVAL);
204		}
205
206		anar = atphy_anar(ife);
207		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
208			bmcr |= BMCR_FDX;
209			/* Enable pause. */
210			anar |= (3 << 10);
211		}
212
213		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
214		    EXTSR_1000THDX)) != 0)
215			PHY_WRITE(sc, MII_100T2CR, 0);
216		PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
217
218		/*
219		 * Reset the PHY so all changes take effect.
220		 */
221		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
222		    BMCR_STARTNEG);
223done:
224		break;
225
226	case MII_TICK:
227		/*
228		 * If we're not currently selected, just return.
229		 */
230		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
231			return (0);
232
233		/*
234		 * Is the interface even up?
235		 */
236		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
237			return (0);
238
239		/*
240		 * Only used for autonegotiation.
241		 */
242		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
243			sc->mii_ticks = 0;
244			break;
245		}
246
247		/*
248		 * check for link.
249		 * Read the status register twice; BMSR_LINK is latch-low.
250		 */
251		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
252		if (bmsr & BMSR_LINK) {
253			sc->mii_ticks = 0;
254			break;
255		}
256
257		/* Announce link loss right after it happens. */
258		if (sc->mii_ticks++ == 0)
259			break;
260		if (sc->mii_ticks <= sc->mii_anegticks)
261			return (0);
262
263		sc->mii_ticks = 0;
264		atphy_auto(sc);
265		break;
266	}
267
268	/* Update the media status. */
269	atphy_status(sc);
270
271	/* Callback if something changed. */
272	mii_phy_update(sc, cmd);
273	return (0);
274}
275
276static void
277atphy_status(struct mii_softc *sc)
278{
279	struct mii_data *mii = sc->mii_pdata;
280	uint32_t bmsr, bmcr, ssr;
281
282	mii->mii_media_status = IFM_AVALID;
283	mii->mii_media_active = IFM_ETHER;
284
285	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
286	if ((bmsr & BMSR_LINK) != 0)
287		mii->mii_media_status |= IFM_ACTIVE;
288
289	bmcr = PHY_READ(sc, MII_BMCR);
290	if ((bmcr & BMCR_ISO) != 0) {
291		mii->mii_media_active |= IFM_NONE;
292		mii->mii_media_status = 0;
293		return;
294	}
295
296	if ((bmcr & BMCR_LOOP) != 0)
297		mii->mii_media_active |= IFM_LOOP;
298
299	ssr = PHY_READ(sc, ATPHY_SSR);
300	if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
301		/* Erg, still trying, I guess... */
302		mii->mii_media_active |= IFM_NONE;
303		return;
304	}
305
306	switch (ssr & ATPHY_SSR_SPEED_MASK) {
307	case ATPHY_SSR_1000MBS:
308		mii->mii_media_active |= IFM_1000_T;
309		/*
310		 * atphy(4) got a valid link so reset mii_ticks.
311		 * Resetting mii_ticks is needed in order to
312		 * detect link loss after auto-negotiation.
313		 */
314		sc->mii_ticks = 0;
315		break;
316	case ATPHY_SSR_100MBS:
317		mii->mii_media_active |= IFM_100_TX;
318		sc->mii_ticks = 0;
319		break;
320	case ATPHY_SSR_10MBS:
321		mii->mii_media_active |= IFM_10_T;
322		sc->mii_ticks = 0;
323		break;
324	default:
325		mii->mii_media_active |= IFM_NONE;
326		return;
327	}
328
329	if ((ssr & ATPHY_SSR_DUPLEX) != 0)
330		mii->mii_media_active |= IFM_FDX;
331	else
332		mii->mii_media_active |= IFM_HDX;
333
334	/* XXX Master/Slave, Flow-control */
335}
336
337static void
338atphy_reset(struct mii_softc *sc)
339{
340	struct atphy_softc *asc;
341	uint32_t reg;
342	int i;
343
344	asc = (struct atphy_softc *)sc;
345
346	/* Take PHY out of power down mode. */
347	PHY_WRITE(sc, 29, 0x29);
348	PHY_WRITE(sc, 30, 0);
349
350	reg = PHY_READ(sc, ATPHY_SCR);
351	/* Enable automatic crossover. */
352	reg |= ATPHY_SCR_AUTO_X_MODE;
353	/* Disable power down. */
354	reg &= ~ATPHY_SCR_MAC_PDOWN;
355	/* Enable CRS on Tx. */
356	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
357	/* Auto correction for reversed cable polarity. */
358	reg |= ATPHY_SCR_POLARITY_REVERSAL;
359	PHY_WRITE(sc, ATPHY_SCR, reg);
360
361	/* Workaround F1 bug to reset phy. */
362	atphy_auto(sc);
363
364	for (i = 0; i < 1000; i++) {
365		DELAY(1);
366		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
367			break;
368	}
369}
370
371static uint16_t
372atphy_anar(struct ifmedia_entry *ife)
373{
374	uint16_t anar;
375
376	anar = 0;
377	switch (IFM_SUBTYPE(ife->ifm_media)) {
378	case IFM_AUTO:
379		anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
380		return (anar);
381	case IFM_1000_T:
382		return (anar);
383	case IFM_100_TX:
384		anar |= ANAR_TX;
385		break;
386	case IFM_10_T:
387		anar |= ANAR_10;
388		break;
389	default:
390		return (0);
391	}
392
393	if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
394		if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
395			anar |= ANAR_TX_FD;
396		else
397			anar |= ANAR_10_FD;
398	}
399
400	return (anar);
401}
402
403static int
404atphy_auto(struct mii_softc *sc)
405{
406	uint16_t anar;
407
408	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities);
409	PHY_WRITE(sc, MII_ANAR, anar | (3 << 10) | ANAR_CSMA);
410	if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
411		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
412		    GTCR_ADV_1000THDX);
413	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
414
415	return (EJUSTRETURN);
416}
417