if_lgereg.h revision 162321
1139749Simp/*- 277542Swpaul * Copyright (c) 2001 Wind River Systems 377542Swpaul * Copyright (c) 1997, 1998, 1999, 2000, 2001 477542Swpaul * Bill Paul <wpaul@bsdi.com>. All rights reserved. 577542Swpaul * 677542Swpaul * Redistribution and use in source and binary forms, with or without 777542Swpaul * modification, are permitted provided that the following conditions 877542Swpaul * are met: 977542Swpaul * 1. Redistributions of source code must retain the above copyright 1077542Swpaul * notice, this list of conditions and the following disclaimer. 1177542Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1277542Swpaul * notice, this list of conditions and the following disclaimer in the 1377542Swpaul * documentation and/or other materials provided with the distribution. 1477542Swpaul * 3. All advertising materials mentioning features or use of this software 1577542Swpaul * must display the following acknowledgement: 1677542Swpaul * This product includes software developed by Bill Paul. 1777542Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1877542Swpaul * may be used to endorse or promote products derived from this software 1977542Swpaul * without specific prior written permission. 2077542Swpaul * 2177542Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2277542Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2377542Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2477542Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2577542Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2677542Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2777542Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2877542Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2977542Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3077542Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3177542Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3277542Swpaul * 3377542Swpaul * $FreeBSD: head/sys/dev/lge/if_lgereg.h 162321 2006-09-15 15:16:12Z glebius $ 3477542Swpaul */ 3577542Swpaul 3677542Swpaul 3777542Swpaul#define LGE_MODE1 0x00 /* CSR00 */ 3877542Swpaul#define LGE_MODE2 0x04 /* CSR01 */ 3977542Swpaul#define LGE_PPTXBUF_IDX 0x08 /* CSR02 */ 4077542Swpaul#define LGE_PRODID 0x0C /* CSR03 */ 4177542Swpaul#define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */ 4277542Swpaul#define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */ 4377542Swpaul#define LGE_RSVD0 0x18 /* CSR06 */ 4477542Swpaul#define LGE_PPRXBUF_IDX 0x1C /* CSR07 */ 4577542Swpaul#define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */ 4677542Swpaul#define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */ 4777542Swpaul#define LGE_EECTL 0x28 /* CSR10 */ 4877542Swpaul#define LGE_CHIPSTS 0x2C /* CSR11 */ 4977542Swpaul#define LGE_TXDESC_ADDR_LO 0x30 /* CSR12 */ 5077542Swpaul#define LGE_TXDESC_ADDR_HI 0x34 /* CSR13 */ 5177542Swpaul#define LGE_RXDESC_ADDR_LO 0x38 /* CSR14 */ 5277542Swpaul#define LGE_RXDESC_ADDR_HI 0x3C /* CSR15 */ 5377542Swpaul#define LGE_PPTXCTL 0x40 /* CSR16 */ 5477542Swpaul#define LGE_PPRXCTL 0x44 /* CSR17 */ 5577542Swpaul#define LGE_INTR_PERIOD 0x48 /* CSR18 */ 5677542Swpaul#define LGE_TXFIFO_PKTCNT 0x4C /* CSR19 */ 5777542Swpaul#define LGE_TXFIFO_LOWAT 0x50 /* CSR20 */ 5877542Swpaul#define LGE_TXFIFO_FREEDWORDS 0x54 /* CSR21 */ 5977542Swpaul#define LGE_TXFIFO_WRITE 0x58 /* CSR22 */ 6077542Swpaul#define LGE_RSVD1 0x5C /* CSR23 */ 6177542Swpaul#define LGE_RXFIFO_READ 0x60 /* CSR24 */ 6277542Swpaul#define LGE_RSVD2 0x64 /* CSR25 */ 6377542Swpaul#define LGE_RXFIFO_DWORDCNT 0x68 /* CSR26 */ 6477542Swpaul#define LGE_RXFIFO_HIWAT 0x6C /* CSR27 */ 6577542Swpaul#define LGE_RXFIFO_PKTCNT 0x70 /* CSR28 */ 6677542Swpaul#define LGE_CMD 0x74 /* CSR29 */ 6777542Swpaul#define LGE_IMR 0x78 /* CSR30 */ 6877542Swpaul#define LGE_RSVD3 0x7C /* CSR31 */ 6977542Swpaul#define LGE_ISR 0x80 /* CSR32 */ 7077542Swpaul#define LGE_RSVD4 0x84 /* CSR33 */ 7177542Swpaul#define LGE_MAR0 0x88 /* CSR34 */ 7277542Swpaul#define LGE_MAR1 0x8C /* CSR35 */ 7377542Swpaul#define LGE_LEDCFG0 0x90 /* CSR36 */ 7477542Swpaul#define LGE_LEDCFG1 0x84 /* CSR37 */ 7577542Swpaul#define LGE_LEDCFG2 0x98 /* CSR38 */ 7677542Swpaul#define LGE_LEDCFG3 0x9C /* CSR39 */ 7777542Swpaul#define LGE_RSVD5 0xA0 /* CSR40 */ 7877542Swpaul#define LGE_EEDATA 0xA4 /* CSR41 */ 7977542Swpaul#define LGE_PAR0 0xA8 /* CSR42 */ 8077542Swpaul#define LGE_PAR1 0xAC /* CSR43 */ 8177542Swpaul#define LGE_GMIICTL 0xB0 /* CSR44 */ 8277542Swpaul#define LGE_GMIIMODE 0xB4 /* CSR45 */ 8377542Swpaul#define LGE_STATSIDX 0xB8 /* CSR46 */ 8477542Swpaul#define LGE_STATSVAL 0xBC /* CSR47 */ 8577542Swpaul#define LGE_VLANCTL 0xC0 /* CSR48 */ 8677542Swpaul#define LGE_RSVD6 0xC4 /* CSR49 */ 8777542Swpaul#define LGE_RSVD7 0xC8 /* CSR50 */ 8877542Swpaul#define LGE_CMDSTS 0xCC /* CSR51 */ 8977542Swpaul#define LGE_FLOWCTL_WAT 0xD0 /* CSR52 */ 9077542Swpaul#define LGE_RSVD8 0xD4 /* CSR53 */ 9177542Swpaul#define LGE_RSVD9 0xD8 /* CSR54 */ 9277542Swpaul#define LGE_RSVD10 0xDC /* CSR55 */ 9377542Swpaul#define LGE_RSVD11 0xE0 /* CSR56 */ 9477542Swpaul#define LGE_RSVD12 0xE4 /* CSR57 */ 9577542Swpaul#define LGE_TIMER0_CNT 0xE8 /* CSR58 */ 9677542Swpaul#define LGE_TIMER0_INT 0xEC /* CSR59 */ 9777542Swpaul#define LGE_TIMER1_CNT 0xF0 /* CSR60 */ 9877542Swpaul#define LGE_TIMER1_INT 0xF4 /* CSR61 */ 9977542Swpaul#define LGE_DBG_CMD 0xF8 /* CSR62 */ 10077542Swpaul#define LGE_DBG_DATA 0xFC /* CSR63 */ 10177542Swpaul 10277542Swpaul 10377542Swpaul/* Mode register 1 */ 10477542Swpaul#define LGE_MODE1_SETRST_CTL0 0x00000001 10577542Swpaul#define LGE_MODE1_SOFTRST 0x00000002 10677542Swpaul#define LGE_MODE1_DEBTOD 0x00000004 /* Not documented? */ 10777542Swpaul#define LGE_MODE1_TX_FLOWCTL 0x00000008 /* Not documented? */ 10877542Swpaul#define LGE_MODE1_RXTXRIO 0x00000010 10977542Swpaul#define LGE_MODE1_GMIIPOLL 0x00000020 11077542Swpaul#define LGE_MODE1_TXPAD 0x00000040 11177542Swpaul#define LGE_MODE1_RMVPAD 0x00000080 /* Not documented? */ 11277542Swpaul#define LGE_MODE1_SETRST_CTL1 0x00000100 11377542Swpaul#define LGE_MODE1_TX_ENB 0x00000200 11477542Swpaul#define LGE_MODE1_RX_ENB 0x00000400 11577542Swpaul#define LGE_MODE1_RX_MCAST 0x00000800 11677542Swpaul#define LGE_MODE1_RX_BCAST 0x00001000 11777542Swpaul#define LGE_MODE1_RX_PROMISC 0x00002000 11877542Swpaul#define LGE_MODE1_RX_UCAST 0x00004000 11977542Swpaul#define LGE_MODE1_RX_GIANTS 0x00008000 12077542Swpaul#define LGE_MODE1_SETRST_CTL2 0x00010000 12177542Swpaul#define LGE_MODE1_RX_CRC 0x00020000 12277542Swpaul#define LGE_MODE1_RX_ERRPKTS 0x00040000 12377542Swpaul#define LGE_MODE1_TX_CRC 0x00080000 12477542Swpaul#define LGE_MODE1_DEMDEN 0x00100000 /* Not documented? */ 12577542Swpaul#define LGE_MODE1_MPACK_ENB 0x00200000 12677542Swpaul#define LGE_MODE1_MPACK_BCAST 0x00400000 12777542Swpaul#define LGE_MODE1_RX_FLOWCTL 0x00800000 12877542Swpaul#define LGE_MODE1_SETRST_CTL3 0x01000000 12977542Swpaul#define LGE_MODE1_VLAN_RX 0x02000000 13077542Swpaul#define LGE_MODE1_VLAN_TX 0x04000000 13177542Swpaul#define LGE_MODE1_VLAN_STRIP 0x08000000 13277542Swpaul#define LGE_MODE1_VLAN_INSERT 0x10000000 13377542Swpaul#define LGE_MODE1_GPIO_CTL0 0x20000000 13477542Swpaul#define LGE_MODE1_GPIO_CTL1 0x40000000 13577542Swpaul#define LGE_MODE1_RX_LENCHK 0x80000000 13677542Swpaul 13777542Swpaul 13877542Swpaul/* Mode register 2 */ 13977542Swpaul#define LGE_MODE2_LOOPBACK 0x000000E0 14077542Swpaul#define LGE_MODE2_RX_IPCSUM 0x00001000 14177542Swpaul#define LGE_MODE2_RX_TCPCSUM 0x00002000 14277542Swpaul#define LGE_MODE2_RX_UDPCSUM 0x00004000 14377542Swpaul#define LGE_MODE2_RX_ERRCSUM 0x00008000 14477542Swpaul 14577542Swpaul 14677542Swpaul/* EEPROM register */ 14777542Swpaul#define LGE_EECTL_HAVE_EEPROM 0x00000001 14877542Swpaul#define LGE_EECTL_CMD_READ 0x00000002 14977542Swpaul#define LGE_EECTL_CMD_WRITE 0x00000004 15077542Swpaul#define LGE_EECTL_CSUMERR 0x00000010 15177542Swpaul#define LGE_EECTL_MULTIACCESS 0x00000020 15277542Swpaul#define LGE_EECTL_SINGLEACCESS 0x00000040 15377542Swpaul#define LGE_EECTL_ADDR 0x00001F00 15477542Swpaul#define LGE_EECTL_ROM_TIMING 0x000F0000 15577542Swpaul#define LGE_EECTL_HAVE_FLASH 0x00100000 15677542Swpaul#define LGE_EECTL_WRITEFLASH 0x00200000 15777542Swpaul 15877542Swpaul#define LGE_EE_NODEADDR_0 0x12 15977542Swpaul#define LGE_EE_NODEADDR_1 0x13 16077542Swpaul#define LGE_EE_NODEADDR_2 0x10 16177542Swpaul 16277542Swpaul 16377542Swpaul/* Chip status register */ 16477542Swpaul#define LGE_CHIPSTS_HAVETXSPC 0x00000001 /* have room in TX FIFO for pkt */ 16577542Swpaul#define LGE_CHIPSTS_HAVERXPKT 0x00000002 /* RX FIFO holds complete pkt */ 16677542Swpaul#define LGE_CHIPSTS_FLOWCTL_STS 0x00000004 16777542Swpaul#define LGE_CHIPSTS_GPIO_STS0 0x00000008 16877542Swpaul#define LGE_CHIPSTS_GPIO_STS1 0x00000010 16977542Swpaul#define LGE_CHIPSTS_TXIDLE 0x00000020 17077542Swpaul#define LGE_CHIPSTS_RXIDLE 0x00000040 17177542Swpaul 17277542Swpaul 17377542Swpaul/* TX PacketPropulsion control register */ 17477542Swpaul#define LGE_PPTXCTL_BUFLEN 0x0000FFFF 17577542Swpaul#define LGE_PPTXCTL_BUFID 0x003F0000 17677542Swpaul#define LGE_PPTXCTL_WANTINTR 0x01000000 17777542Swpaul 17877542Swpaul 17977542Swpaul/* RX PacketPropulsion control register */ 18077542Swpaul#define LGE_PPRXCTL_BUFLEN 0x0000FFFF 18177542Swpaul#define LGE_PPRXCTL_BUFID 0x003F0000 18277542Swpaul#define LGE_PPRXCTL_WANTINTR 0x10000000 18377542Swpaul 18477542Swpaul 18577542Swpaul/* Command register */ 18677542Swpaul#define LGE_CMD_SETRST_CTL0 0x00000001 18777542Swpaul#define LGE_CMD_STARTTX 0x00000002 18877542Swpaul#define LGE_CMD_SKIP_RXPKT 0x00000004 18977542Swpaul#define LGE_CMD_DEL_INTREQ 0x00000008 19077542Swpaul#define LGE_CMD_PER_INTREQ 0x00000010 19177542Swpaul#define LGE_CMD_TIMER0 0x00000020 19277542Swpaul#define LGE_CMD_TIMER1 0x00000040 19377542Swpaul 19477542Swpaul 19577542Swpaul/* Interrupt mask register */ 19677542Swpaul#define LGE_IMR_SETRST_CTL0 0x00000001 19777542Swpaul#define LGE_IMR_TXCMDFIFO_EMPTY 0x00000002 19877542Swpaul#define LGE_IMR_TXFIFO_WAT 0x00000004 19977542Swpaul#define LGE_IMR_TXDMA_DONE 0x00000008 20077542Swpaul#define LGE_IMR_DELAYEDINTR 0x00000040 20177542Swpaul#define LGE_IMR_INTR_ENB 0x00000080 20277542Swpaul#define LGE_IMR_SETRST_CTL1 0x00000100 20377542Swpaul#define LGE_IMR_RXCMDFIFO_EMPTY 0x00000200 20477542Swpaul#define LGE_IMR_RXFIFO_WAT 0x00000400 20577542Swpaul#define LGE_IMR_RX_DONE 0x00000800 20677542Swpaul#define LGE_IMR_RXDMA_DONE 0x00001000 20777542Swpaul#define LGE_IMR_PHY_INTR 0x00002000 20877542Swpaul#define LGE_IMR_MAGICPKT 0x00004000 20977542Swpaul#define LGE_IMR_SETRST_CTL2 0x00010000 21077542Swpaul#define LGE_IMR_GPIO0 0x00020000 21177542Swpaul#define LGE_IMR_GPIO1 0x00040000 21277542Swpaul#define LGE_IMR_TIMER0 0x00080000 21377542Swpaul#define LGE_IMR_TIMER1 0x00100000 21477542Swpaul 21577542Swpaul 21677542Swpaul#define LGE_INTRS \ 21777542Swpaul (LGE_IMR_TXCMDFIFO_EMPTY|LGE_IMR_TXDMA_DONE|LGE_IMR_RX_DONE| \ 21877542Swpaul LGE_IMR_RXCMDFIFO_EMPTY|LGE_IMR_RXDMA_DONE|LGE_IMR_PHY_INTR) 21977542Swpaul 22077542Swpaul 22177542Swpaul/* Interrupt status register */ 22277542Swpaul#define LGE_ISR_TXCMDFIFO_EMPTY 0x00000002 22377542Swpaul#define LGE_ISR_TXFIFO_WAT 0x00000004 22477542Swpaul#define LGE_ISR_TXDMA_DONE 0x00000008 22577542Swpaul#define LGE_ISR_DELAYEDINTR 0x00000040 22677542Swpaul#define LGE_ISR_INTR_ENB 0x00000080 22777542Swpaul#define LGE_ISR_RXCMDFIFO_EMPTY 0x00000200 22877542Swpaul#define LGE_ISR_RXFIFO_WAT 0x00000400 22977542Swpaul#define LGE_ISR_RX_DONE 0x00000800 23077542Swpaul#define LGE_ISR_RXDMA_DONE 0x00001000 23177542Swpaul#define LGE_ISR_PHY_INTR 0x00002000 23277542Swpaul#define LGE_ISR_MAGICPKT 0x00004000 23377542Swpaul#define LGE_ISR_GPIO0 0x00020000 23477542Swpaul#define LGE_ISR_GPIO1 0x00040000 23577542Swpaul#define LGE_ISR_TIMER0 0x00080000 23677542Swpaul#define LGE_ISR_TIMER1 0x00100000 23777542Swpaul#define LGE_ISR_RXDMADONE_CNT 0xFF000000 23877542Swpaul#define LGE_RX_DMACNT(x) ((x & LGE_ISR_RXDMADONE_CNT) >> 24) 23977542Swpaul 24077542Swpaul/* LED0 config register */ 24177542Swpaul#define LGE_LED0CFG_ENABLE 0x00000002 24277542Swpaul#define LGE_LED0CFG_INPUT_POL 0x00000004 24377542Swpaul#define LGE_LED0CFG_PULSE_EXP 0x00000008 24477542Swpaul#define LGE_LED0CFG_10MBPS 0x00000010 24577542Swpaul#define LGE_LED0CFG_100MBPS 0x00000100 24677542Swpaul#define LGE_LED0CFG_1000MBPS 0x00000200 24777542Swpaul#define LGE_LED0CFG_FDX 0x00000400 24877542Swpaul#define LGE_LED0CFG_ANEG 0x00000800 24977542Swpaul#define LGE_LED0CFG_LINKSTS 0x00001000 25077542Swpaul#define LGE_LED0CFG_RXMATCH 0x00002000 25177542Swpaul#define LGE_LED0CFG_TX 0x00004000 25277542Swpaul#define LGE_LED0CFG_RX 0x00008000 25377542Swpaul#define LGE_LED0CFG_JABBER 0x00010000 25477542Swpaul#define LGE_LED0CFG_COLLISION 0x00020000 25577542Swpaul#define LGE_LED0CFG_CARRIER 0x00040000 25677542Swpaul#define LGE_LED0CFG_LEDOUT 0x10000000 25777542Swpaul 25877542Swpaul 25977542Swpaul/* LED1 config register */ 26077542Swpaul#define LGE_LED1CFG_ENABLE 0x00000002 26177542Swpaul#define LGE_LED1CFG_INPUT_POL 0x00000004 26277542Swpaul#define LGE_LED1CFG_PULSE_EXP 0x00000008 26377542Swpaul#define LGE_LED1CFG_10MBPS 0x00000010 26477542Swpaul#define LGE_LED1CFG_100MBPS 0x00000100 26577542Swpaul#define LGE_LED1CFG_1000MBPS 0x00000200 26677542Swpaul#define LGE_LED1CFG_FDX 0x00000400 26777542Swpaul#define LGE_LED1CFG_ANEG 0x00000800 26877542Swpaul#define LGE_LED1CFG_LINKSTS 0x00001000 26977542Swpaul#define LGE_LED1CFG_RXMATCH 0x00002000 27077542Swpaul#define LGE_LED1CFG_TX 0x00004000 27177542Swpaul#define LGE_LED1CFG_RX 0x00008000 27277542Swpaul#define LGE_LED1CFG_JABBER 0x00010000 27377542Swpaul#define LGE_LED1CFG_COLLISION 0x00020000 27477542Swpaul#define LGE_LED1CFG_CARRIER 0x00040000 27577542Swpaul#define LGE_LED1CFG_LEDOUT 0x10000000 27677542Swpaul 27777542Swpaul 27877542Swpaul/* LED2 config register */ 27977542Swpaul#define LGE_LED2CFG_ENABLE 0x00000002 28077542Swpaul#define LGE_LED2CFG_INPUT_POL 0x00000004 28177542Swpaul#define LGE_LED2CFG_PULSE_EXP 0x00000008 28277542Swpaul#define LGE_LED2CFG_10MBPS 0x00000010 28377542Swpaul#define LGE_LED2CFG_100MBPS 0x00000100 28477542Swpaul#define LGE_LED2CFG_1000MBPS 0x00000200 28577542Swpaul#define LGE_LED2CFG_FDX 0x00000400 28677542Swpaul#define LGE_LED2CFG_ANEG 0x00000800 28777542Swpaul#define LGE_LED2CFG_LINKSTS 0x00001000 28877542Swpaul#define LGE_LED2CFG_RXMATCH 0x00002000 28977542Swpaul#define LGE_LED2CFG_TX 0x00004000 29077542Swpaul#define LGE_LED2CFG_RX 0x00008000 29177542Swpaul#define LGE_LED2CFG_JABBER 0x00010000 29277542Swpaul#define LGE_LED2CFG_COLLISION 0x00020000 29377542Swpaul#define LGE_LED2CFG_CARRIER 0x00040000 29477542Swpaul#define LGE_LED2CFG_LEDOUT 0x10000000 29577542Swpaul 29677542Swpaul 29777542Swpaul/* GMII PHY access register */ 29877542Swpaul#define LGE_GMIICTL_PHYREG 0x0000001F 29977542Swpaul#define LGE_GMIICTL_CMD 0x00000080 30077542Swpaul#define LGE_GMIICTL_PHYADDR 0x00001F00 30177542Swpaul#define LGE_GMIICTL_CMDBUSY 0x00008000 30277542Swpaul#define LGE_GMIICTL_DATA 0xFFFF0000 30377542Swpaul 30477542Swpaul#define LGE_GMIICMD_READ 0x00000000 30577542Swpaul#define LGE_GMIICMD_WRITE 0x00000080 30677542Swpaul 30777542Swpaul/* GMII PHY mode register */ 30877542Swpaul#define LGE_GMIIMODE_SPEED 0x00000003 30977542Swpaul#define LGE_GMIIMODE_FDX 0x00000004 31077542Swpaul#define LGE_GMIIMODE_PROTSEL 0x00000100 /* 0 == GMII, 1 == TBI */ 31177542Swpaul#define LGE_GMIIMODE_PCSENH 0x00000200 31277542Swpaul 31377542Swpaul#define LGE_SPEED_10 0x00000000 31477542Swpaul#define LGE_SPEED_100 0x00000001 31577542Swpaul#define LGE_SPEED_1000 0x00000002 31677542Swpaul 31777542Swpaul 31877542Swpaul/* VLAN tag control register */ 31977542Swpaul#define LGE_VLANCTL_VLID 0x00000FFF 32077542Swpaul#define LGE_VLANCTL_USERPRIO 0x0000E000 32177542Swpaul#define LGE_VLANCTL_TCI_IDX 0x000D0000 32277542Swpaul#define LGE_VLANCTL_TBLCMD 0x00200000 32377542Swpaul 32477542Swpaul 32577542Swpaul/* Command status register */ 32677542Swpaul#define LGE_CMDSTS_TXDMADONE 0x000000FF 32777542Swpaul#define LGE_CMDSTS_RXDMADONE 0x0000FF00 32877542Swpaul#define LGE_CMDSTS_TXCMDFREE 0x003F0000 32977542Swpaul#define LGE_CMDSTS_RXCMDFREE 0x3F000000 33077542Swpaul 33177542Swpaul#define LGE_TXDMADONE_8BIT LGE_CMDSTS 33277542Swpaul#define LGE_RXDMADONE_8BIT (LGE_CMDSTS + 1) 33377542Swpaul#define LGE_TXCMDFREE_8BIT (LGE_CMDSTS + 2) 33477542Swpaul#define LGE_RXCMDFREE_8BIT (LGE_CMDSTS + 3) 33577542Swpaul 33677542Swpaul#define LGE_MAXCMDS 31 33777542Swpaul 33877542Swpaul/* Index for statistics counters. */ 33977542Swpaul#define LGE_STATS_TX_PKTS_OK 0x00 34077542Swpaul#define LGE_STATS_SINGLE_COLL_PKTS 0x01 34177542Swpaul#define LGE_STATS_MULTI_COLL_PKTS 0x02 34277542Swpaul#define LGE_STATS_RX_PKTS_OK 0x03 34377542Swpaul#define LGE_STATS_FCS_ERRS 0x04 34477542Swpaul#define LGE_STATS_ALIGN_ERRS 0x05 34577542Swpaul#define LGE_STATS_DROPPED_PKTS 0x06 34677542Swpaul#define LGE_STATS_RX_ERR_PKTS 0x07 34777542Swpaul#define LGE_STATS_TX_ERR_PKTS 0x08 34877542Swpaul#define LGE_STATS_LATE_COLLS 0x09 34977542Swpaul#define LGE_STATS_RX_RUNTS 0x0A 35077542Swpaul#define LGE_STATS_RX_GIANTS 0x0B 35177542Swpaul#define LGE_STATS_VLAN_PKTS_ACCEPT 0x0C 35277542Swpaul#define LGE_STATS_VLAN_PKTS_REJECT 0x0D 35377542Swpaul#define LGE_STATS_IP_CSUM_ERR 0x0E 35477542Swpaul#define LGE_STATS_UDP_CSUM_ERR 0x0F 35577542Swpaul#define LGE_STATS_RANGELEN_ERRS 0x10 35677542Swpaul#define LGE_STATS_TCP_CSUM_ERR 0x11 35777542Swpaul#define LGE_STATS_RSVD0 0x12 35877542Swpaul#define LGE_STATS_TX_EXCESS_COLLS 0x13 35977542Swpaul#define LGE_STATS_RX_UCASTS 0x14 36077542Swpaul#define LGE_STATS_RX_MCASTS 0x15 36177542Swpaul#define LGE_STATS_RX_BCASTS 0x16 36277542Swpaul#define LGE_STATS_RX_PAUSE_PKTS 0x17 36377542Swpaul#define LGE_STATS_TX_PAUSE_PKTS 0x18 36477542Swpaul#define LGE_STATS_TX_PKTS_DEFERRED 0x19 36577542Swpaul#define LGE_STATS_TX_EXCESS_DEFER 0x1A 36677542Swpaul#define LGE_STATS_CARRIER_SENSE_ERR 0x1B 36777542Swpaul 36877542Swpaul 36977542Swpaul/* 37077542Swpaul * RX and TX DMA descriptor structures for scatter/gather. 37177542Swpaul * Each descriptor can have up to 31 fragments in it, however for 37277542Swpaul * RX we only need one fragment, and for transmit we only allocate 37377542Swpaul * 10 in order to reduce the amount of space we need for the 37477542Swpaul * descriptor lists. 37577542Swpaul * Note: descriptor structures must be 64-bit aligned. 37677542Swpaul */ 37777542Swpaul 37877542Swpaulstruct lge_rx_desc { 37977542Swpaul /* Hardware descriptor section */ 38077542Swpaul u_int32_t lge_ctl; 38177542Swpaul u_int32_t lge_sts; 38277542Swpaul u_int32_t lge_fragptr_lo; 38377542Swpaul u_int32_t lge_fragptr_hi; 38477542Swpaul u_int16_t lge_fraglen; 38577542Swpaul u_int16_t lge_rsvd0; 38677542Swpaul u_int32_t lge_rsvd1; 38777542Swpaul /* Driver software section */ 38877542Swpaul union { 38977542Swpaul struct mbuf *lge_mbuf; 39077542Swpaul u_int64_t lge_dummy; 39177542Swpaul } lge_u; 39277542Swpaul}; 39377542Swpaul 39477542Swpaulstruct lge_frag { 39577542Swpaul u_int32_t lge_rsvd0; 39677542Swpaul u_int32_t lge_fragptr_lo; 39777542Swpaul u_int32_t lge_fragptr_hi; 39877542Swpaul u_int16_t lge_fraglen; 39977542Swpaul u_int16_t lge_rsvd1; 40077542Swpaul}; 40177542Swpaul 40277542Swpaulstruct lge_tx_desc { 40377542Swpaul /* Hardware descriptor section */ 40477542Swpaul u_int32_t lge_ctl; 40577542Swpaul struct lge_frag lge_frags[10]; 40677542Swpaul u_int32_t lge_rsvd0; 40777542Swpaul union { 40877542Swpaul struct mbuf *lge_mbuf; 40977542Swpaul u_int64_t lge_dummy; 41077542Swpaul } lge_u; 41177542Swpaul}; 41277542Swpaul 41377542Swpaul#define lge_mbuf lge_u.lge_mbuf 41477542Swpaul 41577542Swpaul#define LGE_RXCTL_BUFLEN 0x0000FFFF 41677542Swpaul#define LGE_RXCTL_FRAGCNT 0x001F0000 41777542Swpaul#define LGE_RXCTL_LENERR 0x00400000 41877542Swpaul#define LGE_RXCTL_UCAST 0x00800000 41977542Swpaul#define LGR_RXCTL_BCAST 0x01000000 42077542Swpaul#define LGE_RXCTL_MCAST 0x02000000 42177542Swpaul#define LGE_RXCTL_GIANT 0x04000000 42277542Swpaul#define LGE_RXCTL_OFLOW 0x08000000 42377542Swpaul#define LGE_RXCTL_CRCERR 0x10000000 42477542Swpaul#define LGE_RXCTL_RUNT 0x20000000 42577542Swpaul#define LGE_RXCTL_ALGNERR 0x40000000 42677542Swpaul#define LGE_RXCTL_WANTINTR 0x80000000 42777542Swpaul 42877542Swpaul#define LGE_RXCTL_ERRMASK \ 42977542Swpaul (LGE_RXCTL_LENERR|LGE_RXCTL_OFLOW| \ 43077542Swpaul LGE_RXCTL_CRCERR|LGE_RXCTL_RUNT| \ 43177542Swpaul LGE_RXCTL_ALGNERR) 43277542Swpaul 43377542Swpaul#define LGE_RXSTS_VLTBIDX 0x0000000F 43477542Swpaul#define LGE_RXSTS_VLTBLHIT 0x00000010 43577542Swpaul#define LGE_RXSTS_IPCSUMERR 0x00000100 43677542Swpaul#define LGE_RXSTS_TCPCSUMERR 0x00000200 43777542Swpaul#define LGE_RXSTS_UDPCSUMERR 0x00000400 43877542Swpaul#define LGE_RXSTS_ISIP 0x00000800 43977542Swpaul#define LGE_RXSTS_ISTCP 0x00001000 44077542Swpaul#define LGE_RXSTS_ISUDP 0x00002000 44177542Swpaul 44277542Swpaul#define LGE_TXCTL_BUFLEN 0x0000FFFF 44377542Swpaul#define LGE_TXCTL_FRAGCNT 0x001F0000 44477542Swpaul#define LGE_TXCTL_VLTBIDX 0x0F000000 44577542Swpaul#define LGE_TXCTL_VLIS 0x10000000 44677542Swpaul#define LGE_TXCTL_WANTINTR 0x80000000 44777542Swpaul 44877542Swpaul#define LGE_INC(x, y) (x) = (x + 1) % y 44977542Swpaul#define LGE_FRAGCNT_1 (1<<16) 45077542Swpaul#define LGE_FRAGCNT_10 (10<<16) 45177542Swpaul#define LGE_FRAGCNT(x) (x<<16) 45277542Swpaul#define LGE_RXBYTES(x) (x->lge_ctl & 0xFFFF) 45377542Swpaul#define LGE_RXTAIL(x) \ 45477542Swpaul (x->lge_ldata->lge_rx_list[x->lge_cdata.lge_rx_prod]) 45577542Swpaul 45677542Swpaul#define LGE_RX_LIST_CNT 64 45777542Swpaul#define LGE_TX_LIST_CNT 128 45877542Swpaul 45977542Swpaulstruct lge_list_data { 46077542Swpaul struct lge_rx_desc lge_rx_list[LGE_RX_LIST_CNT]; 46177542Swpaul struct lge_tx_desc lge_tx_list[LGE_TX_LIST_CNT]; 46277542Swpaul}; 46377542Swpaul 46477542Swpaul 46577542Swpaul/* 46677542Swpaul * Level 1 PCI vendor ID. 46777542Swpaul */ 46877542Swpaul#define LGE_VENDORID 0x1394 46977542Swpaul 47077542Swpaul/* 47177542Swpaul * LXT 1001 PCI device IDs 47277542Swpaul */ 47377542Swpaul#define LGE_DEVICEID 0x0001 47477542Swpaul 47577542Swpaulstruct lge_type { 47677542Swpaul u_int16_t lge_vid; 47777542Swpaul u_int16_t lge_did; 47877542Swpaul char *lge_name; 47977542Swpaul}; 48077542Swpaul 48177542Swpaulstruct lge_mii_frame { 48277542Swpaul u_int8_t mii_stdelim; 48377542Swpaul u_int8_t mii_opcode; 48477542Swpaul u_int8_t mii_phyaddr; 48577542Swpaul u_int8_t mii_regaddr; 48677542Swpaul u_int8_t mii_turnaround; 48777542Swpaul u_int16_t mii_data; 48877542Swpaul}; 48977542Swpaul 49077542Swpaul/* 49177542Swpaul * MII constants 49277542Swpaul */ 49377542Swpaul#define LGE_MII_STARTDELIM 0x01 49477542Swpaul#define LGE_MII_READOP 0x02 49577542Swpaul#define LGE_MII_WRITEOP 0x01 49677542Swpaul#define LGE_MII_TURNAROUND 0x02 49777542Swpaul 49877542Swpaul#define LGE_JUMBO_FRAMELEN 9018 49977542Swpaul#define LGE_JUMBO_MTU (LGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 50077542Swpaul#define LGE_JSLOTS 384 50177542Swpaul 50277542Swpaul#define LGE_JRAWLEN (LGE_JUMBO_FRAMELEN + ETHER_ALIGN) 50377542Swpaul#define LGE_JLEN (LGE_JRAWLEN + (sizeof(u_int64_t) - \ 50477542Swpaul (LGE_JRAWLEN % sizeof(u_int64_t)))) 50577542Swpaul#define LGE_JPAGESZ PAGE_SIZE 50677542Swpaul#define LGE_RESID (LGE_JPAGESZ - (LGE_JLEN * LGE_JSLOTS) % LGE_JPAGESZ) 50777542Swpaul#define LGE_JMEM ((LGE_JLEN * LGE_JSLOTS) + LGE_RESID) 50877542Swpaul 50977542Swpaulstruct lge_jpool_entry { 51077542Swpaul int slot; 51177542Swpaul SLIST_ENTRY(lge_jpool_entry) jpool_entries; 51277542Swpaul}; 51377542Swpaul 51477542Swpaulstruct lge_ring_data { 51577542Swpaul int lge_rx_prod; 51677542Swpaul int lge_rx_cons; 51777542Swpaul int lge_tx_prod; 51877542Swpaul int lge_tx_cons; 51977542Swpaul /* Stick the jumbo mem management stuff here too. */ 52077542Swpaul caddr_t lge_jslots[LGE_JSLOTS]; 52177542Swpaul void *lge_jumbo_buf; 52277542Swpaul}; 52377542Swpaul 52477542Swpaulstruct lge_softc { 525147256Sbrooks struct ifnet *lge_ifp; 526162321Sglebius device_t lge_dev; 52777542Swpaul bus_space_handle_t lge_bhandle; 52877542Swpaul bus_space_tag_t lge_btag; 52977542Swpaul struct resource *lge_res; 53077542Swpaul struct resource *lge_irq; 53177542Swpaul void *lge_intrhand; 53277542Swpaul device_t lge_miibus; 53377542Swpaul u_int8_t lge_type; 53477542Swpaul u_int8_t lge_link; 53577542Swpaul u_int8_t lge_pcs; 53677542Swpaul int lge_if_flags; 53777542Swpaul struct lge_list_data *lge_ldata; 53877542Swpaul struct lge_ring_data lge_cdata; 539152727Sjhb struct callout lge_stat_callout; 540152727Sjhb struct mtx lge_mtx; 54177542Swpaul SLIST_HEAD(__lge_jfreehead, lge_jpool_entry) lge_jfree_listhead; 54277542Swpaul SLIST_HEAD(__lge_jinusehead, lge_jpool_entry) lge_jinuse_listhead; 54377542Swpaul}; 54477542Swpaul 54577542Swpaul/* 54677542Swpaul * register space access macros 54777542Swpaul */ 54877542Swpaul#define CSR_WRITE_4(sc, reg, val) \ 54977542Swpaul bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val) 55077542Swpaul 55177542Swpaul#define CSR_READ_2(sc, reg) \ 55277542Swpaul bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg) 55377542Swpaul 55477542Swpaul#define CSR_WRITE_2(sc, reg, val) \ 55577542Swpaul bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val) 55677542Swpaul 55777542Swpaul#define CSR_READ_4(sc, reg) \ 55877542Swpaul bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg) 55977542Swpaul 56077542Swpaul#define CSR_WRITE_1(sc, reg, val) \ 56177542Swpaul bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val) 56277542Swpaul 56377542Swpaul#define CSR_READ_1(sc, reg) \ 56477542Swpaul bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg) 56577542Swpaul 566152727Sjhb#define LGE_LOCK(sc) mtx_lock(&(sc)->lge_mtx) 567152727Sjhb#define LGE_UNLOCK(sc) mtx_unlock(&(sc)->lge_mtx) 568152727Sjhb#define LGE_LOCK_ASSERT(sc) mtx_assert(&(sc)->lge_mtx, MA_OWNED) 569152727Sjhb 57077542Swpaul#define LGE_TIMEOUT 1000 57177542Swpaul#define LGE_RXLEN 1536 57277542Swpaul#define LGE_MIN_FRAMELEN 60 57377542Swpaul 57477542Swpaul/* 57577542Swpaul * PCI low memory base and low I/O base register, and 57677542Swpaul * other PCI registers. 57777542Swpaul */ 57877542Swpaul 57977542Swpaul#define LGE_PCI_VENDOR_ID 0x00 58077542Swpaul#define LGE_PCI_DEVICE_ID 0x02 58177542Swpaul#define LGE_PCI_COMMAND 0x04 58277542Swpaul#define LGE_PCI_STATUS 0x06 58377542Swpaul#define LGE_PCI_REVID 0x08 58477542Swpaul#define LGE_PCI_CLASSCODE 0x09 58577542Swpaul#define LGE_PCI_CACHELEN 0x0C 58677542Swpaul#define LGE_PCI_LATENCY_TIMER 0x0D 58777542Swpaul#define LGE_PCI_HEADER_TYPE 0x0E 58877542Swpaul#define LGE_PCI_LOIO 0x10 58977542Swpaul#define LGE_PCI_LOMEM 0x14 59077542Swpaul#define LGE_PCI_BIOSROM 0x30 59177542Swpaul#define LGE_PCI_INTLINE 0x3C 59277542Swpaul#define LGE_PCI_INTPIN 0x3D 59377542Swpaul#define LGE_PCI_MINGNT 0x3E 59477542Swpaul#define LGE_PCI_MINLAT 0x0F 59577542Swpaul#define LGE_PCI_RESETOPT 0x48 59677542Swpaul#define LGE_PCI_EEPROM_DATA 0x4C 59777542Swpaul 59877542Swpaul/* power management registers */ 59977542Swpaul#define LGE_PCI_CAPID 0x50 /* 8 bits */ 60077542Swpaul#define LGE_PCI_NEXTPTR 0x51 /* 8 bits */ 60177542Swpaul#define LGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 60277542Swpaul#define LGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 60377542Swpaul 60477542Swpaul#define LGE_PSTATE_MASK 0x0003 60577542Swpaul#define LGE_PSTATE_D0 0x0000 60677542Swpaul#define LGE_PSTATE_D1 0x0001 60777542Swpaul#define LGE_PSTATE_D2 0x0002 60877542Swpaul#define LGE_PSTATE_D3 0x0003 60977542Swpaul#define LGE_PME_EN 0x0010 61077542Swpaul#define LGE_PME_STATUS 0x8000 611