1179055Sjfv/****************************************************************************** 2171384Sjfv 3283620Serj Copyright (c) 2001-2015, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: releng/10.3/sys/dev/ixgbe/ixgbe_api.c 295524 2016-02-11 16:16:10Z sbruno $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_api.h" 36171384Sjfv#include "ixgbe_common.h" 37171384Sjfv 38295524Ssbruno#define IXGBE_EMPTY_PARAM 39295524Ssbruno 40283620Serjstatic const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41295524Ssbruno IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42283620Serj}; 43283620Serj 44283620Serjstatic const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45283620Serj IXGBE_MVALS_INIT(_X540) 46283620Serj}; 47283620Serj 48283620Serjstatic const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49283620Serj IXGBE_MVALS_INIT(_X550) 50283620Serj}; 51283620Serj 52283620Serjstatic const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53283620Serj IXGBE_MVALS_INIT(_X550EM_x) 54283620Serj}; 55283620Serj 56171384Sjfv/** 57251964Sjfv * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 58251964Sjfv * @hw: pointer to hardware structure 59251964Sjfv * @map: pointer to u8 arr for returning map 60251964Sjfv * 61251964Sjfv * Read the rtrup2tc HW register and resolve its content into map 62251964Sjfv **/ 63251964Sjfvvoid ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 64251964Sjfv{ 65251964Sjfv if (hw->mac.ops.get_rtrup2tc) 66251964Sjfv hw->mac.ops.get_rtrup2tc(hw, map); 67251964Sjfv} 68251964Sjfv 69251964Sjfv/** 70171384Sjfv * ixgbe_init_shared_code - Initialize the shared code 71171384Sjfv * @hw: pointer to hardware structure 72171384Sjfv * 73171384Sjfv * This will assign function pointers and assign the MAC type and PHY code. 74171384Sjfv * Does not touch the hardware. This function must be called prior to any 75171384Sjfv * other function in the shared code. The ixgbe_hw structure should be 76171384Sjfv * memset to 0 prior to calling this function. The following fields in 77171384Sjfv * hw structure should be filled in prior to calling this function: 78171384Sjfv * hw_addr, back, device_id, vendor_id, subsystem_device_id, 79185352Sjfv * subsystem_vendor_id, and revision_id 80171384Sjfv **/ 81171384Sjfvs32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 82171384Sjfv{ 83172043Sjfv s32 status; 84171384Sjfv 85200239Sjfv DEBUGFUNC("ixgbe_init_shared_code"); 86200239Sjfv 87171384Sjfv /* 88172043Sjfv * Set the mac type 89172043Sjfv */ 90172043Sjfv ixgbe_set_mac_type(hw); 91172043Sjfv 92172043Sjfv switch (hw->mac.type) { 93172043Sjfv case ixgbe_mac_82598EB: 94179055Sjfv status = ixgbe_init_ops_82598(hw); 95172043Sjfv break; 96190873Sjfv case ixgbe_mac_82599EB: 97190873Sjfv status = ixgbe_init_ops_82599(hw); 98190873Sjfv break; 99283620Serj case ixgbe_mac_X540: 100283620Serj status = ixgbe_init_ops_X540(hw); 101283620Serj break; 102283620Serj case ixgbe_mac_X550: 103283620Serj status = ixgbe_init_ops_X550(hw); 104283620Serj break; 105283620Serj case ixgbe_mac_X550EM_x: 106283620Serj status = ixgbe_init_ops_X550EM(hw); 107283620Serj break; 108215911Sjfv case ixgbe_mac_82599_vf: 109230775Sjfv case ixgbe_mac_X540_vf: 110283620Serj case ixgbe_mac_X550_vf: 111283620Serj case ixgbe_mac_X550EM_x_vf: 112215911Sjfv status = ixgbe_init_ops_vf(hw); 113215911Sjfv break; 114172043Sjfv default: 115172043Sjfv status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 116172043Sjfv break; 117172043Sjfv } 118295524Ssbruno hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 119172043Sjfv 120172043Sjfv return status; 121172043Sjfv} 122172043Sjfv 123172043Sjfv/** 124172043Sjfv * ixgbe_set_mac_type - Sets MAC type 125172043Sjfv * @hw: pointer to the HW structure 126172043Sjfv * 127172043Sjfv * This function sets the mac type of the adapter based on the 128172043Sjfv * vendor ID and device ID stored in the hw structure. 129172043Sjfv **/ 130172043Sjfvs32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 131172043Sjfv{ 132172043Sjfv s32 ret_val = IXGBE_SUCCESS; 133172043Sjfv 134179055Sjfv DEBUGFUNC("ixgbe_set_mac_type\n"); 135172043Sjfv 136251964Sjfv if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 137251964Sjfv ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 138251964Sjfv "Unsupported vendor id: %x", hw->vendor_id); 139251964Sjfv return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 140251964Sjfv } 141251964Sjfv 142283620Serj hw->mvals = ixgbe_mvals_base; 143283620Serj 144247822Sjfv switch (hw->device_id) { 145247822Sjfv case IXGBE_DEV_ID_82598: 146247822Sjfv case IXGBE_DEV_ID_82598_BX: 147247822Sjfv case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 148247822Sjfv case IXGBE_DEV_ID_82598AF_DUAL_PORT: 149247822Sjfv case IXGBE_DEV_ID_82598AT: 150247822Sjfv case IXGBE_DEV_ID_82598AT2: 151247822Sjfv case IXGBE_DEV_ID_82598EB_CX4: 152247822Sjfv case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 153247822Sjfv case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 154247822Sjfv case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 155247822Sjfv case IXGBE_DEV_ID_82598EB_XF_LR: 156247822Sjfv case IXGBE_DEV_ID_82598EB_SFP_LOM: 157247822Sjfv hw->mac.type = ixgbe_mac_82598EB; 158247822Sjfv break; 159247822Sjfv case IXGBE_DEV_ID_82599_KX4: 160247822Sjfv case IXGBE_DEV_ID_82599_KX4_MEZZ: 161247822Sjfv case IXGBE_DEV_ID_82599_XAUI_LOM: 162247822Sjfv case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 163247822Sjfv case IXGBE_DEV_ID_82599_KR: 164247822Sjfv case IXGBE_DEV_ID_82599_SFP: 165247822Sjfv case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 166247822Sjfv case IXGBE_DEV_ID_82599_SFP_FCOE: 167247822Sjfv case IXGBE_DEV_ID_82599_SFP_EM: 168247822Sjfv case IXGBE_DEV_ID_82599_SFP_SF2: 169247822Sjfv case IXGBE_DEV_ID_82599_SFP_SF_QP: 170283620Serj case IXGBE_DEV_ID_82599_QSFP_SF_QP: 171247822Sjfv case IXGBE_DEV_ID_82599EN_SFP: 172247822Sjfv case IXGBE_DEV_ID_82599_CX4: 173247822Sjfv case IXGBE_DEV_ID_82599_BYPASS: 174247822Sjfv case IXGBE_DEV_ID_82599_T3_LOM: 175247822Sjfv hw->mac.type = ixgbe_mac_82599EB; 176247822Sjfv break; 177247822Sjfv case IXGBE_DEV_ID_82599_VF: 178247822Sjfv case IXGBE_DEV_ID_82599_VF_HV: 179247822Sjfv hw->mac.type = ixgbe_mac_82599_vf; 180247822Sjfv break; 181247822Sjfv case IXGBE_DEV_ID_X540_VF: 182247822Sjfv case IXGBE_DEV_ID_X540_VF_HV: 183247822Sjfv hw->mac.type = ixgbe_mac_X540_vf; 184283620Serj hw->mvals = ixgbe_mvals_X540; 185247822Sjfv break; 186247822Sjfv case IXGBE_DEV_ID_X540T: 187283620Serj case IXGBE_DEV_ID_X540T1: 188247822Sjfv case IXGBE_DEV_ID_X540_BYPASS: 189247822Sjfv hw->mac.type = ixgbe_mac_X540; 190283620Serj hw->mvals = ixgbe_mvals_X540; 191247822Sjfv break; 192283620Serj case IXGBE_DEV_ID_X550T: 193295524Ssbruno case IXGBE_DEV_ID_X550T1: 194283620Serj hw->mac.type = ixgbe_mac_X550; 195283620Serj hw->mvals = ixgbe_mvals_X550; 196283620Serj break; 197283620Serj case IXGBE_DEV_ID_X550EM_X_KX4: 198283620Serj case IXGBE_DEV_ID_X550EM_X_KR: 199283620Serj case IXGBE_DEV_ID_X550EM_X_10G_T: 200283620Serj case IXGBE_DEV_ID_X550EM_X_1G_T: 201283620Serj case IXGBE_DEV_ID_X550EM_X_SFP: 202283620Serj hw->mac.type = ixgbe_mac_X550EM_x; 203283620Serj hw->mvals = ixgbe_mvals_X550EM_x; 204283620Serj break; 205283620Serj case IXGBE_DEV_ID_X550_VF: 206283620Serj case IXGBE_DEV_ID_X550_VF_HV: 207283620Serj hw->mac.type = ixgbe_mac_X550_vf; 208283620Serj hw->mvals = ixgbe_mvals_X550; 209283620Serj break; 210283620Serj case IXGBE_DEV_ID_X550EM_X_VF: 211283620Serj case IXGBE_DEV_ID_X550EM_X_VF_HV: 212283620Serj hw->mac.type = ixgbe_mac_X550EM_x_vf; 213283620Serj hw->mvals = ixgbe_mvals_X550EM_x; 214283620Serj break; 215247822Sjfv default: 216172043Sjfv ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 217251964Sjfv ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 218251964Sjfv "Unsupported device id: %x", 219251964Sjfv hw->device_id); 220247822Sjfv break; 221171384Sjfv } 222171384Sjfv 223179055Sjfv DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 224230775Sjfv hw->mac.type, ret_val); 225172043Sjfv return ret_val; 226171384Sjfv} 227171384Sjfv 228171384Sjfv/** 229171384Sjfv * ixgbe_init_hw - Initialize the hardware 230171384Sjfv * @hw: pointer to hardware structure 231171384Sjfv * 232171384Sjfv * Initialize the hardware by resetting and then starting the hardware 233171384Sjfv **/ 234171384Sjfvs32 ixgbe_init_hw(struct ixgbe_hw *hw) 235171384Sjfv{ 236179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 237230775Sjfv IXGBE_NOT_IMPLEMENTED); 238171384Sjfv} 239171384Sjfv 240171384Sjfv/** 241171384Sjfv * ixgbe_reset_hw - Performs a hardware reset 242171384Sjfv * @hw: pointer to hardware structure 243171384Sjfv * 244171384Sjfv * Resets the hardware by resetting the transmit and receive units, masks and 245171384Sjfv * clears all interrupts, performs a PHY reset, and performs a MAC reset 246171384Sjfv **/ 247171384Sjfvs32 ixgbe_reset_hw(struct ixgbe_hw *hw) 248171384Sjfv{ 249179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 250230775Sjfv IXGBE_NOT_IMPLEMENTED); 251171384Sjfv} 252171384Sjfv 253171384Sjfv/** 254179055Sjfv * ixgbe_start_hw - Prepares hardware for Rx/Tx 255171384Sjfv * @hw: pointer to hardware structure 256171384Sjfv * 257171384Sjfv * Starts the hardware by filling the bus info structure and media type, 258171384Sjfv * clears all on chip counters, initializes receive address registers, 259171384Sjfv * multicast table, VLAN filter table, calls routine to setup link and 260171384Sjfv * flow control settings, and leaves transmit and receive units disabled 261171384Sjfv * and uninitialized. 262171384Sjfv **/ 263171384Sjfvs32 ixgbe_start_hw(struct ixgbe_hw *hw) 264171384Sjfv{ 265179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 266230775Sjfv IXGBE_NOT_IMPLEMENTED); 267171384Sjfv} 268171384Sjfv 269171384Sjfv/** 270205720Sjfv * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 271205720Sjfv * which is disabled by default in ixgbe_start_hw(); 272205720Sjfv * 273205720Sjfv * @hw: pointer to hardware structure 274205720Sjfv * 275205720Sjfv * Enable relaxed ordering; 276205720Sjfv **/ 277205720Sjfvvoid ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 278205720Sjfv{ 279205720Sjfv if (hw->mac.ops.enable_relaxed_ordering) 280205720Sjfv hw->mac.ops.enable_relaxed_ordering(hw); 281205720Sjfv} 282205720Sjfv 283205720Sjfv/** 284171384Sjfv * ixgbe_clear_hw_cntrs - Clear hardware counters 285171384Sjfv * @hw: pointer to hardware structure 286171384Sjfv * 287171384Sjfv * Clears all hardware statistics counters by reading them from the hardware 288171384Sjfv * Statistics counters are clear on read. 289171384Sjfv **/ 290171384Sjfvs32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 291171384Sjfv{ 292179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 293230775Sjfv IXGBE_NOT_IMPLEMENTED); 294171384Sjfv} 295171384Sjfv 296171384Sjfv/** 297171384Sjfv * ixgbe_get_media_type - Get media type 298171384Sjfv * @hw: pointer to hardware structure 299171384Sjfv * 300171384Sjfv * Returns the media type (fiber, copper, backplane) 301171384Sjfv **/ 302171384Sjfvenum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 303171384Sjfv{ 304179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 305230775Sjfv ixgbe_media_type_unknown); 306171384Sjfv} 307171384Sjfv 308171384Sjfv/** 309171384Sjfv * ixgbe_get_mac_addr - Get MAC address 310171384Sjfv * @hw: pointer to hardware structure 311171384Sjfv * @mac_addr: Adapter MAC address 312171384Sjfv * 313171384Sjfv * Reads the adapter's MAC address from the first Receive Address Register 314179055Sjfv * (RAR0) A reset of the adapter must have been performed prior to calling 315179055Sjfv * this function in order for the MAC address to have been loaded from the 316179055Sjfv * EEPROM into RAR0 317171384Sjfv **/ 318171384Sjfvs32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 319171384Sjfv{ 320179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 321230775Sjfv (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 322171384Sjfv} 323171384Sjfv 324171384Sjfv/** 325190873Sjfv * ixgbe_get_san_mac_addr - Get SAN MAC address 326190873Sjfv * @hw: pointer to hardware structure 327190873Sjfv * @san_mac_addr: SAN MAC address 328190873Sjfv * 329190873Sjfv * Reads the SAN MAC address from the EEPROM, if it's available. This is 330190873Sjfv * per-port, so set_lan_id() must be called before reading the addresses. 331190873Sjfv **/ 332190873Sjfvs32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 333190873Sjfv{ 334190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 335230775Sjfv (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 336190873Sjfv} 337190873Sjfv 338190873Sjfv/** 339190873Sjfv * ixgbe_set_san_mac_addr - Write a SAN MAC address 340190873Sjfv * @hw: pointer to hardware structure 341190873Sjfv * @san_mac_addr: SAN MAC address 342190873Sjfv * 343190873Sjfv * Writes A SAN MAC address to the EEPROM. 344190873Sjfv **/ 345190873Sjfvs32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 346190873Sjfv{ 347190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 348230775Sjfv (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 349190873Sjfv} 350190873Sjfv 351190873Sjfv/** 352190873Sjfv * ixgbe_get_device_caps - Get additional device capabilities 353190873Sjfv * @hw: pointer to hardware structure 354190873Sjfv * @device_caps: the EEPROM word for device capabilities 355190873Sjfv * 356190873Sjfv * Reads the extra device capabilities from the EEPROM 357190873Sjfv **/ 358190873Sjfvs32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 359190873Sjfv{ 360190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 361230775Sjfv (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 362190873Sjfv} 363190873Sjfv 364190873Sjfv/** 365200239Sjfv * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 366200239Sjfv * @hw: pointer to hardware structure 367200239Sjfv * @wwnn_prefix: the alternative WWNN prefix 368200239Sjfv * @wwpn_prefix: the alternative WWPN prefix 369200239Sjfv * 370200239Sjfv * This function will read the EEPROM from the alternative SAN MAC address 371200239Sjfv * block to check the support for the alternative WWNN/WWPN prefix support. 372200239Sjfv **/ 373200239Sjfvs32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 374230775Sjfv u16 *wwpn_prefix) 375200239Sjfv{ 376200239Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 377230775Sjfv (hw, wwnn_prefix, wwpn_prefix), 378230775Sjfv IXGBE_NOT_IMPLEMENTED); 379200239Sjfv} 380200239Sjfv 381200239Sjfv/** 382215911Sjfv * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 383215911Sjfv * @hw: pointer to hardware structure 384215911Sjfv * @bs: the fcoe boot status 385215911Sjfv * 386215911Sjfv * This function will read the FCOE boot status from the iSCSI FCOE block 387215911Sjfv **/ 388215911Sjfvs32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 389215911Sjfv{ 390215911Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 391230775Sjfv (hw, bs), 392230775Sjfv IXGBE_NOT_IMPLEMENTED); 393215911Sjfv} 394215911Sjfv 395215911Sjfv/** 396171384Sjfv * ixgbe_get_bus_info - Set PCI bus info 397171384Sjfv * @hw: pointer to hardware structure 398171384Sjfv * 399171384Sjfv * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 400171384Sjfv **/ 401171384Sjfvs32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 402171384Sjfv{ 403179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 404230775Sjfv IXGBE_NOT_IMPLEMENTED); 405171384Sjfv} 406171384Sjfv 407171384Sjfv/** 408179055Sjfv * ixgbe_get_num_of_tx_queues - Get Tx queues 409171384Sjfv * @hw: pointer to hardware structure 410171384Sjfv * 411171384Sjfv * Returns the number of transmit queues for the given adapter. 412171384Sjfv **/ 413171384Sjfvu32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 414171384Sjfv{ 415179055Sjfv return hw->mac.max_tx_queues; 416171384Sjfv} 417171384Sjfv 418171384Sjfv/** 419179055Sjfv * ixgbe_get_num_of_rx_queues - Get Rx queues 420171384Sjfv * @hw: pointer to hardware structure 421171384Sjfv * 422171384Sjfv * Returns the number of receive queues for the given adapter. 423171384Sjfv **/ 424171384Sjfvu32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 425171384Sjfv{ 426179055Sjfv return hw->mac.max_rx_queues; 427171384Sjfv} 428171384Sjfv 429171384Sjfv/** 430179055Sjfv * ixgbe_stop_adapter - Disable Rx/Tx units 431171384Sjfv * @hw: pointer to hardware structure 432171384Sjfv * 433171384Sjfv * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 434171384Sjfv * disables transmit and receive units. The adapter_stopped flag is used by 435171384Sjfv * the shared code and drivers to determine if the adapter is in a stopped 436171384Sjfv * state and should not touch the hardware. 437171384Sjfv **/ 438171384Sjfvs32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 439171384Sjfv{ 440179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 441230775Sjfv IXGBE_NOT_IMPLEMENTED); 442171384Sjfv} 443171384Sjfv 444171384Sjfv/** 445215911Sjfv * ixgbe_read_pba_string - Reads part number string from EEPROM 446215911Sjfv * @hw: pointer to hardware structure 447215911Sjfv * @pba_num: stores the part number string from the EEPROM 448215911Sjfv * @pba_num_size: part number string buffer length 449215911Sjfv * 450215911Sjfv * Reads the part number string from the EEPROM. 451215911Sjfv **/ 452215911Sjfvs32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 453215911Sjfv{ 454215911Sjfv return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 455215911Sjfv} 456215911Sjfv 457215911Sjfv/** 458179055Sjfv * ixgbe_read_pba_num - Reads part number from EEPROM 459179055Sjfv * @hw: pointer to hardware structure 460179055Sjfv * @pba_num: stores the part number from the EEPROM 461179055Sjfv * 462179055Sjfv * Reads the part number from the EEPROM. 463179055Sjfv **/ 464179055Sjfvs32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 465179055Sjfv{ 466179055Sjfv return ixgbe_read_pba_num_generic(hw, pba_num); 467179055Sjfv} 468179055Sjfv 469179055Sjfv/** 470171384Sjfv * ixgbe_identify_phy - Get PHY type 471171384Sjfv * @hw: pointer to hardware structure 472171384Sjfv * 473171384Sjfv * Determines the physical layer module found on the current adapter. 474171384Sjfv **/ 475171384Sjfvs32 ixgbe_identify_phy(struct ixgbe_hw *hw) 476171384Sjfv{ 477171384Sjfv s32 status = IXGBE_SUCCESS; 478171384Sjfv 479171384Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 480215911Sjfv status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 481230775Sjfv IXGBE_NOT_IMPLEMENTED); 482171384Sjfv } 483171384Sjfv 484171384Sjfv return status; 485171384Sjfv} 486171384Sjfv 487171384Sjfv/** 488171384Sjfv * ixgbe_reset_phy - Perform a PHY reset 489171384Sjfv * @hw: pointer to hardware structure 490171384Sjfv **/ 491171384Sjfvs32 ixgbe_reset_phy(struct ixgbe_hw *hw) 492171384Sjfv{ 493171384Sjfv s32 status = IXGBE_SUCCESS; 494171384Sjfv 495171384Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 496185352Sjfv if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 497185352Sjfv status = IXGBE_ERR_PHY; 498171384Sjfv } 499171384Sjfv 500171384Sjfv if (status == IXGBE_SUCCESS) { 501179055Sjfv status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 502230775Sjfv IXGBE_NOT_IMPLEMENTED); 503171384Sjfv } 504171384Sjfv return status; 505171384Sjfv} 506171384Sjfv 507171384Sjfv/** 508179055Sjfv * ixgbe_get_phy_firmware_version - 509179055Sjfv * @hw: pointer to hardware structure 510179055Sjfv * @firmware_version: pointer to firmware version 511179055Sjfv **/ 512179055Sjfvs32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 513179055Sjfv{ 514179055Sjfv s32 status = IXGBE_SUCCESS; 515179055Sjfv 516179055Sjfv status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 517230775Sjfv (hw, firmware_version), 518230775Sjfv IXGBE_NOT_IMPLEMENTED); 519179055Sjfv return status; 520179055Sjfv} 521179055Sjfv 522179055Sjfv/** 523171384Sjfv * ixgbe_read_phy_reg - Read PHY register 524171384Sjfv * @hw: pointer to hardware structure 525171384Sjfv * @reg_addr: 32 bit address of PHY register to read 526171384Sjfv * @phy_data: Pointer to read data from PHY register 527171384Sjfv * 528171384Sjfv * Reads a value from a specified PHY register 529171384Sjfv **/ 530171384Sjfvs32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 531230775Sjfv u16 *phy_data) 532171384Sjfv{ 533190873Sjfv if (hw->phy.id == 0) 534190873Sjfv ixgbe_identify_phy(hw); 535190873Sjfv 536179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 537230775Sjfv device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 538171384Sjfv} 539171384Sjfv 540171384Sjfv/** 541171384Sjfv * ixgbe_write_phy_reg - Write PHY register 542171384Sjfv * @hw: pointer to hardware structure 543171384Sjfv * @reg_addr: 32 bit PHY register to write 544171384Sjfv * @phy_data: Data to write to the PHY register 545171384Sjfv * 546171384Sjfv * Writes a value to specified PHY register 547171384Sjfv **/ 548171384Sjfvs32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 549230775Sjfv u16 phy_data) 550171384Sjfv{ 551190873Sjfv if (hw->phy.id == 0) 552190873Sjfv ixgbe_identify_phy(hw); 553190873Sjfv 554179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 555230775Sjfv device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 556179055Sjfv} 557171384Sjfv 558179055Sjfv/** 559179055Sjfv * ixgbe_setup_phy_link - Restart PHY autoneg 560179055Sjfv * @hw: pointer to hardware structure 561179055Sjfv * 562179055Sjfv * Restart autonegotiation and PHY and waits for completion. 563179055Sjfv **/ 564179055Sjfvs32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 565179055Sjfv{ 566179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 567230775Sjfv IXGBE_NOT_IMPLEMENTED); 568179055Sjfv} 569171384Sjfv 570179055Sjfv/** 571283620Serj * ixgbe_setup_internal_phy - Configure integrated PHY 572283620Serj * @hw: pointer to hardware structure 573283620Serj * 574283620Serj * Reconfigure the integrated PHY in order to enable talk to the external PHY. 575283620Serj * Returns success if not implemented, since nothing needs to be done in this 576283620Serj * case. 577283620Serj */ 578283620Serjs32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 579283620Serj{ 580283620Serj return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 581283620Serj IXGBE_SUCCESS); 582283620Serj} 583283620Serj 584283620Serj/** 585179055Sjfv * ixgbe_check_phy_link - Determine link and speed status 586179055Sjfv * @hw: pointer to hardware structure 587179055Sjfv * 588179055Sjfv * Reads a PHY register to determine if link is up and the current speed for 589179055Sjfv * the PHY. 590179055Sjfv **/ 591179055Sjfvs32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 592230775Sjfv bool *link_up) 593179055Sjfv{ 594179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 595230775Sjfv link_up), IXGBE_NOT_IMPLEMENTED); 596171384Sjfv} 597171384Sjfv 598171384Sjfv/** 599179055Sjfv * ixgbe_setup_phy_link_speed - Set auto advertise 600179055Sjfv * @hw: pointer to hardware structure 601179055Sjfv * @speed: new link speed 602179055Sjfv * 603179055Sjfv * Sets the auto advertised capabilities 604179055Sjfv **/ 605179055Sjfvs32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 606230775Sjfv bool autoneg_wait_to_complete) 607179055Sjfv{ 608179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 609247822Sjfv autoneg_wait_to_complete), 610230775Sjfv IXGBE_NOT_IMPLEMENTED); 611179055Sjfv} 612179055Sjfv 613179055Sjfv/** 614283620Serj * ixgbe_set_phy_power - Control the phy power state 615283620Serj * @hw: pointer to hardware structure 616283620Serj * @on: TRUE for on, FALSE for off 617283620Serj */ 618283620Serjs32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 619283620Serj{ 620283620Serj return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 621283620Serj IXGBE_NOT_IMPLEMENTED); 622283620Serj} 623283620Serj 624283620Serj/** 625171384Sjfv * ixgbe_check_link - Get link and speed status 626171384Sjfv * @hw: pointer to hardware structure 627171384Sjfv * 628171384Sjfv * Reads the links register to determine if link is up and the current speed 629171384Sjfv **/ 630171384Sjfvs32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 631230775Sjfv bool *link_up, bool link_up_wait_to_complete) 632171384Sjfv{ 633179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 634230775Sjfv link_up, link_up_wait_to_complete), 635230775Sjfv IXGBE_NOT_IMPLEMENTED); 636171384Sjfv} 637171384Sjfv 638171384Sjfv/** 639215911Sjfv * ixgbe_disable_tx_laser - Disable Tx laser 640215911Sjfv * @hw: pointer to hardware structure 641215911Sjfv * 642215911Sjfv * If the driver needs to disable the laser on SFI optics. 643215911Sjfv **/ 644215911Sjfvvoid ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 645215911Sjfv{ 646215911Sjfv if (hw->mac.ops.disable_tx_laser) 647215911Sjfv hw->mac.ops.disable_tx_laser(hw); 648215911Sjfv} 649215911Sjfv 650215911Sjfv/** 651215911Sjfv * ixgbe_enable_tx_laser - Enable Tx laser 652215911Sjfv * @hw: pointer to hardware structure 653215911Sjfv * 654215911Sjfv * If the driver needs to enable the laser on SFI optics. 655215911Sjfv **/ 656215911Sjfvvoid ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 657215911Sjfv{ 658215911Sjfv if (hw->mac.ops.enable_tx_laser) 659215911Sjfv hw->mac.ops.enable_tx_laser(hw); 660215911Sjfv} 661215911Sjfv 662215911Sjfv/** 663215911Sjfv * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 664215911Sjfv * @hw: pointer to hardware structure 665215911Sjfv * 666215911Sjfv * When the driver changes the link speeds that it can support then 667215911Sjfv * flap the tx laser to alert the link partner to start autotry 668215911Sjfv * process on its end. 669215911Sjfv **/ 670215911Sjfvvoid ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 671215911Sjfv{ 672215911Sjfv if (hw->mac.ops.flap_tx_laser) 673215911Sjfv hw->mac.ops.flap_tx_laser(hw); 674215911Sjfv} 675215911Sjfv 676215911Sjfv/** 677200239Sjfv * ixgbe_setup_link - Set link speed 678171384Sjfv * @hw: pointer to hardware structure 679171384Sjfv * @speed: new link speed 680171384Sjfv * 681200239Sjfv * Configures link settings. Restarts the link. 682200239Sjfv * Performs autonegotiation if needed. 683171384Sjfv **/ 684200239Sjfvs32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 685230775Sjfv bool autoneg_wait_to_complete) 686171384Sjfv{ 687200239Sjfv return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 688247822Sjfv autoneg_wait_to_complete), 689230775Sjfv IXGBE_NOT_IMPLEMENTED); 690171384Sjfv} 691171384Sjfv 692171384Sjfv/** 693283620Serj * ixgbe_setup_mac_link - Set link speed 694283620Serj * @hw: pointer to hardware structure 695283620Serj * @speed: new link speed 696283620Serj * 697283620Serj * Configures link settings. Restarts the link. 698283620Serj * Performs autonegotiation if needed. 699283620Serj **/ 700283620Serjs32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 701283620Serj bool autoneg_wait_to_complete) 702283620Serj{ 703283620Serj return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 704283620Serj autoneg_wait_to_complete), 705283620Serj IXGBE_NOT_IMPLEMENTED); 706283620Serj} 707283620Serj 708283620Serj/** 709179055Sjfv * ixgbe_get_link_capabilities - Returns link capabilities 710171384Sjfv * @hw: pointer to hardware structure 711171384Sjfv * 712179055Sjfv * Determines the link capabilities of the current configuration. 713171384Sjfv **/ 714179055Sjfvs32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 715230775Sjfv bool *autoneg) 716171384Sjfv{ 717179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 718230775Sjfv speed, autoneg), IXGBE_NOT_IMPLEMENTED); 719171384Sjfv} 720171384Sjfv 721171384Sjfv/** 722179055Sjfv * ixgbe_led_on - Turn on LEDs 723171384Sjfv * @hw: pointer to hardware structure 724171384Sjfv * @index: led number to turn on 725171384Sjfv * 726171384Sjfv * Turns on the software controllable LEDs. 727171384Sjfv **/ 728171384Sjfvs32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 729171384Sjfv{ 730179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 731230775Sjfv IXGBE_NOT_IMPLEMENTED); 732171384Sjfv} 733171384Sjfv 734171384Sjfv/** 735179055Sjfv * ixgbe_led_off - Turn off LEDs 736171384Sjfv * @hw: pointer to hardware structure 737171384Sjfv * @index: led number to turn off 738171384Sjfv * 739171384Sjfv * Turns off the software controllable LEDs. 740171384Sjfv **/ 741171384Sjfvs32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 742171384Sjfv{ 743179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 744230775Sjfv IXGBE_NOT_IMPLEMENTED); 745171384Sjfv} 746171384Sjfv 747171384Sjfv/** 748179055Sjfv * ixgbe_blink_led_start - Blink LEDs 749171384Sjfv * @hw: pointer to hardware structure 750171384Sjfv * @index: led number to blink 751171384Sjfv * 752171384Sjfv * Blink LED based on index. 753171384Sjfv **/ 754171384Sjfvs32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 755171384Sjfv{ 756179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 757230775Sjfv IXGBE_NOT_IMPLEMENTED); 758171384Sjfv} 759171384Sjfv 760171384Sjfv/** 761179055Sjfv * ixgbe_blink_led_stop - Stop blinking LEDs 762171384Sjfv * @hw: pointer to hardware structure 763171384Sjfv * 764171384Sjfv * Stop blinking LED based on index. 765171384Sjfv **/ 766171384Sjfvs32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 767171384Sjfv{ 768179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 769230775Sjfv IXGBE_NOT_IMPLEMENTED); 770171384Sjfv} 771171384Sjfv 772171384Sjfv/** 773179055Sjfv * ixgbe_init_eeprom_params - Initialize EEPROM parameters 774171384Sjfv * @hw: pointer to hardware structure 775171384Sjfv * 776171384Sjfv * Initializes the EEPROM parameters ixgbe_eeprom_info within the 777171384Sjfv * ixgbe_hw struct in order to set up EEPROM access. 778171384Sjfv **/ 779171384Sjfvs32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 780171384Sjfv{ 781179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 782230775Sjfv IXGBE_NOT_IMPLEMENTED); 783171384Sjfv} 784171384Sjfv 785171384Sjfv 786171384Sjfv/** 787171384Sjfv * ixgbe_write_eeprom - Write word to EEPROM 788171384Sjfv * @hw: pointer to hardware structure 789171384Sjfv * @offset: offset within the EEPROM to be written to 790171384Sjfv * @data: 16 bit word to be written to the EEPROM 791171384Sjfv * 792171384Sjfv * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 793171384Sjfv * called after this function, the EEPROM will most likely contain an 794171384Sjfv * invalid checksum. 795171384Sjfv **/ 796171384Sjfvs32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 797171384Sjfv{ 798179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 799230775Sjfv IXGBE_NOT_IMPLEMENTED); 800171384Sjfv} 801171384Sjfv 802171384Sjfv/** 803230775Sjfv * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 804230775Sjfv * @hw: pointer to hardware structure 805230775Sjfv * @offset: offset within the EEPROM to be written to 806230775Sjfv * @data: 16 bit word(s) to be written to the EEPROM 807230775Sjfv * @words: number of words 808230775Sjfv * 809230775Sjfv * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 810230775Sjfv * called after this function, the EEPROM will most likely contain an 811230775Sjfv * invalid checksum. 812230775Sjfv **/ 813230775Sjfvs32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 814230775Sjfv u16 *data) 815230775Sjfv{ 816230775Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 817230775Sjfv (hw, offset, words, data), 818230775Sjfv IXGBE_NOT_IMPLEMENTED); 819230775Sjfv} 820230775Sjfv 821230775Sjfv/** 822171384Sjfv * ixgbe_read_eeprom - Read word from EEPROM 823171384Sjfv * @hw: pointer to hardware structure 824171384Sjfv * @offset: offset within the EEPROM to be read 825171384Sjfv * @data: read 16 bit value from EEPROM 826171384Sjfv * 827171384Sjfv * Reads 16 bit value from EEPROM 828171384Sjfv **/ 829171384Sjfvs32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 830171384Sjfv{ 831179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 832230775Sjfv IXGBE_NOT_IMPLEMENTED); 833171384Sjfv} 834171384Sjfv 835171384Sjfv/** 836230775Sjfv * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 837230775Sjfv * @hw: pointer to hardware structure 838230775Sjfv * @offset: offset within the EEPROM to be read 839230775Sjfv * @data: read 16 bit word(s) from EEPROM 840230775Sjfv * @words: number of words 841230775Sjfv * 842230775Sjfv * Reads 16 bit word(s) from EEPROM 843230775Sjfv **/ 844230775Sjfvs32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 845230775Sjfv u16 words, u16 *data) 846230775Sjfv{ 847230775Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 848230775Sjfv (hw, offset, words, data), 849230775Sjfv IXGBE_NOT_IMPLEMENTED); 850230775Sjfv} 851230775Sjfv 852230775Sjfv/** 853171384Sjfv * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 854171384Sjfv * @hw: pointer to hardware structure 855171384Sjfv * @checksum_val: calculated checksum 856171384Sjfv * 857171384Sjfv * Performs checksum calculation and validates the EEPROM checksum 858171384Sjfv **/ 859171384Sjfvs32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 860171384Sjfv{ 861179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 862230775Sjfv (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 863171384Sjfv} 864171384Sjfv 865171384Sjfv/** 866171384Sjfv * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 867171384Sjfv * @hw: pointer to hardware structure 868171384Sjfv **/ 869171384Sjfvs32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 870171384Sjfv{ 871179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 872230775Sjfv IXGBE_NOT_IMPLEMENTED); 873171384Sjfv} 874171384Sjfv 875171384Sjfv/** 876190873Sjfv * ixgbe_insert_mac_addr - Find a RAR for this mac address 877190873Sjfv * @hw: pointer to hardware structure 878190873Sjfv * @addr: Address to put into receive address register 879190873Sjfv * @vmdq: VMDq pool to assign 880190873Sjfv * 881190873Sjfv * Puts an ethernet address into a receive address register, or 882190873Sjfv * finds the rar that it is aleady in; adds to the pool list 883190873Sjfv **/ 884190873Sjfvs32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 885190873Sjfv{ 886190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 887230775Sjfv (hw, addr, vmdq), 888190873Sjfv IXGBE_NOT_IMPLEMENTED); 889190873Sjfv} 890190873Sjfv 891190873Sjfv/** 892179055Sjfv * ixgbe_set_rar - Set Rx address register 893171384Sjfv * @hw: pointer to hardware structure 894179055Sjfv * @index: Receive address register to write 895171384Sjfv * @addr: Address to put into receive address register 896179055Sjfv * @vmdq: VMDq "set" 897171384Sjfv * @enable_addr: set flag that address is active 898171384Sjfv * 899171384Sjfv * Puts an ethernet address into a receive address register. 900171384Sjfv **/ 901179055Sjfvs32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 902230775Sjfv u32 enable_addr) 903171384Sjfv{ 904179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 905230775Sjfv enable_addr), IXGBE_NOT_IMPLEMENTED); 906171384Sjfv} 907171384Sjfv 908171384Sjfv/** 909181003Sjfv * ixgbe_clear_rar - Clear Rx address register 910181003Sjfv * @hw: pointer to hardware structure 911181003Sjfv * @index: Receive address register to write 912181003Sjfv * 913181003Sjfv * Puts an ethernet address into a receive address register. 914181003Sjfv **/ 915181003Sjfvs32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 916181003Sjfv{ 917181003Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 918230775Sjfv IXGBE_NOT_IMPLEMENTED); 919181003Sjfv} 920181003Sjfv 921181003Sjfv/** 922179055Sjfv * ixgbe_set_vmdq - Associate a VMDq index with a receive address 923179055Sjfv * @hw: pointer to hardware structure 924179055Sjfv * @rar: receive address register index to associate with VMDq index 925179055Sjfv * @vmdq: VMDq set or pool index 926179055Sjfv **/ 927179055Sjfvs32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 928179055Sjfv{ 929179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 930230775Sjfv IXGBE_NOT_IMPLEMENTED); 931238149Sjfv 932179055Sjfv} 933179055Sjfv 934179055Sjfv/** 935238149Sjfv * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 936238149Sjfv * @hw: pointer to hardware structure 937238149Sjfv * @vmdq: VMDq default pool index 938238149Sjfv **/ 939238149Sjfvs32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 940238149Sjfv{ 941238149Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 942238149Sjfv (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 943238149Sjfv} 944238149Sjfv 945238149Sjfv/** 946181003Sjfv * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 947181003Sjfv * @hw: pointer to hardware structure 948181003Sjfv * @rar: receive address register index to disassociate with VMDq index 949181003Sjfv * @vmdq: VMDq set or pool index 950181003Sjfv **/ 951181003Sjfvs32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 952181003Sjfv{ 953181003Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 954230775Sjfv IXGBE_NOT_IMPLEMENTED); 955181003Sjfv} 956181003Sjfv 957181003Sjfv/** 958171384Sjfv * ixgbe_init_rx_addrs - Initializes receive address filters. 959171384Sjfv * @hw: pointer to hardware structure 960171384Sjfv * 961171384Sjfv * Places the MAC address in receive address register 0 and clears the rest 962179055Sjfv * of the receive address registers. Clears the multicast table. Assumes 963171384Sjfv * the receiver is in reset when the routine is called. 964171384Sjfv **/ 965171384Sjfvs32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 966171384Sjfv{ 967179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 968230775Sjfv IXGBE_NOT_IMPLEMENTED); 969171384Sjfv} 970171384Sjfv 971171384Sjfv/** 972171384Sjfv * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 973171384Sjfv * @hw: pointer to hardware structure 974171384Sjfv **/ 975171384Sjfvu32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 976171384Sjfv{ 977179055Sjfv return hw->mac.num_rar_entries; 978171384Sjfv} 979171384Sjfv 980171384Sjfv/** 981179055Sjfv * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 982179055Sjfv * @hw: pointer to hardware structure 983179055Sjfv * @addr_list: the list of new multicast addresses 984179055Sjfv * @addr_count: number of addresses 985179055Sjfv * @func: iterator function to walk the multicast address list 986179055Sjfv * 987179055Sjfv * The given list replaces any existing list. Clears the secondary addrs from 988179055Sjfv * receive address registers. Uses unused receive address registers for the 989179055Sjfv * first secondary addresses, and falls back to promiscuous mode as needed. 990179055Sjfv **/ 991179055Sjfvs32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 992230775Sjfv u32 addr_count, ixgbe_mc_addr_itr func) 993179055Sjfv{ 994179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 995230775Sjfv addr_list, addr_count, func), 996230775Sjfv IXGBE_NOT_IMPLEMENTED); 997179055Sjfv} 998179055Sjfv 999179055Sjfv/** 1000171384Sjfv * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1001171384Sjfv * @hw: pointer to hardware structure 1002171384Sjfv * @mc_addr_list: the list of new multicast addresses 1003171384Sjfv * @mc_addr_count: number of addresses 1004179055Sjfv * @func: iterator function to walk the multicast address list 1005171384Sjfv * 1006171384Sjfv * The given list replaces any existing list. Clears the MC addrs from receive 1007179055Sjfv * address registers and the multicast table. Uses unused receive address 1008171384Sjfv * registers for the first multicast addresses, and hashes the rest into the 1009171384Sjfv * multicast table. 1010171384Sjfv **/ 1011171384Sjfvs32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1012230775Sjfv u32 mc_addr_count, ixgbe_mc_addr_itr func, 1013230775Sjfv bool clear) 1014171384Sjfv{ 1015179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1016230775Sjfv mc_addr_list, mc_addr_count, func, clear), 1017230775Sjfv IXGBE_NOT_IMPLEMENTED); 1018171384Sjfv} 1019171384Sjfv 1020171384Sjfv/** 1021171384Sjfv * ixgbe_enable_mc - Enable multicast address in RAR 1022171384Sjfv * @hw: pointer to hardware structure 1023171384Sjfv * 1024171384Sjfv * Enables multicast address in RAR and the use of the multicast hash table. 1025171384Sjfv **/ 1026171384Sjfvs32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1027171384Sjfv{ 1028179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1029230775Sjfv IXGBE_NOT_IMPLEMENTED); 1030171384Sjfv} 1031171384Sjfv 1032171384Sjfv/** 1033171384Sjfv * ixgbe_disable_mc - Disable multicast address in RAR 1034171384Sjfv * @hw: pointer to hardware structure 1035171384Sjfv * 1036171384Sjfv * Disables multicast address in RAR and the use of the multicast hash table. 1037171384Sjfv **/ 1038171384Sjfvs32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1039171384Sjfv{ 1040179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1041230775Sjfv IXGBE_NOT_IMPLEMENTED); 1042171384Sjfv} 1043171384Sjfv 1044171384Sjfv/** 1045171384Sjfv * ixgbe_clear_vfta - Clear VLAN filter table 1046171384Sjfv * @hw: pointer to hardware structure 1047171384Sjfv * 1048171384Sjfv * Clears the VLAN filer table, and the VMDq index associated with the filter 1049171384Sjfv **/ 1050171384Sjfvs32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1051171384Sjfv{ 1052179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1053230775Sjfv IXGBE_NOT_IMPLEMENTED); 1054171384Sjfv} 1055171384Sjfv 1056171384Sjfv/** 1057171384Sjfv * ixgbe_set_vfta - Set VLAN filter table 1058171384Sjfv * @hw: pointer to hardware structure 1059171384Sjfv * @vlan: VLAN id to write to VLAN filter 1060171384Sjfv * @vind: VMDq output index that maps queue to VLAN id in VFTA 1061171384Sjfv * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1062171384Sjfv * 1063171384Sjfv * Turn on/off specified VLAN in the VLAN filter table. 1064171384Sjfv **/ 1065171384Sjfvs32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 1066171384Sjfv{ 1067179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1068230775Sjfv vlan_on), IXGBE_NOT_IMPLEMENTED); 1069171384Sjfv} 1070171384Sjfv 1071171384Sjfv/** 1072230775Sjfv * ixgbe_set_vlvf - Set VLAN Pool Filter 1073230775Sjfv * @hw: pointer to hardware structure 1074230775Sjfv * @vlan: VLAN id to write to VLAN filter 1075230775Sjfv * @vind: VMDq output index that maps queue to VLAN id in VFVFB 1076230775Sjfv * @vlan_on: boolean flag to turn on/off VLAN in VFVF 1077230775Sjfv * @vfta_changed: pointer to boolean flag which indicates whether VFTA 1078230775Sjfv * should be changed 1079230775Sjfv * 1080230775Sjfv * Turn on/off specified bit in VLVF table. 1081230775Sjfv **/ 1082230775Sjfvs32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1083230775Sjfv bool *vfta_changed) 1084230775Sjfv{ 1085230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1086230775Sjfv vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 1087230775Sjfv} 1088230775Sjfv 1089230775Sjfv/** 1090190873Sjfv * ixgbe_fc_enable - Enable flow control 1091171384Sjfv * @hw: pointer to hardware structure 1092171384Sjfv * 1093171384Sjfv * Configures the flow control settings based on SW configuration. 1094171384Sjfv **/ 1095238149Sjfvs32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1096171384Sjfv{ 1097238149Sjfv return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1098230775Sjfv IXGBE_NOT_IMPLEMENTED); 1099171384Sjfv} 1100171384Sjfv 1101172043Sjfv/** 1102283620Serj * ixgbe_setup_fc - Set up flow control 1103283620Serj * @hw: pointer to hardware structure 1104283620Serj * 1105283620Serj * Called at init time to set up flow control. 1106283620Serj **/ 1107283620Serjs32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1108283620Serj{ 1109283620Serj return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1110283620Serj IXGBE_NOT_IMPLEMENTED); 1111283620Serj} 1112283620Serj 1113283620Serj/** 1114230775Sjfv * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1115230775Sjfv * @hw: pointer to hardware structure 1116230775Sjfv * @maj: driver major number to be sent to firmware 1117230775Sjfv * @min: driver minor number to be sent to firmware 1118230775Sjfv * @build: driver build number to be sent to firmware 1119230775Sjfv * @ver: driver version number to be sent to firmware 1120230775Sjfv **/ 1121230775Sjfvs32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1122230775Sjfv u8 ver) 1123230775Sjfv{ 1124230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1125230775Sjfv build, ver), IXGBE_NOT_IMPLEMENTED); 1126230775Sjfv} 1127230775Sjfv 1128230775Sjfv 1129251964Sjfv 1130283620Serj/** 1131283620Serj * ixgbe_dmac_config - Configure DMA Coalescing registers. 1132283620Serj * @hw: pointer to hardware structure 1133283620Serj * 1134283620Serj * Configure DMA coalescing. If enabling dmac, dmac is activated. 1135283620Serj * When disabling dmac, dmac enable dmac bit is cleared. 1136283620Serj **/ 1137283620Serjs32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1138283620Serj{ 1139283620Serj return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1140283620Serj IXGBE_NOT_IMPLEMENTED); 1141283620Serj} 1142251964Sjfv 1143230775Sjfv/** 1144283620Serj * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1145283620Serj * @hw: pointer to hardware structure 1146283620Serj * 1147283620Serj * Disables dmac, updates per TC settings, and then enable dmac. 1148283620Serj **/ 1149283620Serjs32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1150283620Serj{ 1151283620Serj return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1152283620Serj IXGBE_NOT_IMPLEMENTED); 1153283620Serj} 1154283620Serj 1155283620Serj/** 1156283620Serj * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1157283620Serj * @hw: pointer to hardware structure 1158283620Serj * 1159283620Serj * Configure DMA coalescing threshold per TC and set high priority bit for 1160283620Serj * FCOE TC. The dmac enable bit must be cleared before configuring. 1161283620Serj **/ 1162283620Serjs32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1163283620Serj{ 1164283620Serj return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1165283620Serj IXGBE_NOT_IMPLEMENTED); 1166283620Serj} 1167283620Serj 1168283620Serj/** 1169283620Serj * ixgbe_setup_eee - Enable/disable EEE support 1170283620Serj * @hw: pointer to the HW structure 1171283620Serj * @enable_eee: boolean flag to enable EEE 1172283620Serj * 1173283620Serj * Enable/disable EEE based on enable_ee flag. 1174283620Serj * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1175283620Serj * are modified. 1176283620Serj * 1177283620Serj **/ 1178283620Serjs32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1179283620Serj{ 1180283620Serj return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1181283620Serj IXGBE_NOT_IMPLEMENTED); 1182283620Serj} 1183283620Serj 1184283620Serj/** 1185283620Serj * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1186283620Serj * @hw: pointer to hardware structure 1187283620Serj * @enbale: enable or disable source address pruning 1188283620Serj * @pool: Rx pool - Rx pool to toggle source address pruning 1189283620Serj **/ 1190283620Serjvoid ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1191283620Serj unsigned int pool) 1192283620Serj{ 1193283620Serj if (hw->mac.ops.set_source_address_pruning) 1194283620Serj hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1195283620Serj} 1196283620Serj 1197283620Serj/** 1198283620Serj * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1199283620Serj * @hw: pointer to hardware structure 1200283620Serj * @enable: enable or disable switch for Ethertype anti-spoofing 1201283620Serj * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1202283620Serj * 1203283620Serj **/ 1204283620Serjvoid ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1205283620Serj{ 1206283620Serj if (hw->mac.ops.set_ethertype_anti_spoofing) 1207283620Serj hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1208283620Serj} 1209283620Serj 1210283620Serj/** 1211283620Serj * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1212283620Serj * @hw: pointer to hardware structure 1213283620Serj * @reg_addr: 32 bit address of PHY register to read 1214283620Serj * @device_type: type of device you want to communicate with 1215283620Serj * @phy_data: Pointer to read data from PHY register 1216283620Serj * 1217283620Serj * Reads a value from a specified PHY register 1218283620Serj **/ 1219283620Serjs32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1220283620Serj u32 device_type, u32 *phy_data) 1221283620Serj{ 1222283620Serj return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1223283620Serj device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1224283620Serj} 1225283620Serj 1226283620Serj/** 1227283620Serj * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1228283620Serj * @hw: pointer to hardware structure 1229283620Serj * @reg_addr: 32 bit PHY register to write 1230283620Serj * @device_type: type of device you want to communicate with 1231283620Serj * @phy_data: Data to write to the PHY register 1232283620Serj * 1233283620Serj * Writes a value to specified PHY register 1234283620Serj **/ 1235283620Serjs32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1236283620Serj u32 device_type, u32 phy_data) 1237283620Serj{ 1238283620Serj return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1239283620Serj device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1240283620Serj} 1241283620Serj 1242283620Serj/** 1243283620Serj * ixgbe_disable_mdd - Disable malicious driver detection 1244283620Serj * @hw: pointer to hardware structure 1245283620Serj * 1246283620Serj **/ 1247283620Serjvoid ixgbe_disable_mdd(struct ixgbe_hw *hw) 1248283620Serj{ 1249283620Serj if (hw->mac.ops.disable_mdd) 1250283620Serj hw->mac.ops.disable_mdd(hw); 1251283620Serj} 1252283620Serj 1253283620Serj/** 1254283620Serj * ixgbe_enable_mdd - Enable malicious driver detection 1255283620Serj * @hw: pointer to hardware structure 1256283620Serj * 1257283620Serj **/ 1258283620Serjvoid ixgbe_enable_mdd(struct ixgbe_hw *hw) 1259283620Serj{ 1260283620Serj if (hw->mac.ops.enable_mdd) 1261283620Serj hw->mac.ops.enable_mdd(hw); 1262283620Serj} 1263283620Serj 1264283620Serj/** 1265283620Serj * ixgbe_mdd_event - Handle malicious driver detection event 1266283620Serj * @hw: pointer to hardware structure 1267283620Serj * @vf_bitmap: vf bitmap of malicious vfs 1268283620Serj * 1269283620Serj **/ 1270283620Serjvoid ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1271283620Serj{ 1272283620Serj if (hw->mac.ops.mdd_event) 1273283620Serj hw->mac.ops.mdd_event(hw, vf_bitmap); 1274283620Serj} 1275283620Serj 1276283620Serj/** 1277283620Serj * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1278283620Serj * detection event 1279283620Serj * @hw: pointer to hardware structure 1280283620Serj * @vf: vf index 1281283620Serj * 1282283620Serj **/ 1283283620Serjvoid ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1284283620Serj{ 1285283620Serj if (hw->mac.ops.restore_mdd_vf) 1286283620Serj hw->mac.ops.restore_mdd_vf(hw, vf); 1287283620Serj} 1288283620Serj 1289283620Serj/** 1290283620Serj * ixgbe_enter_lplu - Transition to low power states 1291283620Serj * @hw: pointer to hardware structure 1292283620Serj * 1293283620Serj * Configures Low Power Link Up on transition to low power states 1294283620Serj * (from D0 to non-D0). 1295283620Serj **/ 1296283620Serjs32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1297283620Serj{ 1298283620Serj return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1299283620Serj IXGBE_NOT_IMPLEMENTED); 1300283620Serj} 1301283620Serj 1302283620Serj/** 1303283620Serj * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1304283620Serj * @hw: pointer to hardware structure 1305283620Serj * 1306283620Serj * Handle external Base T PHY interrupt. If high temperature 1307283620Serj * failure alarm then return error, else if link status change 1308283620Serj * then setup internal/external PHY link 1309283620Serj * 1310283620Serj * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1311283620Serj * failure alarm, else return PHY access status. 1312283620Serj */ 1313283620Serjs32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1314283620Serj{ 1315283620Serj return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1316283620Serj IXGBE_NOT_IMPLEMENTED); 1317283620Serj} 1318283620Serj 1319283620Serj/** 1320172043Sjfv * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1321172043Sjfv * @hw: pointer to hardware structure 1322172043Sjfv * @reg: analog register to read 1323172043Sjfv * @val: read value 1324172043Sjfv * 1325172043Sjfv * Performs write operation to analog register specified. 1326172043Sjfv **/ 1327172043Sjfvs32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1328172043Sjfv{ 1329179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1330230775Sjfv val), IXGBE_NOT_IMPLEMENTED); 1331172043Sjfv} 1332172043Sjfv 1333172043Sjfv/** 1334172043Sjfv * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1335172043Sjfv * @hw: pointer to hardware structure 1336172043Sjfv * @reg: analog register to write 1337172043Sjfv * @val: value to write 1338172043Sjfv * 1339172043Sjfv * Performs write operation to Atlas analog register specified. 1340172043Sjfv **/ 1341172043Sjfvs32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1342172043Sjfv{ 1343179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1344230775Sjfv val), IXGBE_NOT_IMPLEMENTED); 1345172043Sjfv} 1346172043Sjfv 1347181003Sjfv/** 1348181003Sjfv * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1349181003Sjfv * @hw: pointer to hardware structure 1350181003Sjfv * 1351185352Sjfv * Initializes the Unicast Table Arrays to zero on device load. This 1352185352Sjfv * is part of the Rx init addr execution path. 1353181003Sjfv **/ 1354181003Sjfvs32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1355181003Sjfv{ 1356181003Sjfv return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1357230775Sjfv IXGBE_NOT_IMPLEMENTED); 1358181003Sjfv} 1359185352Sjfv 1360185352Sjfv/** 1361190873Sjfv * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1362190873Sjfv * @hw: pointer to hardware structure 1363190873Sjfv * @byte_offset: byte offset to read 1364283620Serj * @dev_addr: I2C bus address to read from 1365190873Sjfv * @data: value read 1366190873Sjfv * 1367190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1368190873Sjfv **/ 1369190873Sjfvs32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1370230775Sjfv u8 *data) 1371190873Sjfv{ 1372190873Sjfv return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1373230775Sjfv dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1374190873Sjfv} 1375190873Sjfv 1376190873Sjfv/** 1377283620Serj * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1378283620Serj * @hw: pointer to hardware structure 1379283620Serj * @byte_offset: byte offset to read 1380283620Serj * @dev_addr: I2C bus address to read from 1381283620Serj * @data: value read 1382283620Serj * 1383283620Serj * Performs byte read operation to SFP module's EEPROM over I2C interface. 1384283620Serj **/ 1385283620Serjs32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1386283620Serj u8 dev_addr, u8 *data) 1387283620Serj{ 1388283620Serj return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1389283620Serj (hw, byte_offset, dev_addr, data), 1390283620Serj IXGBE_NOT_IMPLEMENTED); 1391283620Serj} 1392283620Serj 1393283620Serj/** 1394283620Serj * ixgbe_read_i2c_combined - Perform I2C read combined operation 1395283620Serj * @hw: pointer to the hardware structure 1396283620Serj * @addr: I2C bus address to read from 1397283620Serj * @reg: I2C device register to read from 1398283620Serj * @val: pointer to location to receive read value 1399283620Serj * 1400283620Serj * Returns an error code on error. 1401283620Serj */ 1402283620Serjs32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1403283620Serj{ 1404283620Serj return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr, 1405283620Serj reg, val), IXGBE_NOT_IMPLEMENTED); 1406283620Serj} 1407283620Serj 1408283620Serj/** 1409283620Serj * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation 1410283620Serj * @hw: pointer to the hardware structure 1411283620Serj * @addr: I2C bus address to read from 1412283620Serj * @reg: I2C device register to read from 1413283620Serj * @val: pointer to location to receive read value 1414283620Serj * 1415283620Serj * Returns an error code on error. 1416283620Serj **/ 1417283620Serjs32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1418283620Serj u16 *val) 1419283620Serj{ 1420283620Serj return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked, 1421283620Serj (hw, addr, reg, val), 1422283620Serj IXGBE_NOT_IMPLEMENTED); 1423283620Serj} 1424283620Serj 1425283620Serj/** 1426190873Sjfv * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1427190873Sjfv * @hw: pointer to hardware structure 1428190873Sjfv * @byte_offset: byte offset to write 1429283620Serj * @dev_addr: I2C bus address to write to 1430190873Sjfv * @data: value to write 1431190873Sjfv * 1432190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface 1433190873Sjfv * at a specified device address. 1434190873Sjfv **/ 1435190873Sjfvs32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1436230775Sjfv u8 data) 1437190873Sjfv{ 1438190873Sjfv return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1439230775Sjfv dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1440190873Sjfv} 1441190873Sjfv 1442190873Sjfv/** 1443283620Serj * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1444283620Serj * @hw: pointer to hardware structure 1445283620Serj * @byte_offset: byte offset to write 1446283620Serj * @dev_addr: I2C bus address to write to 1447283620Serj * @data: value to write 1448283620Serj * 1449283620Serj * Performs byte write operation to SFP module's EEPROM over I2C interface 1450283620Serj * at a specified device address. 1451283620Serj **/ 1452283620Serjs32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1453283620Serj u8 dev_addr, u8 data) 1454283620Serj{ 1455283620Serj return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1456283620Serj (hw, byte_offset, dev_addr, data), 1457283620Serj IXGBE_NOT_IMPLEMENTED); 1458283620Serj} 1459283620Serj 1460283620Serj/** 1461283620Serj * ixgbe_write_i2c_combined - Perform I2C write combined operation 1462283620Serj * @hw: pointer to the hardware structure 1463283620Serj * @addr: I2C bus address to write to 1464283620Serj * @reg: I2C device register to write to 1465283620Serj * @val: value to write 1466283620Serj * 1467283620Serj * Returns an error code on error. 1468283620Serj */ 1469283620Serjs32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1470283620Serj{ 1471283620Serj return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, 1472283620Serj reg, val), IXGBE_NOT_IMPLEMENTED); 1473283620Serj} 1474283620Serj 1475283620Serj/** 1476283620Serj * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation 1477283620Serj * @hw: pointer to the hardware structure 1478283620Serj * @addr: I2C bus address to write to 1479283620Serj * @reg: I2C device register to write to 1480283620Serj * @val: value to write 1481283620Serj * 1482283620Serj * Returns an error code on error. 1483283620Serj **/ 1484283620Serjs32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1485283620Serj u16 val) 1486283620Serj{ 1487283620Serj return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked, 1488283620Serj (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1489283620Serj} 1490283620Serj 1491283620Serj/** 1492190873Sjfv * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1493190873Sjfv * @hw: pointer to hardware structure 1494190873Sjfv * @byte_offset: EEPROM byte offset to write 1495190873Sjfv * @eeprom_data: value to write 1496190873Sjfv * 1497190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface. 1498190873Sjfv **/ 1499190873Sjfvs32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1500230775Sjfv u8 byte_offset, u8 eeprom_data) 1501190873Sjfv{ 1502190873Sjfv return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1503230775Sjfv (hw, byte_offset, eeprom_data), 1504230775Sjfv IXGBE_NOT_IMPLEMENTED); 1505190873Sjfv} 1506190873Sjfv 1507190873Sjfv/** 1508185352Sjfv * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1509185352Sjfv * @hw: pointer to hardware structure 1510185352Sjfv * @byte_offset: EEPROM byte offset to read 1511185352Sjfv * @eeprom_data: value read 1512185352Sjfv * 1513185352Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1514185352Sjfv **/ 1515185352Sjfvs32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1516185352Sjfv{ 1517185352Sjfv return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1518230775Sjfv (hw, byte_offset, eeprom_data), 1519230775Sjfv IXGBE_NOT_IMPLEMENTED); 1520185352Sjfv} 1521185352Sjfv 1522185352Sjfv/** 1523185352Sjfv * ixgbe_get_supported_physical_layer - Returns physical layer type 1524185352Sjfv * @hw: pointer to hardware structure 1525185352Sjfv * 1526185352Sjfv * Determines physical layer capabilities of the current configuration. 1527185352Sjfv **/ 1528185352Sjfvu32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1529185352Sjfv{ 1530185352Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1531230775Sjfv (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1532185352Sjfv} 1533190873Sjfv 1534190873Sjfv/** 1535238149Sjfv * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1536190873Sjfv * @hw: pointer to hardware structure 1537190873Sjfv * @regval: bitfield to write to the Rx DMA register 1538190873Sjfv * 1539190873Sjfv * Enables the Rx DMA unit of the device. 1540190873Sjfv **/ 1541190873Sjfvs32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1542190873Sjfv{ 1543190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1544230775Sjfv (hw, regval), IXGBE_NOT_IMPLEMENTED); 1545190873Sjfv} 1546194875Sjfv 1547194875Sjfv/** 1548230775Sjfv * ixgbe_disable_sec_rx_path - Stops the receive data path 1549230775Sjfv * @hw: pointer to hardware structure 1550230775Sjfv * 1551230775Sjfv * Stops the receive data path. 1552230775Sjfv **/ 1553230775Sjfvs32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1554230775Sjfv{ 1555230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1556230775Sjfv (hw), IXGBE_NOT_IMPLEMENTED); 1557230775Sjfv} 1558230775Sjfv 1559230775Sjfv/** 1560230775Sjfv * ixgbe_enable_sec_rx_path - Enables the receive data path 1561230775Sjfv * @hw: pointer to hardware structure 1562230775Sjfv * 1563230775Sjfv * Enables the receive data path. 1564230775Sjfv **/ 1565230775Sjfvs32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1566230775Sjfv{ 1567230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1568230775Sjfv (hw), IXGBE_NOT_IMPLEMENTED); 1569230775Sjfv} 1570230775Sjfv 1571230775Sjfv/** 1572194875Sjfv * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1573194875Sjfv * @hw: pointer to hardware structure 1574194875Sjfv * @mask: Mask to specify which semaphore to acquire 1575194875Sjfv * 1576194875Sjfv * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1577194875Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 1578194875Sjfv **/ 1579283620Serjs32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1580194875Sjfv{ 1581194875Sjfv return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1582230775Sjfv (hw, mask), IXGBE_NOT_IMPLEMENTED); 1583194875Sjfv} 1584194875Sjfv 1585194875Sjfv/** 1586194875Sjfv * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1587194875Sjfv * @hw: pointer to hardware structure 1588194875Sjfv * @mask: Mask to specify which semaphore to release 1589194875Sjfv * 1590194875Sjfv * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1591194875Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 1592194875Sjfv **/ 1593283620Serjvoid ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1594194875Sjfv{ 1595194875Sjfv if (hw->mac.ops.release_swfw_sync) 1596194875Sjfv hw->mac.ops.release_swfw_sync(hw, mask); 1597194875Sjfv} 1598194875Sjfv 1599283620Serj 1600283620Serjvoid ixgbe_disable_rx(struct ixgbe_hw *hw) 1601283620Serj{ 1602283620Serj if (hw->mac.ops.disable_rx) 1603283620Serj hw->mac.ops.disable_rx(hw); 1604283620Serj} 1605283620Serj 1606283620Serjvoid ixgbe_enable_rx(struct ixgbe_hw *hw) 1607283620Serj{ 1608283620Serj if (hw->mac.ops.enable_rx) 1609283620Serj hw->mac.ops.enable_rx(hw); 1610283620Serj} 1611283620Serj 1612283620Serj/** 1613283620Serj * ixgbe_set_rate_select_speed - Set module link speed 1614283620Serj * @hw: pointer to hardware structure 1615283620Serj * @speed: link speed to set 1616283620Serj * 1617283620Serj * Set module link speed via the rate select. 1618283620Serj */ 1619283620Serjvoid ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1620283620Serj{ 1621283620Serj if (hw->mac.ops.set_rate_select_speed) 1622283620Serj hw->mac.ops.set_rate_select_speed(hw, speed); 1623283620Serj} 1624