1190877Sjfv/****************************************************************************** 2190877Sjfv 3283620Serj Copyright (c) 2001-2015, Intel Corporation 4190877Sjfv All rights reserved. 5190877Sjfv 6190877Sjfv Redistribution and use in source and binary forms, with or without 7190877Sjfv modification, are permitted provided that the following conditions are met: 8190877Sjfv 9190877Sjfv 1. Redistributions of source code must retain the above copyright notice, 10190877Sjfv this list of conditions and the following disclaimer. 11190877Sjfv 12190877Sjfv 2. Redistributions in binary form must reproduce the above copyright 13190877Sjfv notice, this list of conditions and the following disclaimer in the 14190877Sjfv documentation and/or other materials provided with the distribution. 15190877Sjfv 16190877Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17190877Sjfv contributors may be used to endorse or promote products derived from 18190877Sjfv this software without specific prior written permission. 19190877Sjfv 20190877Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21190877Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22190877Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23190877Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24190877Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25190877Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26190877Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27190877Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28190877Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29190877Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30190877Sjfv POSSIBILITY OF SUCH DAMAGE. 31190877Sjfv 32190877Sjfv******************************************************************************/ 33190877Sjfv/*$FreeBSD: releng/10.3/sys/dev/ixgbe/ixgbe_82599.c 295524 2016-02-11 16:16:10Z sbruno $*/ 34190877Sjfv 35190877Sjfv#include "ixgbe_type.h" 36230775Sjfv#include "ixgbe_82599.h" 37190877Sjfv#include "ixgbe_api.h" 38190877Sjfv#include "ixgbe_common.h" 39190877Sjfv#include "ixgbe_phy.h" 40190877Sjfv 41283620Serj#define IXGBE_82599_MAX_TX_QUEUES 128 42283620Serj#define IXGBE_82599_MAX_RX_QUEUES 128 43283620Serj#define IXGBE_82599_RAR_ENTRIES 128 44283620Serj#define IXGBE_82599_MC_TBL_SIZE 128 45283620Serj#define IXGBE_82599_VFT_TBL_SIZE 128 46283620Serj#define IXGBE_82599_RX_PB_SIZE 512 47283620Serj 48200239Sjfvstatic s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 49230775Sjfv ixgbe_link_speed speed, 50230775Sjfv bool autoneg_wait_to_complete); 51194875Sjfvstatic s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 52230775Sjfvstatic s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 53230775Sjfv u16 offset, u16 *data); 54230775Sjfvstatic s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 55230775Sjfv u16 words, u16 *data); 56283620Serjstatic s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 57283620Serj u8 dev_addr, u8 *data); 58283620Serjstatic s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 59283620Serj u8 dev_addr, u8 data); 60190877Sjfv 61190877Sjfvvoid ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 62190877Sjfv{ 63190877Sjfv struct ixgbe_mac_info *mac = &hw->mac; 64190877Sjfv 65190877Sjfv DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 66190877Sjfv 67247822Sjfv /* 68247822Sjfv * enable the laser control functions for SFP+ fiber 69247822Sjfv * and MNG not enabled 70247822Sjfv */ 71247822Sjfv if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 72283620Serj !ixgbe_mng_enabled(hw)) { 73215911Sjfv mac->ops.disable_tx_laser = 74283620Serj ixgbe_disable_tx_laser_multispeed_fiber; 75215911Sjfv mac->ops.enable_tx_laser = 76283620Serj ixgbe_enable_tx_laser_multispeed_fiber; 77283620Serj mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; 78215911Sjfv 79215911Sjfv } else { 80215911Sjfv mac->ops.disable_tx_laser = NULL; 81215911Sjfv mac->ops.enable_tx_laser = NULL; 82215911Sjfv mac->ops.flap_tx_laser = NULL; 83215911Sjfv } 84215911Sjfv 85190877Sjfv if (hw->phy.multispeed_fiber) { 86190877Sjfv /* Set up dual speed SFP+ support */ 87283620Serj mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 88283620Serj mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 89283620Serj mac->ops.set_rate_select_speed = 90283620Serj ixgbe_set_hard_rate_select_speed; 91283620Serj if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) 92283620Serj mac->ops.set_rate_select_speed = 93283620Serj ixgbe_set_soft_rate_select_speed; 94190877Sjfv } else { 95200239Sjfv if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 96200239Sjfv (hw->phy.smart_speed == ixgbe_smart_speed_auto || 97217593Sjfv hw->phy.smart_speed == ixgbe_smart_speed_on) && 98217593Sjfv !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 99283620Serj mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; 100215911Sjfv } else { 101283620Serj mac->ops.setup_link = ixgbe_setup_mac_link_82599; 102215911Sjfv } 103190877Sjfv } 104190877Sjfv} 105190877Sjfv 106190877Sjfv/** 107190877Sjfv * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 108190877Sjfv * @hw: pointer to hardware structure 109190877Sjfv * 110190877Sjfv * Initialize any function pointers that were not able to be 111190877Sjfv * set during init_shared_code because the PHY/SFP type was 112190877Sjfv * not known. Perform the SFP init if necessary. 113190877Sjfv * 114190877Sjfv **/ 115190877Sjfvs32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 116190877Sjfv{ 117190877Sjfv struct ixgbe_mac_info *mac = &hw->mac; 118190877Sjfv struct ixgbe_phy_info *phy = &hw->phy; 119190877Sjfv s32 ret_val = IXGBE_SUCCESS; 120283620Serj u32 esdp; 121190877Sjfv 122190877Sjfv DEBUGFUNC("ixgbe_init_phy_ops_82599"); 123190877Sjfv 124283620Serj if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 125283620Serj /* Store flag indicating I2C bus access control unit. */ 126283620Serj hw->phy.qsfp_shared_i2c_bus = TRUE; 127283620Serj 128283620Serj /* Initialize access to QSFP+ I2C bus */ 129283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 130283620Serj esdp |= IXGBE_ESDP_SDP0_DIR; 131283620Serj esdp &= ~IXGBE_ESDP_SDP1_DIR; 132283620Serj esdp &= ~IXGBE_ESDP_SDP0; 133283620Serj esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 134283620Serj esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 135283620Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 136283620Serj IXGBE_WRITE_FLUSH(hw); 137283620Serj 138283620Serj phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; 139283620Serj phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; 140283620Serj } 141190877Sjfv /* Identify the PHY or SFP module */ 142190877Sjfv ret_val = phy->ops.identify(hw); 143190877Sjfv if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 144190877Sjfv goto init_phy_ops_out; 145190877Sjfv 146190877Sjfv /* Setup function pointers based on detected SFP module and speeds */ 147190877Sjfv ixgbe_init_mac_link_ops_82599(hw); 148190877Sjfv if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 149190877Sjfv hw->phy.ops.reset = NULL; 150190877Sjfv 151190877Sjfv /* If copper media, overwrite with copper function pointers */ 152190877Sjfv if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 153283620Serj mac->ops.setup_link = ixgbe_setup_copper_link_82599; 154190877Sjfv mac->ops.get_link_capabilities = 155283620Serj ixgbe_get_copper_link_capabilities_generic; 156190877Sjfv } 157190877Sjfv 158283620Serj /* Set necessary function pointers based on PHY type */ 159190877Sjfv switch (hw->phy.type) { 160190877Sjfv case ixgbe_phy_tn: 161283620Serj phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 162283620Serj phy->ops.check_link = ixgbe_check_phy_link_tnx; 163190877Sjfv phy->ops.get_firmware_version = 164283620Serj ixgbe_get_phy_firmware_version_tnx; 165190877Sjfv break; 166190877Sjfv default: 167190877Sjfv break; 168190877Sjfv } 169190877Sjfvinit_phy_ops_out: 170190877Sjfv return ret_val; 171190877Sjfv} 172190877Sjfv 173190877Sjfvs32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 174190877Sjfv{ 175190877Sjfv s32 ret_val = IXGBE_SUCCESS; 176190877Sjfv u16 list_offset, data_offset, data_value; 177190877Sjfv 178190877Sjfv DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 179190877Sjfv 180190877Sjfv if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 181190877Sjfv ixgbe_init_mac_link_ops_82599(hw); 182190877Sjfv 183190877Sjfv hw->phy.ops.reset = NULL; 184190877Sjfv 185190877Sjfv ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 186230775Sjfv &data_offset); 187190877Sjfv if (ret_val != IXGBE_SUCCESS) 188190877Sjfv goto setup_sfp_out; 189190877Sjfv 190194875Sjfv /* PHY config will finish before releasing the semaphore */ 191230775Sjfv ret_val = hw->mac.ops.acquire_swfw_sync(hw, 192230775Sjfv IXGBE_GSSR_MAC_CSR_SM); 193194875Sjfv if (ret_val != IXGBE_SUCCESS) { 194194875Sjfv ret_val = IXGBE_ERR_SWFW_SYNC; 195194875Sjfv goto setup_sfp_out; 196194875Sjfv } 197194875Sjfv 198251964Sjfv if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 199251964Sjfv goto setup_sfp_err; 200190877Sjfv while (data_value != 0xffff) { 201190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 202190877Sjfv IXGBE_WRITE_FLUSH(hw); 203251964Sjfv if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 204251964Sjfv goto setup_sfp_err; 205190877Sjfv } 206194875Sjfv 207194875Sjfv /* Release the semaphore */ 208230775Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 209283620Serj /* Delay obtaining semaphore again to allow FW access 210283620Serj * prot_autoc_write uses the semaphore too. 211283620Serj */ 212194875Sjfv msec_delay(hw->eeprom.semaphore_delay); 213215911Sjfv 214247822Sjfv /* Restart DSP and set SFI mode */ 215283620Serj ret_val = hw->mac.ops.prot_autoc_write(hw, 216283620Serj hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 217283620Serj FALSE); 218247822Sjfv 219247822Sjfv if (ret_val) { 220215911Sjfv DEBUGOUT("sfp module setup not complete\n"); 221215911Sjfv ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 222215911Sjfv goto setup_sfp_out; 223215911Sjfv } 224215911Sjfv 225190877Sjfv } 226190877Sjfv 227190877Sjfvsetup_sfp_out: 228190877Sjfv return ret_val; 229251964Sjfv 230251964Sjfvsetup_sfp_err: 231251964Sjfv /* Release the semaphore */ 232251964Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 233251964Sjfv /* Delay obtaining semaphore again to allow FW access */ 234251964Sjfv msec_delay(hw->eeprom.semaphore_delay); 235251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 236251964Sjfv "eeprom read at offset %d failed", data_offset); 237251964Sjfv return IXGBE_ERR_PHY; 238190877Sjfv} 239190877Sjfv 240190877Sjfv/** 241283620Serj * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 242283620Serj * @hw: pointer to hardware structure 243283620Serj * @locked: Return the if we locked for this read. 244283620Serj * @reg_val: Value we read from AUTOC 245283620Serj * 246283620Serj * For this part (82599) we need to wrap read-modify-writes with a possible 247283620Serj * FW/SW lock. It is assumed this lock will be freed with the next 248283620Serj * prot_autoc_write_82599(). 249283620Serj */ 250283620Serjs32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 251283620Serj{ 252283620Serj s32 ret_val; 253283620Serj 254283620Serj *locked = FALSE; 255283620Serj /* If LESM is on then we need to hold the SW/FW semaphore. */ 256283620Serj if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 257283620Serj ret_val = hw->mac.ops.acquire_swfw_sync(hw, 258283620Serj IXGBE_GSSR_MAC_CSR_SM); 259283620Serj if (ret_val != IXGBE_SUCCESS) 260283620Serj return IXGBE_ERR_SWFW_SYNC; 261283620Serj 262283620Serj *locked = TRUE; 263283620Serj } 264283620Serj 265283620Serj *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 266283620Serj return IXGBE_SUCCESS; 267283620Serj} 268283620Serj 269283620Serj/** 270283620Serj * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 271283620Serj * @hw: pointer to hardware structure 272283620Serj * @reg_val: value to write to AUTOC 273283620Serj * @locked: bool to indicate whether the SW/FW lock was already taken by 274283620Serj * previous proc_autoc_read_82599. 275283620Serj * 276283620Serj * This part (82599) may need to hold the SW/FW lock around all writes to 277283620Serj * AUTOC. Likewise after a write we need to do a pipeline reset. 278283620Serj */ 279283620Serjs32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 280283620Serj{ 281283620Serj s32 ret_val = IXGBE_SUCCESS; 282283620Serj 283283620Serj /* Blocked by MNG FW so bail */ 284283620Serj if (ixgbe_check_reset_blocked(hw)) 285283620Serj goto out; 286283620Serj 287283620Serj /* We only need to get the lock if: 288283620Serj * - We didn't do it already (in the read part of a read-modify-write) 289283620Serj * - LESM is enabled. 290283620Serj */ 291283620Serj if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 292283620Serj ret_val = hw->mac.ops.acquire_swfw_sync(hw, 293283620Serj IXGBE_GSSR_MAC_CSR_SM); 294283620Serj if (ret_val != IXGBE_SUCCESS) 295283620Serj return IXGBE_ERR_SWFW_SYNC; 296283620Serj 297283620Serj locked = TRUE; 298283620Serj } 299283620Serj 300283620Serj IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 301283620Serj ret_val = ixgbe_reset_pipeline_82599(hw); 302283620Serj 303283620Serjout: 304283620Serj /* Free the SW/FW semaphore as we either grabbed it here or 305283620Serj * already had it when this function was called. 306283620Serj */ 307283620Serj if (locked) 308283620Serj hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 309283620Serj 310283620Serj return ret_val; 311283620Serj} 312283620Serj 313283620Serj/** 314190877Sjfv * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 315190877Sjfv * @hw: pointer to hardware structure 316190877Sjfv * 317190877Sjfv * Initialize the function pointers and assign the MAC type for 82599. 318190877Sjfv * Does not touch the hardware. 319190877Sjfv **/ 320190877Sjfv 321190877Sjfvs32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 322190877Sjfv{ 323190877Sjfv struct ixgbe_mac_info *mac = &hw->mac; 324190877Sjfv struct ixgbe_phy_info *phy = &hw->phy; 325230775Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 326190877Sjfv s32 ret_val; 327190877Sjfv 328200239Sjfv DEBUGFUNC("ixgbe_init_ops_82599"); 329200239Sjfv 330247822Sjfv ixgbe_init_phy_ops_generic(hw); 331190877Sjfv ret_val = ixgbe_init_ops_generic(hw); 332190877Sjfv 333190877Sjfv /* PHY */ 334283620Serj phy->ops.identify = ixgbe_identify_phy_82599; 335283620Serj phy->ops.init = ixgbe_init_phy_ops_82599; 336190877Sjfv 337190877Sjfv /* MAC */ 338283620Serj mac->ops.reset_hw = ixgbe_reset_hw_82599; 339283620Serj mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 340283620Serj mac->ops.get_media_type = ixgbe_get_media_type_82599; 341190877Sjfv mac->ops.get_supported_physical_layer = 342283620Serj ixgbe_get_supported_physical_layer_82599; 343283620Serj mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 344283620Serj mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 345283620Serj mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; 346283620Serj mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; 347283620Serj mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; 348283620Serj mac->ops.start_hw = ixgbe_start_hw_82599; 349283620Serj mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 350283620Serj mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 351283620Serj mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 352283620Serj mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 353283620Serj mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 354283620Serj mac->ops.prot_autoc_read = prot_autoc_read_82599; 355283620Serj mac->ops.prot_autoc_write = prot_autoc_write_82599; 356190877Sjfv 357190877Sjfv /* RAR, Multicast, VLAN */ 358283620Serj mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 359283620Serj mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 360283620Serj mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 361283620Serj mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 362190877Sjfv mac->rar_highwater = 1; 363283620Serj mac->ops.set_vfta = ixgbe_set_vfta_generic; 364283620Serj mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 365283620Serj mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 366283620Serj mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 367283620Serj mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; 368283620Serj mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 369283620Serj mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 370190877Sjfv 371190877Sjfv /* Link */ 372283620Serj mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; 373283620Serj mac->ops.check_link = ixgbe_check_mac_link_generic; 374283620Serj mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 375190877Sjfv ixgbe_init_mac_link_ops_82599(hw); 376190877Sjfv 377283620Serj mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 378283620Serj mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 379283620Serj mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 380283620Serj mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 381283620Serj mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 382283620Serj mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 383230775Sjfv mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 384190877Sjfv 385295524Ssbruno mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 386295524Ssbruno & IXGBE_FWSM_MODE_MASK); 387230775Sjfv 388215911Sjfv hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 389194875Sjfv 390230775Sjfv /* EEPROM */ 391283620Serj eeprom->ops.read = ixgbe_read_eeprom_82599; 392283620Serj eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; 393230775Sjfv 394230775Sjfv /* Manageability interface */ 395283620Serj mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 396230775Sjfv 397230775Sjfv 398283620Serj mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 399251964Sjfv 400190877Sjfv return ret_val; 401190877Sjfv} 402190877Sjfv 403190877Sjfv/** 404190877Sjfv * ixgbe_get_link_capabilities_82599 - Determines link capabilities 405190877Sjfv * @hw: pointer to hardware structure 406190877Sjfv * @speed: pointer to link speed 407247822Sjfv * @autoneg: TRUE when autoneg or autotry is enabled 408190877Sjfv * 409190877Sjfv * Determines the link capabilities by reading the AUTOC register. 410190877Sjfv **/ 411190877Sjfvs32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 412230775Sjfv ixgbe_link_speed *speed, 413247822Sjfv bool *autoneg) 414190877Sjfv{ 415190877Sjfv s32 status = IXGBE_SUCCESS; 416190877Sjfv u32 autoc = 0; 417190877Sjfv 418200239Sjfv DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 419200239Sjfv 420205720Sjfv 421215911Sjfv /* Check if 1G SFP module. */ 422215911Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 423238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 424283620Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 425283620Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 426238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 427238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 428215911Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 429247822Sjfv *autoneg = TRUE; 430215911Sjfv goto out; 431215911Sjfv } 432205720Sjfv 433190877Sjfv /* 434190877Sjfv * Determine link capabilities based on the stored value of AUTOC, 435190877Sjfv * which represents EEPROM defaults. If AUTOC value has not 436190877Sjfv * been stored, use the current register values. 437190877Sjfv */ 438190877Sjfv if (hw->mac.orig_link_settings_stored) 439190877Sjfv autoc = hw->mac.orig_autoc; 440190877Sjfv else 441190877Sjfv autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 442190877Sjfv 443190877Sjfv switch (autoc & IXGBE_AUTOC_LMS_MASK) { 444190877Sjfv case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 445190877Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 446247822Sjfv *autoneg = FALSE; 447190877Sjfv break; 448190877Sjfv 449190877Sjfv case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 450190877Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 451247822Sjfv *autoneg = FALSE; 452190877Sjfv break; 453190877Sjfv 454190877Sjfv case IXGBE_AUTOC_LMS_1G_AN: 455190877Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 456247822Sjfv *autoneg = TRUE; 457190877Sjfv break; 458190877Sjfv 459190877Sjfv case IXGBE_AUTOC_LMS_10G_SERIAL: 460190877Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 461247822Sjfv *autoneg = FALSE; 462190877Sjfv break; 463190877Sjfv 464190877Sjfv case IXGBE_AUTOC_LMS_KX4_KX_KR: 465190877Sjfv case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 466190877Sjfv *speed = IXGBE_LINK_SPEED_UNKNOWN; 467190877Sjfv if (autoc & IXGBE_AUTOC_KR_SUPP) 468190877Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 469190877Sjfv if (autoc & IXGBE_AUTOC_KX4_SUPP) 470190877Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 471190877Sjfv if (autoc & IXGBE_AUTOC_KX_SUPP) 472190877Sjfv *speed |= IXGBE_LINK_SPEED_1GB_FULL; 473247822Sjfv *autoneg = TRUE; 474190877Sjfv break; 475190877Sjfv 476190877Sjfv case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 477190877Sjfv *speed = IXGBE_LINK_SPEED_100_FULL; 478190877Sjfv if (autoc & IXGBE_AUTOC_KR_SUPP) 479190877Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 480190877Sjfv if (autoc & IXGBE_AUTOC_KX4_SUPP) 481190877Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 482190877Sjfv if (autoc & IXGBE_AUTOC_KX_SUPP) 483190877Sjfv *speed |= IXGBE_LINK_SPEED_1GB_FULL; 484247822Sjfv *autoneg = TRUE; 485190877Sjfv break; 486190877Sjfv 487190877Sjfv case IXGBE_AUTOC_LMS_SGMII_1G_100M: 488190877Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 489247822Sjfv *autoneg = FALSE; 490190877Sjfv break; 491190877Sjfv 492190877Sjfv default: 493190877Sjfv status = IXGBE_ERR_LINK_SETUP; 494190877Sjfv goto out; 495190877Sjfv break; 496190877Sjfv } 497190877Sjfv 498190877Sjfv if (hw->phy.multispeed_fiber) { 499190877Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL | 500230775Sjfv IXGBE_LINK_SPEED_1GB_FULL; 501283620Serj 502283620Serj /* QSFP must not enable full auto-negotiation 503283620Serj * Limited autoneg is enabled at 1G 504283620Serj */ 505283620Serj if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 506283620Serj *autoneg = FALSE; 507283620Serj else 508283620Serj *autoneg = TRUE; 509190877Sjfv } 510190877Sjfv 511190877Sjfvout: 512190877Sjfv return status; 513190877Sjfv} 514190877Sjfv 515190877Sjfv/** 516190877Sjfv * ixgbe_get_media_type_82599 - Get media type 517190877Sjfv * @hw: pointer to hardware structure 518190877Sjfv * 519190877Sjfv * Returns the media type (fiber, copper, backplane) 520190877Sjfv **/ 521190877Sjfvenum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 522190877Sjfv{ 523190877Sjfv enum ixgbe_media_type media_type; 524190877Sjfv 525200239Sjfv DEBUGFUNC("ixgbe_get_media_type_82599"); 526200239Sjfv 527190877Sjfv /* Detect if there is a copper PHY attached. */ 528215911Sjfv switch (hw->phy.type) { 529215911Sjfv case ixgbe_phy_cu_unknown: 530215911Sjfv case ixgbe_phy_tn: 531190877Sjfv media_type = ixgbe_media_type_copper; 532190877Sjfv goto out; 533215911Sjfv default: 534215911Sjfv break; 535190877Sjfv } 536190877Sjfv 537190877Sjfv switch (hw->device_id) { 538190877Sjfv case IXGBE_DEV_ID_82599_KX4: 539200239Sjfv case IXGBE_DEV_ID_82599_KX4_MEZZ: 540200239Sjfv case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 541230775Sjfv case IXGBE_DEV_ID_82599_KR: 542215911Sjfv case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 543194875Sjfv case IXGBE_DEV_ID_82599_XAUI_LOM: 544190877Sjfv /* Default device ID is mezzanine card KX/KX4 */ 545190877Sjfv media_type = ixgbe_media_type_backplane; 546190877Sjfv break; 547190877Sjfv case IXGBE_DEV_ID_82599_SFP: 548215911Sjfv case IXGBE_DEV_ID_82599_SFP_FCOE: 549230775Sjfv case IXGBE_DEV_ID_82599_SFP_EM: 550238149Sjfv case IXGBE_DEV_ID_82599_SFP_SF2: 551247822Sjfv case IXGBE_DEV_ID_82599_SFP_SF_QP: 552230775Sjfv case IXGBE_DEV_ID_82599EN_SFP: 553190877Sjfv media_type = ixgbe_media_type_fiber; 554190877Sjfv break; 555190877Sjfv case IXGBE_DEV_ID_82599_CX4: 556200239Sjfv media_type = ixgbe_media_type_cx4; 557190877Sjfv break; 558215911Sjfv case IXGBE_DEV_ID_82599_T3_LOM: 559215911Sjfv media_type = ixgbe_media_type_copper; 560215911Sjfv break; 561283620Serj case IXGBE_DEV_ID_82599_QSFP_SF_QP: 562283620Serj media_type = ixgbe_media_type_fiber_qsfp; 563283620Serj break; 564247822Sjfv case IXGBE_DEV_ID_82599_BYPASS: 565247822Sjfv media_type = ixgbe_media_type_fiber_fixed; 566247822Sjfv hw->phy.multispeed_fiber = TRUE; 567247822Sjfv break; 568190877Sjfv default: 569190877Sjfv media_type = ixgbe_media_type_unknown; 570190877Sjfv break; 571190877Sjfv } 572190877Sjfvout: 573190877Sjfv return media_type; 574190877Sjfv} 575190877Sjfv 576190877Sjfv/** 577251964Sjfv * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 578251964Sjfv * @hw: pointer to hardware structure 579251964Sjfv * 580251964Sjfv * Disables link during D3 power down sequence. 581251964Sjfv * 582251964Sjfv **/ 583251964Sjfvvoid ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 584251964Sjfv{ 585251964Sjfv u32 autoc2_reg; 586251964Sjfv u16 ee_ctrl_2 = 0; 587251964Sjfv 588251964Sjfv DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 589251964Sjfv ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 590251964Sjfv 591283620Serj if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 592283620Serj ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 593251964Sjfv autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 594251964Sjfv autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 595251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 596251964Sjfv } 597251964Sjfv} 598251964Sjfv 599251964Sjfv/** 600200239Sjfv * ixgbe_start_mac_link_82599 - Setup MAC link settings 601190877Sjfv * @hw: pointer to hardware structure 602215911Sjfv * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 603190877Sjfv * 604190877Sjfv * Configures link settings based on values in the ixgbe_hw struct. 605190877Sjfv * Restarts the link. Performs autonegotiation if needed. 606190877Sjfv **/ 607200239Sjfvs32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 608230775Sjfv bool autoneg_wait_to_complete) 609190877Sjfv{ 610190877Sjfv u32 autoc_reg; 611190877Sjfv u32 links_reg; 612190877Sjfv u32 i; 613190877Sjfv s32 status = IXGBE_SUCCESS; 614247822Sjfv bool got_lock = FALSE; 615190877Sjfv 616200239Sjfv DEBUGFUNC("ixgbe_start_mac_link_82599"); 617194875Sjfv 618200239Sjfv 619247822Sjfv /* reset_pipeline requires us to hold this lock as it writes to 620247822Sjfv * AUTOC. 621247822Sjfv */ 622247822Sjfv if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 623247822Sjfv status = hw->mac.ops.acquire_swfw_sync(hw, 624247822Sjfv IXGBE_GSSR_MAC_CSR_SM); 625247822Sjfv if (status != IXGBE_SUCCESS) 626247822Sjfv goto out; 627247822Sjfv 628247822Sjfv got_lock = TRUE; 629247822Sjfv } 630247822Sjfv 631190877Sjfv /* Restart link */ 632247822Sjfv ixgbe_reset_pipeline_82599(hw); 633190877Sjfv 634247822Sjfv if (got_lock) 635247822Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 636247822Sjfv 637190877Sjfv /* Only poll for autoneg to complete if specified to do so */ 638200239Sjfv if (autoneg_wait_to_complete) { 639247822Sjfv autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 640190877Sjfv if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 641190877Sjfv IXGBE_AUTOC_LMS_KX4_KX_KR || 642190877Sjfv (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 643215911Sjfv IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 644215911Sjfv (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 645190877Sjfv IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 646190877Sjfv links_reg = 0; /* Just in case Autoneg time = 0 */ 647190877Sjfv for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 648190877Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 649190877Sjfv if (links_reg & IXGBE_LINKS_KX_AN_COMP) 650190877Sjfv break; 651190877Sjfv msec_delay(100); 652190877Sjfv } 653190877Sjfv if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 654190877Sjfv status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 655190877Sjfv DEBUGOUT("Autoneg did not complete.\n"); 656190877Sjfv } 657190877Sjfv } 658190877Sjfv } 659190877Sjfv 660190877Sjfv /* Add delay to filter out noises during initial link setup */ 661190877Sjfv msec_delay(50); 662190877Sjfv 663247822Sjfvout: 664190877Sjfv return status; 665190877Sjfv} 666190877Sjfv 667190877Sjfv/** 668215911Sjfv * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 669215911Sjfv * @hw: pointer to hardware structure 670215911Sjfv * 671215911Sjfv * The base drivers may require better control over SFP+ module 672215911Sjfv * PHY states. This includes selectively shutting down the Tx 673215911Sjfv * laser on the PHY, effectively halting physical link. 674215911Sjfv **/ 675215911Sjfvvoid ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 676215911Sjfv{ 677215911Sjfv u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 678215911Sjfv 679283620Serj /* Blocked by MNG FW so bail */ 680283620Serj if (ixgbe_check_reset_blocked(hw)) 681283620Serj return; 682283620Serj 683283620Serj /* Disable Tx laser; allow 100us to go dark per spec */ 684215911Sjfv esdp_reg |= IXGBE_ESDP_SDP3; 685215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 686215911Sjfv IXGBE_WRITE_FLUSH(hw); 687215911Sjfv usec_delay(100); 688215911Sjfv} 689215911Sjfv 690215911Sjfv/** 691215911Sjfv * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 692215911Sjfv * @hw: pointer to hardware structure 693215911Sjfv * 694215911Sjfv * The base drivers may require better control over SFP+ module 695215911Sjfv * PHY states. This includes selectively turning on the Tx 696215911Sjfv * laser on the PHY, effectively starting physical link. 697215911Sjfv **/ 698215911Sjfvvoid ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 699215911Sjfv{ 700215911Sjfv u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 701215911Sjfv 702283620Serj /* Enable Tx laser; allow 100ms to light up */ 703215911Sjfv esdp_reg &= ~IXGBE_ESDP_SDP3; 704215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 705215911Sjfv IXGBE_WRITE_FLUSH(hw); 706215911Sjfv msec_delay(100); 707215911Sjfv} 708215911Sjfv 709215911Sjfv/** 710215911Sjfv * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 711215911Sjfv * @hw: pointer to hardware structure 712215911Sjfv * 713215911Sjfv * When the driver changes the link speeds that it can support, 714215911Sjfv * it sets autotry_restart to TRUE to indicate that we need to 715215911Sjfv * initiate a new autotry session with the link partner. To do 716283620Serj * so, we set the speed then disable and re-enable the Tx laser, to 717215911Sjfv * alert the link partner that it also needs to restart autotry on its 718215911Sjfv * end. This is consistent with TRUE clause 37 autoneg, which also 719215911Sjfv * involves a loss of signal. 720215911Sjfv **/ 721215911Sjfvvoid ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 722215911Sjfv{ 723215911Sjfv DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 724215911Sjfv 725283620Serj /* Blocked by MNG FW so bail */ 726283620Serj if (ixgbe_check_reset_blocked(hw)) 727283620Serj return; 728283620Serj 729215911Sjfv if (hw->mac.autotry_restart) { 730215911Sjfv ixgbe_disable_tx_laser_multispeed_fiber(hw); 731215911Sjfv ixgbe_enable_tx_laser_multispeed_fiber(hw); 732215911Sjfv hw->mac.autotry_restart = FALSE; 733215911Sjfv } 734215911Sjfv} 735215911Sjfv 736215911Sjfv/** 737283620Serj * ixgbe_set_hard_rate_select_speed - Set module link speed 738247822Sjfv * @hw: pointer to hardware structure 739247822Sjfv * @speed: link speed to set 740247822Sjfv * 741283620Serj * Set module link speed via RS0/RS1 rate select pins. 742247822Sjfv */ 743283620Serjvoid ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 744247822Sjfv ixgbe_link_speed speed) 745247822Sjfv{ 746283620Serj u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 747247822Sjfv 748247822Sjfv switch (speed) { 749247822Sjfv case IXGBE_LINK_SPEED_10GB_FULL: 750283620Serj esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 751247822Sjfv break; 752247822Sjfv case IXGBE_LINK_SPEED_1GB_FULL: 753283620Serj esdp_reg &= ~IXGBE_ESDP_SDP5; 754283620Serj esdp_reg |= IXGBE_ESDP_SDP5_DIR; 755247822Sjfv break; 756247822Sjfv default: 757247822Sjfv DEBUGOUT("Invalid fixed module speed\n"); 758247822Sjfv return; 759247822Sjfv } 760247822Sjfv 761283620Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 762283620Serj IXGBE_WRITE_FLUSH(hw); 763247822Sjfv} 764247822Sjfv 765247822Sjfv/** 766200239Sjfv * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 767190877Sjfv * @hw: pointer to hardware structure 768200239Sjfv * @speed: new link speed 769200239Sjfv * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 770190877Sjfv * 771200239Sjfv * Implements the Intel SmartSpeed algorithm. 772190877Sjfv **/ 773200239Sjfvs32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 774247822Sjfv ixgbe_link_speed speed, 775230775Sjfv bool autoneg_wait_to_complete) 776190877Sjfv{ 777200239Sjfv s32 status = IXGBE_SUCCESS; 778215911Sjfv ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 779200239Sjfv s32 i, j; 780200239Sjfv bool link_up = FALSE; 781200239Sjfv u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 782190877Sjfv 783200239Sjfv DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 784200239Sjfv 785200239Sjfv /* Set autoneg_advertised value based on input link speed */ 786200239Sjfv hw->phy.autoneg_advertised = 0; 787200239Sjfv 788200239Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) 789200239Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 790200239Sjfv 791200239Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) 792200239Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 793200239Sjfv 794200239Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) 795200239Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 796200239Sjfv 797200239Sjfv /* 798200239Sjfv * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 799200239Sjfv * autoneg advertisement if link is unable to be established at the 800200239Sjfv * highest negotiated rate. This can sometimes happen due to integrity 801200239Sjfv * issues with the physical media connection. 802200239Sjfv */ 803200239Sjfv 804200239Sjfv /* First, try to get link with full advertisement */ 805200239Sjfv hw->phy.smart_speed_active = FALSE; 806200239Sjfv for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 807247822Sjfv status = ixgbe_setup_mac_link_82599(hw, speed, 808200239Sjfv autoneg_wait_to_complete); 809200239Sjfv if (status != IXGBE_SUCCESS) 810200239Sjfv goto out; 811200239Sjfv 812200239Sjfv /* 813200239Sjfv * Wait for the controller to acquire link. Per IEEE 802.3ap, 814200239Sjfv * Section 73.10.2, we may have to wait up to 500ms if KR is 815200239Sjfv * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 816200239Sjfv * Table 9 in the AN MAS. 817200239Sjfv */ 818200239Sjfv for (i = 0; i < 5; i++) { 819190877Sjfv msec_delay(100); 820200239Sjfv 821200239Sjfv /* If we have link, just jump out */ 822200239Sjfv status = ixgbe_check_link(hw, &link_speed, &link_up, 823200239Sjfv FALSE); 824200239Sjfv if (status != IXGBE_SUCCESS) 825200239Sjfv goto out; 826200239Sjfv 827200239Sjfv if (link_up) 828200239Sjfv goto out; 829190877Sjfv } 830190877Sjfv } 831190877Sjfv 832200239Sjfv /* 833200239Sjfv * We didn't get link. If we advertised KR plus one of KX4/KX 834200239Sjfv * (or BX4/BX), then disable KR and try again. 835200239Sjfv */ 836200239Sjfv if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 837200239Sjfv ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 838200239Sjfv goto out; 839190877Sjfv 840200239Sjfv /* Turn SmartSpeed on to disable KR support */ 841200239Sjfv hw->phy.smart_speed_active = TRUE; 842247822Sjfv status = ixgbe_setup_mac_link_82599(hw, speed, 843200239Sjfv autoneg_wait_to_complete); 844200239Sjfv if (status != IXGBE_SUCCESS) 845200239Sjfv goto out; 846200239Sjfv 847200239Sjfv /* 848200239Sjfv * Wait for the controller to acquire link. 600ms will allow for 849200239Sjfv * the AN link_fail_inhibit_timer as well for multiple cycles of 850200239Sjfv * parallel detect, both 10g and 1g. This allows for the maximum 851200239Sjfv * connect attempts as defined in the AN MAS table 73-7. 852200239Sjfv */ 853200239Sjfv for (i = 0; i < 6; i++) { 854200239Sjfv msec_delay(100); 855200239Sjfv 856200239Sjfv /* If we have link, just jump out */ 857200239Sjfv status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 858200239Sjfv if (status != IXGBE_SUCCESS) 859200239Sjfv goto out; 860200239Sjfv 861200239Sjfv if (link_up) 862200239Sjfv goto out; 863190877Sjfv } 864190877Sjfv 865200239Sjfv /* We didn't get link. Turn SmartSpeed back off. */ 866200239Sjfv hw->phy.smart_speed_active = FALSE; 867247822Sjfv status = ixgbe_setup_mac_link_82599(hw, speed, 868200239Sjfv autoneg_wait_to_complete); 869200239Sjfv 870200239Sjfvout: 871215911Sjfv if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 872215911Sjfv DEBUGOUT("Smartspeed has downgraded the link speed " 873215911Sjfv "from the maximum advertised\n"); 874200239Sjfv return status; 875190877Sjfv} 876190877Sjfv 877190877Sjfv/** 878200239Sjfv * ixgbe_setup_mac_link_82599 - Set MAC link speed 879190877Sjfv * @hw: pointer to hardware structure 880190877Sjfv * @speed: new link speed 881190877Sjfv * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 882190877Sjfv * 883190877Sjfv * Set the link speed in the AUTOC register and restarts link. 884190877Sjfv **/ 885200239Sjfvs32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 886247822Sjfv ixgbe_link_speed speed, 887230775Sjfv bool autoneg_wait_to_complete) 888190877Sjfv{ 889247822Sjfv bool autoneg = FALSE; 890190877Sjfv s32 status = IXGBE_SUCCESS; 891283620Serj u32 pma_pmd_1g, link_mode; 892283620Serj u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */ 893283620Serj u32 orig_autoc = 0; /* holds the cached value of AUTOC register */ 894283620Serj u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */ 895190877Sjfv u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 896190877Sjfv u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 897190877Sjfv u32 links_reg; 898190877Sjfv u32 i; 899190877Sjfv ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 900190877Sjfv 901200239Sjfv DEBUGFUNC("ixgbe_setup_mac_link_82599"); 902200239Sjfv 903190877Sjfv /* Check to see if speed passed in is supported. */ 904190877Sjfv status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 905247822Sjfv if (status) 906190877Sjfv goto out; 907190877Sjfv 908190877Sjfv speed &= link_capabilities; 909190877Sjfv 910194875Sjfv if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 911194875Sjfv status = IXGBE_ERR_LINK_SETUP; 912194875Sjfv goto out; 913194875Sjfv } 914194875Sjfv 915190877Sjfv /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 916190877Sjfv if (hw->mac.orig_link_settings_stored) 917283620Serj orig_autoc = hw->mac.orig_autoc; 918190877Sjfv else 919283620Serj orig_autoc = autoc; 920190877Sjfv 921247822Sjfv link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 922247822Sjfv pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 923247822Sjfv 924194875Sjfv if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 925215911Sjfv link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 926215911Sjfv link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 927190877Sjfv /* Set KX4/KX/KR support according to speed requested */ 928190877Sjfv autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 929240155Skevlo if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 930190877Sjfv if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 931190877Sjfv autoc |= IXGBE_AUTOC_KX4_SUPP; 932200239Sjfv if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 933200239Sjfv (hw->phy.smart_speed_active == FALSE)) 934190877Sjfv autoc |= IXGBE_AUTOC_KR_SUPP; 935240155Skevlo } 936190877Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) 937190877Sjfv autoc |= IXGBE_AUTOC_KX_SUPP; 938190877Sjfv } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 939230775Sjfv (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 940230775Sjfv link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 941190877Sjfv /* Switch from 1G SFI to 10G SFI if requested */ 942190877Sjfv if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 943190877Sjfv (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 944190877Sjfv autoc &= ~IXGBE_AUTOC_LMS_MASK; 945190877Sjfv autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 946190877Sjfv } 947190877Sjfv } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 948230775Sjfv (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 949190877Sjfv /* Switch from 10G SFI to 1G SFI if requested */ 950190877Sjfv if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 951190877Sjfv (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 952190877Sjfv autoc &= ~IXGBE_AUTOC_LMS_MASK; 953283620Serj if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) 954190877Sjfv autoc |= IXGBE_AUTOC_LMS_1G_AN; 955190877Sjfv else 956190877Sjfv autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 957190877Sjfv } 958190877Sjfv } 959190877Sjfv 960283620Serj if (autoc != current_autoc) { 961190877Sjfv /* Restart link */ 962283620Serj status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE); 963283620Serj if (status != IXGBE_SUCCESS) 964283620Serj goto out; 965190877Sjfv 966190877Sjfv /* Only poll for autoneg to complete if specified to do so */ 967190877Sjfv if (autoneg_wait_to_complete) { 968190877Sjfv if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 969190877Sjfv link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 970190877Sjfv link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 971190877Sjfv links_reg = 0; /*Just in case Autoneg time=0*/ 972190877Sjfv for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 973190877Sjfv links_reg = 974190877Sjfv IXGBE_READ_REG(hw, IXGBE_LINKS); 975190877Sjfv if (links_reg & IXGBE_LINKS_KX_AN_COMP) 976190877Sjfv break; 977190877Sjfv msec_delay(100); 978190877Sjfv } 979190877Sjfv if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 980190877Sjfv status = 981190877Sjfv IXGBE_ERR_AUTONEG_NOT_COMPLETE; 982190877Sjfv DEBUGOUT("Autoneg did not complete.\n"); 983190877Sjfv } 984190877Sjfv } 985190877Sjfv } 986190877Sjfv 987190877Sjfv /* Add delay to filter out noises during initial link setup */ 988190877Sjfv msec_delay(50); 989190877Sjfv } 990190877Sjfv 991190877Sjfvout: 992190877Sjfv return status; 993190877Sjfv} 994190877Sjfv 995190877Sjfv/** 996200239Sjfv * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 997190877Sjfv * @hw: pointer to hardware structure 998190877Sjfv * @speed: new link speed 999190877Sjfv * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 1000190877Sjfv * 1001190877Sjfv * Restarts link on PHY and MAC based on settings passed in. 1002190877Sjfv **/ 1003200239Sjfvstatic s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1004230775Sjfv ixgbe_link_speed speed, 1005230775Sjfv bool autoneg_wait_to_complete) 1006190877Sjfv{ 1007190877Sjfv s32 status; 1008190877Sjfv 1009200239Sjfv DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1010200239Sjfv 1011190877Sjfv /* Setup the PHY according to input speed */ 1012247822Sjfv status = hw->phy.ops.setup_link_speed(hw, speed, 1013230775Sjfv autoneg_wait_to_complete); 1014190877Sjfv /* Set up MAC */ 1015200239Sjfv ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1016190877Sjfv 1017190877Sjfv return status; 1018190877Sjfv} 1019215911Sjfv 1020190877Sjfv/** 1021190877Sjfv * ixgbe_reset_hw_82599 - Perform hardware reset 1022190877Sjfv * @hw: pointer to hardware structure 1023190877Sjfv * 1024190877Sjfv * Resets the hardware by resetting the transmit and receive units, masks 1025190877Sjfv * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1026190877Sjfv * reset. 1027190877Sjfv **/ 1028190877Sjfvs32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1029190877Sjfv{ 1030230775Sjfv ixgbe_link_speed link_speed; 1031230775Sjfv s32 status; 1032283620Serj u32 ctrl = 0; 1033283620Serj u32 i, autoc, autoc2; 1034251964Sjfv u32 curr_lms; 1035230775Sjfv bool link_up = FALSE; 1036190877Sjfv 1037200239Sjfv DEBUGFUNC("ixgbe_reset_hw_82599"); 1038200239Sjfv 1039190877Sjfv /* Call adapter stop to disable tx/rx and clear interrupts */ 1040230775Sjfv status = hw->mac.ops.stop_adapter(hw); 1041230775Sjfv if (status != IXGBE_SUCCESS) 1042230775Sjfv goto reset_hw_out; 1043190877Sjfv 1044230775Sjfv /* flush pending Tx transactions */ 1045230775Sjfv ixgbe_clear_tx_pending(hw); 1046230775Sjfv 1047190877Sjfv /* PHY ops must be identified and initialized prior to reset */ 1048190877Sjfv 1049190877Sjfv /* Identify PHY and related function pointers */ 1050190877Sjfv status = hw->phy.ops.init(hw); 1051190877Sjfv 1052190877Sjfv if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1053190877Sjfv goto reset_hw_out; 1054190877Sjfv 1055190877Sjfv /* Setup SFP module if there is one present. */ 1056190877Sjfv if (hw->phy.sfp_setup_needed) { 1057190877Sjfv status = hw->mac.ops.setup_sfp(hw); 1058190877Sjfv hw->phy.sfp_setup_needed = FALSE; 1059190877Sjfv } 1060190877Sjfv 1061190877Sjfv if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1062190877Sjfv goto reset_hw_out; 1063190877Sjfv 1064190877Sjfv /* Reset PHY */ 1065190877Sjfv if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1066190877Sjfv hw->phy.ops.reset(hw); 1067190877Sjfv 1068251964Sjfv /* remember AUTOC from before we reset */ 1069283620Serj curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1070251964Sjfv 1071230775Sjfvmac_reset_top: 1072190877Sjfv /* 1073230775Sjfv * Issue global reset to the MAC. Needs to be SW reset if link is up. 1074230775Sjfv * If link reset is used when link is up, it might reset the PHY when 1075230775Sjfv * mng is using it. If link is down or the flag to force full link 1076230775Sjfv * reset is set, then perform link reset. 1077190877Sjfv */ 1078230775Sjfv ctrl = IXGBE_CTRL_LNK_RST; 1079230775Sjfv if (!hw->force_full_reset) { 1080230775Sjfv hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1081230775Sjfv if (link_up) 1082230775Sjfv ctrl = IXGBE_CTRL_RST; 1083230775Sjfv } 1084190877Sjfv 1085230775Sjfv ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1086230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1087190877Sjfv IXGBE_WRITE_FLUSH(hw); 1088190877Sjfv 1089283620Serj /* Poll for reset bit to self-clear meaning reset is complete */ 1090190877Sjfv for (i = 0; i < 10; i++) { 1091190877Sjfv usec_delay(1); 1092190877Sjfv ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1093230775Sjfv if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1094190877Sjfv break; 1095190877Sjfv } 1096230775Sjfv 1097230775Sjfv if (ctrl & IXGBE_CTRL_RST_MASK) { 1098190877Sjfv status = IXGBE_ERR_RESET_FAILED; 1099190877Sjfv DEBUGOUT("Reset polling failed to complete.\n"); 1100190877Sjfv } 1101190877Sjfv 1102230775Sjfv msec_delay(50); 1103230775Sjfv 1104205720Sjfv /* 1105205720Sjfv * Double resets are required for recovery from certain error 1106283620Serj * conditions. Between resets, it is necessary to stall to 1107283620Serj * allow time for any pending HW events to complete. 1108205720Sjfv */ 1109205720Sjfv if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1110205720Sjfv hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1111205720Sjfv goto mac_reset_top; 1112205720Sjfv } 1113205720Sjfv 1114190877Sjfv /* 1115190877Sjfv * Store the original AUTOC/AUTOC2 values if they have not been 1116190877Sjfv * stored off yet. Otherwise restore the stored original 1117190877Sjfv * values since the reset operation sets back to defaults. 1118190877Sjfv */ 1119283620Serj autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1120190877Sjfv autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1121247822Sjfv 1122247822Sjfv /* Enable link if disabled in NVM */ 1123247822Sjfv if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1124247822Sjfv autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1125247822Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1126247822Sjfv IXGBE_WRITE_FLUSH(hw); 1127247822Sjfv } 1128247822Sjfv 1129190877Sjfv if (hw->mac.orig_link_settings_stored == FALSE) { 1130283620Serj hw->mac.orig_autoc = autoc; 1131190877Sjfv hw->mac.orig_autoc2 = autoc2; 1132190877Sjfv hw->mac.orig_link_settings_stored = TRUE; 1133190877Sjfv } else { 1134251964Sjfv 1135251964Sjfv /* If MNG FW is running on a multi-speed device that 1136251964Sjfv * doesn't autoneg with out driver support we need to 1137251964Sjfv * leave LMS in the state it was before we MAC reset. 1138251964Sjfv * Likewise if we support WoL we don't want change the 1139251964Sjfv * LMS state. 1140251964Sjfv */ 1141283620Serj if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1142251964Sjfv hw->wol_enabled) 1143251964Sjfv hw->mac.orig_autoc = 1144251964Sjfv (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1145251964Sjfv curr_lms; 1146251964Sjfv 1147283620Serj if (autoc != hw->mac.orig_autoc) { 1148283620Serj status = hw->mac.ops.prot_autoc_write(hw, 1149283620Serj hw->mac.orig_autoc, 1150283620Serj FALSE); 1151283620Serj if (status != IXGBE_SUCCESS) 1152283620Serj goto reset_hw_out; 1153247822Sjfv } 1154247822Sjfv 1155190877Sjfv if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1156190877Sjfv (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1157190877Sjfv autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1158190877Sjfv autoc2 |= (hw->mac.orig_autoc2 & 1159230775Sjfv IXGBE_AUTOC2_UPPER_MASK); 1160190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1161190877Sjfv } 1162190877Sjfv } 1163190877Sjfv 1164215911Sjfv /* Store the permanent mac address */ 1165194875Sjfv hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1166194875Sjfv 1167190877Sjfv /* 1168190877Sjfv * Store MAC address from RAR0, clear receive address registers, and 1169190877Sjfv * clear the multicast table. Also reset num_rar_entries to 128, 1170190877Sjfv * since we modify this value when programming the SAN MAC address. 1171190877Sjfv */ 1172190877Sjfv hw->mac.num_rar_entries = 128; 1173190877Sjfv hw->mac.ops.init_rx_addrs(hw); 1174190877Sjfv 1175190877Sjfv /* Store the permanent SAN mac address */ 1176190877Sjfv hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1177190877Sjfv 1178190877Sjfv /* Add the SAN MAC address to the RAR only if it's a valid address */ 1179190877Sjfv if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1180190877Sjfv hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1181230775Sjfv hw->mac.san_addr, 0, IXGBE_RAH_AV); 1182190877Sjfv 1183238149Sjfv /* Save the SAN MAC RAR index */ 1184238149Sjfv hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1185238149Sjfv 1186190877Sjfv /* Reserve the last RAR for the SAN MAC address */ 1187190877Sjfv hw->mac.num_rar_entries--; 1188215911Sjfv } 1189190877Sjfv 1190200239Sjfv /* Store the alternative WWNN/WWPN prefix */ 1191200239Sjfv hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1192230775Sjfv &hw->mac.wwpn_prefix); 1193200239Sjfv 1194190877Sjfvreset_hw_out: 1195190877Sjfv return status; 1196190877Sjfv} 1197190877Sjfv 1198190877Sjfv/** 1199283620Serj * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1200283620Serj * @hw: pointer to hardware structure 1201283620Serj * @fdircmd: current value of FDIRCMD register 1202283620Serj */ 1203283620Serjstatic s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1204283620Serj{ 1205283620Serj int i; 1206283620Serj 1207283620Serj for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1208283620Serj *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1209283620Serj if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1210283620Serj return IXGBE_SUCCESS; 1211283620Serj usec_delay(10); 1212283620Serj } 1213283620Serj 1214283620Serj return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1215283620Serj} 1216283620Serj 1217283620Serj/** 1218190877Sjfv * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1219190877Sjfv * @hw: pointer to hardware structure 1220190877Sjfv **/ 1221190877Sjfvs32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1222190877Sjfv{ 1223283620Serj s32 err; 1224194875Sjfv int i; 1225190877Sjfv u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1226283620Serj u32 fdircmd; 1227190877Sjfv fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1228194875Sjfv 1229200239Sjfv DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1230200239Sjfv 1231194875Sjfv /* 1232194875Sjfv * Before starting reinitialization process, 1233194875Sjfv * FDIRCMD.CMD must be zero. 1234194875Sjfv */ 1235283620Serj err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1236283620Serj if (err) { 1237283620Serj DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); 1238283620Serj return err; 1239194875Sjfv } 1240194875Sjfv 1241190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1242190877Sjfv IXGBE_WRITE_FLUSH(hw); 1243194875Sjfv /* 1244194875Sjfv * 82599 adapters flow director init flow cannot be restarted, 1245194875Sjfv * Workaround 82599 silicon errata by performing the following steps 1246194875Sjfv * before re-writing the FDIRCTRL control register with the same value. 1247194875Sjfv * - write 1 to bit 8 of FDIRCMD register & 1248194875Sjfv * - write 0 to bit 8 of FDIRCMD register 1249194875Sjfv */ 1250194875Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1251230775Sjfv (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1252230775Sjfv IXGBE_FDIRCMD_CLEARHT)); 1253194875Sjfv IXGBE_WRITE_FLUSH(hw); 1254194875Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1255230775Sjfv (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1256230775Sjfv ~IXGBE_FDIRCMD_CLEARHT)); 1257194875Sjfv IXGBE_WRITE_FLUSH(hw); 1258194875Sjfv /* 1259194875Sjfv * Clear FDIR Hash register to clear any leftover hashes 1260194875Sjfv * waiting to be programmed. 1261194875Sjfv */ 1262194875Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1263194875Sjfv IXGBE_WRITE_FLUSH(hw); 1264194875Sjfv 1265190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1266194875Sjfv IXGBE_WRITE_FLUSH(hw); 1267190877Sjfv 1268194875Sjfv /* Poll init-done after we write FDIRCTRL register */ 1269194875Sjfv for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1270194875Sjfv if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1271230775Sjfv IXGBE_FDIRCTRL_INIT_DONE) 1272194875Sjfv break; 1273247822Sjfv msec_delay(1); 1274194875Sjfv } 1275194875Sjfv if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1276194875Sjfv DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1277194875Sjfv return IXGBE_ERR_FDIR_REINIT_FAILED; 1278194875Sjfv } 1279194875Sjfv 1280194875Sjfv /* Clear FDIR statistics registers (read to clear) */ 1281194875Sjfv IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1282194875Sjfv IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1283194875Sjfv IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1284194875Sjfv IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1285194875Sjfv IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1286194875Sjfv 1287190877Sjfv return IXGBE_SUCCESS; 1288190877Sjfv} 1289190877Sjfv 1290190877Sjfv/** 1291230775Sjfv * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1292190877Sjfv * @hw: pointer to hardware structure 1293230775Sjfv * @fdirctrl: value to write to flow director control register 1294190877Sjfv **/ 1295230775Sjfvstatic void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1296190877Sjfv{ 1297190877Sjfv int i; 1298190877Sjfv 1299230775Sjfv DEBUGFUNC("ixgbe_fdir_enable_82599"); 1300200239Sjfv 1301190877Sjfv /* Prime the keys for hashing */ 1302215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1303215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1304190877Sjfv 1305190877Sjfv /* 1306190877Sjfv * Poll init-done after we write the register. Estimated times: 1307190877Sjfv * 10G: PBALLOC = 11b, timing is 60us 1308190877Sjfv * 1G: PBALLOC = 11b, timing is 600us 1309190877Sjfv * 100M: PBALLOC = 11b, timing is 6ms 1310190877Sjfv * 1311190877Sjfv * Multiple these timings by 4 if under full Rx load 1312190877Sjfv * 1313190877Sjfv * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1314190877Sjfv * 1 msec per poll time. If we're at line rate and drop to 100M, then 1315190877Sjfv * this might not finish in our poll time, but we can live with that 1316190877Sjfv * for now. 1317190877Sjfv */ 1318190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1319190877Sjfv IXGBE_WRITE_FLUSH(hw); 1320190877Sjfv for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1321190877Sjfv if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1322230775Sjfv IXGBE_FDIRCTRL_INIT_DONE) 1323190877Sjfv break; 1324190877Sjfv msec_delay(1); 1325190877Sjfv } 1326230775Sjfv 1327190877Sjfv if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1328230775Sjfv DEBUGOUT("Flow Director poll time exceeded!\n"); 1329190877Sjfv} 1330190877Sjfv 1331190877Sjfv/** 1332230775Sjfv * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1333190877Sjfv * @hw: pointer to hardware structure 1334230775Sjfv * @fdirctrl: value to write to flow director control register, initially 1335230775Sjfv * contains just the value of the Rx packet buffer allocation 1336190877Sjfv **/ 1337230775Sjfvs32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1338190877Sjfv{ 1339230775Sjfv DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1340190877Sjfv 1341190877Sjfv /* 1342230775Sjfv * Continue setup of fdirctrl register bits: 1343230775Sjfv * Move the flexible bytes to use the ethertype - shift 6 words 1344230775Sjfv * Set the maximum length per hash bucket to 0xA filters 1345230775Sjfv * Send interrupt when 64 filters are left 1346190877Sjfv */ 1347230775Sjfv fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1348230775Sjfv (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1349230775Sjfv (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1350190877Sjfv 1351230775Sjfv /* write hashes and fdirctrl register, poll for completion */ 1352230775Sjfv ixgbe_fdir_enable_82599(hw, fdirctrl); 1353190877Sjfv 1354190877Sjfv return IXGBE_SUCCESS; 1355190877Sjfv} 1356190877Sjfv 1357190877Sjfv/** 1358230775Sjfv * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1359230775Sjfv * @hw: pointer to hardware structure 1360230775Sjfv * @fdirctrl: value to write to flow director control register, initially 1361230775Sjfv * contains just the value of the Rx packet buffer allocation 1362283620Serj * @cloud_mode: TRUE - cloud mode, FALSE - other mode 1363190877Sjfv **/ 1364283620Serjs32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, 1365283620Serj bool cloud_mode) 1366190877Sjfv{ 1367230775Sjfv DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1368190877Sjfv 1369194875Sjfv /* 1370230775Sjfv * Continue setup of fdirctrl register bits: 1371230775Sjfv * Turn perfect match filtering on 1372230775Sjfv * Report hash in RSS field of Rx wb descriptor 1373295524Ssbruno * Initialize the drop queue to queue 127 1374230775Sjfv * Move the flexible bytes to use the ethertype - shift 6 words 1375230775Sjfv * Set the maximum length per hash bucket to 0xA filters 1376230775Sjfv * Send interrupt when 64 (0x4 * 16) filters are left 1377194875Sjfv */ 1378230775Sjfv fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1379230775Sjfv IXGBE_FDIRCTRL_REPORT_STATUS | 1380230775Sjfv (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1381230775Sjfv (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1382230775Sjfv (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1383230775Sjfv (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1384295524Ssbruno if ((hw->mac.type == ixgbe_mac_X550) || 1385295524Ssbruno (hw->mac.type == ixgbe_mac_X550EM_x)) 1386295524Ssbruno fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; 1387194875Sjfv 1388283620Serj if (cloud_mode) 1389283620Serj fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << 1390283620Serj IXGBE_FDIRCTRL_FILTERMODE_SHIFT); 1391283620Serj 1392230775Sjfv /* write hashes and fdirctrl register, poll for completion */ 1393230775Sjfv ixgbe_fdir_enable_82599(hw, fdirctrl); 1394217593Sjfv 1395230775Sjfv return IXGBE_SUCCESS; 1396215911Sjfv} 1397194875Sjfv 1398295524Ssbruno/** 1399295524Ssbruno * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue 1400295524Ssbruno * @hw: pointer to hardware structure 1401295524Ssbruno * @dropqueue: Rx queue index used for the dropped packets 1402295524Ssbruno **/ 1403295524Ssbrunovoid ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) 1404295524Ssbruno{ 1405295524Ssbruno u32 fdirctrl; 1406295524Ssbruno 1407295524Ssbruno DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599"); 1408295524Ssbruno /* Clear init done bit and drop queue field */ 1409295524Ssbruno fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1410295524Ssbruno fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE); 1411295524Ssbruno 1412295524Ssbruno /* Set drop queue */ 1413295524Ssbruno fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1414295524Ssbruno if ((hw->mac.type == ixgbe_mac_X550) || 1415295524Ssbruno (hw->mac.type == ixgbe_mac_X550EM_x)) 1416295524Ssbruno fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH; 1417295524Ssbruno 1418295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1419295524Ssbruno (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1420295524Ssbruno IXGBE_FDIRCMD_CLEARHT)); 1421295524Ssbruno IXGBE_WRITE_FLUSH(hw); 1422295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1423295524Ssbruno (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1424295524Ssbruno ~IXGBE_FDIRCMD_CLEARHT)); 1425295524Ssbruno IXGBE_WRITE_FLUSH(hw); 1426295524Ssbruno 1427295524Ssbruno /* write hashes and fdirctrl register, poll for completion */ 1428295524Ssbruno ixgbe_fdir_enable_82599(hw, fdirctrl); 1429295524Ssbruno} 1430295524Ssbruno 1431215911Sjfv/* 1432215911Sjfv * These defines allow us to quickly generate all of the necessary instructions 1433215911Sjfv * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1434215911Sjfv * for values 0 through 15 1435215911Sjfv */ 1436215911Sjfv#define IXGBE_ATR_COMMON_HASH_KEY \ 1437215911Sjfv (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1438215911Sjfv#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1439215911Sjfvdo { \ 1440215911Sjfv u32 n = (_n); \ 1441217593Sjfv if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1442215911Sjfv common_hash ^= lo_hash_dword >> n; \ 1443217593Sjfv else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1444215911Sjfv bucket_hash ^= lo_hash_dword >> n; \ 1445217593Sjfv else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1446217593Sjfv sig_hash ^= lo_hash_dword << (16 - n); \ 1447217593Sjfv if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1448215911Sjfv common_hash ^= hi_hash_dword >> n; \ 1449217593Sjfv else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1450215911Sjfv bucket_hash ^= hi_hash_dword >> n; \ 1451217593Sjfv else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1452217593Sjfv sig_hash ^= hi_hash_dword << (16 - n); \ 1453283620Serj} while (0) 1454190877Sjfv 1455215911Sjfv/** 1456215911Sjfv * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1457215911Sjfv * @stream: input bitstream to compute the hash on 1458215911Sjfv * 1459215911Sjfv * This function is almost identical to the function above but contains 1460283620Serj * several optimizations such as unwinding all of the loops, letting the 1461215911Sjfv * compiler work out all of the conditional ifs since the keys are static 1462215911Sjfv * defines, and computing two keys at once since the hashed dword stream 1463215911Sjfv * will be the same for both keys. 1464215911Sjfv **/ 1465230775Sjfvu32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1466230775Sjfv union ixgbe_atr_hash_dword common) 1467215911Sjfv{ 1468217593Sjfv u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1469217593Sjfv u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1470215911Sjfv 1471217593Sjfv /* record the flow_vm_vlan bits as they are a key part to the hash */ 1472217593Sjfv flow_vm_vlan = IXGBE_NTOHL(input.dword); 1473190877Sjfv 1474215911Sjfv /* generate common hash dword */ 1475217593Sjfv hi_hash_dword = IXGBE_NTOHL(common.dword); 1476215911Sjfv 1477215911Sjfv /* low dword is word swapped version of common */ 1478217593Sjfv lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1479215911Sjfv 1480217593Sjfv /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1481217593Sjfv hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1482215911Sjfv 1483217593Sjfv /* Process bits 0 and 16 */ 1484217593Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1485217593Sjfv 1486190877Sjfv /* 1487217593Sjfv * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1488217593Sjfv * delay this because bit 0 of the stream should not be processed 1489283620Serj * so we do not add the VLAN until after bit 0 was processed 1490190877Sjfv */ 1491217593Sjfv lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1492217593Sjfv 1493217593Sjfv /* Process remaining 30 bit of the key */ 1494215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1495215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1496215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1497215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1498215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1499215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1500215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1501215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1502215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1503215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1504215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1505215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1506215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1507215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1508215911Sjfv IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1509190877Sjfv 1510215911Sjfv /* combine common_hash result with signature and bucket hashes */ 1511215911Sjfv bucket_hash ^= common_hash; 1512217593Sjfv bucket_hash &= IXGBE_ATR_HASH_MASK; 1513215911Sjfv 1514217593Sjfv sig_hash ^= common_hash << 16; 1515217593Sjfv sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1516217593Sjfv 1517215911Sjfv /* return completed signature hash */ 1518217593Sjfv return sig_hash ^ bucket_hash; 1519190877Sjfv} 1520190877Sjfv 1521190877Sjfv/** 1522190877Sjfv * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1523190877Sjfv * @hw: pointer to hardware structure 1524230775Sjfv * @input: unique input dword 1525230775Sjfv * @common: compressed common input dword 1526190877Sjfv * @queue: queue index to direct traffic to 1527283620Serj * 1528283620Serj * Note that the tunnel bit in input must not be set when the hardware 1529283620Serj * tunneling support does not exist. 1530190877Sjfv **/ 1531295524Ssbrunovoid ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1532295524Ssbruno union ixgbe_atr_hash_dword input, 1533295524Ssbruno union ixgbe_atr_hash_dword common, 1534295524Ssbruno u8 queue) 1535190877Sjfv{ 1536283620Serj u64 fdirhashcmd; 1537283620Serj u8 flow_type; 1538283620Serj bool tunnel; 1539283620Serj u32 fdircmd; 1540190877Sjfv 1541200239Sjfv DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1542200239Sjfv 1543190877Sjfv /* 1544215911Sjfv * Get the flow_type in order to program FDIRCMD properly 1545215911Sjfv * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1546283620Serj * fifth is FDIRCMD.TUNNEL_FILTER 1547190877Sjfv */ 1548283620Serj tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1549283620Serj flow_type = input.formatted.flow_type & 1550283620Serj (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1551283620Serj switch (flow_type) { 1552215911Sjfv case IXGBE_ATR_FLOW_TYPE_TCPV4: 1553215911Sjfv case IXGBE_ATR_FLOW_TYPE_UDPV4: 1554215911Sjfv case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1555215911Sjfv case IXGBE_ATR_FLOW_TYPE_TCPV6: 1556215911Sjfv case IXGBE_ATR_FLOW_TYPE_UDPV6: 1557215911Sjfv case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1558190877Sjfv break; 1559190877Sjfv default: 1560215911Sjfv DEBUGOUT(" Error on flow type input\n"); 1561295524Ssbruno return; 1562190877Sjfv } 1563190877Sjfv 1564215911Sjfv /* configure FDIRCMD register */ 1565215911Sjfv fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1566230775Sjfv IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1567283620Serj fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1568217593Sjfv fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1569283620Serj if (tunnel) 1570283620Serj fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1571190877Sjfv 1572215911Sjfv /* 1573215911Sjfv * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1574215911Sjfv * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1575215911Sjfv */ 1576217593Sjfv fdirhashcmd = (u64)fdircmd << 32; 1577217593Sjfv fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1578190877Sjfv IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1579190877Sjfv 1580215911Sjfv DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1581215911Sjfv 1582295524Ssbruno return; 1583190877Sjfv} 1584190877Sjfv 1585230775Sjfv#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1586230775Sjfvdo { \ 1587230775Sjfv u32 n = (_n); \ 1588230775Sjfv if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1589230775Sjfv bucket_hash ^= lo_hash_dword >> n; \ 1590230775Sjfv if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1591230775Sjfv bucket_hash ^= hi_hash_dword >> n; \ 1592283620Serj} while (0) 1593230775Sjfv 1594190877Sjfv/** 1595230775Sjfv * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1596230775Sjfv * @atr_input: input bitstream to compute the hash on 1597230775Sjfv * @input_mask: mask for the input bitstream 1598230775Sjfv * 1599283620Serj * This function serves two main purposes. First it applies the input_mask 1600230775Sjfv * to the atr_input resulting in a cleaned up atr_input data stream. 1601230775Sjfv * Secondly it computes the hash and stores it in the bkt_hash field at 1602230775Sjfv * the end of the input byte stream. This way it will be available for 1603230775Sjfv * future use without needing to recompute the hash. 1604230775Sjfv **/ 1605230775Sjfvvoid ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1606230775Sjfv union ixgbe_atr_input *input_mask) 1607230775Sjfv{ 1608230775Sjfv 1609230775Sjfv u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1610230775Sjfv u32 bucket_hash = 0; 1611283620Serj u32 hi_dword = 0; 1612283620Serj u32 i = 0; 1613230775Sjfv 1614230775Sjfv /* Apply masks to input data */ 1615283620Serj for (i = 0; i < 14; i++) 1616283620Serj input->dword_stream[i] &= input_mask->dword_stream[i]; 1617230775Sjfv 1618230775Sjfv /* record the flow_vm_vlan bits as they are a key part to the hash */ 1619230775Sjfv flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); 1620230775Sjfv 1621230775Sjfv /* generate common hash dword */ 1622283620Serj for (i = 1; i <= 13; i++) 1623283620Serj hi_dword ^= input->dword_stream[i]; 1624283620Serj hi_hash_dword = IXGBE_NTOHL(hi_dword); 1625230775Sjfv 1626230775Sjfv /* low dword is word swapped version of common */ 1627230775Sjfv lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1628230775Sjfv 1629230775Sjfv /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1630230775Sjfv hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1631230775Sjfv 1632230775Sjfv /* Process bits 0 and 16 */ 1633230775Sjfv IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1634230775Sjfv 1635230775Sjfv /* 1636230775Sjfv * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1637230775Sjfv * delay this because bit 0 of the stream should not be processed 1638283620Serj * so we do not add the VLAN until after bit 0 was processed 1639230775Sjfv */ 1640230775Sjfv lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1641230775Sjfv 1642230775Sjfv /* Process remaining 30 bit of the key */ 1643283620Serj for (i = 1; i <= 15; i++) 1644283620Serj IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1645230775Sjfv 1646230775Sjfv /* 1647230775Sjfv * Limit hash to 13 bits since max bucket count is 8K. 1648230775Sjfv * Store result at the end of the input stream. 1649230775Sjfv */ 1650230775Sjfv input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1651230775Sjfv} 1652230775Sjfv 1653230775Sjfv/** 1654283620Serj * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks 1655215911Sjfv * @input_mask: mask to be bit swapped 1656215911Sjfv * 1657215911Sjfv * The source and destination port masks for flow director are bit swapped 1658215911Sjfv * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1659215911Sjfv * generate a correctly swapped value we need to bit swap the mask and that 1660215911Sjfv * is what is accomplished by this function. 1661215911Sjfv **/ 1662230775Sjfvstatic u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1663215911Sjfv{ 1664230775Sjfv u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); 1665215911Sjfv mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1666230775Sjfv mask |= IXGBE_NTOHS(input_mask->formatted.src_port); 1667215911Sjfv mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1668215911Sjfv mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1669215911Sjfv mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1670215911Sjfv return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1671215911Sjfv} 1672215911Sjfv 1673215911Sjfv/* 1674215911Sjfv * These two macros are meant to address the fact that we have registers 1675215911Sjfv * that are either all or in part big-endian. As a result on big-endian 1676215911Sjfv * systems we will end up byte swapping the value to little-endian before 1677215911Sjfv * it is byte swapped again and written to the hardware in the original 1678215911Sjfv * big-endian format. 1679215911Sjfv */ 1680215911Sjfv#define IXGBE_STORE_AS_BE32(_value) \ 1681215911Sjfv (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1682215911Sjfv (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1683215911Sjfv 1684215911Sjfv#define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1685215911Sjfv IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1686215911Sjfv 1687215911Sjfv#define IXGBE_STORE_AS_BE16(_value) \ 1688230775Sjfv IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1689215911Sjfv 1690230775Sjfvs32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1691283620Serj union ixgbe_atr_input *input_mask, bool cloud_mode) 1692190877Sjfv{ 1693230775Sjfv /* mask IPv6 since it is currently not supported */ 1694230775Sjfv u32 fdirm = IXGBE_FDIRM_DIPv6; 1695230775Sjfv u32 fdirtcpm; 1696283620Serj u32 fdirip6m; 1697230775Sjfv DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599"); 1698200239Sjfv 1699190877Sjfv /* 1700205720Sjfv * Program the relevant mask registers. If src/dst_port or src/dst_addr 1701205720Sjfv * are zero, then assume a full mask for that field. Also assume that 1702205720Sjfv * a VLAN of 0 is unspecified, so mask that out as well. L4type 1703205720Sjfv * cannot be masked out in this implementation. 1704205720Sjfv * 1705205720Sjfv * This also assumes IPv4 only. IPv6 masking isn't supported at this 1706205720Sjfv * point in time. 1707205720Sjfv */ 1708205720Sjfv 1709230775Sjfv /* verify bucket hash is cleared on hash generation */ 1710230775Sjfv if (input_mask->formatted.bkt_hash) 1711230775Sjfv DEBUGOUT(" bucket hash should always be 0 in mask\n"); 1712230775Sjfv 1713230775Sjfv /* Program FDIRM and verify partial masks */ 1714230775Sjfv switch (input_mask->formatted.vm_pool & 0x7F) { 1715230775Sjfv case 0x0: 1716230775Sjfv fdirm |= IXGBE_FDIRM_POOL; 1717230775Sjfv case 0x7F: 1718205720Sjfv break; 1719230775Sjfv default: 1720230775Sjfv DEBUGOUT(" Error on vm pool mask\n"); 1721230775Sjfv return IXGBE_ERR_CONFIG; 1722230775Sjfv } 1723230775Sjfv 1724230775Sjfv switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1725230775Sjfv case 0x0: 1726230775Sjfv fdirm |= IXGBE_FDIRM_L4P; 1727230775Sjfv if (input_mask->formatted.dst_port || 1728230775Sjfv input_mask->formatted.src_port) { 1729230775Sjfv DEBUGOUT(" Error on src/dst port mask\n"); 1730230775Sjfv return IXGBE_ERR_CONFIG; 1731230775Sjfv } 1732230775Sjfv case IXGBE_ATR_L4TYPE_MASK: 1733205720Sjfv break; 1734230775Sjfv default: 1735230775Sjfv DEBUGOUT(" Error on flow type mask\n"); 1736230775Sjfv return IXGBE_ERR_CONFIG; 1737230775Sjfv } 1738230775Sjfv 1739230775Sjfv switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { 1740215911Sjfv case 0x0000: 1741230775Sjfv /* mask VLAN ID, fall through to mask VLAN priority */ 1742230775Sjfv fdirm |= IXGBE_FDIRM_VLANID; 1743230775Sjfv case 0x0FFF: 1744230775Sjfv /* mask VLAN priority */ 1745230775Sjfv fdirm |= IXGBE_FDIRM_VLANP; 1746215911Sjfv break; 1747230775Sjfv case 0xE000: 1748230775Sjfv /* mask VLAN ID only, fall through */ 1749230775Sjfv fdirm |= IXGBE_FDIRM_VLANID; 1750230775Sjfv case 0xEFFF: 1751230775Sjfv /* no VLAN fields masked */ 1752230775Sjfv break; 1753205720Sjfv default: 1754215911Sjfv DEBUGOUT(" Error on VLAN mask\n"); 1755215911Sjfv return IXGBE_ERR_CONFIG; 1756205720Sjfv } 1757205720Sjfv 1758230775Sjfv switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1759230775Sjfv case 0x0000: 1760230775Sjfv /* Mask Flex Bytes, fall through */ 1761230775Sjfv fdirm |= IXGBE_FDIRM_FLEX; 1762230775Sjfv case 0xFFFF: 1763230775Sjfv break; 1764230775Sjfv default: 1765230775Sjfv DEBUGOUT(" Error on flexible byte mask\n"); 1766230775Sjfv return IXGBE_ERR_CONFIG; 1767215911Sjfv } 1768205720Sjfv 1769283620Serj if (cloud_mode) { 1770283620Serj fdirm |= IXGBE_FDIRM_L3P; 1771283620Serj fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); 1772283620Serj fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK; 1773283620Serj 1774283620Serj switch (input_mask->formatted.inner_mac[0] & 0xFF) { 1775283620Serj case 0x00: 1776283620Serj /* Mask inner MAC, fall through */ 1777283620Serj fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC; 1778283620Serj case 0xFF: 1779283620Serj break; 1780283620Serj default: 1781283620Serj DEBUGOUT(" Error on inner_mac byte mask\n"); 1782283620Serj return IXGBE_ERR_CONFIG; 1783283620Serj } 1784283620Serj 1785283620Serj switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { 1786283620Serj case 0x0: 1787283620Serj /* Mask vxlan id */ 1788283620Serj fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI; 1789283620Serj break; 1790283620Serj case 0x00FFFFFF: 1791283620Serj fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24; 1792283620Serj break; 1793283620Serj case 0xFFFFFFFF: 1794283620Serj break; 1795283620Serj default: 1796283620Serj DEBUGOUT(" Error on TNI/VNI byte mask\n"); 1797283620Serj return IXGBE_ERR_CONFIG; 1798283620Serj } 1799283620Serj 1800283620Serj switch (input_mask->formatted.tunnel_type & 0xFFFF) { 1801283620Serj case 0x0: 1802283620Serj /* Mask turnnel type, fall through */ 1803283620Serj fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE; 1804283620Serj case 0xFFFF: 1805283620Serj break; 1806283620Serj default: 1807283620Serj DEBUGOUT(" Error on tunnel type byte mask\n"); 1808283620Serj return IXGBE_ERR_CONFIG; 1809283620Serj } 1810283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); 1811283620Serj 1812283620Serj /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and 1813283620Serj * FDIRDIP4M in cloud mode to allow L3/L3 packets to 1814283620Serj * tunnel. 1815283620Serj */ 1816283620Serj IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); 1817283620Serj IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); 1818283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); 1819283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); 1820283620Serj } 1821283620Serj 1822205720Sjfv /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1823205720Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1824205720Sjfv 1825283620Serj if (!cloud_mode) { 1826283620Serj /* store the TCP/UDP port masks, bit reversed from port 1827283620Serj * layout */ 1828283620Serj fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1829215911Sjfv 1830283620Serj /* write both the same so that UDP and TCP use the same mask */ 1831283620Serj IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1832283620Serj IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1833283620Serj /* also use it for SCTP */ 1834283620Serj switch (hw->mac.type) { 1835283620Serj case ixgbe_mac_X550: 1836283620Serj case ixgbe_mac_X550EM_x: 1837283620Serj IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1838283620Serj break; 1839283620Serj default: 1840283620Serj break; 1841283620Serj } 1842215911Sjfv 1843283620Serj /* store source and destination IP masks (big-enian) */ 1844283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1845283620Serj ~input_mask->formatted.src_ip[0]); 1846283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1847283620Serj ~input_mask->formatted.dst_ip[0]); 1848283620Serj } 1849230775Sjfv return IXGBE_SUCCESS; 1850230775Sjfv} 1851215911Sjfv 1852230775Sjfvs32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1853230775Sjfv union ixgbe_atr_input *input, 1854283620Serj u16 soft_id, u8 queue, bool cloud_mode) 1855230775Sjfv{ 1856230775Sjfv u32 fdirport, fdirvlan, fdirhash, fdircmd; 1857283620Serj u32 addr_low, addr_high; 1858283620Serj u32 cloud_type = 0; 1859283620Serj s32 err; 1860215911Sjfv 1861230775Sjfv DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599"); 1862283620Serj if (!cloud_mode) { 1863283620Serj /* currently IPv6 is not supported, must be programmed with 0 */ 1864283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1865283620Serj input->formatted.src_ip[0]); 1866283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1867283620Serj input->formatted.src_ip[1]); 1868283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1869283620Serj input->formatted.src_ip[2]); 1870230775Sjfv 1871283620Serj /* record the source address (big-endian) */ 1872283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, 1873283620Serj input->formatted.src_ip[0]); 1874230775Sjfv 1875283620Serj /* record the first 32 bits of the destination address 1876283620Serj * (big-endian) */ 1877283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, 1878283620Serj input->formatted.dst_ip[0]); 1879230775Sjfv 1880283620Serj /* record source and destination port (little-endian)*/ 1881283620Serj fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1882283620Serj fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1883283620Serj fdirport |= IXGBE_NTOHS(input->formatted.src_port); 1884283620Serj IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1885283620Serj } 1886230775Sjfv 1887283620Serj /* record VLAN (little-endian) and flex_bytes(big-endian) */ 1888230775Sjfv fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1889230775Sjfv fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1890230775Sjfv fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1891230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1892215911Sjfv 1893283620Serj if (cloud_mode) { 1894283620Serj if (input->formatted.tunnel_type != 0) 1895283620Serj cloud_type = 0x80000000; 1896283620Serj 1897283620Serj addr_low = ((u32)input->formatted.inner_mac[0] | 1898283620Serj ((u32)input->formatted.inner_mac[1] << 8) | 1899283620Serj ((u32)input->formatted.inner_mac[2] << 16) | 1900283620Serj ((u32)input->formatted.inner_mac[3] << 24)); 1901283620Serj addr_high = ((u32)input->formatted.inner_mac[4] | 1902283620Serj ((u32)input->formatted.inner_mac[5] << 8)); 1903283620Serj cloud_type |= addr_high; 1904283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); 1905283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); 1906283620Serj IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); 1907283620Serj } 1908283620Serj 1909230775Sjfv /* configure FDIRHASH register */ 1910230775Sjfv fdirhash = input->formatted.bkt_hash; 1911230775Sjfv fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1912230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1913215911Sjfv 1914230775Sjfv /* 1915230775Sjfv * flush all previous writes to make certain registers are 1916230775Sjfv * programmed prior to issuing the command 1917230775Sjfv */ 1918230775Sjfv IXGBE_WRITE_FLUSH(hw); 1919230775Sjfv 1920217593Sjfv /* configure FDIRCMD register */ 1921217593Sjfv fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1922217593Sjfv IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1923230775Sjfv if (queue == IXGBE_FDIR_DROP_QUEUE) 1924230775Sjfv fdircmd |= IXGBE_FDIRCMD_DROP; 1925283620Serj if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) 1926283620Serj fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1927217593Sjfv fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1928217593Sjfv fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1929230775Sjfv fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1930215911Sjfv 1931190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1932283620Serj err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1933283620Serj if (err) { 1934283620Serj DEBUGOUT("Flow Director command did not complete!\n"); 1935283620Serj return err; 1936283620Serj } 1937190877Sjfv 1938190877Sjfv return IXGBE_SUCCESS; 1939190877Sjfv} 1940190877Sjfv 1941230775Sjfvs32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1942230775Sjfv union ixgbe_atr_input *input, 1943230775Sjfv u16 soft_id) 1944230775Sjfv{ 1945230775Sjfv u32 fdirhash; 1946283620Serj u32 fdircmd; 1947283620Serj s32 err; 1948230775Sjfv 1949230775Sjfv /* configure FDIRHASH register */ 1950230775Sjfv fdirhash = input->formatted.bkt_hash; 1951230775Sjfv fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1952230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1953230775Sjfv 1954230775Sjfv /* flush hash to HW */ 1955230775Sjfv IXGBE_WRITE_FLUSH(hw); 1956230775Sjfv 1957230775Sjfv /* Query if filter is present */ 1958230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1959230775Sjfv 1960283620Serj err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1961283620Serj if (err) { 1962283620Serj DEBUGOUT("Flow Director command did not complete!\n"); 1963283620Serj return err; 1964230775Sjfv } 1965230775Sjfv 1966230775Sjfv /* if filter exists in hardware then remove it */ 1967230775Sjfv if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1968230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1969230775Sjfv IXGBE_WRITE_FLUSH(hw); 1970230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1971230775Sjfv IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1972230775Sjfv } 1973230775Sjfv 1974283620Serj return IXGBE_SUCCESS; 1975230775Sjfv} 1976230775Sjfv 1977190877Sjfv/** 1978230775Sjfv * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1979230775Sjfv * @hw: pointer to hardware structure 1980230775Sjfv * @input: input bitstream 1981230775Sjfv * @input_mask: mask for the input bitstream 1982230775Sjfv * @soft_id: software index for the filters 1983230775Sjfv * @queue: queue index to direct traffic to 1984230775Sjfv * 1985230775Sjfv * Note that the caller to this function must lock before calling, since the 1986230775Sjfv * hardware writes must be protected from one another. 1987230775Sjfv **/ 1988230775Sjfvs32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1989230775Sjfv union ixgbe_atr_input *input, 1990230775Sjfv union ixgbe_atr_input *input_mask, 1991283620Serj u16 soft_id, u8 queue, bool cloud_mode) 1992230775Sjfv{ 1993230775Sjfv s32 err = IXGBE_ERR_CONFIG; 1994230775Sjfv 1995230775Sjfv DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 1996230775Sjfv 1997230775Sjfv /* 1998230775Sjfv * Check flow_type formatting, and bail out before we touch the hardware 1999230775Sjfv * if there's a configuration issue 2000230775Sjfv */ 2001230775Sjfv switch (input->formatted.flow_type) { 2002230775Sjfv case IXGBE_ATR_FLOW_TYPE_IPV4: 2003283620Serj case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4: 2004230775Sjfv input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; 2005230775Sjfv if (input->formatted.dst_port || input->formatted.src_port) { 2006230775Sjfv DEBUGOUT(" Error on src/dst port\n"); 2007230775Sjfv return IXGBE_ERR_CONFIG; 2008230775Sjfv } 2009230775Sjfv break; 2010230775Sjfv case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2011283620Serj case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4: 2012230775Sjfv if (input->formatted.dst_port || input->formatted.src_port) { 2013230775Sjfv DEBUGOUT(" Error on src/dst port\n"); 2014230775Sjfv return IXGBE_ERR_CONFIG; 2015230775Sjfv } 2016230775Sjfv case IXGBE_ATR_FLOW_TYPE_TCPV4: 2017283620Serj case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4: 2018230775Sjfv case IXGBE_ATR_FLOW_TYPE_UDPV4: 2019283620Serj case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4: 2020230775Sjfv input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2021230775Sjfv IXGBE_ATR_L4TYPE_MASK; 2022230775Sjfv break; 2023230775Sjfv default: 2024230775Sjfv DEBUGOUT(" Error on flow type input\n"); 2025230775Sjfv return err; 2026230775Sjfv } 2027230775Sjfv 2028230775Sjfv /* program input mask into the HW */ 2029283620Serj err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); 2030230775Sjfv if (err) 2031230775Sjfv return err; 2032230775Sjfv 2033230775Sjfv /* apply mask and compute/store hash */ 2034230775Sjfv ixgbe_atr_compute_perfect_hash_82599(input, input_mask); 2035230775Sjfv 2036230775Sjfv /* program filters to filter memory */ 2037230775Sjfv return ixgbe_fdir_write_perfect_filter_82599(hw, input, 2038283620Serj soft_id, queue, cloud_mode); 2039230775Sjfv} 2040230775Sjfv 2041230775Sjfv/** 2042190877Sjfv * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 2043190877Sjfv * @hw: pointer to hardware structure 2044190877Sjfv * @reg: analog register to read 2045190877Sjfv * @val: read value 2046190877Sjfv * 2047190877Sjfv * Performs read operation to Omer analog register specified. 2048190877Sjfv **/ 2049190877Sjfvs32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 2050190877Sjfv{ 2051190877Sjfv u32 core_ctl; 2052190877Sjfv 2053200239Sjfv DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 2054200239Sjfv 2055190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 2056230775Sjfv (reg << 8)); 2057190877Sjfv IXGBE_WRITE_FLUSH(hw); 2058190877Sjfv usec_delay(10); 2059190877Sjfv core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 2060190877Sjfv *val = (u8)core_ctl; 2061190877Sjfv 2062190877Sjfv return IXGBE_SUCCESS; 2063190877Sjfv} 2064190877Sjfv 2065190877Sjfv/** 2066190877Sjfv * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 2067190877Sjfv * @hw: pointer to hardware structure 2068190877Sjfv * @reg: atlas register to write 2069190877Sjfv * @val: value to write 2070190877Sjfv * 2071190877Sjfv * Performs write operation to Omer analog register specified. 2072190877Sjfv **/ 2073190877Sjfvs32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 2074190877Sjfv{ 2075190877Sjfv u32 core_ctl; 2076190877Sjfv 2077200239Sjfv DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 2078200239Sjfv 2079190877Sjfv core_ctl = (reg << 8) | val; 2080190877Sjfv IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 2081190877Sjfv IXGBE_WRITE_FLUSH(hw); 2082190877Sjfv usec_delay(10); 2083190877Sjfv 2084190877Sjfv return IXGBE_SUCCESS; 2085190877Sjfv} 2086190877Sjfv 2087190877Sjfv/** 2088230775Sjfv * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 2089190877Sjfv * @hw: pointer to hardware structure 2090190877Sjfv * 2091215911Sjfv * Starts the hardware using the generic start_hw function 2092215911Sjfv * and the generation start_hw function. 2093215911Sjfv * Then performs revision-specific operations, if any. 2094190877Sjfv **/ 2095230775Sjfvs32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 2096190877Sjfv{ 2097190877Sjfv s32 ret_val = IXGBE_SUCCESS; 2098190877Sjfv 2099230775Sjfv DEBUGFUNC("ixgbe_start_hw_82599"); 2100200239Sjfv 2101190877Sjfv ret_val = ixgbe_start_hw_generic(hw); 2102215911Sjfv if (ret_val != IXGBE_SUCCESS) 2103215911Sjfv goto out; 2104190877Sjfv 2105215911Sjfv ret_val = ixgbe_start_hw_gen2(hw); 2106215911Sjfv if (ret_val != IXGBE_SUCCESS) 2107215911Sjfv goto out; 2108190877Sjfv 2109194875Sjfv /* We need to run link autotry after the driver loads */ 2110194875Sjfv hw->mac.autotry_restart = TRUE; 2111194875Sjfv 2112194875Sjfv if (ret_val == IXGBE_SUCCESS) 2113194875Sjfv ret_val = ixgbe_verify_fw_version_82599(hw); 2114215911Sjfvout: 2115190877Sjfv return ret_val; 2116190877Sjfv} 2117190877Sjfv 2118190877Sjfv/** 2119190877Sjfv * ixgbe_identify_phy_82599 - Get physical layer module 2120190877Sjfv * @hw: pointer to hardware structure 2121190877Sjfv * 2122190877Sjfv * Determines the physical layer module found on the current adapter. 2123190877Sjfv * If PHY already detected, maintains current PHY type in hw struct, 2124190877Sjfv * otherwise executes the PHY detection routine. 2125190877Sjfv **/ 2126190877Sjfvs32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 2127190877Sjfv{ 2128283620Serj s32 status; 2129190877Sjfv 2130200239Sjfv DEBUGFUNC("ixgbe_identify_phy_82599"); 2131200239Sjfv 2132190877Sjfv /* Detect PHY if not unknown - returns success if already detected. */ 2133190877Sjfv status = ixgbe_identify_phy_generic(hw); 2134215911Sjfv if (status != IXGBE_SUCCESS) { 2135215911Sjfv /* 82599 10GBASE-T requires an external PHY */ 2136215911Sjfv if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 2137283620Serj return status; 2138215911Sjfv else 2139230775Sjfv status = ixgbe_identify_module_generic(hw); 2140215911Sjfv } 2141215911Sjfv 2142190877Sjfv /* Set PHY type none if no PHY detected */ 2143190877Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 2144190877Sjfv hw->phy.type = ixgbe_phy_none; 2145283620Serj return IXGBE_SUCCESS; 2146190877Sjfv } 2147190877Sjfv 2148190877Sjfv /* Return error if SFP module has been detected but is not supported */ 2149190877Sjfv if (hw->phy.type == ixgbe_phy_sfp_unsupported) 2150283620Serj return IXGBE_ERR_SFP_NOT_SUPPORTED; 2151190877Sjfv 2152190877Sjfv return status; 2153190877Sjfv} 2154190877Sjfv 2155190877Sjfv/** 2156190877Sjfv * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 2157190877Sjfv * @hw: pointer to hardware structure 2158190877Sjfv * 2159190877Sjfv * Determines physical layer capabilities of the current configuration. 2160190877Sjfv **/ 2161190877Sjfvu32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 2162190877Sjfv{ 2163190877Sjfv u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2164190877Sjfv u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2165190877Sjfv u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2166190877Sjfv u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 2167190877Sjfv u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 2168190877Sjfv u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 2169190877Sjfv u16 ext_ability = 0; 2170190877Sjfv 2171200239Sjfv DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 2172200239Sjfv 2173190877Sjfv hw->phy.ops.identify(hw); 2174190877Sjfv 2175215911Sjfv switch (hw->phy.type) { 2176215911Sjfv case ixgbe_phy_tn: 2177215911Sjfv case ixgbe_phy_cu_unknown: 2178190877Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2179190877Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 2180190877Sjfv if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2181190877Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2182190877Sjfv if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2183190877Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2184190877Sjfv if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 2185190877Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 2186190877Sjfv goto out; 2187215911Sjfv default: 2188215911Sjfv break; 2189190877Sjfv } 2190190877Sjfv 2191190877Sjfv switch (autoc & IXGBE_AUTOC_LMS_MASK) { 2192190877Sjfv case IXGBE_AUTOC_LMS_1G_AN: 2193190877Sjfv case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 2194190877Sjfv if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 2195190877Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 2196190877Sjfv IXGBE_PHYSICAL_LAYER_1000BASE_BX; 2197190877Sjfv goto out; 2198190877Sjfv } else 2199190877Sjfv /* SFI mode so read SFP module */ 2200190877Sjfv goto sfp_check; 2201190877Sjfv break; 2202190877Sjfv case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 2203190877Sjfv if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 2204190877Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 2205190877Sjfv else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 2206190877Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2207194875Sjfv else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 2208194875Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 2209190877Sjfv goto out; 2210190877Sjfv break; 2211190877Sjfv case IXGBE_AUTOC_LMS_10G_SERIAL: 2212190877Sjfv if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 2213190877Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2214190877Sjfv goto out; 2215190877Sjfv } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 2216190877Sjfv goto sfp_check; 2217190877Sjfv break; 2218190877Sjfv case IXGBE_AUTOC_LMS_KX4_KX_KR: 2219190877Sjfv case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 2220190877Sjfv if (autoc & IXGBE_AUTOC_KX_SUPP) 2221190877Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2222190877Sjfv if (autoc & IXGBE_AUTOC_KX4_SUPP) 2223190877Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2224190877Sjfv if (autoc & IXGBE_AUTOC_KR_SUPP) 2225190877Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 2226190877Sjfv goto out; 2227190877Sjfv break; 2228190877Sjfv default: 2229190877Sjfv goto out; 2230190877Sjfv break; 2231190877Sjfv } 2232190877Sjfv 2233190877Sjfvsfp_check: 2234190877Sjfv /* SFP check must be done last since DA modules are sometimes used to 2235190877Sjfv * test KR mode - we need to id KR mode correctly before SFP module. 2236190877Sjfv * Call identify_sfp because the pluggable module may have changed */ 2237283620Serj physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2238190877Sjfvout: 2239190877Sjfv return physical_layer; 2240190877Sjfv} 2241190877Sjfv 2242190877Sjfv/** 2243190877Sjfv * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2244190877Sjfv * @hw: pointer to hardware structure 2245190877Sjfv * @regval: register value to write to RXCTRL 2246190877Sjfv * 2247190877Sjfv * Enables the Rx DMA unit for 82599 2248190877Sjfv **/ 2249190877Sjfvs32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2250190877Sjfv{ 2251190877Sjfv 2252200239Sjfv DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2253200239Sjfv 2254190877Sjfv /* 2255190877Sjfv * Workaround for 82599 silicon errata when enabling the Rx datapath. 2256190877Sjfv * If traffic is incoming before we enable the Rx unit, it could hang 2257190877Sjfv * the Rx DMA unit. Therefore, make sure the security engine is 2258190877Sjfv * completely disabled prior to enabling the Rx unit. 2259190877Sjfv */ 2260190877Sjfv 2261230775Sjfv hw->mac.ops.disable_sec_rx_path(hw); 2262190877Sjfv 2263283620Serj if (regval & IXGBE_RXCTRL_RXEN) 2264283620Serj ixgbe_enable_rx(hw); 2265283620Serj else 2266283620Serj ixgbe_disable_rx(hw); 2267190877Sjfv 2268230775Sjfv hw->mac.ops.enable_sec_rx_path(hw); 2269230775Sjfv 2270190877Sjfv return IXGBE_SUCCESS; 2271190877Sjfv} 2272190877Sjfv 2273190877Sjfv/** 2274283620Serj * ixgbe_verify_fw_version_82599 - verify FW version for 82599 2275194875Sjfv * @hw: pointer to hardware structure 2276194875Sjfv * 2277194875Sjfv * Verifies that installed the firmware version is 0.6 or higher 2278194875Sjfv * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2279194875Sjfv * 2280194875Sjfv * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2281194875Sjfv * if the FW version is not supported. 2282194875Sjfv **/ 2283251964Sjfvstatic s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2284194875Sjfv{ 2285194875Sjfv s32 status = IXGBE_ERR_EEPROM_VERSION; 2286194875Sjfv u16 fw_offset, fw_ptp_cfg_offset; 2287251964Sjfv u16 fw_version; 2288194875Sjfv 2289200239Sjfv DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2290200239Sjfv 2291194875Sjfv /* firmware check is only necessary for SFI devices */ 2292194875Sjfv if (hw->phy.media_type != ixgbe_media_type_fiber) { 2293194875Sjfv status = IXGBE_SUCCESS; 2294194875Sjfv goto fw_version_out; 2295194875Sjfv } 2296194875Sjfv 2297194875Sjfv /* get the offset to the Firmware Module block */ 2298251964Sjfv if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 2299251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2300251964Sjfv "eeprom read at offset %d failed", IXGBE_FW_PTR); 2301251964Sjfv return IXGBE_ERR_EEPROM_VERSION; 2302251964Sjfv } 2303194875Sjfv 2304194875Sjfv if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2305194875Sjfv goto fw_version_out; 2306194875Sjfv 2307194875Sjfv /* get the offset to the Pass Through Patch Configuration block */ 2308251964Sjfv if (hw->eeprom.ops.read(hw, (fw_offset + 2309230775Sjfv IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2310251964Sjfv &fw_ptp_cfg_offset)) { 2311251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2312251964Sjfv "eeprom read at offset %d failed", 2313251964Sjfv fw_offset + 2314251964Sjfv IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 2315251964Sjfv return IXGBE_ERR_EEPROM_VERSION; 2316251964Sjfv } 2317194875Sjfv 2318194875Sjfv if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2319194875Sjfv goto fw_version_out; 2320194875Sjfv 2321194875Sjfv /* get the firmware version */ 2322251964Sjfv if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2323251964Sjfv IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 2324251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2325251964Sjfv "eeprom read at offset %d failed", 2326251964Sjfv fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 2327251964Sjfv return IXGBE_ERR_EEPROM_VERSION; 2328251964Sjfv } 2329194875Sjfv 2330194875Sjfv if (fw_version > 0x5) 2331194875Sjfv status = IXGBE_SUCCESS; 2332194875Sjfv 2333194875Sjfvfw_version_out: 2334194875Sjfv return status; 2335194875Sjfv} 2336217593Sjfv 2337205720Sjfv/** 2338217593Sjfv * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2339205720Sjfv * @hw: pointer to hardware structure 2340205720Sjfv * 2341217593Sjfv * Returns TRUE if the LESM FW module is present and enabled. Otherwise 2342217593Sjfv * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 2343205720Sjfv **/ 2344217593Sjfvbool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2345205720Sjfv{ 2346217593Sjfv bool lesm_enabled = FALSE; 2347217593Sjfv u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2348217593Sjfv s32 status; 2349205720Sjfv 2350217593Sjfv DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2351205720Sjfv 2352217593Sjfv /* get the offset to the Firmware Module block */ 2353217593Sjfv status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2354205720Sjfv 2355217593Sjfv if ((status != IXGBE_SUCCESS) || 2356217593Sjfv (fw_offset == 0) || (fw_offset == 0xFFFF)) 2357217593Sjfv goto out; 2358205720Sjfv 2359217593Sjfv /* get the offset to the LESM Parameters block */ 2360217593Sjfv status = hw->eeprom.ops.read(hw, (fw_offset + 2361230775Sjfv IXGBE_FW_LESM_PARAMETERS_PTR), 2362230775Sjfv &fw_lesm_param_offset); 2363217593Sjfv 2364217593Sjfv if ((status != IXGBE_SUCCESS) || 2365217593Sjfv (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2366217593Sjfv goto out; 2367217593Sjfv 2368283620Serj /* get the LESM state word */ 2369217593Sjfv status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2370230775Sjfv IXGBE_FW_LESM_STATE_1), 2371230775Sjfv &fw_lesm_state); 2372217593Sjfv 2373217593Sjfv if ((status == IXGBE_SUCCESS) && 2374217593Sjfv (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2375217593Sjfv lesm_enabled = TRUE; 2376217593Sjfv 2377217593Sjfvout: 2378217593Sjfv return lesm_enabled; 2379205720Sjfv} 2380217593Sjfv 2381230775Sjfv/** 2382230775Sjfv * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2383230775Sjfv * fastest available method 2384230775Sjfv * 2385230775Sjfv * @hw: pointer to hardware structure 2386230775Sjfv * @offset: offset of word in EEPROM to read 2387230775Sjfv * @words: number of words 2388230775Sjfv * @data: word(s) read from the EEPROM 2389230775Sjfv * 2390230775Sjfv * Retrieves 16 bit word(s) read from EEPROM 2391230775Sjfv **/ 2392230775Sjfvstatic s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2393230775Sjfv u16 words, u16 *data) 2394230775Sjfv{ 2395230775Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2396230775Sjfv s32 ret_val = IXGBE_ERR_CONFIG; 2397217593Sjfv 2398230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_buffer_82599"); 2399230775Sjfv 2400230775Sjfv /* 2401230775Sjfv * If EEPROM is detected and can be addressed using 14 bits, 2402230775Sjfv * use EERD otherwise use bit bang 2403230775Sjfv */ 2404230775Sjfv if ((eeprom->type == ixgbe_eeprom_spi) && 2405230775Sjfv (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2406230775Sjfv ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2407230775Sjfv data); 2408230775Sjfv else 2409230775Sjfv ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2410230775Sjfv words, 2411230775Sjfv data); 2412230775Sjfv 2413230775Sjfv return ret_val; 2414230775Sjfv} 2415230775Sjfv 2416230775Sjfv/** 2417230775Sjfv * ixgbe_read_eeprom_82599 - Read EEPROM word using 2418230775Sjfv * fastest available method 2419230775Sjfv * 2420230775Sjfv * @hw: pointer to hardware structure 2421230775Sjfv * @offset: offset of word in the EEPROM to read 2422230775Sjfv * @data: word read from the EEPROM 2423230775Sjfv * 2424230775Sjfv * Reads a 16 bit word from the EEPROM 2425230775Sjfv **/ 2426230775Sjfvstatic s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2427230775Sjfv u16 offset, u16 *data) 2428230775Sjfv{ 2429230775Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2430230775Sjfv s32 ret_val = IXGBE_ERR_CONFIG; 2431230775Sjfv 2432230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_82599"); 2433230775Sjfv 2434230775Sjfv /* 2435230775Sjfv * If EEPROM is detected and can be addressed using 14 bits, 2436230775Sjfv * use EERD otherwise use bit bang 2437230775Sjfv */ 2438230775Sjfv if ((eeprom->type == ixgbe_eeprom_spi) && 2439230775Sjfv (offset <= IXGBE_EERD_MAX_ADDR)) 2440230775Sjfv ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2441230775Sjfv else 2442230775Sjfv ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2443230775Sjfv 2444230775Sjfv return ret_val; 2445230775Sjfv} 2446230775Sjfv 2447247822Sjfv/** 2448247822Sjfv * ixgbe_reset_pipeline_82599 - perform pipeline reset 2449247822Sjfv * 2450247822Sjfv * @hw: pointer to hardware structure 2451247822Sjfv * 2452247822Sjfv * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2453283620Serj * full pipeline reset. This function assumes the SW/FW lock is held. 2454247822Sjfv **/ 2455247822Sjfvs32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2456247822Sjfv{ 2457247822Sjfv s32 ret_val; 2458247822Sjfv u32 anlp1_reg = 0; 2459247822Sjfv u32 i, autoc_reg, autoc2_reg; 2460238149Sjfv 2461247822Sjfv /* Enable link if disabled in NVM */ 2462247822Sjfv autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2463247822Sjfv if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2464247822Sjfv autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2465247822Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2466247822Sjfv IXGBE_WRITE_FLUSH(hw); 2467247822Sjfv } 2468247822Sjfv 2469283620Serj autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2470247822Sjfv autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2471247822Sjfv /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2472283620Serj IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2473283620Serj autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2474247822Sjfv /* Wait for AN to leave state 0 */ 2475247822Sjfv for (i = 0; i < 10; i++) { 2476247822Sjfv msec_delay(4); 2477247822Sjfv anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2478247822Sjfv if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2479247822Sjfv break; 2480247822Sjfv } 2481247822Sjfv 2482247822Sjfv if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2483247822Sjfv DEBUGOUT("auto negotiation not completed\n"); 2484247822Sjfv ret_val = IXGBE_ERR_RESET_FAILED; 2485247822Sjfv goto reset_pipeline_out; 2486247822Sjfv } 2487247822Sjfv 2488247822Sjfv ret_val = IXGBE_SUCCESS; 2489247822Sjfv 2490247822Sjfvreset_pipeline_out: 2491247822Sjfv /* Write AUTOC register with original LMS field and Restart_AN */ 2492247822Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2493247822Sjfv IXGBE_WRITE_FLUSH(hw); 2494247822Sjfv 2495247822Sjfv return ret_val; 2496247822Sjfv} 2497247822Sjfv 2498283620Serj/** 2499283620Serj * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2500283620Serj * @hw: pointer to hardware structure 2501283620Serj * @byte_offset: byte offset to read 2502283620Serj * @data: value read 2503283620Serj * 2504283620Serj * Performs byte read operation to SFP module's EEPROM over I2C interface at 2505283620Serj * a specified device address. 2506283620Serj **/ 2507283620Serjstatic s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2508283620Serj u8 dev_addr, u8 *data) 2509283620Serj{ 2510283620Serj u32 esdp; 2511283620Serj s32 status; 2512283620Serj s32 timeout = 200; 2513247822Sjfv 2514283620Serj DEBUGFUNC("ixgbe_read_i2c_byte_82599"); 2515247822Sjfv 2516283620Serj if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2517283620Serj /* Acquire I2C bus ownership. */ 2518283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2519283620Serj esdp |= IXGBE_ESDP_SDP0; 2520283620Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2521283620Serj IXGBE_WRITE_FLUSH(hw); 2522283620Serj 2523283620Serj while (timeout) { 2524283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2525283620Serj if (esdp & IXGBE_ESDP_SDP1) 2526283620Serj break; 2527283620Serj 2528283620Serj msec_delay(5); 2529283620Serj timeout--; 2530283620Serj } 2531283620Serj 2532283620Serj if (!timeout) { 2533283620Serj DEBUGOUT("Driver can't access resource," 2534283620Serj " acquiring I2C bus timeout.\n"); 2535283620Serj status = IXGBE_ERR_I2C; 2536283620Serj goto release_i2c_access; 2537283620Serj } 2538283620Serj } 2539283620Serj 2540283620Serj status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2541283620Serj 2542283620Serjrelease_i2c_access: 2543283620Serj 2544283620Serj if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2545283620Serj /* Release I2C bus ownership. */ 2546283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2547283620Serj esdp &= ~IXGBE_ESDP_SDP0; 2548283620Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2549283620Serj IXGBE_WRITE_FLUSH(hw); 2550283620Serj } 2551283620Serj 2552283620Serj return status; 2553283620Serj} 2554283620Serj 2555283620Serj/** 2556283620Serj * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2557283620Serj * @hw: pointer to hardware structure 2558283620Serj * @byte_offset: byte offset to write 2559283620Serj * @data: value to write 2560283620Serj * 2561283620Serj * Performs byte write operation to SFP module's EEPROM over I2C interface at 2562283620Serj * a specified device address. 2563283620Serj **/ 2564283620Serjstatic s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2565283620Serj u8 dev_addr, u8 data) 2566283620Serj{ 2567283620Serj u32 esdp; 2568283620Serj s32 status; 2569283620Serj s32 timeout = 200; 2570283620Serj 2571283620Serj DEBUGFUNC("ixgbe_write_i2c_byte_82599"); 2572283620Serj 2573283620Serj if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2574283620Serj /* Acquire I2C bus ownership. */ 2575283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2576283620Serj esdp |= IXGBE_ESDP_SDP0; 2577283620Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2578283620Serj IXGBE_WRITE_FLUSH(hw); 2579283620Serj 2580283620Serj while (timeout) { 2581283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2582283620Serj if (esdp & IXGBE_ESDP_SDP1) 2583283620Serj break; 2584283620Serj 2585283620Serj msec_delay(5); 2586283620Serj timeout--; 2587283620Serj } 2588283620Serj 2589283620Serj if (!timeout) { 2590283620Serj DEBUGOUT("Driver can't access resource," 2591283620Serj " acquiring I2C bus timeout.\n"); 2592283620Serj status = IXGBE_ERR_I2C; 2593283620Serj goto release_i2c_access; 2594283620Serj } 2595283620Serj } 2596283620Serj 2597283620Serj status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2598283620Serj 2599283620Serjrelease_i2c_access: 2600283620Serj 2601283620Serj if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 2602283620Serj /* Release I2C bus ownership. */ 2603283620Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2604283620Serj esdp &= ~IXGBE_ESDP_SDP0; 2605283620Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2606283620Serj IXGBE_WRITE_FLUSH(hw); 2607283620Serj } 2608283620Serj 2609283620Serj return status; 2610283620Serj} 2611