ixgbe_82598.c revision 200239
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 200239 2009-12-07 21:30:54Z jfv $*/ 34 35#include "ixgbe_type.h" 36#include "ixgbe_api.h" 37#include "ixgbe_common.h" 38#include "ixgbe_phy.h" 39 40u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); 41s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); 42static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 43 ixgbe_link_speed *speed, 44 bool *autoneg); 45static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 46s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num); 47static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 48 bool autoneg_wait_to_complete); 49static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 50 ixgbe_link_speed *speed, bool *link_up, 51 bool link_up_wait_to_complete); 52static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 53 ixgbe_link_speed speed, 54 bool autoneg, 55 bool autoneg_wait_to_complete); 56static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg, 59 bool autoneg_wait_to_complete); 60static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 61s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw); 62s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 63static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 64s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, 65 u32 vind, bool vlan_on); 66static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 67s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val); 68s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val); 69s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 70 u8 *eeprom_data); 71u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); 72s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); 73void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); 74void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw); 75static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw); 76 77/** 78 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 79 * @hw: pointer to the HW structure 80 * 81 * The defaults for 82598 should be in the range of 50us to 50ms, 82 * however the hardware default for these parts is 500us to 1ms which is less 83 * than the 10ms recommended by the pci-e spec. To address this we need to 84 * increase the value to either 10ms to 250ms for capability version 1 config, 85 * or 16ms to 55ms for version 2. 86 **/ 87void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 88{ 89 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 90 u16 pcie_devctl2; 91 92 /* only take action if timeout value is defaulted to 0 */ 93 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 94 goto out; 95 96 /* 97 * if capababilities version is type 1 we can write the 98 * timeout of 10ms to 250ms through the GCR register 99 */ 100 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 101 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 102 goto out; 103 } 104 105 /* 106 * for version 2 capabilities we need to write the config space 107 * directly in order to set the completion timeout value for 108 * 16ms to 55ms 109 */ 110 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 111 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 112 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 113out: 114 /* disable completion timeout resend */ 115 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 116 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 117} 118 119/** 120 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 121 * @hw: pointer to hardware structure 122 * 123 * Read PCIe configuration space, and get the MSI-X vector count from 124 * the capabilities table. 125 **/ 126u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 127{ 128 u32 msix_count = 18; 129 130 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598"); 131 132 if (hw->mac.msix_vectors_from_pcie) { 133 msix_count = IXGBE_READ_PCIE_WORD(hw, 134 IXGBE_PCIE_MSIX_82598_CAPS); 135 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 136 137 /* MSI-X count is zero-based in HW, so increment to give 138 * proper value */ 139 msix_count++; 140 } 141 return msix_count; 142} 143 144/** 145 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 146 * @hw: pointer to hardware structure 147 * 148 * Initialize the function pointers and assign the MAC type for 82598. 149 * Does not touch the hardware. 150 **/ 151s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 152{ 153 struct ixgbe_mac_info *mac = &hw->mac; 154 struct ixgbe_phy_info *phy = &hw->phy; 155 s32 ret_val; 156 157 DEBUGFUNC("ixgbe_init_ops_82598"); 158 159 ret_val = ixgbe_init_phy_ops_generic(hw); 160 ret_val = ixgbe_init_ops_generic(hw); 161 162 /* PHY */ 163 phy->ops.init = &ixgbe_init_phy_ops_82598; 164 165 /* MAC */ 166 mac->ops.start_hw = &ixgbe_start_hw_82598; 167 mac->ops.reset_hw = &ixgbe_reset_hw_82598; 168 mac->ops.get_media_type = &ixgbe_get_media_type_82598; 169 mac->ops.get_supported_physical_layer = 170 &ixgbe_get_supported_physical_layer_82598; 171 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; 172 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; 173 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598; 174 175 /* RAR, Multicast, VLAN */ 176 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598; 177 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598; 178 mac->ops.set_vfta = &ixgbe_set_vfta_82598; 179 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598; 180 181 /* Flow Control */ 182 mac->ops.fc_enable = &ixgbe_fc_enable_82598; 183 184 mac->mcft_size = 128; 185 mac->vft_size = 128; 186 mac->num_rar_entries = 16; 187 mac->max_tx_queues = 32; 188 mac->max_rx_queues = 64; 189 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 190 191 /* SFP+ Module */ 192 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598; 193 194 /* Link */ 195 mac->ops.check_link = &ixgbe_check_mac_link_82598; 196 mac->ops.setup_link = &ixgbe_setup_mac_link_82598; 197 mac->ops.get_link_capabilities = 198 &ixgbe_get_link_capabilities_82598; 199 200 return ret_val; 201} 202 203/** 204 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 205 * @hw: pointer to hardware structure 206 * 207 * Initialize any function pointers that were not able to be 208 * set during init_shared_code because the PHY/SFP type was 209 * not known. Perform the SFP init if necessary. 210 * 211 **/ 212s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 213{ 214 struct ixgbe_mac_info *mac = &hw->mac; 215 struct ixgbe_phy_info *phy = &hw->phy; 216 s32 ret_val = IXGBE_SUCCESS; 217 u16 list_offset, data_offset; 218 219 DEBUGFUNC("ixgbe_init_phy_ops_82598"); 220 221 /* Identify the PHY */ 222 phy->ops.identify(hw); 223 224 /* Overwrite the link function pointers if copper PHY */ 225 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 226 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 227 mac->ops.get_link_capabilities = 228 &ixgbe_get_copper_link_capabilities_generic; 229 } 230 231 switch (hw->phy.type) { 232 case ixgbe_phy_tn: 233 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 234 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 235 phy->ops.get_firmware_version = 236 &ixgbe_get_phy_firmware_version_tnx; 237 break; 238 case ixgbe_phy_aq: 239 phy->ops.get_firmware_version = 240 &ixgbe_get_phy_firmware_version_generic; 241 break; 242 case ixgbe_phy_nl: 243 phy->ops.reset = &ixgbe_reset_phy_nl; 244 245 /* Call SFP+ identify routine to get the SFP+ module type */ 246 ret_val = phy->ops.identify_sfp(hw); 247 if (ret_val != IXGBE_SUCCESS) 248 goto out; 249 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 250 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 251 goto out; 252 } 253 254 /* Check to see if SFP+ module is supported */ 255 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 256 &list_offset, 257 &data_offset); 258 if (ret_val != IXGBE_SUCCESS) { 259 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 260 goto out; 261 } 262 break; 263 default: 264 break; 265 } 266 267out: 268 return ret_val; 269} 270 271/** 272 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 273 * @hw: pointer to hardware structure 274 * 275 * Starts the hardware using the generic start_hw function. 276 * Then set pcie completion timeout 277 **/ 278s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 279{ 280 u32 regval; 281 u32 i; 282 s32 ret_val = IXGBE_SUCCESS; 283 284 DEBUGFUNC("ixgbe_start_hw_82598"); 285 286 ret_val = ixgbe_start_hw_generic(hw); 287 288 /* Disable relaxed ordering */ 289 for (i = 0; ((i < hw->mac.max_tx_queues) && 290 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 291 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 292 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 293 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 294 } 295 296 for (i = 0; ((i < hw->mac.max_rx_queues) && 297 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 298 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 299 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | 300 IXGBE_DCA_RXCTRL_DESC_HSRO_EN); 301 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 302 } 303 304 /* set the completion timeout for interface */ 305 if (ret_val == IXGBE_SUCCESS) 306 ixgbe_set_pcie_completion_timeout(hw); 307 308 return ret_val; 309} 310 311/** 312 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 313 * @hw: pointer to hardware structure 314 * @speed: pointer to link speed 315 * @autoneg: boolean auto-negotiation value 316 * 317 * Determines the link capabilities by reading the AUTOC register. 318 **/ 319static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 320 ixgbe_link_speed *speed, 321 bool *autoneg) 322{ 323 s32 status = IXGBE_SUCCESS; 324 u32 autoc = 0; 325 326 DEBUGFUNC("ixgbe_get_link_capabilities_82598"); 327 328 /* 329 * Determine link capabilities based on the stored value of AUTOC, 330 * which represents EEPROM defaults. If AUTOC value has not been 331 * stored, use the current register value. 332 */ 333 if (hw->mac.orig_link_settings_stored) 334 autoc = hw->mac.orig_autoc; 335 else 336 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 337 338 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 339 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 340 *speed = IXGBE_LINK_SPEED_1GB_FULL; 341 *autoneg = FALSE; 342 break; 343 344 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 345 *speed = IXGBE_LINK_SPEED_10GB_FULL; 346 *autoneg = FALSE; 347 break; 348 349 case IXGBE_AUTOC_LMS_1G_AN: 350 *speed = IXGBE_LINK_SPEED_1GB_FULL; 351 *autoneg = TRUE; 352 break; 353 354 case IXGBE_AUTOC_LMS_KX4_AN: 355 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 356 *speed = IXGBE_LINK_SPEED_UNKNOWN; 357 if (autoc & IXGBE_AUTOC_KX4_SUPP) 358 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 359 if (autoc & IXGBE_AUTOC_KX_SUPP) 360 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 361 *autoneg = TRUE; 362 break; 363 364 default: 365 status = IXGBE_ERR_LINK_SETUP; 366 break; 367 } 368 369 return status; 370} 371 372/** 373 * ixgbe_get_media_type_82598 - Determines media type 374 * @hw: pointer to hardware structure 375 * 376 * Returns the media type (fiber, copper, backplane) 377 **/ 378static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 379{ 380 enum ixgbe_media_type media_type; 381 382 DEBUGFUNC("ixgbe_get_media_type_82598"); 383 384 /* Detect if there is a copper PHY attached. */ 385 if (hw->phy.type == ixgbe_phy_cu_unknown || 386 hw->phy.type == ixgbe_phy_tn || 387 hw->phy.type == ixgbe_phy_aq) { 388 media_type = ixgbe_media_type_copper; 389 goto out; 390 } 391 392 /* Media type for I82598 is based on device ID */ 393 switch (hw->device_id) { 394 case IXGBE_DEV_ID_82598: 395 case IXGBE_DEV_ID_82598_BX: 396 /* Default device ID is mezzanine card KX/KX4 */ 397 media_type = ixgbe_media_type_backplane; 398 break; 399 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 400 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 401 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 402 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 403 case IXGBE_DEV_ID_82598EB_XF_LR: 404 case IXGBE_DEV_ID_82598EB_SFP_LOM: 405 media_type = ixgbe_media_type_fiber; 406 break; 407 case IXGBE_DEV_ID_82598EB_CX4: 408 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 409 media_type = ixgbe_media_type_cx4; 410 break; 411 case IXGBE_DEV_ID_82598AT: 412 case IXGBE_DEV_ID_82598AT2: 413 media_type = ixgbe_media_type_copper; 414 break; 415 default: 416 media_type = ixgbe_media_type_unknown; 417 break; 418 } 419out: 420 return media_type; 421} 422 423/** 424 * ixgbe_fc_enable_82598 - Enable flow control 425 * @hw: pointer to hardware structure 426 * @packetbuf_num: packet buffer number (0-7) 427 * 428 * Enable flow control according to the current settings. 429 **/ 430s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 431{ 432 s32 ret_val = IXGBE_SUCCESS; 433 u32 fctrl_reg; 434 u32 rmcs_reg; 435 u32 reg; 436 u32 link_speed = 0; 437 bool link_up; 438 439 DEBUGFUNC("ixgbe_fc_enable_82598"); 440 441 /* 442 * On 82598 backplane having FC on causes resets while doing 443 * KX, so turn off here. 444 */ 445 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 446 if (link_up && 447 link_speed == IXGBE_LINK_SPEED_1GB_FULL && 448 hw->mac.ops.get_media_type(hw) == ixgbe_media_type_backplane) { 449 hw->fc.disable_fc_autoneg = TRUE; 450 hw->fc.requested_mode = ixgbe_fc_none; 451 } 452 453 /* Negotiate the fc mode to use */ 454 ret_val = ixgbe_fc_autoneg(hw); 455 if (ret_val) 456 goto out; 457 458 /* Disable any previous flow control settings */ 459 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 460 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 461 462 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 463 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 464 465 /* 466 * The possible values of fc.current_mode are: 467 * 0: Flow control is completely disabled 468 * 1: Rx flow control is enabled (we can receive pause frames, 469 * but not send pause frames). 470 * 2: Tx flow control is enabled (we can send pause frames but 471 * we do not support receiving pause frames). 472 * 3: Both Rx and Tx flow control (symmetric) are enabled. 473 * other: Invalid. 474 */ 475 switch (hw->fc.current_mode) { 476 case ixgbe_fc_none: 477 /* Flow control is disabled by software override or autoneg. 478 * The code below will actually disable it in the HW. 479 */ 480 break; 481 case ixgbe_fc_rx_pause: 482 /* 483 * Rx Flow control is enabled and Tx Flow control is 484 * disabled by software override. Since there really 485 * isn't a way to advertise that we are capable of RX 486 * Pause ONLY, we will advertise that we support both 487 * symmetric and asymmetric Rx PAUSE. Later, we will 488 * disable the adapter's ability to send PAUSE frames. 489 */ 490 fctrl_reg |= IXGBE_FCTRL_RFCE; 491 break; 492 case ixgbe_fc_tx_pause: 493 /* 494 * Tx Flow control is enabled, and Rx Flow control is 495 * disabled by software override. 496 */ 497 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 498 break; 499 case ixgbe_fc_full: 500 /* Flow control (both Rx and Tx) is enabled by SW override. */ 501 fctrl_reg |= IXGBE_FCTRL_RFCE; 502 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 503 break; 504 default: 505 DEBUGOUT("Flow control param set incorrectly\n"); 506 ret_val = IXGBE_ERR_CONFIG; 507 goto out; 508 break; 509 } 510 511 /* Set 802.3x based flow control settings. */ 512 fctrl_reg |= IXGBE_FCTRL_DPF; 513 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 514 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 515 516 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 517 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 518 if (hw->fc.send_xon) { 519 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 520 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 521 } else { 522 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 523 hw->fc.low_water); 524 } 525 526 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 527 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 528 } 529 530 /* Configure pause time (2 TCs per register) */ 531 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 532 if ((packetbuf_num & 1) == 0) 533 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 534 else 535 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 536 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 537 538 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 539 540out: 541 return ret_val; 542} 543 544/** 545 * ixgbe_start_mac_link_82598 - Configures MAC link settings 546 * @hw: pointer to hardware structure 547 * 548 * Configures link settings based on values in the ixgbe_hw struct. 549 * Restarts the link. Performs autonegotiation if needed. 550 **/ 551static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 552 bool autoneg_wait_to_complete) 553{ 554 u32 autoc_reg; 555 u32 links_reg; 556 u32 i; 557 s32 status = IXGBE_SUCCESS; 558 559 DEBUGFUNC("ixgbe_start_mac_link_82598"); 560 561 /* Restart link */ 562 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 563 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 564 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 565 566 /* Only poll for autoneg to complete if specified to do so */ 567 if (autoneg_wait_to_complete) { 568 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 569 IXGBE_AUTOC_LMS_KX4_AN || 570 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 571 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 572 links_reg = 0; /* Just in case Autoneg time = 0 */ 573 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 574 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 575 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 576 break; 577 msec_delay(100); 578 } 579 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 580 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 581 DEBUGOUT("Autonegotiation did not complete.\n"); 582 } 583 } 584 } 585 586 /* Add delay to filter out noises during initial link setup */ 587 msec_delay(50); 588 589 return status; 590} 591 592/** 593 * ixgbe_check_mac_link_82598 - Get link/speed status 594 * @hw: pointer to hardware structure 595 * @speed: pointer to link speed 596 * @link_up: TRUE is link is up, FALSE otherwise 597 * @link_up_wait_to_complete: bool used to wait for link up or not 598 * 599 * Reads the links register to determine if link is up and the current speed 600 **/ 601static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 602 ixgbe_link_speed *speed, bool *link_up, 603 bool link_up_wait_to_complete) 604{ 605 u32 links_reg; 606 u32 i; 607 u16 link_reg, adapt_comp_reg; 608 609 DEBUGFUNC("ixgbe_check_mac_link_82598"); 610 611 /* 612 * SERDES PHY requires us to read link status from undocumented 613 * register 0xC79F. Bit 0 set indicates link is up/ready; clear 614 * indicates link down. OxC00C is read to check that the XAUI lanes 615 * are active. Bit 0 clear indicates active; set indicates inactive. 616 */ 617 if (hw->phy.type == ixgbe_phy_nl) { 618 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 619 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 620 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 621 &adapt_comp_reg); 622 if (link_up_wait_to_complete) { 623 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 624 if ((link_reg & 1) && 625 ((adapt_comp_reg & 1) == 0)) { 626 *link_up = TRUE; 627 break; 628 } else { 629 *link_up = FALSE; 630 } 631 msec_delay(100); 632 hw->phy.ops.read_reg(hw, 0xC79F, 633 IXGBE_TWINAX_DEV, 634 &link_reg); 635 hw->phy.ops.read_reg(hw, 0xC00C, 636 IXGBE_TWINAX_DEV, 637 &adapt_comp_reg); 638 } 639 } else { 640 if ((link_reg & 1) && 641 ((adapt_comp_reg & 1) == 0)) 642 *link_up = TRUE; 643 else 644 *link_up = FALSE; 645 } 646 647 if (*link_up == FALSE) 648 goto out; 649 } 650 651 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 652 if (link_up_wait_to_complete) { 653 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 654 if (links_reg & IXGBE_LINKS_UP) { 655 *link_up = TRUE; 656 break; 657 } else { 658 *link_up = FALSE; 659 } 660 msec_delay(100); 661 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 662 } 663 } else { 664 if (links_reg & IXGBE_LINKS_UP) 665 *link_up = TRUE; 666 else 667 *link_up = FALSE; 668 } 669 670 if (links_reg & IXGBE_LINKS_SPEED) 671 *speed = IXGBE_LINK_SPEED_10GB_FULL; 672 else 673 *speed = IXGBE_LINK_SPEED_1GB_FULL; 674 675 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) && 676 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS)) 677 *link_up = FALSE; 678 679 /* if link is down, zero out the current_mode */ 680 if (*link_up == FALSE) { 681 hw->fc.current_mode = ixgbe_fc_none; 682 hw->fc.fc_was_autonegged = FALSE; 683 } 684 685out: 686 return IXGBE_SUCCESS; 687} 688 689/** 690 * ixgbe_setup_mac_link_82598 - Set MAC link speed 691 * @hw: pointer to hardware structure 692 * @speed: new link speed 693 * @autoneg: TRUE if autonegotiation enabled 694 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 695 * 696 * Set the link speed in the AUTOC register and restarts link. 697 **/ 698static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 699 ixgbe_link_speed speed, bool autoneg, 700 bool autoneg_wait_to_complete) 701{ 702 s32 status = IXGBE_SUCCESS; 703 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 704 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 705 u32 autoc = curr_autoc; 706 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 707 708 DEBUGFUNC("ixgbe_setup_mac_link_82598"); 709 710 /* Check to see if speed passed in is supported. */ 711 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 712 speed &= link_capabilities; 713 714 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 715 status = IXGBE_ERR_LINK_SETUP; 716 717 /* Set KX4/KX support according to speed requested */ 718 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 719 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 720 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 721 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 722 autoc |= IXGBE_AUTOC_KX4_SUPP; 723 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 724 autoc |= IXGBE_AUTOC_KX_SUPP; 725 if (autoc != curr_autoc) 726 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 727 } 728 729 if (status == IXGBE_SUCCESS) { 730 /* 731 * Setup and restart the link based on the new values in 732 * ixgbe_hw This will write the AUTOC register based on the new 733 * stored values 734 */ 735 status = ixgbe_start_mac_link_82598(hw, 736 autoneg_wait_to_complete); 737 } 738 739 return status; 740} 741 742 743/** 744 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 745 * @hw: pointer to hardware structure 746 * @speed: new link speed 747 * @autoneg: TRUE if autonegotiation enabled 748 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 749 * 750 * Sets the link speed in the AUTOC register in the MAC and restarts link. 751 **/ 752static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 753 ixgbe_link_speed speed, 754 bool autoneg, 755 bool autoneg_wait_to_complete) 756{ 757 s32 status; 758 759 DEBUGFUNC("ixgbe_setup_copper_link_82598"); 760 761 /* Setup the PHY according to input speed */ 762 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 763 autoneg_wait_to_complete); 764 /* Set up MAC */ 765 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 766 767 return status; 768} 769 770/** 771 * ixgbe_reset_hw_82598 - Performs hardware reset 772 * @hw: pointer to hardware structure 773 * 774 * Resets the hardware by resetting the transmit and receive units, masks and 775 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 776 * reset. 777 **/ 778static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 779{ 780 s32 status = IXGBE_SUCCESS; 781 s32 phy_status = IXGBE_SUCCESS; 782 u32 ctrl; 783 u32 gheccr; 784 u32 i; 785 u32 autoc; 786 u8 analog_val; 787 788 DEBUGFUNC("ixgbe_reset_hw_82598"); 789 790 /* Call adapter stop to disable tx/rx and clear interrupts */ 791 hw->mac.ops.stop_adapter(hw); 792 793 /* 794 * Power up the Atlas Tx lanes if they are currently powered down. 795 * Atlas Tx lanes are powered down for MAC loopback tests, but 796 * they are not automatically restored on reset. 797 */ 798 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 799 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 800 /* Enable Tx Atlas so packets can be transmitted again */ 801 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 802 &analog_val); 803 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 804 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 805 analog_val); 806 807 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 808 &analog_val); 809 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 810 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 811 analog_val); 812 813 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 814 &analog_val); 815 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 816 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 817 analog_val); 818 819 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 820 &analog_val); 821 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 822 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 823 analog_val); 824 } 825 826 /* Reset PHY */ 827 if (hw->phy.reset_disable == FALSE) { 828 /* PHY ops must be identified and initialized prior to reset */ 829 830 /* Init PHY and function pointers, perform SFP setup */ 831 phy_status = hw->phy.ops.init(hw); 832 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 833 goto reset_hw_out; 834 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 835 goto no_phy_reset; 836 837 hw->phy.ops.reset(hw); 838 } 839 840no_phy_reset: 841 /* 842 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 843 * access and verify no pending requests before reset 844 */ 845 status = ixgbe_disable_pcie_master(hw); 846 if (status != IXGBE_SUCCESS) { 847 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 848 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 849 } 850 851 /* 852 * Issue global reset to the MAC. This needs to be a SW reset. 853 * If link reset is used, it might reset the MAC when mng is using it 854 */ 855 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 856 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 857 IXGBE_WRITE_FLUSH(hw); 858 859 /* Poll for reset bit to self-clear indicating reset is complete */ 860 for (i = 0; i < 10; i++) { 861 usec_delay(1); 862 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 863 if (!(ctrl & IXGBE_CTRL_RST)) 864 break; 865 } 866 if (ctrl & IXGBE_CTRL_RST) { 867 status = IXGBE_ERR_RESET_FAILED; 868 DEBUGOUT("Reset polling failed to complete.\n"); 869 } 870 871 msec_delay(50); 872 873 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 874 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 875 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 876 877 /* 878 * Store the original AUTOC value if it has not been 879 * stored off yet. Otherwise restore the stored original 880 * AUTOC value since the reset operation sets back to deaults. 881 */ 882 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 883 if (hw->mac.orig_link_settings_stored == FALSE) { 884 hw->mac.orig_autoc = autoc; 885 hw->mac.orig_link_settings_stored = TRUE; 886 } else if (autoc != hw->mac.orig_autoc) 887 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 888 889 /* Store the permanent mac address */ 890 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 891 892 /* 893 * Store MAC address from RAR0, clear receive address registers, and 894 * clear the multicast table 895 */ 896 hw->mac.ops.init_rx_addrs(hw); 897 898 899 900reset_hw_out: 901 if (phy_status != IXGBE_SUCCESS) 902 status = phy_status; 903 return status; 904} 905 906/** 907 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 908 * @hw: pointer to hardware struct 909 * @rar: receive address register index to associate with a VMDq index 910 * @vmdq: VMDq set index 911 **/ 912s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 913{ 914 u32 rar_high; 915 916 DEBUGFUNC("ixgbe_set_vmdq_82598"); 917 918 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 919 rar_high &= ~IXGBE_RAH_VIND_MASK; 920 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 921 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 922 return IXGBE_SUCCESS; 923} 924 925/** 926 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 927 * @hw: pointer to hardware struct 928 * @rar: receive address register index to associate with a VMDq index 929 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 930 **/ 931static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 932{ 933 u32 rar_high; 934 u32 rar_entries = hw->mac.num_rar_entries; 935 936 UNREFERENCED_PARAMETER(vmdq); 937 938 if (rar < rar_entries) { 939 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 940 if (rar_high & IXGBE_RAH_VIND_MASK) { 941 rar_high &= ~IXGBE_RAH_VIND_MASK; 942 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 943 } 944 } else { 945 DEBUGOUT1("RAR index %d is out of range.\n", rar); 946 } 947 948 return IXGBE_SUCCESS; 949} 950 951/** 952 * ixgbe_set_vfta_82598 - Set VLAN filter table 953 * @hw: pointer to hardware structure 954 * @vlan: VLAN id to write to VLAN filter 955 * @vind: VMDq output index that maps queue to VLAN id in VFTA 956 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 957 * 958 * Turn on/off specified VLAN in the VLAN filter table. 959 **/ 960s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 961 bool vlan_on) 962{ 963 u32 regindex; 964 u32 bitindex; 965 u32 bits; 966 u32 vftabyte; 967 968 DEBUGFUNC("ixgbe_set_vfta_82598"); 969 970 if (vlan > 4095) 971 return IXGBE_ERR_PARAM; 972 973 /* Determine 32-bit word position in array */ 974 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 975 976 /* Determine the location of the (VMD) queue index */ 977 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 978 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 979 980 /* Set the nibble for VMD queue index */ 981 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 982 bits &= (~(0x0F << bitindex)); 983 bits |= (vind << bitindex); 984 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 985 986 /* Determine the location of the bit for this VLAN id */ 987 bitindex = vlan & 0x1F; /* lower five bits */ 988 989 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 990 if (vlan_on) 991 /* Turn on this VLAN id */ 992 bits |= (1 << bitindex); 993 else 994 /* Turn off this VLAN id */ 995 bits &= ~(1 << bitindex); 996 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 997 998 return IXGBE_SUCCESS; 999} 1000 1001/** 1002 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1003 * @hw: pointer to hardware structure 1004 * 1005 * Clears the VLAN filer table, and the VMDq index associated with the filter 1006 **/ 1007static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1008{ 1009 u32 offset; 1010 u32 vlanbyte; 1011 1012 DEBUGFUNC("ixgbe_clear_vfta_82598"); 1013 1014 for (offset = 0; offset < hw->mac.vft_size; offset++) 1015 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1016 1017 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1018 for (offset = 0; offset < hw->mac.vft_size; offset++) 1019 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1020 0); 1021 1022 return IXGBE_SUCCESS; 1023} 1024 1025/** 1026 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 1027 * @hw: pointer to hardware structure 1028 * @reg: analog register to read 1029 * @val: read value 1030 * 1031 * Performs read operation to Atlas analog register specified. 1032 **/ 1033s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 1034{ 1035 u32 atlas_ctl; 1036 1037 DEBUGFUNC("ixgbe_read_analog_reg8_82598"); 1038 1039 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1040 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1041 IXGBE_WRITE_FLUSH(hw); 1042 usec_delay(10); 1043 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1044 *val = (u8)atlas_ctl; 1045 1046 return IXGBE_SUCCESS; 1047} 1048 1049/** 1050 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1051 * @hw: pointer to hardware structure 1052 * @reg: atlas register to write 1053 * @val: value to write 1054 * 1055 * Performs write operation to Atlas analog register specified. 1056 **/ 1057s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1058{ 1059 u32 atlas_ctl; 1060 1061 DEBUGFUNC("ixgbe_write_analog_reg8_82598"); 1062 1063 atlas_ctl = (reg << 8) | val; 1064 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1065 IXGBE_WRITE_FLUSH(hw); 1066 usec_delay(10); 1067 1068 return IXGBE_SUCCESS; 1069} 1070 1071/** 1072 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1073 * @hw: pointer to hardware structure 1074 * @byte_offset: EEPROM byte offset to read 1075 * @eeprom_data: value read 1076 * 1077 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1078 **/ 1079s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1080 u8 *eeprom_data) 1081{ 1082 s32 status = IXGBE_SUCCESS; 1083 u16 sfp_addr = 0; 1084 u16 sfp_data = 0; 1085 u16 sfp_stat = 0; 1086 u32 i; 1087 1088 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598"); 1089 1090 if (hw->phy.type == ixgbe_phy_nl) { 1091 /* 1092 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1093 * 0xC30D. These registers are used to talk to the SFP+ 1094 * module's EEPROM through the SDA/SCL (I2C) interface. 1095 */ 1096 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1097 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1098 hw->phy.ops.write_reg(hw, 1099 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1100 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1101 sfp_addr); 1102 1103 /* Poll status */ 1104 for (i = 0; i < 100; i++) { 1105 hw->phy.ops.read_reg(hw, 1106 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1107 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1108 &sfp_stat); 1109 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1110 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1111 break; 1112 msec_delay(10); 1113 } 1114 1115 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1116 DEBUGOUT("EEPROM read did not pass.\n"); 1117 status = IXGBE_ERR_SFP_NOT_PRESENT; 1118 goto out; 1119 } 1120 1121 /* Read data */ 1122 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1123 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1124 1125 *eeprom_data = (u8)(sfp_data >> 8); 1126 } else { 1127 status = IXGBE_ERR_PHY; 1128 goto out; 1129 } 1130 1131out: 1132 return status; 1133} 1134 1135/** 1136 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1137 * @hw: pointer to hardware structure 1138 * 1139 * Determines physical layer capabilities of the current configuration. 1140 **/ 1141u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1142{ 1143 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1144 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1145 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1146 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1147 u16 ext_ability = 0; 1148 1149 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598"); 1150 1151 hw->phy.ops.identify(hw); 1152 1153 /* Copper PHY must be checked before AUTOC LMS to determine correct 1154 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1155 if (hw->phy.type == ixgbe_phy_tn || 1156 hw->phy.type == ixgbe_phy_cu_unknown) { 1157 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1158 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1159 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1160 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1161 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1162 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1163 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1164 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1165 goto out; 1166 } 1167 1168 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1169 case IXGBE_AUTOC_LMS_1G_AN: 1170 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1171 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1172 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1173 else 1174 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1175 break; 1176 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1177 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1178 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1179 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1180 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1181 else /* XAUI */ 1182 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1183 break; 1184 case IXGBE_AUTOC_LMS_KX4_AN: 1185 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1186 if (autoc & IXGBE_AUTOC_KX_SUPP) 1187 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1188 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1189 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1190 break; 1191 default: 1192 break; 1193 } 1194 1195 if (hw->phy.type == ixgbe_phy_nl) { 1196 hw->phy.ops.identify_sfp(hw); 1197 1198 switch (hw->phy.sfp_type) { 1199 case ixgbe_sfp_type_da_cu: 1200 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1201 break; 1202 case ixgbe_sfp_type_sr: 1203 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1204 break; 1205 case ixgbe_sfp_type_lr: 1206 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1207 break; 1208 default: 1209 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1210 break; 1211 } 1212 } 1213 1214 switch (hw->device_id) { 1215 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1216 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1217 break; 1218 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1219 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1220 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1221 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1222 break; 1223 case IXGBE_DEV_ID_82598EB_XF_LR: 1224 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1225 break; 1226 default: 1227 break; 1228 } 1229 1230out: 1231 return physical_layer; 1232} 1233 1234/** 1235 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1236 * port devices. 1237 * @hw: pointer to the HW structure 1238 * 1239 * Calls common function and corrects issue with some single port devices 1240 * that enable LAN1 but not LAN0. 1241 **/ 1242void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1243{ 1244 struct ixgbe_bus_info *bus = &hw->bus; 1245 u16 pci_gen, pci_ctrl2; 1246 1247 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598"); 1248 1249 ixgbe_set_lan_id_multi_port_pcie(hw); 1250 1251 /* check if LAN0 is disabled */ 1252 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1253 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1254 1255 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1256 1257 /* if LAN0 is completely disabled force function to 0 */ 1258 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1259 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1260 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1261 1262 bus->func = 0; 1263 } 1264 } 1265} 1266 1267/** 1268 * ixgbe_validate_link_ready - Function looks for phy link 1269 * @hw: pointer to hardware structure 1270 * 1271 * Function indicates success when phy link is available. If phy is not ready 1272 * within 5 seconds of MAC indicating link, the function returns error. 1273 **/ 1274static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 1275{ 1276 u32 timeout; 1277 u16 an_reg; 1278 1279 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 1280 return IXGBE_SUCCESS; 1281 1282 for (timeout = 0; 1283 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 1284 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1285 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); 1286 1287 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) && 1288 (an_reg & IXGBE_MII_AUTONEG_LINK_UP)) 1289 break; 1290 1291 msec_delay(100); 1292 } 1293 1294 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 1295 DEBUGOUT("Link was indicated but link is down\n"); 1296 return IXGBE_ERR_LINK_SETUP; 1297 } 1298 1299 return IXGBE_SUCCESS; 1300} 1301 1302