1179055Sjfv/****************************************************************************** 2171384Sjfv 3283620Serj Copyright (c) 2001-2015, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: releng/10.3/sys/dev/ixgbe/ixgbe_82598.c 295524 2016-02-11 16:16:10Z sbruno $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_type.h" 36230775Sjfv#include "ixgbe_82598.h" 37171384Sjfv#include "ixgbe_api.h" 38171384Sjfv#include "ixgbe_common.h" 39171384Sjfv#include "ixgbe_phy.h" 40171384Sjfv 41283620Serj#define IXGBE_82598_MAX_TX_QUEUES 32 42283620Serj#define IXGBE_82598_MAX_RX_QUEUES 64 43283620Serj#define IXGBE_82598_RAR_ENTRIES 16 44283620Serj#define IXGBE_82598_MC_TBL_SIZE 128 45283620Serj#define IXGBE_82598_VFT_TBL_SIZE 128 46283620Serj#define IXGBE_82598_RX_PB_SIZE 512 47283620Serj 48185352Sjfvstatic s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 49230775Sjfv ixgbe_link_speed *speed, 50230775Sjfv bool *autoneg); 51185352Sjfvstatic enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 52200239Sjfvstatic s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 53230775Sjfv bool autoneg_wait_to_complete); 54185352Sjfvstatic s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 55230775Sjfv ixgbe_link_speed *speed, bool *link_up, 56230775Sjfv bool link_up_wait_to_complete); 57200239Sjfvstatic s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 58230775Sjfv ixgbe_link_speed speed, 59230775Sjfv bool autoneg_wait_to_complete); 60200239Sjfvstatic s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 61230775Sjfv ixgbe_link_speed speed, 62230775Sjfv bool autoneg_wait_to_complete); 63185352Sjfvstatic s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 64185352Sjfvstatic s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 65185352Sjfvstatic s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 66230775Sjfvstatic void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 67230775Sjfv u32 headroom, int strategy); 68247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 69247822Sjfv u8 *sff8472_data); 70200239Sjfv/** 71200239Sjfv * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 72200239Sjfv * @hw: pointer to the HW structure 73200239Sjfv * 74200239Sjfv * The defaults for 82598 should be in the range of 50us to 50ms, 75200239Sjfv * however the hardware default for these parts is 500us to 1ms which is less 76200239Sjfv * than the 10ms recommended by the pci-e spec. To address this we need to 77200239Sjfv * increase the value to either 10ms to 250ms for capability version 1 config, 78200239Sjfv * or 16ms to 55ms for version 2. 79200239Sjfv **/ 80200239Sjfvvoid ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 81200239Sjfv{ 82200239Sjfv u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 83200239Sjfv u16 pcie_devctl2; 84194875Sjfv 85200239Sjfv /* only take action if timeout value is defaulted to 0 */ 86200239Sjfv if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 87200239Sjfv goto out; 88200239Sjfv 89200239Sjfv /* 90200239Sjfv * if capababilities version is type 1 we can write the 91200239Sjfv * timeout of 10ms to 250ms through the GCR register 92200239Sjfv */ 93200239Sjfv if (!(gcr & IXGBE_GCR_CAP_VER2)) { 94200239Sjfv gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 95200239Sjfv goto out; 96200239Sjfv } 97200239Sjfv 98200239Sjfv /* 99200239Sjfv * for version 2 capabilities we need to write the config space 100200239Sjfv * directly in order to set the completion timeout value for 101200239Sjfv * 16ms to 55ms 102200239Sjfv */ 103200239Sjfv pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 104200239Sjfv pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 105200239Sjfv IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 106200239Sjfvout: 107200239Sjfv /* disable completion timeout resend */ 108200239Sjfv gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 109200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 110200239Sjfv} 111200239Sjfv 112171384Sjfv/** 113179055Sjfv * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 114171384Sjfv * @hw: pointer to hardware structure 115171384Sjfv * 116179055Sjfv * Initialize the function pointers and assign the MAC type for 82598. 117179055Sjfv * Does not touch the hardware. 118171384Sjfv **/ 119179055Sjfvs32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 120171384Sjfv{ 121179055Sjfv struct ixgbe_mac_info *mac = &hw->mac; 122179055Sjfv struct ixgbe_phy_info *phy = &hw->phy; 123179055Sjfv s32 ret_val; 124171384Sjfv 125200239Sjfv DEBUGFUNC("ixgbe_init_ops_82598"); 126200239Sjfv 127179055Sjfv ret_val = ixgbe_init_phy_ops_generic(hw); 128179055Sjfv ret_val = ixgbe_init_ops_generic(hw); 129171384Sjfv 130190873Sjfv /* PHY */ 131283620Serj phy->ops.init = ixgbe_init_phy_ops_82598; 132190873Sjfv 133179055Sjfv /* MAC */ 134283620Serj mac->ops.start_hw = ixgbe_start_hw_82598; 135283620Serj mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598; 136283620Serj mac->ops.reset_hw = ixgbe_reset_hw_82598; 137283620Serj mac->ops.get_media_type = ixgbe_get_media_type_82598; 138185352Sjfv mac->ops.get_supported_physical_layer = 139283620Serj ixgbe_get_supported_physical_layer_82598; 140283620Serj mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598; 141283620Serj mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598; 142283620Serj mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598; 143283620Serj mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598; 144171384Sjfv 145179055Sjfv /* RAR, Multicast, VLAN */ 146283620Serj mac->ops.set_vmdq = ixgbe_set_vmdq_82598; 147283620Serj mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598; 148283620Serj mac->ops.set_vfta = ixgbe_set_vfta_82598; 149230775Sjfv mac->ops.set_vlvf = NULL; 150283620Serj mac->ops.clear_vfta = ixgbe_clear_vfta_82598; 151179055Sjfv 152179055Sjfv /* Flow Control */ 153283620Serj mac->ops.fc_enable = ixgbe_fc_enable_82598; 154179055Sjfv 155283620Serj mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 156283620Serj mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 157283620Serj mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 158283620Serj mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 159283620Serj mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 160283620Serj mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 161238149Sjfv mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 162179055Sjfv 163185352Sjfv /* SFP+ Module */ 164283620Serj phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598; 165283620Serj phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598; 166185352Sjfv 167190873Sjfv /* Link */ 168283620Serj mac->ops.check_link = ixgbe_check_mac_link_82598; 169283620Serj mac->ops.setup_link = ixgbe_setup_mac_link_82598; 170215911Sjfv mac->ops.flap_tx_laser = NULL; 171283620Serj mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598; 172283620Serj mac->ops.setup_rxpba = ixgbe_set_rxpba_82598; 173190873Sjfv 174230775Sjfv /* Manageability interface */ 175230775Sjfv mac->ops.set_fw_drv_ver = NULL; 176230775Sjfv 177251964Sjfv mac->ops.get_rtrup2tc = NULL; 178251964Sjfv 179190873Sjfv return ret_val; 180190873Sjfv} 181190873Sjfv 182190873Sjfv/** 183190873Sjfv * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 184190873Sjfv * @hw: pointer to hardware structure 185190873Sjfv * 186190873Sjfv * Initialize any function pointers that were not able to be 187190873Sjfv * set during init_shared_code because the PHY/SFP type was 188190873Sjfv * not known. Perform the SFP init if necessary. 189190873Sjfv * 190190873Sjfv **/ 191190873Sjfvs32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 192190873Sjfv{ 193190873Sjfv struct ixgbe_mac_info *mac = &hw->mac; 194190873Sjfv struct ixgbe_phy_info *phy = &hw->phy; 195190873Sjfv s32 ret_val = IXGBE_SUCCESS; 196190873Sjfv u16 list_offset, data_offset; 197190873Sjfv 198200239Sjfv DEBUGFUNC("ixgbe_init_phy_ops_82598"); 199190873Sjfv 200190873Sjfv /* Identify the PHY */ 201185352Sjfv phy->ops.identify(hw); 202185352Sjfv 203190873Sjfv /* Overwrite the link function pointers if copper PHY */ 204190873Sjfv if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 205283620Serj mac->ops.setup_link = ixgbe_setup_copper_link_82598; 206190873Sjfv mac->ops.get_link_capabilities = 207283620Serj ixgbe_get_copper_link_capabilities_generic; 208190873Sjfv } 209190873Sjfv 210185352Sjfv switch (hw->phy.type) { 211185352Sjfv case ixgbe_phy_tn: 212283620Serj phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 213283620Serj phy->ops.check_link = ixgbe_check_phy_link_tnx; 214185352Sjfv phy->ops.get_firmware_version = 215283620Serj ixgbe_get_phy_firmware_version_tnx; 216185352Sjfv break; 217185352Sjfv case ixgbe_phy_nl: 218283620Serj phy->ops.reset = ixgbe_reset_phy_nl; 219185352Sjfv 220185352Sjfv /* Call SFP+ identify routine to get the SFP+ module type */ 221185352Sjfv ret_val = phy->ops.identify_sfp(hw); 222185352Sjfv if (ret_val != IXGBE_SUCCESS) 223185352Sjfv goto out; 224185352Sjfv else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 225185352Sjfv ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 226185352Sjfv goto out; 227185352Sjfv } 228185352Sjfv 229185352Sjfv /* Check to see if SFP+ module is supported */ 230185352Sjfv ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 231230775Sjfv &list_offset, 232230775Sjfv &data_offset); 233185352Sjfv if (ret_val != IXGBE_SUCCESS) { 234185352Sjfv ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 235185352Sjfv goto out; 236185352Sjfv } 237185352Sjfv break; 238185352Sjfv default: 239185352Sjfv break; 240185352Sjfv } 241185352Sjfv 242185352Sjfvout: 243185352Sjfv return ret_val; 244171384Sjfv} 245171384Sjfv 246171384Sjfv/** 247200239Sjfv * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 248200239Sjfv * @hw: pointer to hardware structure 249200239Sjfv * 250200239Sjfv * Starts the hardware using the generic start_hw function. 251205720Sjfv * Disables relaxed ordering Then set pcie completion timeout 252205720Sjfv * 253200239Sjfv **/ 254200239Sjfvs32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 255200239Sjfv{ 256200239Sjfv u32 regval; 257200239Sjfv u32 i; 258200239Sjfv s32 ret_val = IXGBE_SUCCESS; 259200239Sjfv 260200239Sjfv DEBUGFUNC("ixgbe_start_hw_82598"); 261200239Sjfv 262200239Sjfv ret_val = ixgbe_start_hw_generic(hw); 263283620Serj if (ret_val) 264283620Serj return ret_val; 265200239Sjfv 266200239Sjfv /* Disable relaxed ordering */ 267200239Sjfv for (i = 0; ((i < hw->mac.max_tx_queues) && 268205720Sjfv (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 269200239Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 270238149Sjfv regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 271200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 272200239Sjfv } 273200239Sjfv 274200239Sjfv for (i = 0; ((i < hw->mac.max_rx_queues) && 275205720Sjfv (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 276200239Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 277238149Sjfv regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 278238149Sjfv IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 279200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 280200239Sjfv } 281200239Sjfv 282200239Sjfv /* set the completion timeout for interface */ 283283620Serj ixgbe_set_pcie_completion_timeout(hw); 284200239Sjfv 285200239Sjfv return ret_val; 286200239Sjfv} 287200239Sjfv 288200239Sjfv/** 289179055Sjfv * ixgbe_get_link_capabilities_82598 - Determines link capabilities 290171384Sjfv * @hw: pointer to hardware structure 291171384Sjfv * @speed: pointer to link speed 292171384Sjfv * @autoneg: boolean auto-negotiation value 293171384Sjfv * 294179055Sjfv * Determines the link capabilities by reading the AUTOC register. 295171384Sjfv **/ 296185352Sjfvstatic s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 297230775Sjfv ixgbe_link_speed *speed, 298230775Sjfv bool *autoneg) 299171384Sjfv{ 300171384Sjfv s32 status = IXGBE_SUCCESS; 301190873Sjfv u32 autoc = 0; 302171384Sjfv 303200239Sjfv DEBUGFUNC("ixgbe_get_link_capabilities_82598"); 304200239Sjfv 305190873Sjfv /* 306190873Sjfv * Determine link capabilities based on the stored value of AUTOC, 307190873Sjfv * which represents EEPROM defaults. If AUTOC value has not been 308190873Sjfv * stored, use the current register value. 309190873Sjfv */ 310190873Sjfv if (hw->mac.orig_link_settings_stored) 311190873Sjfv autoc = hw->mac.orig_autoc; 312190873Sjfv else 313190873Sjfv autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 314171384Sjfv 315190873Sjfv switch (autoc & IXGBE_AUTOC_LMS_MASK) { 316171384Sjfv case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 317171384Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 318171384Sjfv *autoneg = FALSE; 319171384Sjfv break; 320171384Sjfv 321171384Sjfv case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 322171384Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 323171384Sjfv *autoneg = FALSE; 324171384Sjfv break; 325171384Sjfv 326171384Sjfv case IXGBE_AUTOC_LMS_1G_AN: 327171384Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 328171384Sjfv *autoneg = TRUE; 329171384Sjfv break; 330171384Sjfv 331171384Sjfv case IXGBE_AUTOC_LMS_KX4_AN: 332171384Sjfv case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 333171384Sjfv *speed = IXGBE_LINK_SPEED_UNKNOWN; 334190873Sjfv if (autoc & IXGBE_AUTOC_KX4_SUPP) 335171384Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 336190873Sjfv if (autoc & IXGBE_AUTOC_KX_SUPP) 337171384Sjfv *speed |= IXGBE_LINK_SPEED_1GB_FULL; 338171384Sjfv *autoneg = TRUE; 339171384Sjfv break; 340171384Sjfv 341171384Sjfv default: 342171384Sjfv status = IXGBE_ERR_LINK_SETUP; 343171384Sjfv break; 344171384Sjfv } 345171384Sjfv 346171384Sjfv return status; 347171384Sjfv} 348171384Sjfv 349171384Sjfv/** 350171384Sjfv * ixgbe_get_media_type_82598 - Determines media type 351171384Sjfv * @hw: pointer to hardware structure 352171384Sjfv * 353171384Sjfv * Returns the media type (fiber, copper, backplane) 354171384Sjfv **/ 355185352Sjfvstatic enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 356171384Sjfv{ 357171384Sjfv enum ixgbe_media_type media_type; 358171384Sjfv 359200239Sjfv DEBUGFUNC("ixgbe_get_media_type_82598"); 360200239Sjfv 361190873Sjfv /* Detect if there is a copper PHY attached. */ 362215911Sjfv switch (hw->phy.type) { 363215911Sjfv case ixgbe_phy_cu_unknown: 364215911Sjfv case ixgbe_phy_tn: 365190873Sjfv media_type = ixgbe_media_type_copper; 366190873Sjfv goto out; 367215911Sjfv default: 368215911Sjfv break; 369190873Sjfv } 370190873Sjfv 371171384Sjfv /* Media type for I82598 is based on device ID */ 372171384Sjfv switch (hw->device_id) { 373185352Sjfv case IXGBE_DEV_ID_82598: 374190873Sjfv case IXGBE_DEV_ID_82598_BX: 375185352Sjfv /* Default device ID is mezzanine card KX/KX4 */ 376185352Sjfv media_type = ixgbe_media_type_backplane; 377185352Sjfv break; 378171384Sjfv case IXGBE_DEV_ID_82598AF_DUAL_PORT: 379171384Sjfv case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 380185352Sjfv case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 381185352Sjfv case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 382179055Sjfv case IXGBE_DEV_ID_82598EB_XF_LR: 383185352Sjfv case IXGBE_DEV_ID_82598EB_SFP_LOM: 384171384Sjfv media_type = ixgbe_media_type_fiber; 385171384Sjfv break; 386200239Sjfv case IXGBE_DEV_ID_82598EB_CX4: 387200239Sjfv case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 388200239Sjfv media_type = ixgbe_media_type_cx4; 389200239Sjfv break; 390179055Sjfv case IXGBE_DEV_ID_82598AT: 391200239Sjfv case IXGBE_DEV_ID_82598AT2: 392179055Sjfv media_type = ixgbe_media_type_copper; 393179055Sjfv break; 394171384Sjfv default: 395171384Sjfv media_type = ixgbe_media_type_unknown; 396171384Sjfv break; 397171384Sjfv } 398190873Sjfvout: 399171384Sjfv return media_type; 400171384Sjfv} 401171384Sjfv 402171384Sjfv/** 403185352Sjfv * ixgbe_fc_enable_82598 - Enable flow control 404171384Sjfv * @hw: pointer to hardware structure 405171384Sjfv * 406185352Sjfv * Enable flow control according to the current settings. 407171384Sjfv **/ 408238149Sjfvs32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 409171384Sjfv{ 410185352Sjfv s32 ret_val = IXGBE_SUCCESS; 411185352Sjfv u32 fctrl_reg; 412179055Sjfv u32 rmcs_reg; 413185352Sjfv u32 reg; 414238149Sjfv u32 fcrtl, fcrth; 415200239Sjfv u32 link_speed = 0; 416238149Sjfv int i; 417200239Sjfv bool link_up; 418171384Sjfv 419185352Sjfv DEBUGFUNC("ixgbe_fc_enable_82598"); 420179055Sjfv 421238149Sjfv /* Validate the water mark configuration */ 422238149Sjfv if (!hw->fc.pause_time) { 423238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 424238149Sjfv goto out; 425238149Sjfv } 426238149Sjfv 427238149Sjfv /* Low water mark of zero causes XOFF floods */ 428238149Sjfv for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 429238149Sjfv if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 430238149Sjfv hw->fc.high_water[i]) { 431238149Sjfv if (!hw->fc.low_water[i] || 432238149Sjfv hw->fc.low_water[i] >= hw->fc.high_water[i]) { 433238149Sjfv DEBUGOUT("Invalid water mark configuration\n"); 434238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 435238149Sjfv goto out; 436238149Sjfv } 437238149Sjfv } 438238149Sjfv } 439238149Sjfv 440200239Sjfv /* 441205720Sjfv * On 82598 having Rx FC on causes resets while doing 1G 442205720Sjfv * so if it's on turn it off once we know link_speed. For 443205720Sjfv * more details see 82598 Specification update. 444200239Sjfv */ 445200239Sjfv hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 446205720Sjfv if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 447205720Sjfv switch (hw->fc.requested_mode) { 448205720Sjfv case ixgbe_fc_full: 449205720Sjfv hw->fc.requested_mode = ixgbe_fc_tx_pause; 450205720Sjfv break; 451205720Sjfv case ixgbe_fc_rx_pause: 452205720Sjfv hw->fc.requested_mode = ixgbe_fc_none; 453205720Sjfv break; 454205720Sjfv default: 455205720Sjfv /* no change */ 456205720Sjfv break; 457205720Sjfv } 458200239Sjfv } 459200239Sjfv 460190873Sjfv /* Negotiate the fc mode to use */ 461238149Sjfv ixgbe_fc_autoneg(hw); 462190873Sjfv 463190873Sjfv /* Disable any previous flow control settings */ 464185352Sjfv fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 465185352Sjfv fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 466179055Sjfv 467179055Sjfv rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 468179055Sjfv rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 469179055Sjfv 470179055Sjfv /* 471185352Sjfv * The possible values of fc.current_mode are: 472179055Sjfv * 0: Flow control is completely disabled 473185352Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 474185352Sjfv * but not send pause frames). 475190873Sjfv * 2: Tx flow control is enabled (we can send pause frames but 476185352Sjfv * we do not support receiving pause frames). 477179055Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 478179055Sjfv * other: Invalid. 479179055Sjfv */ 480185352Sjfv switch (hw->fc.current_mode) { 481179055Sjfv case ixgbe_fc_none: 482215911Sjfv /* 483215911Sjfv * Flow control is disabled by software override or autoneg. 484190873Sjfv * The code below will actually disable it in the HW. 485190873Sjfv */ 486179055Sjfv break; 487179055Sjfv case ixgbe_fc_rx_pause: 488179055Sjfv /* 489185352Sjfv * Rx Flow control is enabled and Tx Flow control is 490185352Sjfv * disabled by software override. Since there really 491185352Sjfv * isn't a way to advertise that we are capable of RX 492185352Sjfv * Pause ONLY, we will advertise that we support both 493185352Sjfv * symmetric and asymmetric Rx PAUSE. Later, we will 494185352Sjfv * disable the adapter's ability to send PAUSE frames. 495179055Sjfv */ 496185352Sjfv fctrl_reg |= IXGBE_FCTRL_RFCE; 497179055Sjfv break; 498179055Sjfv case ixgbe_fc_tx_pause: 499179055Sjfv /* 500185352Sjfv * Tx Flow control is enabled, and Rx Flow control is 501185352Sjfv * disabled by software override. 502179055Sjfv */ 503179055Sjfv rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 504179055Sjfv break; 505179055Sjfv case ixgbe_fc_full: 506185352Sjfv /* Flow control (both Rx and Tx) is enabled by SW override. */ 507185352Sjfv fctrl_reg |= IXGBE_FCTRL_RFCE; 508179055Sjfv rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 509179055Sjfv break; 510179055Sjfv default: 511179055Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 512200239Sjfv ret_val = IXGBE_ERR_CONFIG; 513185352Sjfv goto out; 514179055Sjfv break; 515179055Sjfv } 516179055Sjfv 517190873Sjfv /* Set 802.3x based flow control settings. */ 518190873Sjfv fctrl_reg |= IXGBE_FCTRL_DPF; 519185352Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 520179055Sjfv IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 521179055Sjfv 522185352Sjfv /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 523238149Sjfv for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 524238149Sjfv if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 525238149Sjfv hw->fc.high_water[i]) { 526238149Sjfv fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 527238149Sjfv fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 528238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 529238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 530238149Sjfv } else { 531238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 532238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 533238149Sjfv } 534215911Sjfv 535179055Sjfv } 536179055Sjfv 537185352Sjfv /* Configure pause time (2 TCs per register) */ 538238149Sjfv reg = hw->fc.pause_time * 0x00010001; 539238149Sjfv for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 540238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 541185352Sjfv 542238149Sjfv /* Configure flow control refresh threshold value */ 543238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 544179055Sjfv 545185352Sjfvout: 546185352Sjfv return ret_val; 547171384Sjfv} 548171384Sjfv 549171384Sjfv/** 550200239Sjfv * ixgbe_start_mac_link_82598 - Configures MAC link settings 551171384Sjfv * @hw: pointer to hardware structure 552171384Sjfv * 553171384Sjfv * Configures link settings based on values in the ixgbe_hw struct. 554171384Sjfv * Restarts the link. Performs autonegotiation if needed. 555171384Sjfv **/ 556200239Sjfvstatic s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 557230775Sjfv bool autoneg_wait_to_complete) 558171384Sjfv{ 559171384Sjfv u32 autoc_reg; 560171384Sjfv u32 links_reg; 561171384Sjfv u32 i; 562171384Sjfv s32 status = IXGBE_SUCCESS; 563171384Sjfv 564200239Sjfv DEBUGFUNC("ixgbe_start_mac_link_82598"); 565200239Sjfv 566190873Sjfv /* Restart link */ 567171384Sjfv autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 568171384Sjfv autoc_reg |= IXGBE_AUTOC_AN_RESTART; 569171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 570171384Sjfv 571171384Sjfv /* Only poll for autoneg to complete if specified to do so */ 572200239Sjfv if (autoneg_wait_to_complete) { 573190873Sjfv if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 574190873Sjfv IXGBE_AUTOC_LMS_KX4_AN || 575190873Sjfv (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 576190873Sjfv IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 577171384Sjfv links_reg = 0; /* Just in case Autoneg time = 0 */ 578171384Sjfv for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 579171384Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 580171384Sjfv if (links_reg & IXGBE_LINKS_KX_AN_COMP) 581171384Sjfv break; 582171384Sjfv msec_delay(100); 583171384Sjfv } 584171384Sjfv if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 585171384Sjfv status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 586171384Sjfv DEBUGOUT("Autonegotiation did not complete.\n"); 587171384Sjfv } 588171384Sjfv } 589171384Sjfv } 590171384Sjfv 591171384Sjfv /* Add delay to filter out noises during initial link setup */ 592171384Sjfv msec_delay(50); 593171384Sjfv 594171384Sjfv return status; 595171384Sjfv} 596171384Sjfv 597171384Sjfv/** 598215911Sjfv * ixgbe_validate_link_ready - Function looks for phy link 599215911Sjfv * @hw: pointer to hardware structure 600215911Sjfv * 601215911Sjfv * Function indicates success when phy link is available. If phy is not ready 602215911Sjfv * within 5 seconds of MAC indicating link, the function returns error. 603215911Sjfv **/ 604215911Sjfvstatic s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 605215911Sjfv{ 606215911Sjfv u32 timeout; 607215911Sjfv u16 an_reg; 608215911Sjfv 609215911Sjfv if (hw->device_id != IXGBE_DEV_ID_82598AT2) 610215911Sjfv return IXGBE_SUCCESS; 611215911Sjfv 612215911Sjfv for (timeout = 0; 613215911Sjfv timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 614215911Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 615230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); 616215911Sjfv 617215911Sjfv if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) && 618215911Sjfv (an_reg & IXGBE_MII_AUTONEG_LINK_UP)) 619215911Sjfv break; 620215911Sjfv 621215911Sjfv msec_delay(100); 622215911Sjfv } 623215911Sjfv 624215911Sjfv if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 625215911Sjfv DEBUGOUT("Link was indicated but link is down\n"); 626215911Sjfv return IXGBE_ERR_LINK_SETUP; 627215911Sjfv } 628215911Sjfv 629215911Sjfv return IXGBE_SUCCESS; 630215911Sjfv} 631215911Sjfv 632215911Sjfv/** 633171384Sjfv * ixgbe_check_mac_link_82598 - Get link/speed status 634171384Sjfv * @hw: pointer to hardware structure 635171384Sjfv * @speed: pointer to link speed 636171384Sjfv * @link_up: TRUE is link is up, FALSE otherwise 637179055Sjfv * @link_up_wait_to_complete: bool used to wait for link up or not 638171384Sjfv * 639171384Sjfv * Reads the links register to determine if link is up and the current speed 640171384Sjfv **/ 641185352Sjfvstatic s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 642230775Sjfv ixgbe_link_speed *speed, bool *link_up, 643230775Sjfv bool link_up_wait_to_complete) 644171384Sjfv{ 645171384Sjfv u32 links_reg; 646179055Sjfv u32 i; 647185352Sjfv u16 link_reg, adapt_comp_reg; 648171384Sjfv 649200239Sjfv DEBUGFUNC("ixgbe_check_mac_link_82598"); 650200239Sjfv 651185352Sjfv /* 652185352Sjfv * SERDES PHY requires us to read link status from undocumented 653185352Sjfv * register 0xC79F. Bit 0 set indicates link is up/ready; clear 654185352Sjfv * indicates link down. OxC00C is read to check that the XAUI lanes 655185352Sjfv * are active. Bit 0 clear indicates active; set indicates inactive. 656185352Sjfv */ 657185352Sjfv if (hw->phy.type == ixgbe_phy_nl) { 658185352Sjfv hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 659185352Sjfv hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 660185352Sjfv hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 661230775Sjfv &adapt_comp_reg); 662185352Sjfv if (link_up_wait_to_complete) { 663295524Ssbruno for (i = 0; i < hw->mac.max_link_up_time; i++) { 664185352Sjfv if ((link_reg & 1) && 665185352Sjfv ((adapt_comp_reg & 1) == 0)) { 666185352Sjfv *link_up = TRUE; 667185352Sjfv break; 668185352Sjfv } else { 669185352Sjfv *link_up = FALSE; 670185352Sjfv } 671185352Sjfv msec_delay(100); 672185352Sjfv hw->phy.ops.read_reg(hw, 0xC79F, 673230775Sjfv IXGBE_TWINAX_DEV, 674230775Sjfv &link_reg); 675185352Sjfv hw->phy.ops.read_reg(hw, 0xC00C, 676230775Sjfv IXGBE_TWINAX_DEV, 677230775Sjfv &adapt_comp_reg); 678185352Sjfv } 679185352Sjfv } else { 680215911Sjfv if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 681185352Sjfv *link_up = TRUE; 682185352Sjfv else 683185352Sjfv *link_up = FALSE; 684185352Sjfv } 685185352Sjfv 686185352Sjfv if (*link_up == FALSE) 687185352Sjfv goto out; 688185352Sjfv } 689185352Sjfv 690171384Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 691179055Sjfv if (link_up_wait_to_complete) { 692295524Ssbruno for (i = 0; i < hw->mac.max_link_up_time; i++) { 693179055Sjfv if (links_reg & IXGBE_LINKS_UP) { 694179055Sjfv *link_up = TRUE; 695179055Sjfv break; 696179055Sjfv } else { 697179055Sjfv *link_up = FALSE; 698179055Sjfv } 699179055Sjfv msec_delay(100); 700179055Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 701179055Sjfv } 702179055Sjfv } else { 703179055Sjfv if (links_reg & IXGBE_LINKS_UP) 704179055Sjfv *link_up = TRUE; 705179055Sjfv else 706179055Sjfv *link_up = FALSE; 707179055Sjfv } 708171384Sjfv 709171384Sjfv if (links_reg & IXGBE_LINKS_SPEED) 710171384Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 711171384Sjfv else 712171384Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 713171384Sjfv 714200239Sjfv if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) && 715215911Sjfv (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS)) 716200239Sjfv *link_up = FALSE; 717200239Sjfv 718172043Sjfvout: 719172043Sjfv return IXGBE_SUCCESS; 720172043Sjfv} 721172043Sjfv 722172043Sjfv/** 723200239Sjfv * ixgbe_setup_mac_link_82598 - Set MAC link speed 724171384Sjfv * @hw: pointer to hardware structure 725171384Sjfv * @speed: new link speed 726185352Sjfv * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 727171384Sjfv * 728171384Sjfv * Set the link speed in the AUTOC register and restarts link. 729171384Sjfv **/ 730200239Sjfvstatic s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 731247822Sjfv ixgbe_link_speed speed, 732230775Sjfv bool autoneg_wait_to_complete) 733171384Sjfv{ 734247822Sjfv bool autoneg = FALSE; 735230775Sjfv s32 status = IXGBE_SUCCESS; 736190873Sjfv ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 737230775Sjfv u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 738230775Sjfv u32 autoc = curr_autoc; 739230775Sjfv u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 740171384Sjfv 741200239Sjfv DEBUGFUNC("ixgbe_setup_mac_link_82598"); 742200239Sjfv 743190873Sjfv /* Check to see if speed passed in is supported. */ 744190873Sjfv ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 745190873Sjfv speed &= link_capabilities; 746190873Sjfv 747190873Sjfv if (speed == IXGBE_LINK_SPEED_UNKNOWN) 748171384Sjfv status = IXGBE_ERR_LINK_SETUP; 749190873Sjfv 750190873Sjfv /* Set KX4/KX support according to speed requested */ 751190873Sjfv else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 752230775Sjfv link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 753190873Sjfv autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 754190873Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) 755190873Sjfv autoc |= IXGBE_AUTOC_KX4_SUPP; 756190873Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) 757190873Sjfv autoc |= IXGBE_AUTOC_KX_SUPP; 758190873Sjfv if (autoc != curr_autoc) 759190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 760171384Sjfv } 761171384Sjfv 762171384Sjfv if (status == IXGBE_SUCCESS) { 763171384Sjfv /* 764171384Sjfv * Setup and restart the link based on the new values in 765171384Sjfv * ixgbe_hw This will write the AUTOC register based on the new 766171384Sjfv * stored values 767171384Sjfv */ 768200239Sjfv status = ixgbe_start_mac_link_82598(hw, 769230775Sjfv autoneg_wait_to_complete); 770171384Sjfv } 771171384Sjfv 772171384Sjfv return status; 773171384Sjfv} 774171384Sjfv 775171384Sjfv 776171384Sjfv/** 777200239Sjfv * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 778171384Sjfv * @hw: pointer to hardware structure 779171384Sjfv * @speed: new link speed 780171384Sjfv * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 781171384Sjfv * 782171384Sjfv * Sets the link speed in the AUTOC register in the MAC and restarts link. 783171384Sjfv **/ 784200239Sjfvstatic s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 785230775Sjfv ixgbe_link_speed speed, 786230775Sjfv bool autoneg_wait_to_complete) 787171384Sjfv{ 788171384Sjfv s32 status; 789171384Sjfv 790200239Sjfv DEBUGFUNC("ixgbe_setup_copper_link_82598"); 791200239Sjfv 792171384Sjfv /* Setup the PHY according to input speed */ 793247822Sjfv status = hw->phy.ops.setup_link_speed(hw, speed, 794230775Sjfv autoneg_wait_to_complete); 795179055Sjfv /* Set up MAC */ 796200239Sjfv ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 797179055Sjfv 798171384Sjfv return status; 799171384Sjfv} 800171384Sjfv 801171384Sjfv/** 802171384Sjfv * ixgbe_reset_hw_82598 - Performs hardware reset 803171384Sjfv * @hw: pointer to hardware structure 804171384Sjfv * 805179055Sjfv * Resets the hardware by resetting the transmit and receive units, masks and 806171384Sjfv * clears all interrupts, performing a PHY reset, and performing a link (MAC) 807171384Sjfv * reset. 808171384Sjfv **/ 809185352Sjfvstatic s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 810171384Sjfv{ 811171384Sjfv s32 status = IXGBE_SUCCESS; 812194875Sjfv s32 phy_status = IXGBE_SUCCESS; 813171384Sjfv u32 ctrl; 814171384Sjfv u32 gheccr; 815171384Sjfv u32 i; 816171384Sjfv u32 autoc; 817172043Sjfv u8 analog_val; 818171384Sjfv 819200239Sjfv DEBUGFUNC("ixgbe_reset_hw_82598"); 820200239Sjfv 821171384Sjfv /* Call adapter stop to disable tx/rx and clear interrupts */ 822230775Sjfv status = hw->mac.ops.stop_adapter(hw); 823230775Sjfv if (status != IXGBE_SUCCESS) 824230775Sjfv goto reset_hw_out; 825171384Sjfv 826172043Sjfv /* 827179055Sjfv * Power up the Atlas Tx lanes if they are currently powered down. 828179055Sjfv * Atlas Tx lanes are powered down for MAC loopback tests, but 829172043Sjfv * they are not automatically restored on reset. 830172043Sjfv */ 831179055Sjfv hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 832172043Sjfv if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 833179055Sjfv /* Enable Tx Atlas so packets can be transmitted again */ 834179055Sjfv hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 835230775Sjfv &analog_val); 836172043Sjfv analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 837179055Sjfv hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 838230775Sjfv analog_val); 839172043Sjfv 840179055Sjfv hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 841230775Sjfv &analog_val); 842185352Sjfv analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 843179055Sjfv hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 844230775Sjfv analog_val); 845172043Sjfv 846179055Sjfv hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 847230775Sjfv &analog_val); 848172043Sjfv analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 849179055Sjfv hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 850230775Sjfv analog_val); 851172043Sjfv 852179055Sjfv hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 853230775Sjfv &analog_val); 854172043Sjfv analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 855179055Sjfv hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 856230775Sjfv analog_val); 857172043Sjfv } 858172043Sjfv 859171384Sjfv /* Reset PHY */ 860190873Sjfv if (hw->phy.reset_disable == FALSE) { 861190873Sjfv /* PHY ops must be identified and initialized prior to reset */ 862190873Sjfv 863190873Sjfv /* Init PHY and function pointers, perform SFP setup */ 864194875Sjfv phy_status = hw->phy.ops.init(hw); 865194875Sjfv if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 866190873Sjfv goto reset_hw_out; 867230775Sjfv if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 868230775Sjfv goto mac_reset_top; 869190873Sjfv 870179055Sjfv hw->phy.ops.reset(hw); 871190873Sjfv } 872171384Sjfv 873205720Sjfvmac_reset_top: 874171384Sjfv /* 875171384Sjfv * Issue global reset to the MAC. This needs to be a SW reset. 876171384Sjfv * If link reset is used, it might reset the MAC when mng is using it 877171384Sjfv */ 878230775Sjfv ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 879230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 880171384Sjfv IXGBE_WRITE_FLUSH(hw); 881171384Sjfv 882171384Sjfv /* Poll for reset bit to self-clear indicating reset is complete */ 883171384Sjfv for (i = 0; i < 10; i++) { 884171384Sjfv usec_delay(1); 885171384Sjfv ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 886171384Sjfv if (!(ctrl & IXGBE_CTRL_RST)) 887171384Sjfv break; 888171384Sjfv } 889171384Sjfv if (ctrl & IXGBE_CTRL_RST) { 890171384Sjfv status = IXGBE_ERR_RESET_FAILED; 891171384Sjfv DEBUGOUT("Reset polling failed to complete.\n"); 892171384Sjfv } 893171384Sjfv 894230775Sjfv msec_delay(50); 895230775Sjfv 896205720Sjfv /* 897205720Sjfv * Double resets are required for recovery from certain error 898205720Sjfv * conditions. Between resets, it is necessary to stall to allow time 899230775Sjfv * for any pending HW events to complete. 900205720Sjfv */ 901205720Sjfv if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 902205720Sjfv hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 903205720Sjfv goto mac_reset_top; 904205720Sjfv } 905205720Sjfv 906171384Sjfv gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 907171384Sjfv gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 908171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 909171384Sjfv 910171384Sjfv /* 911190873Sjfv * Store the original AUTOC value if it has not been 912190873Sjfv * stored off yet. Otherwise restore the stored original 913190873Sjfv * AUTOC value since the reset operation sets back to deaults. 914171384Sjfv */ 915171384Sjfv autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 916190873Sjfv if (hw->mac.orig_link_settings_stored == FALSE) { 917190873Sjfv hw->mac.orig_autoc = autoc; 918190873Sjfv hw->mac.orig_link_settings_stored = TRUE; 919215911Sjfv } else if (autoc != hw->mac.orig_autoc) { 920190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 921215911Sjfv } 922171384Sjfv 923194875Sjfv /* Store the permanent mac address */ 924194875Sjfv hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 925194875Sjfv 926190873Sjfv /* 927190873Sjfv * Store MAC address from RAR0, clear receive address registers, and 928190873Sjfv * clear the multicast table 929190873Sjfv */ 930190873Sjfv hw->mac.ops.init_rx_addrs(hw); 931190873Sjfv 932190873Sjfvreset_hw_out: 933194875Sjfv if (phy_status != IXGBE_SUCCESS) 934194875Sjfv status = phy_status; 935215911Sjfv 936171384Sjfv return status; 937171384Sjfv} 938171384Sjfv 939171384Sjfv/** 940179055Sjfv * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 941179055Sjfv * @hw: pointer to hardware struct 942179055Sjfv * @rar: receive address register index to associate with a VMDq index 943179055Sjfv * @vmdq: VMDq set index 944172043Sjfv **/ 945179055Sjfvs32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 946172043Sjfv{ 947179055Sjfv u32 rar_high; 948215911Sjfv u32 rar_entries = hw->mac.num_rar_entries; 949172043Sjfv 950200239Sjfv DEBUGFUNC("ixgbe_set_vmdq_82598"); 951200239Sjfv 952215911Sjfv /* Make sure we are using a valid rar index range */ 953215911Sjfv if (rar >= rar_entries) { 954215911Sjfv DEBUGOUT1("RAR index %d is out of range.\n", rar); 955215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 956215911Sjfv } 957215911Sjfv 958179055Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 959179055Sjfv rar_high &= ~IXGBE_RAH_VIND_MASK; 960179055Sjfv rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 961179055Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 962172043Sjfv return IXGBE_SUCCESS; 963172043Sjfv} 964172043Sjfv 965172043Sjfv/** 966181003Sjfv * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 967181003Sjfv * @hw: pointer to hardware struct 968181003Sjfv * @rar: receive address register index to associate with a VMDq index 969181003Sjfv * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 970181003Sjfv **/ 971185352Sjfvstatic s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 972181003Sjfv{ 973181003Sjfv u32 rar_high; 974181003Sjfv u32 rar_entries = hw->mac.num_rar_entries; 975181003Sjfv 976230775Sjfv UNREFERENCED_1PARAMETER(vmdq); 977181003Sjfv 978215911Sjfv /* Make sure we are using a valid rar index range */ 979215911Sjfv if (rar >= rar_entries) { 980181003Sjfv DEBUGOUT1("RAR index %d is out of range.\n", rar); 981215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 982181003Sjfv } 983181003Sjfv 984215911Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 985215911Sjfv if (rar_high & IXGBE_RAH_VIND_MASK) { 986215911Sjfv rar_high &= ~IXGBE_RAH_VIND_MASK; 987215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 988215911Sjfv } 989215911Sjfv 990181003Sjfv return IXGBE_SUCCESS; 991181003Sjfv} 992181003Sjfv 993181003Sjfv/** 994181003Sjfv * ixgbe_set_vfta_82598 - Set VLAN filter table 995181003Sjfv * @hw: pointer to hardware structure 996181003Sjfv * @vlan: VLAN id to write to VLAN filter 997181003Sjfv * @vind: VMDq output index that maps queue to VLAN id in VFTA 998181003Sjfv * @vlan_on: boolean flag to turn on/off VLAN in VFTA 999181003Sjfv * 1000181003Sjfv * Turn on/off specified VLAN in the VLAN filter table. 1001181003Sjfv **/ 1002181003Sjfvs32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 1003230775Sjfv bool vlan_on) 1004181003Sjfv{ 1005181003Sjfv u32 regindex; 1006181003Sjfv u32 bitindex; 1007181003Sjfv u32 bits; 1008181003Sjfv u32 vftabyte; 1009181003Sjfv 1010200239Sjfv DEBUGFUNC("ixgbe_set_vfta_82598"); 1011200239Sjfv 1012185352Sjfv if (vlan > 4095) 1013181003Sjfv return IXGBE_ERR_PARAM; 1014181003Sjfv 1015181003Sjfv /* Determine 32-bit word position in array */ 1016181003Sjfv regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1017181003Sjfv 1018181003Sjfv /* Determine the location of the (VMD) queue index */ 1019181003Sjfv vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 1020181003Sjfv bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 1021181003Sjfv 1022181003Sjfv /* Set the nibble for VMD queue index */ 1023181003Sjfv bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 1024181003Sjfv bits &= (~(0x0F << bitindex)); 1025181003Sjfv bits |= (vind << bitindex); 1026181003Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 1027181003Sjfv 1028181003Sjfv /* Determine the location of the bit for this VLAN id */ 1029181003Sjfv bitindex = vlan & 0x1F; /* lower five bits */ 1030181003Sjfv 1031181003Sjfv bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1032181003Sjfv if (vlan_on) 1033181003Sjfv /* Turn on this VLAN id */ 1034181003Sjfv bits |= (1 << bitindex); 1035181003Sjfv else 1036181003Sjfv /* Turn off this VLAN id */ 1037181003Sjfv bits &= ~(1 << bitindex); 1038181003Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1039181003Sjfv 1040181003Sjfv return IXGBE_SUCCESS; 1041181003Sjfv} 1042181003Sjfv 1043181003Sjfv/** 1044181003Sjfv * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1045181003Sjfv * @hw: pointer to hardware structure 1046181003Sjfv * 1047181003Sjfv * Clears the VLAN filer table, and the VMDq index associated with the filter 1048181003Sjfv **/ 1049185352Sjfvstatic s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1050181003Sjfv{ 1051181003Sjfv u32 offset; 1052181003Sjfv u32 vlanbyte; 1053181003Sjfv 1054200239Sjfv DEBUGFUNC("ixgbe_clear_vfta_82598"); 1055200239Sjfv 1056181003Sjfv for (offset = 0; offset < hw->mac.vft_size; offset++) 1057181003Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 1058181003Sjfv 1059181003Sjfv for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 1060181003Sjfv for (offset = 0; offset < hw->mac.vft_size; offset++) 1061181003Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 1062230775Sjfv 0); 1063181003Sjfv 1064181003Sjfv return IXGBE_SUCCESS; 1065181003Sjfv} 1066181003Sjfv 1067181003Sjfv/** 1068185352Sjfv * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 1069185352Sjfv * @hw: pointer to hardware structure 1070185352Sjfv * @reg: analog register to read 1071185352Sjfv * @val: read value 1072185352Sjfv * 1073185352Sjfv * Performs read operation to Atlas analog register specified. 1074185352Sjfv **/ 1075185352Sjfvs32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 1076185352Sjfv{ 1077185352Sjfv u32 atlas_ctl; 1078185352Sjfv 1079200239Sjfv DEBUGFUNC("ixgbe_read_analog_reg8_82598"); 1080200239Sjfv 1081185352Sjfv IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1082230775Sjfv IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1083185352Sjfv IXGBE_WRITE_FLUSH(hw); 1084185352Sjfv usec_delay(10); 1085185352Sjfv atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1086185352Sjfv *val = (u8)atlas_ctl; 1087185352Sjfv 1088185352Sjfv return IXGBE_SUCCESS; 1089185352Sjfv} 1090185352Sjfv 1091185352Sjfv/** 1092185352Sjfv * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1093185352Sjfv * @hw: pointer to hardware structure 1094185352Sjfv * @reg: atlas register to write 1095185352Sjfv * @val: value to write 1096185352Sjfv * 1097185352Sjfv * Performs write operation to Atlas analog register specified. 1098185352Sjfv **/ 1099185352Sjfvs32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1100185352Sjfv{ 1101185352Sjfv u32 atlas_ctl; 1102185352Sjfv 1103200239Sjfv DEBUGFUNC("ixgbe_write_analog_reg8_82598"); 1104200239Sjfv 1105185352Sjfv atlas_ctl = (reg << 8) | val; 1106185352Sjfv IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1107185352Sjfv IXGBE_WRITE_FLUSH(hw); 1108185352Sjfv usec_delay(10); 1109185352Sjfv 1110185352Sjfv return IXGBE_SUCCESS; 1111185352Sjfv} 1112185352Sjfv 1113185352Sjfv/** 1114247822Sjfv * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 1115185352Sjfv * @hw: pointer to hardware structure 1116247822Sjfv * @dev_addr: address to read from 1117247822Sjfv * @byte_offset: byte offset to read from dev_addr 1118185352Sjfv * @eeprom_data: value read 1119185352Sjfv * 1120185352Sjfv * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1121185352Sjfv **/ 1122247822Sjfvstatic s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 1123247822Sjfv u8 byte_offset, u8 *eeprom_data) 1124185352Sjfv{ 1125185352Sjfv s32 status = IXGBE_SUCCESS; 1126185352Sjfv u16 sfp_addr = 0; 1127185352Sjfv u16 sfp_data = 0; 1128185352Sjfv u16 sfp_stat = 0; 1129251964Sjfv u16 gssr; 1130185352Sjfv u32 i; 1131185352Sjfv 1132247822Sjfv DEBUGFUNC("ixgbe_read_i2c_phy_82598"); 1133200239Sjfv 1134251964Sjfv if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1135251964Sjfv gssr = IXGBE_GSSR_PHY1_SM; 1136251964Sjfv else 1137251964Sjfv gssr = IXGBE_GSSR_PHY0_SM; 1138251964Sjfv 1139251964Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 1140251964Sjfv return IXGBE_ERR_SWFW_SYNC; 1141251964Sjfv 1142185352Sjfv if (hw->phy.type == ixgbe_phy_nl) { 1143185352Sjfv /* 1144185352Sjfv * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1145185352Sjfv * 0xC30D. These registers are used to talk to the SFP+ 1146185352Sjfv * module's EEPROM through the SDA/SCL (I2C) interface. 1147185352Sjfv */ 1148247822Sjfv sfp_addr = (dev_addr << 8) + byte_offset; 1149185352Sjfv sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1150251964Sjfv hw->phy.ops.write_reg_mdi(hw, 1151251964Sjfv IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1152251964Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1153251964Sjfv sfp_addr); 1154185352Sjfv 1155185352Sjfv /* Poll status */ 1156185352Sjfv for (i = 0; i < 100; i++) { 1157251964Sjfv hw->phy.ops.read_reg_mdi(hw, 1158251964Sjfv IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1159251964Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1160251964Sjfv &sfp_stat); 1161185352Sjfv sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1162185352Sjfv if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1163185352Sjfv break; 1164185352Sjfv msec_delay(10); 1165185352Sjfv } 1166185352Sjfv 1167185352Sjfv if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1168185352Sjfv DEBUGOUT("EEPROM read did not pass.\n"); 1169185352Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1170185352Sjfv goto out; 1171185352Sjfv } 1172185352Sjfv 1173185352Sjfv /* Read data */ 1174251964Sjfv hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1175251964Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1176185352Sjfv 1177185352Sjfv *eeprom_data = (u8)(sfp_data >> 8); 1178185352Sjfv } else { 1179185352Sjfv status = IXGBE_ERR_PHY; 1180185352Sjfv } 1181185352Sjfv 1182185352Sjfvout: 1183251964Sjfv hw->mac.ops.release_swfw_sync(hw, gssr); 1184185352Sjfv return status; 1185185352Sjfv} 1186185352Sjfv 1187185352Sjfv/** 1188247822Sjfv * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1189247822Sjfv * @hw: pointer to hardware structure 1190247822Sjfv * @byte_offset: EEPROM byte offset to read 1191247822Sjfv * @eeprom_data: value read 1192247822Sjfv * 1193247822Sjfv * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1194247822Sjfv **/ 1195247822Sjfvs32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1196247822Sjfv u8 *eeprom_data) 1197247822Sjfv{ 1198247822Sjfv return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 1199247822Sjfv byte_offset, eeprom_data); 1200247822Sjfv} 1201247822Sjfv 1202247822Sjfv/** 1203247822Sjfv * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. 1204247822Sjfv * @hw: pointer to hardware structure 1205247822Sjfv * @byte_offset: byte offset at address 0xA2 1206247822Sjfv * @eeprom_data: value read 1207247822Sjfv * 1208247822Sjfv * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C 1209247822Sjfv **/ 1210247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 1211247822Sjfv u8 *sff8472_data) 1212247822Sjfv{ 1213247822Sjfv return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, 1214247822Sjfv byte_offset, sff8472_data); 1215247822Sjfv} 1216247822Sjfv 1217247822Sjfv/** 1218185352Sjfv * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1219185352Sjfv * @hw: pointer to hardware structure 1220185352Sjfv * 1221185352Sjfv * Determines physical layer capabilities of the current configuration. 1222185352Sjfv **/ 1223185352Sjfvu32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1224185352Sjfv{ 1225185352Sjfv u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1226190873Sjfv u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1227190873Sjfv u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1228190873Sjfv u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1229190873Sjfv u16 ext_ability = 0; 1230185352Sjfv 1231200239Sjfv DEBUGFUNC("ixgbe_get_supported_physical_layer_82598"); 1232200239Sjfv 1233190873Sjfv hw->phy.ops.identify(hw); 1234190873Sjfv 1235190873Sjfv /* Copper PHY must be checked before AUTOC LMS to determine correct 1236190873Sjfv * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1237215911Sjfv switch (hw->phy.type) { 1238215911Sjfv case ixgbe_phy_tn: 1239215911Sjfv case ixgbe_phy_cu_unknown: 1240190873Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1241190873Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1242190873Sjfv if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1243190873Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1244190873Sjfv if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1245190873Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1246190873Sjfv if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1247190873Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1248190873Sjfv goto out; 1249215911Sjfv default: 1250215911Sjfv break; 1251190873Sjfv } 1252190873Sjfv 1253190873Sjfv switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1254190873Sjfv case IXGBE_AUTOC_LMS_1G_AN: 1255190873Sjfv case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1256190873Sjfv if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1257190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1258190873Sjfv else 1259190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1260185352Sjfv break; 1261190873Sjfv case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1262190873Sjfv if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1263190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1264190873Sjfv else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1265190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1266190873Sjfv else /* XAUI */ 1267190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1268185352Sjfv break; 1269190873Sjfv case IXGBE_AUTOC_LMS_KX4_AN: 1270190873Sjfv case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1271190873Sjfv if (autoc & IXGBE_AUTOC_KX_SUPP) 1272190873Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1273190873Sjfv if (autoc & IXGBE_AUTOC_KX4_SUPP) 1274190873Sjfv physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1275185352Sjfv break; 1276190873Sjfv default: 1277185352Sjfv break; 1278190873Sjfv } 1279190873Sjfv 1280190873Sjfv if (hw->phy.type == ixgbe_phy_nl) { 1281185352Sjfv hw->phy.ops.identify_sfp(hw); 1282185352Sjfv 1283185352Sjfv switch (hw->phy.sfp_type) { 1284185352Sjfv case ixgbe_sfp_type_da_cu: 1285185352Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1286185352Sjfv break; 1287185352Sjfv case ixgbe_sfp_type_sr: 1288185352Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1289185352Sjfv break; 1290185352Sjfv case ixgbe_sfp_type_lr: 1291185352Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1292185352Sjfv break; 1293185352Sjfv default: 1294185352Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1295185352Sjfv break; 1296185352Sjfv } 1297190873Sjfv } 1298190873Sjfv 1299190873Sjfv switch (hw->device_id) { 1300190873Sjfv case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1301190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1302185352Sjfv break; 1303190873Sjfv case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1304190873Sjfv case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1305190873Sjfv case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1306190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1307190873Sjfv break; 1308190873Sjfv case IXGBE_DEV_ID_82598EB_XF_LR: 1309190873Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1310190873Sjfv break; 1311185352Sjfv default: 1312185352Sjfv break; 1313185352Sjfv } 1314185352Sjfv 1315190873Sjfvout: 1316185352Sjfv return physical_layer; 1317185352Sjfv} 1318194875Sjfv 1319194875Sjfv/** 1320194875Sjfv * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1321194875Sjfv * port devices. 1322194875Sjfv * @hw: pointer to the HW structure 1323194875Sjfv * 1324194875Sjfv * Calls common function and corrects issue with some single port devices 1325194875Sjfv * that enable LAN1 but not LAN0. 1326194875Sjfv **/ 1327194875Sjfvvoid ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1328194875Sjfv{ 1329194875Sjfv struct ixgbe_bus_info *bus = &hw->bus; 1330215911Sjfv u16 pci_gen = 0; 1331215911Sjfv u16 pci_ctrl2 = 0; 1332194875Sjfv 1333200239Sjfv DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598"); 1334200239Sjfv 1335194875Sjfv ixgbe_set_lan_id_multi_port_pcie(hw); 1336194875Sjfv 1337194875Sjfv /* check if LAN0 is disabled */ 1338194875Sjfv hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1339194875Sjfv if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1340194875Sjfv 1341194875Sjfv hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1342194875Sjfv 1343194875Sjfv /* if LAN0 is completely disabled force function to 0 */ 1344194875Sjfv if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1345194875Sjfv !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1346194875Sjfv !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1347194875Sjfv 1348194875Sjfv bus->func = 0; 1349194875Sjfv } 1350194875Sjfv } 1351194875Sjfv} 1352194875Sjfv 1353200239Sjfv/** 1354205720Sjfv * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering 1355205720Sjfv * @hw: pointer to hardware structure 1356205720Sjfv * 1357205720Sjfv **/ 1358205720Sjfvvoid ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw) 1359205720Sjfv{ 1360205720Sjfv u32 regval; 1361205720Sjfv u32 i; 1362205720Sjfv 1363205720Sjfv DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598"); 1364205720Sjfv 1365205720Sjfv /* Enable relaxed ordering */ 1366205720Sjfv for (i = 0; ((i < hw->mac.max_tx_queues) && 1367205720Sjfv (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 1368205720Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 1369238149Sjfv regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 1370205720Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 1371205720Sjfv } 1372205720Sjfv 1373205720Sjfv for (i = 0; ((i < hw->mac.max_rx_queues) && 1374205720Sjfv (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 1375205720Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 1376238149Sjfv regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 1377238149Sjfv IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 1378205720Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 1379205720Sjfv } 1380205720Sjfv 1381205720Sjfv} 1382230775Sjfv 1383230775Sjfv/** 1384230775Sjfv * ixgbe_set_rxpba_82598 - Initialize RX packet buffer 1385230775Sjfv * @hw: pointer to hardware structure 1386230775Sjfv * @num_pb: number of packet buffers to allocate 1387230775Sjfv * @headroom: reserve n KB of headroom 1388230775Sjfv * @strategy: packet buffer allocation strategy 1389230775Sjfv **/ 1390230775Sjfvstatic void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 1391230775Sjfv u32 headroom, int strategy) 1392230775Sjfv{ 1393230775Sjfv u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1394230775Sjfv u8 i = 0; 1395230775Sjfv UNREFERENCED_1PARAMETER(headroom); 1396230775Sjfv 1397230775Sjfv if (!num_pb) 1398230775Sjfv return; 1399230775Sjfv 1400230775Sjfv /* Setup Rx packet buffer sizes */ 1401230775Sjfv switch (strategy) { 1402230775Sjfv case PBA_STRATEGY_WEIGHTED: 1403230775Sjfv /* Setup the first four at 80KB */ 1404230775Sjfv rxpktsize = IXGBE_RXPBSIZE_80KB; 1405230775Sjfv for (; i < 4; i++) 1406230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1407230775Sjfv /* Setup the last four at 48KB...don't re-init i */ 1408230775Sjfv rxpktsize = IXGBE_RXPBSIZE_48KB; 1409230775Sjfv /* Fall Through */ 1410230775Sjfv case PBA_STRATEGY_EQUAL: 1411230775Sjfv default: 1412230775Sjfv /* Divide the remaining Rx packet buffer evenly among the TCs */ 1413230775Sjfv for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1414230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1415230775Sjfv break; 1416230775Sjfv } 1417230775Sjfv 1418230775Sjfv /* Setup Tx packet buffer sizes */ 1419230775Sjfv for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1420230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1421283620Serj} 1422230775Sjfv 1423283620Serj/** 1424283620Serj * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit 1425283620Serj * @hw: pointer to hardware structure 1426283620Serj * @regval: register value to write to RXCTRL 1427283620Serj * 1428283620Serj * Enables the Rx DMA unit 1429283620Serj **/ 1430283620Serjs32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval) 1431283620Serj{ 1432283620Serj DEBUGFUNC("ixgbe_enable_rx_dma_82598"); 1433283620Serj 1434283620Serj IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1435283620Serj 1436283620Serj return IXGBE_SUCCESS; 1437230775Sjfv} 1438