1179055Sjfv/****************************************************************************** 2171384Sjfv 3283620Serj Copyright (c) 2001-2015, Intel Corporation 4179055Sjfv All rights reserved. 5179055Sjfv 6179055Sjfv Redistribution and use in source and binary forms, with or without 7179055Sjfv modification, are permitted provided that the following conditions are met: 8179055Sjfv 9179055Sjfv 1. Redistributions of source code must retain the above copyright notice, 10179055Sjfv this list of conditions and the following disclaimer. 11179055Sjfv 12179055Sjfv 2. Redistributions in binary form must reproduce the above copyright 13179055Sjfv notice, this list of conditions and the following disclaimer in the 14179055Sjfv documentation and/or other materials provided with the distribution. 15179055Sjfv 16179055Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17179055Sjfv contributors may be used to endorse or promote products derived from 18179055Sjfv this software without specific prior written permission. 19179055Sjfv 20179055Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21179055Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22179055Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23179055Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24179055Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25179055Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26179055Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27179055Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28179055Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29179055Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30179055Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: releng/10.3/sys/dev/ixgbe/ixgbe.h 295534 2016-02-11 17:34:26Z smh $*/ 34171384Sjfv 35185352Sjfv 36171384Sjfv#ifndef _IXGBE_H_ 37171384Sjfv#define _IXGBE_H_ 38171384Sjfv 39171384Sjfv 40171384Sjfv#include <sys/param.h> 41171384Sjfv#include <sys/systm.h> 42243725Sjfv#ifndef IXGBE_LEGACY_TX 43194875Sjfv#include <sys/buf_ring.h> 44194875Sjfv#endif 45171384Sjfv#include <sys/mbuf.h> 46171384Sjfv#include <sys/protosw.h> 47171384Sjfv#include <sys/socket.h> 48171384Sjfv#include <sys/malloc.h> 49171384Sjfv#include <sys/kernel.h> 50171384Sjfv#include <sys/module.h> 51171384Sjfv#include <sys/sockio.h> 52295008Ssbruno#include <sys/eventhandler.h> 53171384Sjfv 54171384Sjfv#include <net/if.h> 55295008Ssbruno#include <net/if_var.h> 56171384Sjfv#include <net/if_arp.h> 57171384Sjfv#include <net/bpf.h> 58171384Sjfv#include <net/ethernet.h> 59171384Sjfv#include <net/if_dl.h> 60171384Sjfv#include <net/if_media.h> 61171384Sjfv 62171384Sjfv#include <net/bpf.h> 63171384Sjfv#include <net/if_types.h> 64171384Sjfv#include <net/if_vlan_var.h> 65171384Sjfv 66171384Sjfv#include <netinet/in_systm.h> 67171384Sjfv#include <netinet/in.h> 68171384Sjfv#include <netinet/if_ether.h> 69171384Sjfv#include <netinet/ip.h> 70171384Sjfv#include <netinet/ip6.h> 71171384Sjfv#include <netinet/tcp.h> 72190873Sjfv#include <netinet/tcp_lro.h> 73171384Sjfv#include <netinet/udp.h> 74171384Sjfv 75171384Sjfv#include <machine/in_cksum.h> 76171384Sjfv 77171384Sjfv#include <sys/bus.h> 78171384Sjfv#include <machine/bus.h> 79171384Sjfv#include <sys/rman.h> 80171384Sjfv#include <machine/resource.h> 81171384Sjfv#include <vm/vm.h> 82171384Sjfv#include <vm/pmap.h> 83171384Sjfv#include <machine/clock.h> 84171384Sjfv#include <dev/pci/pcivar.h> 85171384Sjfv#include <dev/pci/pcireg.h> 86171384Sjfv#include <sys/proc.h> 87171384Sjfv#include <sys/sysctl.h> 88171384Sjfv#include <sys/endian.h> 89171384Sjfv#include <sys/taskqueue.h> 90179055Sjfv#include <sys/pcpu.h> 91194875Sjfv#include <sys/smp.h> 92194875Sjfv#include <machine/smp.h> 93283620Serj#include <sys/sbuf.h> 94171384Sjfv 95295008Ssbruno#ifdef PCI_IOV 96295008Ssbruno#include <sys/nv.h> 97295008Ssbruno#include <sys/iov_schema.h> 98295008Ssbruno#include <dev/pci/pci_iov.h> 99295008Ssbruno#endif 100295008Ssbruno 101171384Sjfv#include "ixgbe_api.h" 102283620Serj#include "ixgbe_common.h" 103283620Serj#include "ixgbe_phy.h" 104283620Serj#include "ixgbe_vf.h" 105171384Sjfv 106295008Ssbruno#ifdef PCI_IOV 107295008Ssbruno#include "ixgbe_common.h" 108295008Ssbruno#include "ixgbe_mbx.h" 109295008Ssbruno#endif 110295008Ssbruno 111171384Sjfv/* Tunables */ 112171384Sjfv 113171384Sjfv/* 114172043Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 115171384Sjfv * number of transmit descriptors allocated by the driver. Increasing this 116171384Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 117172043Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 118172043Sjfv * performance. 119171384Sjfv */ 120190873Sjfv#define DEFAULT_TXD 1024 121172043Sjfv#define PERFORM_TXD 2048 122171384Sjfv#define MAX_TXD 4096 123171384Sjfv#define MIN_TXD 64 124171384Sjfv 125171384Sjfv/* 126172043Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 127172043Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 128171384Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 129172043Sjfv * is 16 bytes. A receive buffer is also allocated for each descriptor. 130171384Sjfv * 131172043Sjfv * Note: with 8 rings and a dual port card, it is possible to bump up 132172043Sjfv * against the system mbuf pool limit, you can tune nmbclusters 133172043Sjfv * to adjust for this. 134171384Sjfv */ 135190873Sjfv#define DEFAULT_RXD 1024 136172043Sjfv#define PERFORM_RXD 2048 137171384Sjfv#define MAX_RXD 4096 138171384Sjfv#define MIN_RXD 64 139171384Sjfv 140172043Sjfv/* Alignment for rings */ 141172043Sjfv#define DBA_ALIGN 128 142172043Sjfv 143171384Sjfv/* 144200239Sjfv * This is the max watchdog interval, ie. the time that can 145200239Sjfv * pass between any two TX clean operations, such only happening 146200239Sjfv * when the TX hardware is functioning. 147171384Sjfv */ 148200239Sjfv#define IXGBE_WATCHDOG (10 * hz) 149171384Sjfv 150171384Sjfv/* 151171384Sjfv * This parameters control when the driver calls the routine to reclaim 152171384Sjfv * transmit descriptors. 153171384Sjfv */ 154171384Sjfv#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 155171384Sjfv#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 156171384Sjfv 157283620Serj/* These defines are used in MTU calculations */ 158283620Serj#define IXGBE_MAX_FRAME_SIZE 9728 159295524Ssbruno#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) 160295524Ssbruno#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 161283620Serj ETHER_VLAN_ENCAP_LEN) 162283620Serj#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 163295524Ssbruno#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) 164171384Sjfv 165172043Sjfv/* Flow control constants */ 166200239Sjfv#define IXGBE_FC_PAUSE 0xFFFF 167172043Sjfv#define IXGBE_FC_HI 0x20000 168172043Sjfv#define IXGBE_FC_LO 0x10000 169171384Sjfv 170239940Sscottl/* 171239940Sscottl * Used for optimizing small rx mbufs. Effort is made to keep the copy 172239940Sscottl * small and aligned for the CPU L1 cache. 173239940Sscottl * 174239940Sscottl * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 175239940Sscottl * 32 byte alignment needed for the fast bcopy results in 8 bytes being 176239940Sscottl * wasted. Getting 64 byte alignment, which _should_ be ideal for 177239940Sscottl * modern Intel CPUs, results in 40 bytes wasted and a significant drop 178239940Sscottl * in observed efficiency of the optimization, 97.9% -> 81.8%. 179239940Sscottl */ 180295524Ssbruno#if __FreeBSD_version < 1002000 181295524Ssbruno#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) 182295524Ssbruno#endif 183281954Sngie#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 184281954Sngie#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 185281954Sngie#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 186239940Sscottl 187221189Sjfv/* Keep older OS drivers building... */ 188221189Sjfv#if !defined(SYSCTL_ADD_UQUAD) 189221189Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 190221189Sjfv#endif 191221189Sjfv 192171384Sjfv/* Defines for printing debug information */ 193171384Sjfv#define DEBUG_INIT 0 194171384Sjfv#define DEBUG_IOCTL 0 195171384Sjfv#define DEBUG_HW 0 196171384Sjfv 197171384Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 198171384Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 199171384Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 200171384Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 201171384Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 202171384Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 203171384Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 204171384Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 205171384Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 206171384Sjfv 207171384Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 208190873Sjfv#define IXGBE_82598_SCATTER 100 209190873Sjfv#define IXGBE_82599_SCATTER 32 210185352Sjfv#define MSIX_82598_BAR 3 211185352Sjfv#define MSIX_82599_BAR 4 212234620Sbz#define IXGBE_TSO_SIZE 262140 213205720Sjfv#define IXGBE_RX_HDR 128 214194875Sjfv#define IXGBE_VFTA_SIZE 128 215194875Sjfv#define IXGBE_BR_SIZE 4096 216230775Sjfv#define IXGBE_QUEUE_MIN_FREE 32 217283620Serj#define IXGBE_MAX_TX_BUSY 10 218283620Serj#define IXGBE_QUEUE_HUNG 0x80000000 219171384Sjfv 220283620Serj#define IXV_EITR_DEFAULT 128 221243718Sjfv 222295524Ssbruno/* Supported offload bits in mbuf flag */ 223295524Ssbruno#if __FreeBSD_version >= 1000000 224295524Ssbruno#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 225295524Ssbruno CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 226295524Ssbruno CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 227295524Ssbruno#elif __FreeBSD_version >= 800000 228205904Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 229205904Sjfv#else 230205904Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 231205904Sjfv#endif 232205904Sjfv 233283620Serj/* Backward compatibility items for very old versions */ 234283620Serj#ifndef pci_find_cap 235283620Serj#define pci_find_cap pci_find_extcap 236283620Serj#endif 237283620Serj 238283620Serj#ifndef DEVMETHOD_END 239283620Serj#define DEVMETHOD_END { NULL, NULL } 240283620Serj#endif 241283620Serj 242171384Sjfv/* 243171384Sjfv * Interrupt Moderation parameters 244171384Sjfv */ 245185352Sjfv#define IXGBE_LOW_LATENCY 128 246185352Sjfv#define IXGBE_AVE_LATENCY 400 247185352Sjfv#define IXGBE_BULK_LATENCY 1200 248171384Sjfv 249295524Ssbruno/* Using 1FF (the max value), the interval is ~1.05ms */ 250295524Ssbruno#define IXGBE_LINK_ITR_QUANTA 0x1FF 251295524Ssbruno#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ 252295524Ssbruno IXGBE_EITR_ITR_INT_MASK) 253295524Ssbruno 254283620Serj/* MAC type macros */ 255283620Serj#define IXGBE_IS_X550VF(_adapter) \ 256283620Serj ((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \ 257283620Serj (_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf)) 258251964Sjfv 259283620Serj#define IXGBE_IS_VF(_adapter) \ 260283620Serj (IXGBE_IS_X550VF(_adapter) || \ 261283620Serj (_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \ 262283620Serj (_adapter->hw.mac.type == ixgbe_mac_82599_vf)) 263283620Serj 264295008Ssbruno#ifdef PCI_IOV 265295008Ssbruno#define IXGBE_VF_INDEX(vmdq) ((vmdq) / 32) 266295008Ssbruno#define IXGBE_VF_BIT(vmdq) (1 << ((vmdq) % 32)) 267283620Serj 268295008Ssbruno#define IXGBE_VT_MSG_MASK 0xFFFF 269295008Ssbruno 270295008Ssbruno#define IXGBE_VT_MSGINFO(msg) \ 271295008Ssbruno (((msg) & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT) 272295008Ssbruno 273295008Ssbruno#define IXGBE_VF_GET_QUEUES_RESP_LEN 5 274295008Ssbruno 275295008Ssbruno#define IXGBE_API_VER_1_0 0 276295008Ssbruno#define IXGBE_API_VER_2_0 1 /* Solaris API. Not supported. */ 277295008Ssbruno#define IXGBE_API_VER_1_1 2 278295008Ssbruno#define IXGBE_API_VER_UNKNOWN UINT16_MAX 279295008Ssbruno 280295008Ssbrunoenum ixgbe_iov_mode { 281295008Ssbruno IXGBE_64_VM, 282295008Ssbruno IXGBE_32_VM, 283295008Ssbruno IXGBE_NO_VM 284295008Ssbruno}; 285295008Ssbruno#endif /* PCI_IOV */ 286295008Ssbruno 287295008Ssbruno 288171384Sjfv/* 289185352Sjfv ***************************************************************************** 290171384Sjfv * vendor_info_array 291171384Sjfv * 292171384Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 293171384Sjfv * should load. 294171384Sjfv * 295185352Sjfv ***************************************************************************** 296171384Sjfv */ 297171384Sjfvtypedef struct _ixgbe_vendor_info_t { 298171384Sjfv unsigned int vendor_id; 299171384Sjfv unsigned int device_id; 300171384Sjfv unsigned int subvendor_id; 301171384Sjfv unsigned int subdevice_id; 302171384Sjfv unsigned int index; 303185352Sjfv} ixgbe_vendor_info_t; 304171384Sjfv 305295008Ssbruno 306171384Sjfvstruct ixgbe_tx_buf { 307243736Sjfv union ixgbe_adv_tx_desc *eop; 308171384Sjfv struct mbuf *m_head; 309171384Sjfv bus_dmamap_t map; 310171384Sjfv}; 311171384Sjfv 312171384Sjfvstruct ixgbe_rx_buf { 313243714Sjfv struct mbuf *buf; 314205720Sjfv struct mbuf *fmp; 315244514Sluigi bus_dmamap_t pmap; 316239940Sscottl u_int flags; 317239940Sscottl#define IXGBE_RX_COPY 0x01 318243714Sjfv uint64_t addr; 319171384Sjfv}; 320171384Sjfv 321171384Sjfv/* 322171384Sjfv * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 323171384Sjfv */ 324171384Sjfvstruct ixgbe_dma_alloc { 325171384Sjfv bus_addr_t dma_paddr; 326171384Sjfv caddr_t dma_vaddr; 327171384Sjfv bus_dma_tag_t dma_tag; 328171384Sjfv bus_dmamap_t dma_map; 329171384Sjfv bus_dma_segment_t dma_seg; 330171384Sjfv bus_size_t dma_size; 331171384Sjfv int dma_nseg; 332171384Sjfv}; 333171384Sjfv 334295008Ssbrunostruct ixgbe_mc_addr { 335295008Ssbruno u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 336295008Ssbruno u32 vmdq; 337295008Ssbruno}; 338295008Ssbruno 339171384Sjfv/* 340205720Sjfv** Driver queue struct: this is the interrupt container 341205720Sjfv** for the associated tx and rx ring. 342205720Sjfv*/ 343205720Sjfvstruct ix_queue { 344205720Sjfv struct adapter *adapter; 345205720Sjfv u32 msix; /* This queue's MSIX vector */ 346205720Sjfv u32 eims; /* This queue's EIMS bit */ 347205720Sjfv u32 eitr_setting; 348283620Serj u32 me; 349205720Sjfv struct resource *res; 350205720Sjfv void *tag; 351283620Serj int busy; 352205720Sjfv struct tx_ring *txr; 353205720Sjfv struct rx_ring *rxr; 354205720Sjfv struct task que_task; 355205720Sjfv struct taskqueue *tq; 356205720Sjfv u64 irqs; 357205720Sjfv}; 358205720Sjfv 359205720Sjfv/* 360205720Sjfv * The transmit ring, one per queue 361171384Sjfv */ 362171384Sjfvstruct tx_ring { 363171384Sjfv struct adapter *adapter; 364179055Sjfv struct mtx tx_mtx; 365171384Sjfv u32 me; 366283620Serj u32 tail; 367283620Serj int busy; 368243729Sjfv union ixgbe_adv_tx_desc *tx_base; 369243729Sjfv struct ixgbe_tx_buf *tx_buffers; 370243729Sjfv struct ixgbe_dma_alloc txdma; 371243729Sjfv volatile u16 tx_avail; 372243729Sjfv u16 next_avail_desc; 373243729Sjfv u16 next_to_clean; 374243729Sjfv u16 num_desc; 375179055Sjfv u32 txd_cmd; 376171384Sjfv bus_dma_tag_t txtag; 377185352Sjfv char mtx_name[16]; 378243725Sjfv#ifndef IXGBE_LEGACY_TX 379194875Sjfv struct buf_ring *br; 380240968Sjhb struct task txq_task; 381194875Sjfv#endif 382200239Sjfv#ifdef IXGBE_FDIR 383200239Sjfv u16 atr_sample; 384200239Sjfv u16 atr_count; 385200239Sjfv#endif 386205720Sjfv u32 bytes; /* used for AIM */ 387205720Sjfv u32 packets; 388179055Sjfv /* Soft Stats */ 389243729Sjfv unsigned long tso_tx; 390243729Sjfv unsigned long no_tx_map_avail; 391243729Sjfv unsigned long no_tx_dma_setup; 392205720Sjfv u64 no_desc_avail; 393185352Sjfv u64 total_packets; 394171384Sjfv}; 395171384Sjfv 396171384Sjfv 397171384Sjfv/* 398171384Sjfv * The Receive ring, one per rx queue 399171384Sjfv */ 400171384Sjfvstruct rx_ring { 401179055Sjfv struct adapter *adapter; 402179055Sjfv struct mtx rx_mtx; 403179055Sjfv u32 me; 404283620Serj u32 tail; 405179055Sjfv union ixgbe_adv_rx_desc *rx_base; 406179055Sjfv struct ixgbe_dma_alloc rxdma; 407179055Sjfv struct lro_ctrl lro; 408194875Sjfv bool lro_enabled; 409200239Sjfv bool hw_rsc; 410230775Sjfv bool vtag_strip; 411243729Sjfv u16 next_to_refresh; 412243729Sjfv u16 next_to_check; 413243729Sjfv u16 num_desc; 414243729Sjfv u16 mbuf_sz; 415205720Sjfv char mtx_name[16]; 416179055Sjfv struct ixgbe_rx_buf *rx_buffers; 417244514Sluigi bus_dma_tag_t ptag; 418185352Sjfv 419185352Sjfv u32 bytes; /* Used for AIM calc */ 420205720Sjfv u32 packets; 421185352Sjfv 422171384Sjfv /* Soft stats */ 423179055Sjfv u64 rx_irq; 424239940Sscottl u64 rx_copies; 425185352Sjfv u64 rx_packets; 426185352Sjfv u64 rx_bytes; 427205720Sjfv u64 rx_discarded; 428200239Sjfv u64 rsc_num; 429200239Sjfv#ifdef IXGBE_FDIR 430200239Sjfv u64 flm; 431200239Sjfv#endif 432171384Sjfv}; 433171384Sjfv 434295008Ssbruno#ifdef PCI_IOV 435295008Ssbruno#define IXGBE_VF_CTS (1 << 0) /* VF is clear to send. */ 436295008Ssbruno#define IXGBE_VF_CAP_MAC (1 << 1) /* VF is permitted to change MAC. */ 437295008Ssbruno#define IXGBE_VF_CAP_VLAN (1 << 2) /* VF is permitted to join vlans. */ 438295008Ssbruno#define IXGBE_VF_ACTIVE (1 << 3) /* VF is active. */ 439295008Ssbruno 440295008Ssbruno#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ 441295008Ssbruno 442295008Ssbrunostruct ixgbe_vf { 443295008Ssbruno u_int pool; 444295008Ssbruno u_int rar_index; 445295008Ssbruno u_int max_frame_size; 446295008Ssbruno uint32_t flags; 447295008Ssbruno uint8_t ether_addr[ETHER_ADDR_LEN]; 448295008Ssbruno uint16_t mc_hash[IXGBE_MAX_VF_MC]; 449295008Ssbruno uint16_t num_mc_hashes; 450295008Ssbruno uint16_t default_vlan; 451295008Ssbruno uint16_t vlan_tag; 452295008Ssbruno uint16_t api_ver; 453295008Ssbruno}; 454295008Ssbruno#endif /* PCI_IOV */ 455295008Ssbruno 456171384Sjfv/* Our adapter structure */ 457171384Sjfvstruct adapter { 458205720Sjfv struct ixgbe_hw hw; 459295524Ssbruno struct ixgbe_osdep osdep; 460171384Sjfv 461205720Sjfv struct device *dev; 462295524Ssbruno struct ifnet *ifp; 463171384Sjfv 464205720Sjfv struct resource *pci_mem; 465205720Sjfv struct resource *msix_mem; 466179055Sjfv 467171384Sjfv /* 468194875Sjfv * Interrupt resources: this set is 469194875Sjfv * either used for legacy, or for Link 470194875Sjfv * when doing MSIX 471171384Sjfv */ 472205720Sjfv void *tag; 473205720Sjfv struct resource *res; 474171384Sjfv 475205720Sjfv struct ifmedia media; 476205720Sjfv struct callout timer; 477205720Sjfv int msix; 478205720Sjfv int if_flags; 479179055Sjfv 480205720Sjfv struct mtx core_mtx; 481179055Sjfv 482205720Sjfv eventhandler_tag vlan_attach; 483205720Sjfv eventhandler_tag vlan_detach; 484194875Sjfv 485205720Sjfv u16 num_vlans; 486205720Sjfv u16 num_queues; 487194875Sjfv 488215911Sjfv /* 489215911Sjfv ** Shadow VFTA table, this is needed because 490215911Sjfv ** the real vlan filter table gets cleared during 491215911Sjfv ** a soft reset and the driver needs to be able 492215911Sjfv ** to repopulate it. 493215911Sjfv */ 494215911Sjfv u32 shadow_vfta[IXGBE_VFTA_SIZE]; 495215911Sjfv 496215911Sjfv /* Info about the interface */ 497205720Sjfv u32 optics; 498230775Sjfv u32 fc; /* local flow ctrl setting */ 499209609Sjfv int advertise; /* link speeds */ 500295534Ssmh bool enable_aim; /* adaptive interrupt moderation */ 501205720Sjfv bool link_active; 502205720Sjfv u16 max_frame_size; 503217593Sjfv u16 num_segs; 504205720Sjfv u32 link_speed; 505205720Sjfv bool link_up; 506283620Serj u32 vector; 507283620Serj u16 dmac; 508283620Serj bool eee_enabled; 509295008Ssbruno u32 phy_layer; 510171384Sjfv 511283620Serj /* Power management-related */ 512283620Serj bool wol_support; 513283620Serj u32 wufc; 514283620Serj 515185352Sjfv /* Mbuf cluster size */ 516205720Sjfv u32 rx_mbuf_sz; 517171384Sjfv 518190873Sjfv /* Support for pluggable optics */ 519205720Sjfv bool sfp_probe; 520205720Sjfv struct task link_task; /* Link tasklet */ 521205720Sjfv struct task mod_task; /* SFP tasklet */ 522205720Sjfv struct task msf_task; /* Multispeed Fiber */ 523295008Ssbruno#ifdef PCI_IOV 524295008Ssbruno struct task mbx_task; /* VF -> PF mailbox interrupt */ 525295008Ssbruno#endif /* PCI_IOV */ 526200239Sjfv#ifdef IXGBE_FDIR 527200239Sjfv int fdir_reinit; 528200239Sjfv struct task fdir_task; 529200239Sjfv#endif 530283620Serj struct task phy_task; /* PHY intr tasklet */ 531190873Sjfv struct taskqueue *tq; 532185352Sjfv 533171384Sjfv /* 534205720Sjfv ** Queues: 535205720Sjfv ** This is the irq holder, it has 536205720Sjfv ** and RX/TX pair or rings associated 537205720Sjfv ** with it. 538205720Sjfv */ 539205720Sjfv struct ix_queue *queues; 540205720Sjfv 541205720Sjfv /* 542171384Sjfv * Transmit rings: 543171384Sjfv * Allocated at run time, an array of rings. 544171384Sjfv */ 545205720Sjfv struct tx_ring *tx_rings; 546243729Sjfv u32 num_tx_desc; 547294034Ssbruno u32 tx_process_limit; 548171384Sjfv 549171384Sjfv /* 550171384Sjfv * Receive rings: 551171384Sjfv * Allocated at run time, an array of rings. 552171384Sjfv */ 553205720Sjfv struct rx_ring *rx_rings; 554283620Serj u64 active_queues; 555243729Sjfv u32 num_rx_desc; 556294034Ssbruno u32 rx_process_limit; 557171384Sjfv 558215914Sjfv /* Multicast array memory */ 559295008Ssbruno struct ixgbe_mc_addr *mta; 560295008Ssbruno int num_vfs; 561295008Ssbruno int pool; 562295008Ssbruno#ifdef PCI_IOV 563295008Ssbruno struct ixgbe_vf *vfs; 564295008Ssbruno#endif 565295524Ssbruno#ifdef DEV_NETMAP 566295524Ssbruno void (*init_locked)(struct adapter *); 567295524Ssbruno void (*stop_locked)(void *); 568295524Ssbruno#endif 569215914Sjfv 570171384Sjfv /* Misc stats maintained by the driver */ 571205720Sjfv unsigned long dropped_pkts; 572205720Sjfv unsigned long mbuf_defrag_failed; 573205720Sjfv unsigned long mbuf_header_failed; 574205720Sjfv unsigned long mbuf_packet_failed; 575205720Sjfv unsigned long watchdog_events; 576205720Sjfv unsigned long link_irq; 577283620Serj union { 578283620Serj struct ixgbe_hw_stats pf; 579283620Serj struct ixgbevf_hw_stats vf; 580283620Serj } stats; 581283620Serj#if __FreeBSD_version >= 1100036 582283620Serj /* counter(9) stats */ 583283620Serj u64 ipackets; 584283620Serj u64 ierrors; 585283620Serj u64 opackets; 586283620Serj u64 oerrors; 587283620Serj u64 ibytes; 588283620Serj u64 obytes; 589283620Serj u64 imcasts; 590283620Serj u64 omcasts; 591283620Serj u64 iqdrops; 592283620Serj u64 noproto; 593283620Serj#endif 594171384Sjfv}; 595171384Sjfv 596251964Sjfv 597190873Sjfv/* Precision Time Sync (IEEE 1588) defines */ 598190873Sjfv#define ETHERTYPE_IEEE1588 0x88F7 599190873Sjfv#define PICOSECS_PER_TICK 20833 600190873Sjfv#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 601190873Sjfv#define IXGBE_ADVTXD_TSTAMP 0x00080000 602190873Sjfv 603190873Sjfv 604179055Sjfv#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 605179055Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 606179055Sjfv#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 607200239Sjfv#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 608200239Sjfv#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 609179055Sjfv#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 610200239Sjfv#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 611200239Sjfv#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 612200239Sjfv#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 613179055Sjfv#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 614179055Sjfv#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 615179055Sjfv#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 616179055Sjfv#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 617179055Sjfv#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 618179055Sjfv 619251964Sjfv/* For backward compatibility */ 620251964Sjfv#if !defined(PCIER_LINK_STA) 621251964Sjfv#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 622251964Sjfv#endif 623179055Sjfv 624283620Serj/* Stats macros */ 625283620Serj#if __FreeBSD_version >= 1100036 626283620Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 627283620Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 628283620Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 629283620Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 630283620Serj#define IXGBE_SET_COLLISIONS(sc, count) 631283620Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 632283620Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 633283620Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 634283620Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 635283620Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 636283620Serj#else 637283620Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 638283620Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 639283620Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 640283620Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 641283620Serj#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 642283620Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 643283620Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 644283620Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 645283620Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 646283620Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 647283620Serj#endif 648283620Serj 649283620Serj/* External PHY register addresses */ 650283620Serj#define IXGBE_PHY_CURRENT_TEMP 0xC820 651283620Serj#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 652283620Serj 653283620Serj/* Sysctl help messages; displayed with sysctl -d */ 654283620Serj#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 655283620Serj "\nControl advertised link speed using these flags:\n" \ 656283620Serj "\t0x1 - advertise 100M\n" \ 657283620Serj "\t0x2 - advertise 1G\n" \ 658283620Serj "\t0x4 - advertise 10G\n\n" \ 659283620Serj "\t100M is only supported on certain 10GBaseT adapters.\n" 660283620Serj 661283620Serj#define IXGBE_SYSCTL_DESC_SET_FC \ 662283620Serj "\nSet flow control mode using these values:\n" \ 663283620Serj "\t0 - off\n" \ 664283620Serj "\t1 - rx pause\n" \ 665283620Serj "\t2 - tx pause\n" \ 666283620Serj "\t3 - tx and rx pause" 667283620Serj 668190873Sjfvstatic inline bool 669190873Sjfvixgbe_is_sfp(struct ixgbe_hw *hw) 670190873Sjfv{ 671190873Sjfv switch (hw->phy.type) { 672190873Sjfv case ixgbe_phy_sfp_avago: 673190873Sjfv case ixgbe_phy_sfp_ftl: 674190873Sjfv case ixgbe_phy_sfp_intel: 675190873Sjfv case ixgbe_phy_sfp_unknown: 676205720Sjfv case ixgbe_phy_sfp_passive_tyco: 677205720Sjfv case ixgbe_phy_sfp_passive_unknown: 678283620Serj case ixgbe_phy_qsfp_passive_unknown: 679283620Serj case ixgbe_phy_qsfp_active_unknown: 680283620Serj case ixgbe_phy_qsfp_intel: 681283620Serj case ixgbe_phy_qsfp_unknown: 682190873Sjfv return TRUE; 683190873Sjfv default: 684190873Sjfv return FALSE; 685190873Sjfv } 686190873Sjfv} 687190873Sjfv 688208762Sjfv/* Workaround to make 8.0 buildable */ 689217129Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 690208762Sjfvstatic __inline int 691208762Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 692208762Sjfv{ 693208762Sjfv#ifdef ALTQ 694208762Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 695208762Sjfv return (1); 696208762Sjfv#endif 697208762Sjfv return (!buf_ring_empty(br)); 698208762Sjfv} 699208762Sjfv#endif 700208762Sjfv 701221041Sjfv/* 702221041Sjfv** Find the number of unrefreshed RX descriptors 703221041Sjfv*/ 704221041Sjfvstatic inline u16 705221041Sjfvixgbe_rx_unrefreshed(struct rx_ring *rxr) 706221041Sjfv{ 707221041Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 708221041Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 709221041Sjfv else 710243729Sjfv return ((rxr->num_desc + rxr->next_to_check) - 711221041Sjfv rxr->next_to_refresh - 1); 712221041Sjfv} 713221041Sjfv 714283620Serj/* 715283620Serj** This checks for a zero mac addr, something that will be likely 716283620Serj** unless the Admin on the Host has created one. 717283620Serj*/ 718283620Serjstatic inline bool 719283620Serjixv_check_ether_addr(u8 *addr) 720283620Serj{ 721283620Serj bool status = TRUE; 722283620Serj 723283620Serj if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 724283620Serj addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 725283620Serj status = FALSE; 726283620Serj return (status); 727283620Serj} 728283620Serj 729283620Serj/* Shared Prototypes */ 730283620Serj 731283620Serj#ifdef IXGBE_LEGACY_TX 732283620Serjvoid ixgbe_start(struct ifnet *); 733283620Serjvoid ixgbe_start_locked(struct tx_ring *, struct ifnet *); 734283620Serj#else /* ! IXGBE_LEGACY_TX */ 735283620Serjint ixgbe_mq_start(struct ifnet *, struct mbuf *); 736283620Serjint ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); 737283620Serjvoid ixgbe_qflush(struct ifnet *); 738283620Serjvoid ixgbe_deferred_mq_start(void *, int); 739283620Serj#endif /* IXGBE_LEGACY_TX */ 740283620Serj 741283620Serjint ixgbe_allocate_queues(struct adapter *); 742283620Serjint ixgbe_allocate_transmit_buffers(struct tx_ring *); 743283620Serjint ixgbe_setup_transmit_structures(struct adapter *); 744283620Serjvoid ixgbe_free_transmit_structures(struct adapter *); 745283620Serjint ixgbe_allocate_receive_buffers(struct rx_ring *); 746283620Serjint ixgbe_setup_receive_structures(struct adapter *); 747283620Serjvoid ixgbe_free_receive_structures(struct adapter *); 748283620Serjvoid ixgbe_txeof(struct tx_ring *); 749283620Serjbool ixgbe_rxeof(struct ix_queue *); 750283620Serj 751283620Serjint ixgbe_dma_malloc(struct adapter *, 752283620Serj bus_size_t, struct ixgbe_dma_alloc *, int); 753283620Serjvoid ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *); 754295008Ssbruno 755295008Ssbruno#ifdef PCI_IOV 756295008Ssbruno 757295008Ssbrunostatic inline boolean_t 758295008Ssbrunoixgbe_vf_mac_changed(struct ixgbe_vf *vf, const uint8_t *mac) 759295008Ssbruno{ 760295008Ssbruno return (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) != 0); 761295008Ssbruno} 762295008Ssbruno 763295008Ssbrunostatic inline void 764295008Ssbrunoixgbe_send_vf_msg(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) 765295008Ssbruno{ 766295008Ssbruno 767295008Ssbruno if (vf->flags & IXGBE_VF_CTS) 768295008Ssbruno msg |= IXGBE_VT_MSGTYPE_CTS; 769295008Ssbruno 770295008Ssbruno ixgbe_write_mbx(&adapter->hw, &msg, 1, vf->pool); 771295008Ssbruno} 772295008Ssbruno 773295008Ssbrunostatic inline void 774295008Ssbrunoixgbe_send_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) 775295008Ssbruno{ 776295008Ssbruno msg &= IXGBE_VT_MSG_MASK; 777295008Ssbruno ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_ACK); 778295008Ssbruno} 779295008Ssbruno 780295008Ssbrunostatic inline void 781295008Ssbrunoixgbe_send_vf_nack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) 782295008Ssbruno{ 783295008Ssbruno msg &= IXGBE_VT_MSG_MASK; 784295008Ssbruno ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_NACK); 785295008Ssbruno} 786295008Ssbruno 787295008Ssbrunostatic inline void 788295008Ssbrunoixgbe_process_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf) 789295008Ssbruno{ 790295008Ssbruno if (!(vf->flags & IXGBE_VF_CTS)) 791295008Ssbruno ixgbe_send_vf_nack(adapter, vf, 0); 792295008Ssbruno} 793295008Ssbruno 794295008Ssbrunostatic inline enum ixgbe_iov_mode 795295008Ssbrunoixgbe_get_iov_mode(struct adapter *adapter) 796295008Ssbruno{ 797295008Ssbruno if (adapter->num_vfs == 0) 798295008Ssbruno return (IXGBE_NO_VM); 799295008Ssbruno if (adapter->num_queues <= 2) 800295008Ssbruno return (IXGBE_64_VM); 801295008Ssbruno else if (adapter->num_queues <= 4) 802295008Ssbruno return (IXGBE_32_VM); 803295008Ssbruno else 804295008Ssbruno return (IXGBE_NO_VM); 805295008Ssbruno} 806295008Ssbruno 807295008Ssbrunostatic inline u16 808295008Ssbrunoixgbe_max_vfs(enum ixgbe_iov_mode mode) 809295008Ssbruno{ 810295008Ssbruno /* 811295008Ssbruno * We return odd numbers below because we 812295008Ssbruno * reserve 1 VM's worth of queues for the PF. 813295008Ssbruno */ 814295008Ssbruno switch (mode) { 815295008Ssbruno case IXGBE_64_VM: 816295008Ssbruno return (63); 817295008Ssbruno case IXGBE_32_VM: 818295008Ssbruno return (31); 819295008Ssbruno case IXGBE_NO_VM: 820295008Ssbruno default: 821295008Ssbruno return (0); 822295008Ssbruno } 823295008Ssbruno} 824295008Ssbruno 825295008Ssbrunostatic inline int 826295008Ssbrunoixgbe_vf_queues(enum ixgbe_iov_mode mode) 827295008Ssbruno{ 828295008Ssbruno switch (mode) { 829295008Ssbruno case IXGBE_64_VM: 830295008Ssbruno return (2); 831295008Ssbruno case IXGBE_32_VM: 832295008Ssbruno return (4); 833295008Ssbruno case IXGBE_NO_VM: 834295008Ssbruno default: 835295008Ssbruno return (0); 836295008Ssbruno } 837295008Ssbruno} 838295008Ssbruno 839295008Ssbrunostatic inline int 840295008Ssbrunoixgbe_vf_que_index(enum ixgbe_iov_mode mode, u32 vfnum, int num) 841295008Ssbruno{ 842295008Ssbruno return ((vfnum * ixgbe_vf_queues(mode)) + num); 843295008Ssbruno} 844295008Ssbruno 845295008Ssbrunostatic inline int 846295008Ssbrunoixgbe_pf_que_index(enum ixgbe_iov_mode mode, int num) 847295008Ssbruno{ 848295008Ssbruno return (ixgbe_vf_que_index(mode, ixgbe_max_vfs(mode), num)); 849295008Ssbruno} 850295008Ssbruno 851295008Ssbrunostatic inline void 852295008Ssbrunoixgbe_update_max_frame(struct adapter * adapter, int max_frame) 853295008Ssbruno{ 854295008Ssbruno if (adapter->max_frame_size < max_frame) 855295008Ssbruno adapter->max_frame_size = max_frame; 856295008Ssbruno} 857295008Ssbruno 858295008Ssbrunostatic inline u32 859295008Ssbrunoixgbe_get_mrqc(enum ixgbe_iov_mode mode) 860295008Ssbruno{ 861295008Ssbruno u32 mrqc = 0; 862295008Ssbruno switch (mode) { 863295008Ssbruno case IXGBE_64_VM: 864295008Ssbruno mrqc = IXGBE_MRQC_VMDQRSS64EN; 865295008Ssbruno break; 866295008Ssbruno case IXGBE_32_VM: 867295008Ssbruno mrqc = IXGBE_MRQC_VMDQRSS32EN; 868295008Ssbruno break; 869295008Ssbruno case IXGBE_NO_VM: 870295008Ssbruno mrqc = 0; 871295008Ssbruno break; 872295008Ssbruno default: 873295008Ssbruno panic("Unexpected SR-IOV mode %d", mode); 874295008Ssbruno } 875295008Ssbruno return(mrqc); 876295008Ssbruno} 877295008Ssbruno 878295008Ssbruno 879295008Ssbrunostatic inline u32 880295008Ssbrunoixgbe_get_mtqc(enum ixgbe_iov_mode mode) 881295008Ssbruno{ 882295008Ssbruno uint32_t mtqc = 0; 883295008Ssbruno switch (mode) { 884295008Ssbruno case IXGBE_64_VM: 885295008Ssbruno mtqc |= IXGBE_MTQC_64VF | IXGBE_MTQC_VT_ENA; 886295008Ssbruno break; 887295008Ssbruno case IXGBE_32_VM: 888295008Ssbruno mtqc |= IXGBE_MTQC_32VF | IXGBE_MTQC_VT_ENA; 889295008Ssbruno break; 890295008Ssbruno case IXGBE_NO_VM: 891295008Ssbruno mtqc = IXGBE_MTQC_64Q_1PB; 892295008Ssbruno break; 893295008Ssbruno default: 894295008Ssbruno panic("Unexpected SR-IOV mode %d", mode); 895295008Ssbruno } 896295008Ssbruno return(mtqc); 897295008Ssbruno} 898295008Ssbruno#endif /* PCI_IOV */ 899295008Ssbruno 900171384Sjfv#endif /* _IXGBE_H_ */ 901