ispreg.h revision 52346
1314125Sdelphij/* $FreeBSD: head/sys/dev/isp/ispreg.h 52346 1999-10-17 18:41:47Z mjacob $ */ 296593Smarkm/* 396593Smarkm * Machine Independent (well, as best as possible) register 4142429Snectar * definitions for Qlogic ISP SCSI adapters. 596593Smarkm * 696593Smarkm * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 796593Smarkm * NASA/Ames Research Center 896593Smarkm * All rights reserved. 996593Smarkm * 1096593Smarkm * Redistribution and use in source and binary forms, with or without 1196593Smarkm * modification, are permitted provided that the following conditions 1296593Smarkm * are met: 1396593Smarkm * 1. Redistributions of source code must retain the above copyright 1496593Smarkm * notice immediately at the beginning of the file, without modification, 1596593Smarkm * this list of conditions, and the following disclaimer. 1696593Smarkm * 2. Redistributions in binary form must reproduce the above copyright 1796593Smarkm * notice, this list of conditions and the following disclaimer in the 1896593Smarkm * documentation and/or other materials provided with the distribution. 1996593Smarkm * 3. The name of the author may not be used to endorse or promote products 20215698Ssimon * derived from this software without specific prior written permission. 21215698Ssimon * 22215698Ssimon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23215698Ssimon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24215698Ssimon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2596593Smarkm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2696593Smarkm * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2796593Smarkm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2896593Smarkm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2996593Smarkm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3096593Smarkm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3196593Smarkm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3296593Smarkm * SUCH DAMAGE. 3396593Smarkm */ 3496593Smarkm#ifndef _ISPREG_H 3596593Smarkm#define _ISPREG_H 3696593Smarkm 3796593Smarkm/* 3896593Smarkm * Hardware definitions for the Qlogic ISP registers. 3996593Smarkm */ 4096593Smarkm 41276861Sjkim/* 42276861Sjkim * This defines types of access to various registers. 4396593Smarkm * 4496593Smarkm * R: Read Only 45215698Ssimon * W: Write Only 46215698Ssimon * RW: Read/Write 47215698Ssimon * 48215698Ssimon * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 49314125Sdelphij * if RISC processor in ISP is paused. 50215698Ssimon */ 51142429Snectar 52142429Snectar/* 53276861Sjkim * Offsets for various register blocks. 54276861Sjkim * 55276861Sjkim * Sad but true, different architectures have different offsets. 5696593Smarkm * 57314125Sdelphij * Don't be alarmed if none of this makes sense. The original register 58314125Sdelphij * layout set some defines in a certain pattern. Everything else has been 59314125Sdelphij * grafted on since. For example, the ISP1080 manual will state that DMA 60314125Sdelphij * registers start at 0x80 from the base of the register address space. 61215698Ssimon * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 62314125Sdelphij * to start at offset 0x60 because the DMA registers are all defined to 63314125Sdelphij * be DMA_BLOCK+0x20 and so on. Clear? 64314125Sdelphij */ 65276861Sjkim 66215698Ssimon#define BIU_REGS_OFF 0x00 6796593Smarkm 6896593Smarkm#define PCI_MBOX_REGS_OFF 0x70 6996593Smarkm#define PCI_MBOX_REGS2100_OFF 0x10 7096593Smarkm#define SBUS_MBOX_REGS_OFF 0x80 7196593Smarkm 7296593Smarkm#define PCI_SXP_REGS_OFF 0x80 7396593Smarkm#define SBUS_SXP_REGS_OFF 0x200 7496593Smarkm 7596593Smarkm#define PCI_RISC_REGS_OFF 0x80 7696593Smarkm#define SBUS_RISC_REGS_OFF 0x400 7796593Smarkm 7896593Smarkm/* Bless me! Chip designers have putzed it again! */ 7996593Smarkm#define ISP1080_DMA_REGS_OFF 0x60 8096593Smarkm#define DMA_REGS_OFF 0x00 /* same as BIU block */ 8196593Smarkm 8296593Smarkm/* 8396593Smarkm * NB: The *_BLOCK definitions have no specific hardware meaning. 8496593Smarkm * They serve simply to note to the MD layer which block of 8596593Smarkm * registers offsets are being accessed. 8696593Smarkm */ 8796593Smarkm#define _NREG_BLKS 5 8896593Smarkm#define _BLK_REG_SHFT 13 8996593Smarkm#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 9096593Smarkm#define BIU_BLOCK (0 << _BLK_REG_SHFT) 9196593Smarkm#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 9296593Smarkm#define SXP_BLOCK (2 << _BLK_REG_SHFT) 9396593Smarkm#define RISC_BLOCK (3 << _BLK_REG_SHFT) 9496593Smarkm#define DMA_BLOCK (4 << _BLK_REG_SHFT) 9596593Smarkm 9696593Smarkm/* 9796593Smarkm * Bus Interface Block Register Offsets 9896593Smarkm */ 9996593Smarkm 10096593Smarkm#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 10196593Smarkm#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 10296593Smarkm#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 10396593Smarkm#define BIU2100_FLASH_DATA BIU_BLOCK+0x2 10496593Smarkm#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 10596593Smarkm#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 10696593Smarkm#define BIU2100_CSR BIU_BLOCK+0x6 10796593Smarkm#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 10896593Smarkm#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 10996593Smarkm#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 11096593Smarkm#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 11196593Smarkm#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 11296593Smarkm#define RDMA2100_CONTROL DFIFO_COMMAND 11396593Smarkm#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 11496593Smarkm 11596593Smarkm/* 11696593Smarkm * Putzed DMA register layouts. 11796593Smarkm */ 11896593Smarkm#define CDMA_CONF DMA_BLOCK+0x20 /* RW*: DMA Configuration */ 11996593Smarkm#define CDMA2100_CONTROL CDMA_CONF 12096593Smarkm#define CDMA_CONTROL DMA_BLOCK+0x22 /* RW*: DMA Control */ 12196593Smarkm#define CDMA_STATUS DMA_BLOCK+0x24 /* R : DMA Status */ 12296593Smarkm#define CDMA_FIFO_STS DMA_BLOCK+0x26 /* R : DMA FIFO Status */ 12396593Smarkm#define CDMA_COUNT DMA_BLOCK+0x28 /* RW*: DMA Transfer Count */ 12496593Smarkm#define CDMA_ADDR0 DMA_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 12596593Smarkm#define CDMA_ADDR1 DMA_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 12696593Smarkm#define CDMA_ADDR2 DMA_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 12796593Smarkm#define CDMA_ADDR3 DMA_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 12896593Smarkm 129142429Snectar#define DDMA_CONF DMA_BLOCK+0x40 /* RW*: DMA Configuration */ 13096593Smarkm#define TDMA2100_CONTROL DDMA_CONF 131100946Snectar#define DDMA_CONTROL DMA_BLOCK+0x42 /* RW*: DMA Control */ 132314125Sdelphij#define DDMA_STATUS DMA_BLOCK+0x44 /* R : DMA Status */ 133215698Ssimon#define DDMA_FIFO_STS DMA_BLOCK+0x46 /* R : DMA FIFO Status */ 134215698Ssimon#define DDMA_COUNT_LO DMA_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 135215698Ssimon#define DDMA_COUNT_HI DMA_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 136215698Ssimon#define DDMA_ADDR0 DMA_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 13796593Smarkm#define DDMA_ADDR1 DMA_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 138142429Snectar/* these are for the 1040A cards */ 13996593Smarkm#define DDMA_ADDR2 DMA_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 14096593Smarkm#define DDMA_ADDR3 DMA_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 14196593Smarkm 14296593Smarkm 143215698Ssimon/* 14496593Smarkm * Bus Interface Block Register Definitions 14596593Smarkm */ 14696593Smarkm/* BUS CONFIGURATION REGISTER #0 */ 14796593Smarkm#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 148276861Sjkim/* BUS CONFIGURATION REGISTER #1 */ 14996593Smarkm 15096593Smarkm#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 15196593Smarkm#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 15296593Smarkm 15396593Smarkm#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 154142429Snectar#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 15596593Smarkm#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 15696593Smarkm#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 15796593Smarkm#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 158#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 159#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 160#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 161#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 162#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 163#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 164 165#define BIU_PCI1080_CONF1_SXP 0x0100 /* SXP bank select */ 166#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 167 168/* ISP2100 Bus Control/Status Register */ 169 170#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 171#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 172#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 173#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 174#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 175#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 176#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 177#define BIU2100_SOFT_RESET 0x01 178/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 179 180 181/* BUS CONTROL REGISTER */ 182#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 183#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 184#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 185#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 186#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 187#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 188 189#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 190#define BIU2100_ICR_ENA_FPM_INT 0x0020 191#define BIU2100_ICR_ENA_FB_INT 0x0010 192#define BIU2100_ICR_ENA_RISC_INT 0x0008 193#define BIU2100_ICR_ENA_CDMA_INT 0x0004 194#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 195#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 196#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 197 198#define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 199 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 200 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 201 202#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 203 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 204 (ISP_READ(isp, BIU_ICR) & \ 205 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 206 207#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 208 209/* BUS STATUS REGISTER */ 210#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 211#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 212#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 213#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 214#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 215 216#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 217#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 218#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 219#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 220#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 221#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 222#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 223 224#define INT_PENDING(isp, isr) (IS_FC(isp)? \ 225 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 226 227/* BUS SEMAPHORE REGISTER */ 228#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 229#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 230 231/* NVRAM SEMAPHORE REGISTER */ 232#define BIU_NVRAM_CLOCK 0x0001 233#define BIU_NVRAM_SELECT 0x0002 234#define BIU_NVRAM_DATAOUT 0x0004 235#define BIU_NVRAM_DATAIN 0x0008 236#define ISP_NVRAM_READ 6 237 238/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 239#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 240#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 241#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 242#define DMA_DMA_DIRECTION 0x0001 /* 243 * Set DMA direction: 244 * 0 - DMA FIFO to host 245 * 1 - Host to DMA FIFO 246 */ 247 248/* COMMAND && DATA DMA CONTROL REGISTER */ 249#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 250#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 251 * Clear FIFO and DMA Channel, 252 * reset DMA registers 253 */ 254#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 255#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 256#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 257 258/* 259 * Variants of same for 2100 260 */ 261#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 262#define DMA_CNTRL2100_RESET_INT 0x0002 263 264 265 266/* DMA STATUS REGISTER */ 267#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 268#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 269#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 270#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 271#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 272#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 273 274#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 275#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 276#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 277#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 278#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 279#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 280#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 281#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 282#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 283#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 284#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 285 286/* DMA Status Register, pipeline status bits */ 287#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 288#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 289#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 290 * Pipeline stage 1 Loaded, 291 * stage 2 empty 292 */ 293#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 294#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 295#define DMA_PCI_PIPE_STAGE1 0x0001 /* 296 * Pipeline stage 1 Loaded, 297 * stage 2 empty 298 */ 299#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 300 301/* DMA Status Register, channel status bits */ 302#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 303#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 304#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 305#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 306#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 307#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 308#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 309 310 311/* DMA FIFO STATUS REGISTER */ 312#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 313#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 314#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 315#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 316 317/* 318 * Mailbox Block Register Offsets 319 */ 320 321#define INMAILBOX0 MBOX_BLOCK+0x0 322#define INMAILBOX1 MBOX_BLOCK+0x2 323#define INMAILBOX2 MBOX_BLOCK+0x4 324#define INMAILBOX3 MBOX_BLOCK+0x6 325#define INMAILBOX4 MBOX_BLOCK+0x8 326#define INMAILBOX5 MBOX_BLOCK+0xA 327#define INMAILBOX6 MBOX_BLOCK+0xC 328#define INMAILBOX7 MBOX_BLOCK+0xE 329 330#define OUTMAILBOX0 MBOX_BLOCK+0x0 331#define OUTMAILBOX1 MBOX_BLOCK+0x2 332#define OUTMAILBOX2 MBOX_BLOCK+0x4 333#define OUTMAILBOX3 MBOX_BLOCK+0x6 334#define OUTMAILBOX4 MBOX_BLOCK+0x8 335#define OUTMAILBOX5 MBOX_BLOCK+0xA 336#define OUTMAILBOX6 MBOX_BLOCK+0xC 337#define OUTMAILBOX7 MBOX_BLOCK+0xE 338 339#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 340#define NMBOX(isp) \ 341 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 342 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 343 344/* 345 * SXP Block Register Offsets 346 */ 347#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 348#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 349#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 350#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 351#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 352#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 353#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 354#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 355#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 356#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 357#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 358#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 359#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 360#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 361#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 362#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 363#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 364#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 365#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 366#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 367#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 368#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 369#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 370#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 371#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 372#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 373#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 374#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 375#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 376#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 377#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 378#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 379#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 380#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 381#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 382#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 383#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 384#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 385#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 386 387 388/* SXP CONF1 REGISTER */ 389#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 390#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 391#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 392#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 393#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 394 395/* SXP CONF2 REGISTER */ 396#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 397#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 398#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 399#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 400#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 401#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 402 403/* SXP INTERRUPT REGISTER */ 404#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 405#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 406#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 407#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 408#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 409#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 410#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 411#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 412#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 413#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 414 415 416/* SXP GROSS ERROR REGISTER */ 417#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 418#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 419#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 420#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 421#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 422#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 423#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 424 425/* SXP EXCEPTION REGISTER */ 426#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 427#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 428#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 429#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 430#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 431#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 432#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 433#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 434#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 435#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 436 437 /* SXP OVERRIDE REGISTER */ 438#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 439#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 440#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 441#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 442#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 443#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 444#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 445#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 446#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 447#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 448#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 449#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 450#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 451 452/* SXP COMMANDS */ 453#define SXP_RESET_BUS_CMD 0x300b 454 455/* SXP SCSI ID REGISTER */ 456#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 457#define SXP_SELECT_ID 0x000F /* Select id */ 458 459/* SXP DEV CONFIG1 REGISTER */ 460#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 461#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 462#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 463 464 465/* SXP DEV CONFIG2 REGISTER */ 466#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 467#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 468#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 469#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 470#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 471 472 473/* SXP PHASE POINTER REGISTER */ 474#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 475#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 476#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 477#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 478 479 480/* SXP FIFO STATUS REGISTER */ 481#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 482#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 483#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 484#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 485 486 487/* SXP CONTROL PINS REGISTER */ 488#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 489#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 490#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 491#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 492#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 493#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 494#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 495#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 496#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 497#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 498#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 499#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 500 501/* 502 * Set the hold time for the SCSI Bus Reset to be 250 ms 503 */ 504#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 505 506/* SXP DIFF PINS REGISTER */ 507#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 508#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 509#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 510#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 511#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 512#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 513 514/* 1080 only */ 515#define SXP_PINS_LVD_MODE 0x1000 516#define SXP_PINS_HVD_MODE 0x0800 517#define SXP_PINS_SE_MODE 0x0400 518 519/* The above have to be put together with the DIFFM pin to make sense */ 520#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 521#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 522#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 523#define ISP1080_MODE_MASK \ 524 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 525 526/* 527 * RISC and Host Command and Control Block Register Offsets 528 */ 529 530#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 531#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 532#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 533#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 534#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 535#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 536#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 537#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 538#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 539#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 540#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 541#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 542#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 543#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 544#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 545#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 546#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 547#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 548#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 549#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 550#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 551#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 552#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 553#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 554#define RISC_MTR2100 RISC_BLOCK+0x30 555 556#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 557#define DUAL_BANK 8 558#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 559#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 560#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 561#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 562#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 563#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 564#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 565 566 567/* PROCESSOR STATUS REGISTER */ 568#define RISC_PSR_FORCE_TRUE 0x8000 569#define RISC_PSR_LOOP_COUNT_DONE 0x4000 570#define RISC_PSR_RISC_INT 0x2000 571#define RISC_PSR_TIMER_ROLLOVER 0x1000 572#define RISC_PSR_ALU_OVERFLOW 0x0800 573#define RISC_PSR_ALU_MSB 0x0400 574#define RISC_PSR_ALU_CARRY 0x0200 575#define RISC_PSR_ALU_ZERO 0x0100 576 577#define RISC_PSR_PCI_ULTRA 0x0080 578#define RISC_PSR_SBUS_ULTRA 0x0020 579 580#define RISC_PSR_DMA_INT 0x0010 581#define RISC_PSR_SXP_INT 0x0008 582#define RISC_PSR_HOST_INT 0x0004 583#define RISC_PSR_INT_PENDING 0x0002 584#define RISC_PSR_FORCE_FALSE 0x0001 585 586 587/* Host Command and Control */ 588#define HCCR_CMD_NOP 0x0000 /* NOP */ 589#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 590#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 591#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 592#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 593#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 594#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 595#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 596#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 597#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 598#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 599#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 600#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 601 602#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 603#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 604#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 605#define ISP2100_HCCR_PARITY 0x0001 606 607#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 608#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 609#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 610 611#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 612#define HCCR_RESET 0x0040 /* R : reset in progress */ 613#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 614 615#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 616 617/* 618 * NVRAM Definitions (PCI cards only) 619 */ 620 621#define ISPBSMX(c, byte, shift, mask) \ 622 (((c)[(byte)] >> (shift)) & (mask)) 623/* 624 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 625 * 626 * Some portion of the front of this is for general host adapter properties 627 * This is followed by an array of per-target parameters, and is tailed off 628 * with a checksum xor byte at offset 127. For non-byte entities data is 629 * stored in Little Endian order. 630 */ 631 632#define ISP_NVRAM_SIZE 128 633 634#define ISP_NVRAM_VERSION(c) (c)[4] 635#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 636#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 637#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 638#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 639#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 640#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 641#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 642#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 643#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 644#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 645#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 646#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 647#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 648#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 649#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 650#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 651#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 652#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 653#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 654#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 655#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 656#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 657#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 658#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 659#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 660#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 661#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 662#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 663#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 664 665#define ISP_NVRAM_TARGOFF 28 666#define ISP_NVARM_TARGSIZE 6 667#define _IxT(tgt, tidx) \ 668 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 669#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 670#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 671#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 672#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 673#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 674#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 675#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 676#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 677#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 678#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 679#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 680#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 681#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 682 683/* 684 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 685 * 686 * Some portion of the front of this is for general host adapter properties 687 * This is followed by an array of per-target parameters, and is tailed off 688 * with a checksum xor byte at offset 256. For non-byte entities data is 689 * stored in Little Endian order. 690 */ 691 692#define ISP1080_NVRAM_SIZE 256 693 694#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 695 696/* Offset 5 */ 697/* 698 uint8_t bios_configuration_mode :2; 699 uint8_t bios_disable :1; 700 uint8_t selectable_scsi_boot_enable :1; 701 uint8_t cd_rom_boot_enable :1; 702 uint8_t disable_loading_risc_code :1; 703 uint8_t enable_64bit_addressing :1; 704 uint8_t unused_7 :1; 705 */ 706 707/* Offsets 6, 7 */ 708/* 709 uint8_t boot_lun_number :5; 710 uint8_t scsi_bus_number :1; 711 uint8_t unused_6 :1; 712 uint8_t unused_7 :1; 713 uint8_t boot_target_number :4; 714 uint8_t unused_12 :1; 715 uint8_t unused_13 :1; 716 uint8_t unused_14 :1; 717 uint8_t unused_15 :1; 718 */ 719 720#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 721 722#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 723#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 724 725#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 726#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 727#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 728 729#define ISP1080_ISP_PARAMETER(c) \ 730 (((c)[18]) | ((c)[19] << 8)) 731 732#define ISP1080_FAST_POST ISPBSMX(c, 20, 0, 0x01) 733#define ISP1080_REPORT_LVD_TRANSITION ISPBSMX(c, 20, 1, 0x01) 734 735#define ISP1080_BUS1_OFF 112 736 737#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 738 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 739#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 740 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 741#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 742 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 743#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 744 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 745 746#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 747 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 748#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 749 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 750#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 751 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 752#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 753 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 754 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 755#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 756 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 757 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 758 759#define ISP1080_NVRAM_TARGOFF(b) \ 760 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 761#define ISP1080_NVRAM_TARGSIZE 6 762#define _IxT8(tgt, tidx, b) \ 763 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 764 765#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 766 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 767#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 768 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 769#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 770 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 771#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 772 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 773#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 774 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 775#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 776 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 777#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 778 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 779#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 780 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 781#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 782 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 783#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 784 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 785#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 786 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 787#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 788 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 789#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 790 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 791 792/* 793 * Qlogic 2XXX NVRAM is an array of 256 bytes. 794 * 795 * Some portion of the front of this is for general RISC engine parameters, 796 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 797 * 798 * This is followed by some general host adapter parameters, and ends with 799 * a checksum xor byte at offset 255. For non-byte entities data is stored 800 * in Little Endian order. 801 */ 802#define ISP2100_NVRAM_SIZE 256 803/* ISP_NVRAM_VERSION is in same overall place */ 804#define ISP2100_NVRAM_RISCVER(c) (c)[6] 805#define ISP2100_NVRAM_OPTIONS(c) (c)[8] 806#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 807#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 808#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 809#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 810#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 811 812#define ISP2100_NVRAM_NODE_NAME(c) (\ 813 (((u_int64_t)(c)[18]) << 56) | \ 814 (((u_int64_t)(c)[19]) << 48) | \ 815 (((u_int64_t)(c)[20]) << 40) | \ 816 (((u_int64_t)(c)[21]) << 32) | \ 817 (((u_int64_t)(c)[22]) << 24) | \ 818 (((u_int64_t)(c)[23]) << 16) | \ 819 (((u_int64_t)(c)[24]) << 8) | \ 820 (((u_int64_t)(c)[25]) << 0)) 821#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 822 823#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 824#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 825#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 826#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 827#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 828#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 829#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 830 831#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 832 (((u_int64_t)(c)[72]) << 56) | \ 833 (((u_int64_t)(c)[73]) << 48) | \ 834 (((u_int64_t)(c)[74]) << 40) | \ 835 (((u_int64_t)(c)[75]) << 32) | \ 836 (((u_int64_t)(c)[76]) << 24) | \ 837 (((u_int64_t)(c)[77]) << 16) | \ 838 (((u_int64_t)(c)[78]) << 8) | \ 839 (((u_int64_t)(c)[79]) << 0)) 840 841#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 842 843#endif /* _ISPREG_H */ 844