ispreg.h revision 82689
150477Speter/* $FreeBSD: head/sys/dev/isp/ispreg.h 82689 2001-08-31 21:39:04Z mjacob $ */ 235388Smjacob/* 335388Smjacob * Machine Independent (well, as best as possible) register 435388Smjacob * definitions for Qlogic ISP SCSI adapters. 535388Smjacob * 666189Smjacob * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 735388Smjacob * All rights reserved. 845040Smjacob * 935388Smjacob * Redistribution and use in source and binary forms, with or without 1035388Smjacob * modification, are permitted provided that the following conditions 1135388Smjacob * are met: 1235388Smjacob * 1. Redistributions of source code must retain the above copyright 1335388Smjacob * notice immediately at the beginning of the file, without modification, 1435388Smjacob * this list of conditions, and the following disclaimer. 1566189Smjacob * 2. The name of the author may not be used to endorse or promote products 1635388Smjacob * derived from this software without specific prior written permission. 1735388Smjacob * 1835388Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1935388Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2035388Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2135388Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2235388Smjacob * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2335388Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2435388Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2535388Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2635388Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2735388Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2835388Smjacob * SUCH DAMAGE. 2935388Smjacob */ 3035388Smjacob#ifndef _ISPREG_H 3135388Smjacob#define _ISPREG_H 3235388Smjacob 3335388Smjacob/* 3435388Smjacob * Hardware definitions for the Qlogic ISP registers. 3535388Smjacob */ 3635388Smjacob 3735388Smjacob/* 3835388Smjacob * This defines types of access to various registers. 3935388Smjacob * 4035388Smjacob * R: Read Only 4135388Smjacob * W: Write Only 4235388Smjacob * RW: Read/Write 4335388Smjacob * 4435388Smjacob * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 4535388Smjacob * if RISC processor in ISP is paused. 4635388Smjacob */ 4735388Smjacob 4835388Smjacob/* 4935388Smjacob * Offsets for various register blocks. 5035388Smjacob * 5135388Smjacob * Sad but true, different architectures have different offsets. 5246967Smjacob * 5346967Smjacob * Don't be alarmed if none of this makes sense. The original register 5446967Smjacob * layout set some defines in a certain pattern. Everything else has been 5546967Smjacob * grafted on since. For example, the ISP1080 manual will state that DMA 5646967Smjacob * registers start at 0x80 from the base of the register address space. 5746967Smjacob * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 5846967Smjacob * to start at offset 0x60 because the DMA registers are all defined to 5946967Smjacob * be DMA_BLOCK+0x20 and so on. Clear? 6035388Smjacob */ 6135388Smjacob 6244819Smjacob#define BIU_REGS_OFF 0x00 6335388Smjacob 6444819Smjacob#define PCI_MBOX_REGS_OFF 0x70 6544819Smjacob#define PCI_MBOX_REGS2100_OFF 0x10 6682689Smjacob#define PCI_MBOX_REGS2300_OFF 0x40 6735388Smjacob#define SBUS_MBOX_REGS_OFF 0x80 6835388Smjacob 6944819Smjacob#define PCI_SXP_REGS_OFF 0x80 7035388Smjacob#define SBUS_SXP_REGS_OFF 0x200 7135388Smjacob 7244819Smjacob#define PCI_RISC_REGS_OFF 0x80 7335388Smjacob#define SBUS_RISC_REGS_OFF 0x400 7435388Smjacob 7544819Smjacob/* Bless me! Chip designers have putzed it again! */ 7644819Smjacob#define ISP1080_DMA_REGS_OFF 0x60 7744819Smjacob#define DMA_REGS_OFF 0x00 /* same as BIU block */ 7844819Smjacob 7964088Smjacob#define SBUS_REGSIZE 0x450 8064088Smjacob#define PCI_REGSIZE 0x100 8164088Smjacob 8235388Smjacob/* 8335388Smjacob * NB: The *_BLOCK definitions have no specific hardware meaning. 8435388Smjacob * They serve simply to note to the MD layer which block of 8535388Smjacob * registers offsets are being accessed. 8635388Smjacob */ 8744819Smjacob#define _NREG_BLKS 5 8844819Smjacob#define _BLK_REG_SHFT 13 8944819Smjacob#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 9044819Smjacob#define BIU_BLOCK (0 << _BLK_REG_SHFT) 9144819Smjacob#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 9244819Smjacob#define SXP_BLOCK (2 << _BLK_REG_SHFT) 9344819Smjacob#define RISC_BLOCK (3 << _BLK_REG_SHFT) 9444819Smjacob#define DMA_BLOCK (4 << _BLK_REG_SHFT) 9535388Smjacob 9635388Smjacob/* 9735388Smjacob * Bus Interface Block Register Offsets 9835388Smjacob */ 9944819Smjacob 10054671Smjacob#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 10154671Smjacob#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 10254671Smjacob#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 10354671Smjacob#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 10454671Smjacob#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 10554671Smjacob#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 10654671Smjacob#define BIU2100_CSR (BIU_BLOCK+0x6) 10754671Smjacob#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 10854671Smjacob#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 10954671Smjacob#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 11054671Smjacob#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 11182689Smjacob/* 11282689Smjacob * These are specific to the 2300. 11382689Smjacob * 11482689Smjacob * They *claim* you can read BIU_R2HSTSLO with a full 32 bit access 11582689Smjacob * and get both registers, but I'm a bit dubious about that. But the 11682689Smjacob * point here is that the top 16 bits are firmware defined bits that 11782689Smjacob * the RISC processor uses to inform the host about something- usually 11882689Smjacob * something which was nominally in a mailbox register. 11982689Smjacob */ 12082689Smjacob#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 12182689Smjacob#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 12282689Smjacob#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 12382689Smjacob#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 12482689Smjacob 12582689Smjacob#define BIU_R2HSTSLO (BIU_BLOCK+0x18) 12682689Smjacob#define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 12782689Smjacob 12882689Smjacob#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 12982689Smjacob#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 13082689Smjacob#define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ 13182689Smjacob#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 13282689Smjacob#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 13382689Smjacob#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 13482689Smjacob#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 13582689Smjacob#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 13682689Smjacob#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 13782689Smjacob#define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ 13882689Smjacob#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 13982689Smjacob#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 14082689Smjacob#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 14182689Smjacob 14254671Smjacob#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 14344819Smjacob#define RDMA2100_CONTROL DFIFO_COMMAND 14454671Smjacob#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 14544819Smjacob 14644819Smjacob/* 14744819Smjacob * Putzed DMA register layouts. 14844819Smjacob */ 14954671Smjacob#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 15035388Smjacob#define CDMA2100_CONTROL CDMA_CONF 15154671Smjacob#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 15254671Smjacob#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 15354671Smjacob#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 15454671Smjacob#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 15554671Smjacob#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 15654671Smjacob#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 15754671Smjacob#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 15854671Smjacob#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 15935388Smjacob 16054671Smjacob#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 16135388Smjacob#define TDMA2100_CONTROL DDMA_CONF 16254671Smjacob#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 16354671Smjacob#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 16454671Smjacob#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 16554671Smjacob#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 16654671Smjacob#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 16754671Smjacob#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 16854671Smjacob#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 16935388Smjacob/* these are for the 1040A cards */ 17054671Smjacob#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 17154671Smjacob#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 17235388Smjacob 17335388Smjacob 17435388Smjacob/* 17535388Smjacob * Bus Interface Block Register Definitions 17635388Smjacob */ 17735388Smjacob/* BUS CONFIGURATION REGISTER #0 */ 17835388Smjacob#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 17935388Smjacob/* BUS CONFIGURATION REGISTER #1 */ 18035388Smjacob 18135388Smjacob#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 18235388Smjacob#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 18335388Smjacob 18435388Smjacob#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 18535388Smjacob#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 18635388Smjacob#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 18735388Smjacob#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 18835388Smjacob#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 18935388Smjacob#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 19035388Smjacob#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 19135388Smjacob#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 19235388Smjacob#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 19335388Smjacob#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 19435388Smjacob#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 19535388Smjacob 19654671Smjacob#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 19754671Smjacob#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 19844819Smjacob#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 19944819Smjacob 20045040Smjacob/* ISP2100 Bus Control/Status Register */ 20135388Smjacob 20235388Smjacob#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 20335388Smjacob#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 20435388Smjacob#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 20535388Smjacob#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 20635388Smjacob#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 20735388Smjacob#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 20835388Smjacob#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 20935388Smjacob#define BIU2100_SOFT_RESET 0x01 21035388Smjacob/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 21135388Smjacob 21235388Smjacob 21335388Smjacob/* BUS CONTROL REGISTER */ 21435388Smjacob#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 21535388Smjacob#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 21635388Smjacob#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 21735388Smjacob#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 21835388Smjacob#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 21935388Smjacob#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 22035388Smjacob 22135388Smjacob#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 22235388Smjacob#define BIU2100_ICR_ENA_FPM_INT 0x0020 22335388Smjacob#define BIU2100_ICR_ENA_FB_INT 0x0010 22435388Smjacob#define BIU2100_ICR_ENA_RISC_INT 0x0008 22535388Smjacob#define BIU2100_ICR_ENA_CDMA_INT 0x0004 22635388Smjacob#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 22735388Smjacob#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 22835388Smjacob#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 22935388Smjacob 23046967Smjacob#define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 23135388Smjacob ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 23235388Smjacob ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 23335388Smjacob 23446967Smjacob#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 23544819Smjacob (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 23644819Smjacob (ISP_READ(isp, BIU_ICR) & \ 23744819Smjacob (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 23844819Smjacob 23935388Smjacob#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 24035388Smjacob 24135388Smjacob/* BUS STATUS REGISTER */ 24235388Smjacob#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 24335388Smjacob#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 24435388Smjacob#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 24535388Smjacob#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 24635388Smjacob#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 24735388Smjacob 24835388Smjacob#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 24935388Smjacob#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 25035388Smjacob#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 25135388Smjacob#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 25235388Smjacob#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 25335388Smjacob#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 25435388Smjacob#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 25535388Smjacob 25652346Smjacob#define INT_PENDING(isp, isr) (IS_FC(isp)? \ 25752346Smjacob ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 25835388Smjacob 25962170Smjacob#define INT_PENDING_MASK(isp) \ 26062170Smjacob (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) 26162170Smjacob 26235388Smjacob/* BUS SEMAPHORE REGISTER */ 26335388Smjacob#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 26435388Smjacob#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 26535388Smjacob 26639235Sgibbs/* NVRAM SEMAPHORE REGISTER */ 26739235Sgibbs#define BIU_NVRAM_CLOCK 0x0001 26839235Sgibbs#define BIU_NVRAM_SELECT 0x0002 26939235Sgibbs#define BIU_NVRAM_DATAOUT 0x0004 27039235Sgibbs#define BIU_NVRAM_DATAIN 0x0008 27139235Sgibbs#define ISP_NVRAM_READ 6 27235388Smjacob 27335388Smjacob/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 27435388Smjacob#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 27535388Smjacob#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 27635388Smjacob#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 27735388Smjacob#define DMA_DMA_DIRECTION 0x0001 /* 27835388Smjacob * Set DMA direction: 27935388Smjacob * 0 - DMA FIFO to host 28035388Smjacob * 1 - Host to DMA FIFO 28135388Smjacob */ 28235388Smjacob 28335388Smjacob/* COMMAND && DATA DMA CONTROL REGISTER */ 28435388Smjacob#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 28535388Smjacob#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 28635388Smjacob * Clear FIFO and DMA Channel, 28735388Smjacob * reset DMA registers 28835388Smjacob */ 28935388Smjacob#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 29035388Smjacob#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 29135388Smjacob#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 29235388Smjacob 29335388Smjacob/* 29435388Smjacob * Variants of same for 2100 29535388Smjacob */ 29635388Smjacob#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 29735388Smjacob#define DMA_CNTRL2100_RESET_INT 0x0002 29835388Smjacob 29935388Smjacob 30035388Smjacob 30135388Smjacob/* DMA STATUS REGISTER */ 30235388Smjacob#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 30335388Smjacob#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 30435388Smjacob#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 30535388Smjacob#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 30635388Smjacob#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 30735388Smjacob#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 30835388Smjacob 30935388Smjacob#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 31035388Smjacob#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 31135388Smjacob#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 31235388Smjacob#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 31335388Smjacob#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 31435388Smjacob#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 31535388Smjacob#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 31635388Smjacob#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 31735388Smjacob#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 31835388Smjacob#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 31935388Smjacob#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 32035388Smjacob 32135388Smjacob/* DMA Status Register, pipeline status bits */ 32235388Smjacob#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 32335388Smjacob#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 32435388Smjacob#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 32535388Smjacob * Pipeline stage 1 Loaded, 32635388Smjacob * stage 2 empty 32735388Smjacob */ 32835388Smjacob#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 32935388Smjacob#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 33035388Smjacob#define DMA_PCI_PIPE_STAGE1 0x0001 /* 33135388Smjacob * Pipeline stage 1 Loaded, 33235388Smjacob * stage 2 empty 33335388Smjacob */ 33435388Smjacob#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 33535388Smjacob 33635388Smjacob/* DMA Status Register, channel status bits */ 33735388Smjacob#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 33835388Smjacob#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 33935388Smjacob#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 34035388Smjacob#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 34135388Smjacob#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 34235388Smjacob#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 34335388Smjacob#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 34435388Smjacob 34535388Smjacob 34635388Smjacob/* DMA FIFO STATUS REGISTER */ 34735388Smjacob#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 34835388Smjacob#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 34935388Smjacob#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 35035388Smjacob#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 35135388Smjacob 35235388Smjacob/* 35335388Smjacob * Mailbox Block Register Offsets 35435388Smjacob */ 35535388Smjacob 35654671Smjacob#define INMAILBOX0 (MBOX_BLOCK+0x0) 35754671Smjacob#define INMAILBOX1 (MBOX_BLOCK+0x2) 35854671Smjacob#define INMAILBOX2 (MBOX_BLOCK+0x4) 35954671Smjacob#define INMAILBOX3 (MBOX_BLOCK+0x6) 36054671Smjacob#define INMAILBOX4 (MBOX_BLOCK+0x8) 36154671Smjacob#define INMAILBOX5 (MBOX_BLOCK+0xA) 36254671Smjacob#define INMAILBOX6 (MBOX_BLOCK+0xC) 36354671Smjacob#define INMAILBOX7 (MBOX_BLOCK+0xE) 36435388Smjacob 36554671Smjacob#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 36654671Smjacob#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 36754671Smjacob#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 36854671Smjacob#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 36954671Smjacob#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 37054671Smjacob#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 37154671Smjacob#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 37254671Smjacob#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 37335388Smjacob 37462170Smjacob#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 37535388Smjacob#define NMBOX(isp) \ 37635388Smjacob (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 37735388Smjacob ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 37862170Smjacob#define NMBOX_BMASK(isp) \ 37962170Smjacob (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 38062170Smjacob ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) 38135388Smjacob 38262170Smjacob#define MAX_MAILBOX 8 38362170Smjacob 38435388Smjacob/* 38571078Smjacob * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 38671078Smjacob * NB: The RISC processor must be paused and the appropriate register 38771078Smjacob * bank selected via BIU2100_CSR bits. 38871078Smjacob */ 38971078Smjacob 39071078Smjacob#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 39171078Smjacob#define FPM_SOFT_RESET 0x0100 39271078Smjacob 39371078Smjacob#define FBM_CMD (BIU_BLOCK + 0xB8) 39471078Smjacob#define FBMCMD_FIFO_RESET_ALL 0xA000 39571078Smjacob 39671078Smjacob 39771078Smjacob/* 39835388Smjacob * SXP Block Register Offsets 39935388Smjacob */ 40054671Smjacob#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 40154671Smjacob#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 40254671Smjacob#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 40354671Smjacob#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 40454671Smjacob#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 40554671Smjacob#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 40654671Smjacob#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 40754671Smjacob#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 40854671Smjacob#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 40954671Smjacob#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 41054671Smjacob#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 41154671Smjacob#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 41254671Smjacob#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 41354671Smjacob#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 41454671Smjacob#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 41554671Smjacob#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 41654671Smjacob#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 41754671Smjacob#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 41854671Smjacob#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 41954671Smjacob#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 42054671Smjacob#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 42154671Smjacob#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 42254671Smjacob#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 42354671Smjacob#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 42454671Smjacob#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 42554671Smjacob#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 42654671Smjacob#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 42754671Smjacob#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 42854671Smjacob#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 42954671Smjacob#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 43054671Smjacob#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 43154671Smjacob#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 43254671Smjacob#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 43354671Smjacob#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 43454671Smjacob#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 43554671Smjacob#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 43654671Smjacob#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 43754671Smjacob#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 43854671Smjacob#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 43935388Smjacob 44054671Smjacob/* for 1080/1280/1240 only */ 44154671Smjacob#define SXP_BANK1_SELECT 0x100 44235388Smjacob 44354671Smjacob 44435388Smjacob/* SXP CONF1 REGISTER */ 44535388Smjacob#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 44635388Smjacob#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 44735388Smjacob#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 44835388Smjacob#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 44935388Smjacob#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 45035388Smjacob 45135388Smjacob/* SXP CONF2 REGISTER */ 45235388Smjacob#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 45335388Smjacob#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 45435388Smjacob#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 45535388Smjacob#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 45635388Smjacob#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 45735388Smjacob#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 45835388Smjacob 45935388Smjacob/* SXP INTERRUPT REGISTER */ 46035388Smjacob#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 46135388Smjacob#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 46235388Smjacob#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 46335388Smjacob#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 46435388Smjacob#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 46535388Smjacob#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 46635388Smjacob#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 46735388Smjacob#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 46835388Smjacob#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 46935388Smjacob#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 47035388Smjacob 47135388Smjacob 47235388Smjacob/* SXP GROSS ERROR REGISTER */ 47335388Smjacob#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 47435388Smjacob#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 47535388Smjacob#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 47635388Smjacob#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 47735388Smjacob#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 47835388Smjacob#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 47935388Smjacob#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 48035388Smjacob 48135388Smjacob/* SXP EXCEPTION REGISTER */ 48235388Smjacob#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 48335388Smjacob#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 48435388Smjacob#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 48535388Smjacob#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 48635388Smjacob#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 48735388Smjacob#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 48835388Smjacob#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 48935388Smjacob#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 49035388Smjacob#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 49135388Smjacob#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 49235388Smjacob 49335388Smjacob /* SXP OVERRIDE REGISTER */ 49435388Smjacob#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 49535388Smjacob#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 49635388Smjacob#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 49735388Smjacob#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 49835388Smjacob#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 49935388Smjacob#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 50035388Smjacob#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 50135388Smjacob#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 50235388Smjacob#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 50335388Smjacob#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 50435388Smjacob#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 50535388Smjacob#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 50635388Smjacob#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 50735388Smjacob 50835388Smjacob/* SXP COMMANDS */ 50935388Smjacob#define SXP_RESET_BUS_CMD 0x300b 51035388Smjacob 51135388Smjacob/* SXP SCSI ID REGISTER */ 51235388Smjacob#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 51335388Smjacob#define SXP_SELECT_ID 0x000F /* Select id */ 51435388Smjacob 51535388Smjacob/* SXP DEV CONFIG1 REGISTER */ 51635388Smjacob#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 51735388Smjacob#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 51835388Smjacob#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 51935388Smjacob 52035388Smjacob 52135388Smjacob/* SXP DEV CONFIG2 REGISTER */ 52235388Smjacob#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 52335388Smjacob#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 52435388Smjacob#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 52535388Smjacob#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 52635388Smjacob#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 52735388Smjacob 52835388Smjacob 52935388Smjacob/* SXP PHASE POINTER REGISTER */ 53035388Smjacob#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 53135388Smjacob#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 53235388Smjacob#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 53335388Smjacob#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 53435388Smjacob 53535388Smjacob 53635388Smjacob/* SXP FIFO STATUS REGISTER */ 53735388Smjacob#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 53835388Smjacob#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 53935388Smjacob#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 54035388Smjacob#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 54135388Smjacob 54235388Smjacob 54335388Smjacob/* SXP CONTROL PINS REGISTER */ 54435388Smjacob#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 54535388Smjacob#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 54635388Smjacob#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 54735388Smjacob#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 54835388Smjacob#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 54935388Smjacob#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 55035388Smjacob#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 55135388Smjacob#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 55235388Smjacob#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 55335388Smjacob#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 55435388Smjacob#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 55535388Smjacob#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 55635388Smjacob 55735388Smjacob/* 55835388Smjacob * Set the hold time for the SCSI Bus Reset to be 250 ms 55935388Smjacob */ 56035388Smjacob#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 56135388Smjacob 56235388Smjacob/* SXP DIFF PINS REGISTER */ 56335388Smjacob#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 56435388Smjacob#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 56535388Smjacob#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 56635388Smjacob#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 56735388Smjacob#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 56835388Smjacob#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 56935388Smjacob 57054671Smjacob/* Ultra2 only */ 57145040Smjacob#define SXP_PINS_LVD_MODE 0x1000 57245040Smjacob#define SXP_PINS_HVD_MODE 0x0800 57345040Smjacob#define SXP_PINS_SE_MODE 0x0400 57445040Smjacob 57545040Smjacob/* The above have to be put together with the DIFFM pin to make sense */ 57645040Smjacob#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 57745040Smjacob#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 57845040Smjacob#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 57945040Smjacob#define ISP1080_MODE_MASK \ 58045040Smjacob (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 58145040Smjacob 58235388Smjacob/* 58335388Smjacob * RISC and Host Command and Control Block Register Offsets 58435388Smjacob */ 58535388Smjacob 58635388Smjacob#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 58735388Smjacob#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 58835388Smjacob#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 58935388Smjacob#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 59035388Smjacob#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 59135388Smjacob#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 59235388Smjacob#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 59335388Smjacob#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 59435388Smjacob#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 59535388Smjacob#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 59635388Smjacob#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 59735388Smjacob#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 59835388Smjacob#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 59935388Smjacob#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 60035388Smjacob#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 60135388Smjacob#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 60235388Smjacob#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 60335388Smjacob#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 60435388Smjacob#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 60535388Smjacob#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 60635388Smjacob#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 60735388Smjacob#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 60835388Smjacob#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 60935388Smjacob#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 61035388Smjacob#define RISC_MTR2100 RISC_BLOCK+0x30 61135388Smjacob 61235388Smjacob#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 61343420Smjacob#define DUAL_BANK 8 61435388Smjacob#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 61535388Smjacob#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 61635388Smjacob#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 61735388Smjacob#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 61835388Smjacob#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 61935388Smjacob#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 62035388Smjacob#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 62135388Smjacob 62235388Smjacob 62335388Smjacob/* PROCESSOR STATUS REGISTER */ 62435388Smjacob#define RISC_PSR_FORCE_TRUE 0x8000 62535388Smjacob#define RISC_PSR_LOOP_COUNT_DONE 0x4000 62635388Smjacob#define RISC_PSR_RISC_INT 0x2000 62735388Smjacob#define RISC_PSR_TIMER_ROLLOVER 0x1000 62835388Smjacob#define RISC_PSR_ALU_OVERFLOW 0x0800 62935388Smjacob#define RISC_PSR_ALU_MSB 0x0400 63035388Smjacob#define RISC_PSR_ALU_CARRY 0x0200 63135388Smjacob#define RISC_PSR_ALU_ZERO 0x0100 63239235Sgibbs 63339235Sgibbs#define RISC_PSR_PCI_ULTRA 0x0080 63439235Sgibbs#define RISC_PSR_SBUS_ULTRA 0x0020 63539235Sgibbs 63635388Smjacob#define RISC_PSR_DMA_INT 0x0010 63735388Smjacob#define RISC_PSR_SXP_INT 0x0008 63835388Smjacob#define RISC_PSR_HOST_INT 0x0004 63935388Smjacob#define RISC_PSR_INT_PENDING 0x0002 64035388Smjacob#define RISC_PSR_FORCE_FALSE 0x0001 64135388Smjacob 64235388Smjacob 64335388Smjacob/* Host Command and Control */ 64435388Smjacob#define HCCR_CMD_NOP 0x0000 /* NOP */ 64535388Smjacob#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 64635388Smjacob#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 64735388Smjacob#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 64835388Smjacob#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 64971078Smjacob#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 65071078Smjacob * Disable RISC pause on FPM 65171078Smjacob * parity error. 65271078Smjacob */ 65335388Smjacob#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 65435388Smjacob#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 65535388Smjacob#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 65635388Smjacob#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 65735388Smjacob#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 65835388Smjacob#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 65935388Smjacob#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 66035388Smjacob#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 66135388Smjacob 66235388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 66335388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 66435388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 66535388Smjacob#define ISP2100_HCCR_PARITY 0x0001 66635388Smjacob 66735388Smjacob#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 66835388Smjacob#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 66935388Smjacob#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 67035388Smjacob 67135388Smjacob#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 67235388Smjacob#define HCCR_RESET 0x0040 /* R : reset in progress */ 67335388Smjacob#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 67435388Smjacob 67535388Smjacob#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 67639235Sgibbs 67739235Sgibbs/* 67846967Smjacob * NVRAM Definitions (PCI cards only) 67946967Smjacob */ 68046967Smjacob 68146967Smjacob#define ISPBSMX(c, byte, shift, mask) \ 68246967Smjacob (((c)[(byte)] >> (shift)) & (mask)) 68346967Smjacob/* 68446967Smjacob * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 68539235Sgibbs * 68639235Sgibbs * Some portion of the front of this is for general host adapter properties 68739235Sgibbs * This is followed by an array of per-target parameters, and is tailed off 68839235Sgibbs * with a checksum xor byte at offset 127. For non-byte entities data is 68939235Sgibbs * stored in Little Endian order. 69039235Sgibbs */ 69139235Sgibbs 69239235Sgibbs#define ISP_NVRAM_SIZE 128 69345040Smjacob 69439235Sgibbs#define ISP_NVRAM_VERSION(c) (c)[4] 69539235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 69639235Sgibbs#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 69739235Sgibbs#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 69839235Sgibbs#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 69939235Sgibbs#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 70039235Sgibbs#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 70139235Sgibbs#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 70239235Sgibbs#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 70339235Sgibbs#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 70439235Sgibbs#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 70539235Sgibbs#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 70639235Sgibbs#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 70739235Sgibbs#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 70839235Sgibbs#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 70939235Sgibbs#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 71039235Sgibbs#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 71139235Sgibbs#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 71239235Sgibbs#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 71339235Sgibbs#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 71439235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 71539235Sgibbs#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 71639235Sgibbs#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 71739235Sgibbs#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 71839235Sgibbs#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 71939235Sgibbs#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 72039235Sgibbs#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 72139235Sgibbs#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 72239235Sgibbs#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 72339235Sgibbs#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 72439235Sgibbs 72539235Sgibbs#define ISP_NVRAM_TARGOFF 28 72639235Sgibbs#define ISP_NVARM_TARGSIZE 6 72739235Sgibbs#define _IxT(tgt, tidx) \ 72839235Sgibbs (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 72939235Sgibbs#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 73039235Sgibbs#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 73139235Sgibbs#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 73239235Sgibbs#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 73339235Sgibbs#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 73439235Sgibbs#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 73539235Sgibbs#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 73639235Sgibbs#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 73739235Sgibbs#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 73839235Sgibbs#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 73939235Sgibbs#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 74039235Sgibbs#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 74139235Sgibbs#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 74239235Sgibbs 74339235Sgibbs/* 74446967Smjacob * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 74546967Smjacob * 74646967Smjacob * Some portion of the front of this is for general host adapter properties 74746967Smjacob * This is followed by an array of per-target parameters, and is tailed off 74846967Smjacob * with a checksum xor byte at offset 256. For non-byte entities data is 74946967Smjacob * stored in Little Endian order. 75046967Smjacob */ 75146967Smjacob 75246967Smjacob#define ISP1080_NVRAM_SIZE 256 75346967Smjacob 75446967Smjacob#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 75546967Smjacob 75646967Smjacob/* Offset 5 */ 75746967Smjacob/* 75861769Smjacob u_int8_t bios_configuration_mode :2; 75961769Smjacob u_int8_t bios_disable :1; 76061769Smjacob u_int8_t selectable_scsi_boot_enable :1; 76161769Smjacob u_int8_t cd_rom_boot_enable :1; 76261769Smjacob u_int8_t disable_loading_risc_code :1; 76361769Smjacob u_int8_t enable_64bit_addressing :1; 76461769Smjacob u_int8_t unused_7 :1; 76546967Smjacob */ 76646967Smjacob 76746967Smjacob/* Offsets 6, 7 */ 76846967Smjacob/* 76961769Smjacob u_int8_t boot_lun_number :5; 77061769Smjacob u_int8_t scsi_bus_number :1; 77161769Smjacob u_int8_t unused_6 :1; 77261769Smjacob u_int8_t unused_7 :1; 77361769Smjacob u_int8_t boot_target_number :4; 77461769Smjacob u_int8_t unused_12 :1; 77561769Smjacob u_int8_t unused_13 :1; 77661769Smjacob u_int8_t unused_14 :1; 77761769Smjacob u_int8_t unused_15 :1; 77846967Smjacob */ 77946967Smjacob 78046967Smjacob#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 78146967Smjacob 78246967Smjacob#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 78346967Smjacob#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 78446967Smjacob 78546967Smjacob#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 78646967Smjacob#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 78746967Smjacob#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 78846967Smjacob 78946967Smjacob#define ISP1080_ISP_PARAMETER(c) \ 79046967Smjacob (((c)[18]) | ((c)[19] << 8)) 79146967Smjacob 79257148Smjacob#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 79357148Smjacob#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 79446967Smjacob 79546967Smjacob#define ISP1080_BUS1_OFF 112 79646967Smjacob 79746967Smjacob#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 79846967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 79946967Smjacob#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 80046967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 80146967Smjacob#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 80246967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 80346967Smjacob#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 80446967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 80546967Smjacob 80646967Smjacob#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 80746967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 80846967Smjacob#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 80946967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 81046967Smjacob#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 81146967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 81246967Smjacob#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 81346967Smjacob (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 81446967Smjacob ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 81546967Smjacob#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 81646967Smjacob (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 81746967Smjacob ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 81846967Smjacob 81946967Smjacob#define ISP1080_NVRAM_TARGOFF(b) \ 82046967Smjacob ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 82146967Smjacob#define ISP1080_NVRAM_TARGSIZE 6 82246967Smjacob#define _IxT8(tgt, tidx, b) \ 82346967Smjacob (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 82446967Smjacob 82546967Smjacob#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 82646967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 82746967Smjacob#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 82846967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 82946967Smjacob#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 83046967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 83146967Smjacob#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 83246967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 83346967Smjacob#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 83446967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 83546967Smjacob#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 83646967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 83746967Smjacob#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 83846967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 83946967Smjacob#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 84046967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 84146967Smjacob#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 84246967Smjacob ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 84346967Smjacob#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 84446967Smjacob ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 84546967Smjacob#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 84646967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 84746967Smjacob#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 84846967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 84946967Smjacob#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 85046967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 85146967Smjacob 85257148Smjacob#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 85357148Smjacob#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 85457148Smjacob#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 85557148Smjacob#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 85657148Smjacob#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 85757148Smjacob#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 85857148Smjacob#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 85957148Smjacob#define ISP12160_FAST_POST ISP1080_FAST_POST 86057148Smjacob#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 86157148Smjacob 86257148Smjacob#define ISP12160_NVRAM_INITIATOR_ID \ 86357148Smjacob ISP1080_NVRAM_INITIATOR_ID 86457148Smjacob#define ISP12160_NVRAM_BUS_RESET_DELAY \ 86557148Smjacob ISP1080_NVRAM_BUS_RESET_DELAY 86657148Smjacob#define ISP12160_NVRAM_BUS_RETRY_COUNT \ 86757148Smjacob ISP1080_NVRAM_BUS_RETRY_COUNT 86857148Smjacob#define ISP12160_NVRAM_BUS_RETRY_DELAY \ 86957148Smjacob ISP1080_NVRAM_BUS_RETRY_DELAY 87057148Smjacob#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 87157148Smjacob ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 87257148Smjacob#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 87357148Smjacob ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 87457148Smjacob#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 87557148Smjacob ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 87657148Smjacob#define ISP12160_NVRAM_SELECTION_TIMEOUT \ 87757148Smjacob ISP1080_NVRAM_SELECTION_TIMEOUT 87857148Smjacob#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 87957148Smjacob ISP1080_NVRAM_MAX_QUEUE_DEPTH 88057148Smjacob 88157148Smjacob 88257148Smjacob#define ISP12160_BUS0_OFF 24 88357148Smjacob#define ISP12160_BUS1_OFF 136 88457148Smjacob 88557148Smjacob#define ISP12160_NVRAM_TARGOFF(b) \ 88657148Smjacob (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 88757148Smjacob 88857148Smjacob#define ISP12160_NVRAM_TARGSIZE 6 88957148Smjacob#define _IxT16(tgt, tidx, b) \ 89057148Smjacob (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 89157148Smjacob 89257148Smjacob#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 89357148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 89457148Smjacob#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 89557148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 89657148Smjacob#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 89757148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 89857148Smjacob#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 89957148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 90057148Smjacob#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 90157148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 90257148Smjacob#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 90357148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 90457148Smjacob#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 90557148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 90657148Smjacob#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 90757148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 90857148Smjacob 90957148Smjacob#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 91057148Smjacob ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 91157148Smjacob#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 91257148Smjacob ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 91357148Smjacob 91457148Smjacob#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 91557148Smjacob ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 91657148Smjacob#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 91757148Smjacob ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 91857148Smjacob 91957148Smjacob#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 92057148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 92157148Smjacob#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 92257148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 92357148Smjacob#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 92457148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 92557148Smjacob 92646967Smjacob/* 92739235Sgibbs * Qlogic 2XXX NVRAM is an array of 256 bytes. 92839235Sgibbs * 92939235Sgibbs * Some portion of the front of this is for general RISC engine parameters, 93039235Sgibbs * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 93139235Sgibbs * 93239235Sgibbs * This is followed by some general host adapter parameters, and ends with 93339235Sgibbs * a checksum xor byte at offset 255. For non-byte entities data is stored 93439235Sgibbs * in Little Endian order. 93539235Sgibbs */ 93639235Sgibbs#define ISP2100_NVRAM_SIZE 256 93739235Sgibbs/* ISP_NVRAM_VERSION is in same overall place */ 93839235Sgibbs#define ISP2100_NVRAM_RISCVER(c) (c)[6] 93943792Smjacob#define ISP2100_NVRAM_OPTIONS(c) (c)[8] 94039235Sgibbs#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 94139235Sgibbs#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 94239235Sgibbs#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 94339235Sgibbs#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 94439235Sgibbs#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 94539235Sgibbs 94660218Smjacob#define ISP2100_NVRAM_PORT_NAME(c) (\ 94739235Sgibbs (((u_int64_t)(c)[18]) << 56) | \ 94839235Sgibbs (((u_int64_t)(c)[19]) << 48) | \ 94939235Sgibbs (((u_int64_t)(c)[20]) << 40) | \ 95039235Sgibbs (((u_int64_t)(c)[21]) << 32) | \ 95139235Sgibbs (((u_int64_t)(c)[22]) << 24) | \ 95239235Sgibbs (((u_int64_t)(c)[23]) << 16) | \ 95339235Sgibbs (((u_int64_t)(c)[24]) << 8) | \ 95439235Sgibbs (((u_int64_t)(c)[25]) << 0)) 95560218Smjacob 95641518Smjacob#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 95739235Sgibbs 95860218Smjacob#define ISP2100_NVRAM_NODE_NAME(c) (\ 95960218Smjacob (((u_int64_t)(c)[30]) << 56) | \ 96060218Smjacob (((u_int64_t)(c)[31]) << 48) | \ 96160218Smjacob (((u_int64_t)(c)[32]) << 40) | \ 96260218Smjacob (((u_int64_t)(c)[33]) << 32) | \ 96360218Smjacob (((u_int64_t)(c)[34]) << 24) | \ 96460218Smjacob (((u_int64_t)(c)[35]) << 16) | \ 96560218Smjacob (((u_int64_t)(c)[36]) << 8) | \ 96660218Smjacob (((u_int64_t)(c)[37]) << 0)) 96760218Smjacob 96843792Smjacob#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 96939235Sgibbs#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 97039235Sgibbs#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 97139235Sgibbs#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 97239235Sgibbs#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 97339235Sgibbs#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 97439235Sgibbs#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 97539235Sgibbs 97645040Smjacob#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 97739235Sgibbs (((u_int64_t)(c)[72]) << 56) | \ 97839235Sgibbs (((u_int64_t)(c)[73]) << 48) | \ 97939235Sgibbs (((u_int64_t)(c)[74]) << 40) | \ 98039235Sgibbs (((u_int64_t)(c)[75]) << 32) | \ 98139235Sgibbs (((u_int64_t)(c)[76]) << 24) | \ 98239235Sgibbs (((u_int64_t)(c)[77]) << 16) | \ 98339235Sgibbs (((u_int64_t)(c)[78]) << 8) | \ 98439235Sgibbs (((u_int64_t)(c)[79]) << 0)) 98543792Smjacob 98639235Sgibbs#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 98739235Sgibbs 98835388Smjacob#endif /* _ISPREG_H */ 989