ispreg.h revision 61769
150477Speter/* $FreeBSD: head/sys/dev/isp/ispreg.h 61769 2000-06-18 04:43:55Z mjacob $ */ 235388Smjacob/* 335388Smjacob * Machine Independent (well, as best as possible) register 435388Smjacob * definitions for Qlogic ISP SCSI adapters. 535388Smjacob * 645040Smjacob * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 735388Smjacob * NASA/Ames Research Center 835388Smjacob * All rights reserved. 945040Smjacob * 1035388Smjacob * Redistribution and use in source and binary forms, with or without 1135388Smjacob * modification, are permitted provided that the following conditions 1235388Smjacob * are met: 1335388Smjacob * 1. Redistributions of source code must retain the above copyright 1435388Smjacob * notice immediately at the beginning of the file, without modification, 1535388Smjacob * this list of conditions, and the following disclaimer. 1635388Smjacob * 2. Redistributions in binary form must reproduce the above copyright 1735388Smjacob * notice, this list of conditions and the following disclaimer in the 1835388Smjacob * documentation and/or other materials provided with the distribution. 1935388Smjacob * 3. The name of the author may not be used to endorse or promote products 2035388Smjacob * derived from this software without specific prior written permission. 2135388Smjacob * 2235388Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2335388Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2435388Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2535388Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2635388Smjacob * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2735388Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2835388Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2935388Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3035388Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3135388Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3235388Smjacob * SUCH DAMAGE. 3335388Smjacob */ 3435388Smjacob#ifndef _ISPREG_H 3535388Smjacob#define _ISPREG_H 3635388Smjacob 3735388Smjacob/* 3835388Smjacob * Hardware definitions for the Qlogic ISP registers. 3935388Smjacob */ 4035388Smjacob 4135388Smjacob/* 4235388Smjacob * This defines types of access to various registers. 4335388Smjacob * 4435388Smjacob * R: Read Only 4535388Smjacob * W: Write Only 4635388Smjacob * RW: Read/Write 4735388Smjacob * 4835388Smjacob * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 4935388Smjacob * if RISC processor in ISP is paused. 5035388Smjacob */ 5135388Smjacob 5235388Smjacob/* 5335388Smjacob * Offsets for various register blocks. 5435388Smjacob * 5535388Smjacob * Sad but true, different architectures have different offsets. 5646967Smjacob * 5746967Smjacob * Don't be alarmed if none of this makes sense. The original register 5846967Smjacob * layout set some defines in a certain pattern. Everything else has been 5946967Smjacob * grafted on since. For example, the ISP1080 manual will state that DMA 6046967Smjacob * registers start at 0x80 from the base of the register address space. 6146967Smjacob * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 6246967Smjacob * to start at offset 0x60 because the DMA registers are all defined to 6346967Smjacob * be DMA_BLOCK+0x20 and so on. Clear? 6435388Smjacob */ 6535388Smjacob 6644819Smjacob#define BIU_REGS_OFF 0x00 6735388Smjacob 6844819Smjacob#define PCI_MBOX_REGS_OFF 0x70 6944819Smjacob#define PCI_MBOX_REGS2100_OFF 0x10 7035388Smjacob#define SBUS_MBOX_REGS_OFF 0x80 7135388Smjacob 7244819Smjacob#define PCI_SXP_REGS_OFF 0x80 7335388Smjacob#define SBUS_SXP_REGS_OFF 0x200 7435388Smjacob 7544819Smjacob#define PCI_RISC_REGS_OFF 0x80 7635388Smjacob#define SBUS_RISC_REGS_OFF 0x400 7735388Smjacob 7844819Smjacob/* Bless me! Chip designers have putzed it again! */ 7944819Smjacob#define ISP1080_DMA_REGS_OFF 0x60 8044819Smjacob#define DMA_REGS_OFF 0x00 /* same as BIU block */ 8144819Smjacob 8235388Smjacob/* 8335388Smjacob * NB: The *_BLOCK definitions have no specific hardware meaning. 8435388Smjacob * They serve simply to note to the MD layer which block of 8535388Smjacob * registers offsets are being accessed. 8635388Smjacob */ 8744819Smjacob#define _NREG_BLKS 5 8844819Smjacob#define _BLK_REG_SHFT 13 8944819Smjacob#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 9044819Smjacob#define BIU_BLOCK (0 << _BLK_REG_SHFT) 9144819Smjacob#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 9244819Smjacob#define SXP_BLOCK (2 << _BLK_REG_SHFT) 9344819Smjacob#define RISC_BLOCK (3 << _BLK_REG_SHFT) 9444819Smjacob#define DMA_BLOCK (4 << _BLK_REG_SHFT) 9535388Smjacob 9635388Smjacob/* 9735388Smjacob * Bus Interface Block Register Offsets 9835388Smjacob */ 9944819Smjacob 10054671Smjacob#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 10154671Smjacob#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 10254671Smjacob#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 10354671Smjacob#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 10454671Smjacob#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 10554671Smjacob#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 10654671Smjacob#define BIU2100_CSR (BIU_BLOCK+0x6) 10754671Smjacob#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 10854671Smjacob#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 10954671Smjacob#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 11054671Smjacob#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 11154671Smjacob#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 11244819Smjacob#define RDMA2100_CONTROL DFIFO_COMMAND 11354671Smjacob#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 11444819Smjacob 11544819Smjacob/* 11644819Smjacob * Putzed DMA register layouts. 11744819Smjacob */ 11854671Smjacob#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 11935388Smjacob#define CDMA2100_CONTROL CDMA_CONF 12054671Smjacob#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 12154671Smjacob#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 12254671Smjacob#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 12354671Smjacob#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 12454671Smjacob#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 12554671Smjacob#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 12654671Smjacob#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 12754671Smjacob#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 12835388Smjacob 12954671Smjacob#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 13035388Smjacob#define TDMA2100_CONTROL DDMA_CONF 13154671Smjacob#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 13254671Smjacob#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 13354671Smjacob#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 13454671Smjacob#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 13554671Smjacob#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 13654671Smjacob#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 13754671Smjacob#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 13835388Smjacob/* these are for the 1040A cards */ 13954671Smjacob#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 14054671Smjacob#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 14135388Smjacob 14235388Smjacob 14335388Smjacob/* 14435388Smjacob * Bus Interface Block Register Definitions 14535388Smjacob */ 14635388Smjacob/* BUS CONFIGURATION REGISTER #0 */ 14735388Smjacob#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 14835388Smjacob/* BUS CONFIGURATION REGISTER #1 */ 14935388Smjacob 15035388Smjacob#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 15135388Smjacob#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 15235388Smjacob 15335388Smjacob#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 15435388Smjacob#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 15535388Smjacob#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 15635388Smjacob#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 15735388Smjacob#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 15835388Smjacob#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 15935388Smjacob#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 16035388Smjacob#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 16135388Smjacob#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 16235388Smjacob#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 16335388Smjacob#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 16435388Smjacob 16554671Smjacob#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 16654671Smjacob#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 16744819Smjacob#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 16844819Smjacob 16945040Smjacob/* ISP2100 Bus Control/Status Register */ 17035388Smjacob 17135388Smjacob#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 17235388Smjacob#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 17335388Smjacob#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 17435388Smjacob#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 17535388Smjacob#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 17635388Smjacob#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 17735388Smjacob#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 17835388Smjacob#define BIU2100_SOFT_RESET 0x01 17935388Smjacob/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 18035388Smjacob 18135388Smjacob 18235388Smjacob/* BUS CONTROL REGISTER */ 18335388Smjacob#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 18435388Smjacob#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 18535388Smjacob#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 18635388Smjacob#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 18735388Smjacob#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 18835388Smjacob#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 18935388Smjacob 19035388Smjacob#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 19135388Smjacob#define BIU2100_ICR_ENA_FPM_INT 0x0020 19235388Smjacob#define BIU2100_ICR_ENA_FB_INT 0x0010 19335388Smjacob#define BIU2100_ICR_ENA_RISC_INT 0x0008 19435388Smjacob#define BIU2100_ICR_ENA_CDMA_INT 0x0004 19535388Smjacob#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 19635388Smjacob#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 19735388Smjacob#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 19835388Smjacob 19946967Smjacob#define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 20035388Smjacob ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 20135388Smjacob ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 20235388Smjacob 20346967Smjacob#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 20444819Smjacob (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 20544819Smjacob (ISP_READ(isp, BIU_ICR) & \ 20644819Smjacob (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 20744819Smjacob 20835388Smjacob#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 20935388Smjacob 21035388Smjacob/* BUS STATUS REGISTER */ 21135388Smjacob#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 21235388Smjacob#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 21335388Smjacob#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 21435388Smjacob#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 21535388Smjacob#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 21635388Smjacob 21735388Smjacob#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 21835388Smjacob#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 21935388Smjacob#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 22035388Smjacob#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 22135388Smjacob#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 22235388Smjacob#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 22335388Smjacob#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 22435388Smjacob 22552346Smjacob#define INT_PENDING(isp, isr) (IS_FC(isp)? \ 22652346Smjacob ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 22735388Smjacob 22835388Smjacob/* BUS SEMAPHORE REGISTER */ 22935388Smjacob#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 23035388Smjacob#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 23135388Smjacob 23239235Sgibbs/* NVRAM SEMAPHORE REGISTER */ 23339235Sgibbs#define BIU_NVRAM_CLOCK 0x0001 23439235Sgibbs#define BIU_NVRAM_SELECT 0x0002 23539235Sgibbs#define BIU_NVRAM_DATAOUT 0x0004 23639235Sgibbs#define BIU_NVRAM_DATAIN 0x0008 23739235Sgibbs#define ISP_NVRAM_READ 6 23835388Smjacob 23935388Smjacob/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 24035388Smjacob#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 24135388Smjacob#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 24235388Smjacob#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 24335388Smjacob#define DMA_DMA_DIRECTION 0x0001 /* 24435388Smjacob * Set DMA direction: 24535388Smjacob * 0 - DMA FIFO to host 24635388Smjacob * 1 - Host to DMA FIFO 24735388Smjacob */ 24835388Smjacob 24935388Smjacob/* COMMAND && DATA DMA CONTROL REGISTER */ 25035388Smjacob#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 25135388Smjacob#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 25235388Smjacob * Clear FIFO and DMA Channel, 25335388Smjacob * reset DMA registers 25435388Smjacob */ 25535388Smjacob#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 25635388Smjacob#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 25735388Smjacob#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 25835388Smjacob 25935388Smjacob/* 26035388Smjacob * Variants of same for 2100 26135388Smjacob */ 26235388Smjacob#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 26335388Smjacob#define DMA_CNTRL2100_RESET_INT 0x0002 26435388Smjacob 26535388Smjacob 26635388Smjacob 26735388Smjacob/* DMA STATUS REGISTER */ 26835388Smjacob#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 26935388Smjacob#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 27035388Smjacob#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 27135388Smjacob#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 27235388Smjacob#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 27335388Smjacob#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 27435388Smjacob 27535388Smjacob#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 27635388Smjacob#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 27735388Smjacob#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 27835388Smjacob#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 27935388Smjacob#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 28035388Smjacob#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 28135388Smjacob#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 28235388Smjacob#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 28335388Smjacob#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 28435388Smjacob#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 28535388Smjacob#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 28635388Smjacob 28735388Smjacob/* DMA Status Register, pipeline status bits */ 28835388Smjacob#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 28935388Smjacob#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 29035388Smjacob#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 29135388Smjacob * Pipeline stage 1 Loaded, 29235388Smjacob * stage 2 empty 29335388Smjacob */ 29435388Smjacob#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 29535388Smjacob#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 29635388Smjacob#define DMA_PCI_PIPE_STAGE1 0x0001 /* 29735388Smjacob * Pipeline stage 1 Loaded, 29835388Smjacob * stage 2 empty 29935388Smjacob */ 30035388Smjacob#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 30135388Smjacob 30235388Smjacob/* DMA Status Register, channel status bits */ 30335388Smjacob#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 30435388Smjacob#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 30535388Smjacob#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 30635388Smjacob#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 30735388Smjacob#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 30835388Smjacob#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 30935388Smjacob#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 31035388Smjacob 31135388Smjacob 31235388Smjacob/* DMA FIFO STATUS REGISTER */ 31335388Smjacob#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 31435388Smjacob#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 31535388Smjacob#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 31635388Smjacob#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 31735388Smjacob 31835388Smjacob/* 31935388Smjacob * Mailbox Block Register Offsets 32035388Smjacob */ 32135388Smjacob 32254671Smjacob#define INMAILBOX0 (MBOX_BLOCK+0x0) 32354671Smjacob#define INMAILBOX1 (MBOX_BLOCK+0x2) 32454671Smjacob#define INMAILBOX2 (MBOX_BLOCK+0x4) 32554671Smjacob#define INMAILBOX3 (MBOX_BLOCK+0x6) 32654671Smjacob#define INMAILBOX4 (MBOX_BLOCK+0x8) 32754671Smjacob#define INMAILBOX5 (MBOX_BLOCK+0xA) 32854671Smjacob#define INMAILBOX6 (MBOX_BLOCK+0xC) 32954671Smjacob#define INMAILBOX7 (MBOX_BLOCK+0xE) 33035388Smjacob 33154671Smjacob#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 33254671Smjacob#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 33354671Smjacob#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 33454671Smjacob#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 33554671Smjacob#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 33654671Smjacob#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 33754671Smjacob#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 33854671Smjacob#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 33935388Smjacob 34035388Smjacob#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 34135388Smjacob#define NMBOX(isp) \ 34235388Smjacob (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 34335388Smjacob ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 34435388Smjacob 34535388Smjacob/* 34635388Smjacob * SXP Block Register Offsets 34735388Smjacob */ 34854671Smjacob#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 34954671Smjacob#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 35054671Smjacob#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 35154671Smjacob#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 35254671Smjacob#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 35354671Smjacob#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 35454671Smjacob#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 35554671Smjacob#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 35654671Smjacob#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 35754671Smjacob#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 35854671Smjacob#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 35954671Smjacob#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 36054671Smjacob#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 36154671Smjacob#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 36254671Smjacob#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 36354671Smjacob#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 36454671Smjacob#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 36554671Smjacob#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 36654671Smjacob#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 36754671Smjacob#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 36854671Smjacob#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 36954671Smjacob#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 37054671Smjacob#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 37154671Smjacob#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 37254671Smjacob#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 37354671Smjacob#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 37454671Smjacob#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 37554671Smjacob#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 37654671Smjacob#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 37754671Smjacob#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 37854671Smjacob#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 37954671Smjacob#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 38054671Smjacob#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 38154671Smjacob#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 38254671Smjacob#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 38354671Smjacob#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 38454671Smjacob#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 38554671Smjacob#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 38654671Smjacob#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 38735388Smjacob 38854671Smjacob/* for 1080/1280/1240 only */ 38954671Smjacob#define SXP_BANK1_SELECT 0x100 39035388Smjacob 39154671Smjacob 39235388Smjacob/* SXP CONF1 REGISTER */ 39335388Smjacob#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 39435388Smjacob#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 39535388Smjacob#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 39635388Smjacob#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 39735388Smjacob#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 39835388Smjacob 39935388Smjacob/* SXP CONF2 REGISTER */ 40035388Smjacob#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 40135388Smjacob#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 40235388Smjacob#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 40335388Smjacob#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 40435388Smjacob#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 40535388Smjacob#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 40635388Smjacob 40735388Smjacob/* SXP INTERRUPT REGISTER */ 40835388Smjacob#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 40935388Smjacob#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 41035388Smjacob#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 41135388Smjacob#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 41235388Smjacob#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 41335388Smjacob#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 41435388Smjacob#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 41535388Smjacob#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 41635388Smjacob#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 41735388Smjacob#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 41835388Smjacob 41935388Smjacob 42035388Smjacob/* SXP GROSS ERROR REGISTER */ 42135388Smjacob#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 42235388Smjacob#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 42335388Smjacob#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 42435388Smjacob#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 42535388Smjacob#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 42635388Smjacob#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 42735388Smjacob#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 42835388Smjacob 42935388Smjacob/* SXP EXCEPTION REGISTER */ 43035388Smjacob#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 43135388Smjacob#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 43235388Smjacob#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 43335388Smjacob#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 43435388Smjacob#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 43535388Smjacob#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 43635388Smjacob#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 43735388Smjacob#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 43835388Smjacob#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 43935388Smjacob#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 44035388Smjacob 44135388Smjacob /* SXP OVERRIDE REGISTER */ 44235388Smjacob#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 44335388Smjacob#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 44435388Smjacob#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 44535388Smjacob#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 44635388Smjacob#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 44735388Smjacob#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 44835388Smjacob#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 44935388Smjacob#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 45035388Smjacob#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 45135388Smjacob#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 45235388Smjacob#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 45335388Smjacob#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 45435388Smjacob#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 45535388Smjacob 45635388Smjacob/* SXP COMMANDS */ 45735388Smjacob#define SXP_RESET_BUS_CMD 0x300b 45835388Smjacob 45935388Smjacob/* SXP SCSI ID REGISTER */ 46035388Smjacob#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 46135388Smjacob#define SXP_SELECT_ID 0x000F /* Select id */ 46235388Smjacob 46335388Smjacob/* SXP DEV CONFIG1 REGISTER */ 46435388Smjacob#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 46535388Smjacob#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 46635388Smjacob#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 46735388Smjacob 46835388Smjacob 46935388Smjacob/* SXP DEV CONFIG2 REGISTER */ 47035388Smjacob#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 47135388Smjacob#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 47235388Smjacob#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 47335388Smjacob#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 47435388Smjacob#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 47535388Smjacob 47635388Smjacob 47735388Smjacob/* SXP PHASE POINTER REGISTER */ 47835388Smjacob#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 47935388Smjacob#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 48035388Smjacob#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 48135388Smjacob#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 48235388Smjacob 48335388Smjacob 48435388Smjacob/* SXP FIFO STATUS REGISTER */ 48535388Smjacob#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 48635388Smjacob#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 48735388Smjacob#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 48835388Smjacob#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 48935388Smjacob 49035388Smjacob 49135388Smjacob/* SXP CONTROL PINS REGISTER */ 49235388Smjacob#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 49335388Smjacob#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 49435388Smjacob#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 49535388Smjacob#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 49635388Smjacob#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 49735388Smjacob#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 49835388Smjacob#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 49935388Smjacob#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 50035388Smjacob#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 50135388Smjacob#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 50235388Smjacob#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 50335388Smjacob#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 50435388Smjacob 50535388Smjacob/* 50635388Smjacob * Set the hold time for the SCSI Bus Reset to be 250 ms 50735388Smjacob */ 50835388Smjacob#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 50935388Smjacob 51035388Smjacob/* SXP DIFF PINS REGISTER */ 51135388Smjacob#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 51235388Smjacob#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 51335388Smjacob#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 51435388Smjacob#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 51535388Smjacob#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 51635388Smjacob#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 51735388Smjacob 51854671Smjacob/* Ultra2 only */ 51945040Smjacob#define SXP_PINS_LVD_MODE 0x1000 52045040Smjacob#define SXP_PINS_HVD_MODE 0x0800 52145040Smjacob#define SXP_PINS_SE_MODE 0x0400 52245040Smjacob 52345040Smjacob/* The above have to be put together with the DIFFM pin to make sense */ 52445040Smjacob#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 52545040Smjacob#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 52645040Smjacob#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 52745040Smjacob#define ISP1080_MODE_MASK \ 52845040Smjacob (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 52945040Smjacob 53035388Smjacob/* 53135388Smjacob * RISC and Host Command and Control Block Register Offsets 53235388Smjacob */ 53335388Smjacob 53435388Smjacob#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 53535388Smjacob#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 53635388Smjacob#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 53735388Smjacob#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 53835388Smjacob#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 53935388Smjacob#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 54035388Smjacob#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 54135388Smjacob#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 54235388Smjacob#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 54335388Smjacob#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 54435388Smjacob#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 54535388Smjacob#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 54635388Smjacob#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 54735388Smjacob#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 54835388Smjacob#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 54935388Smjacob#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 55035388Smjacob#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 55135388Smjacob#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 55235388Smjacob#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 55335388Smjacob#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 55435388Smjacob#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 55535388Smjacob#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 55635388Smjacob#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 55735388Smjacob#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 55835388Smjacob#define RISC_MTR2100 RISC_BLOCK+0x30 55935388Smjacob 56035388Smjacob#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 56143420Smjacob#define DUAL_BANK 8 56235388Smjacob#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 56335388Smjacob#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 56435388Smjacob#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 56535388Smjacob#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 56635388Smjacob#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 56735388Smjacob#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 56835388Smjacob#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 56935388Smjacob 57035388Smjacob 57135388Smjacob/* PROCESSOR STATUS REGISTER */ 57235388Smjacob#define RISC_PSR_FORCE_TRUE 0x8000 57335388Smjacob#define RISC_PSR_LOOP_COUNT_DONE 0x4000 57435388Smjacob#define RISC_PSR_RISC_INT 0x2000 57535388Smjacob#define RISC_PSR_TIMER_ROLLOVER 0x1000 57635388Smjacob#define RISC_PSR_ALU_OVERFLOW 0x0800 57735388Smjacob#define RISC_PSR_ALU_MSB 0x0400 57835388Smjacob#define RISC_PSR_ALU_CARRY 0x0200 57935388Smjacob#define RISC_PSR_ALU_ZERO 0x0100 58039235Sgibbs 58139235Sgibbs#define RISC_PSR_PCI_ULTRA 0x0080 58239235Sgibbs#define RISC_PSR_SBUS_ULTRA 0x0020 58339235Sgibbs 58435388Smjacob#define RISC_PSR_DMA_INT 0x0010 58535388Smjacob#define RISC_PSR_SXP_INT 0x0008 58635388Smjacob#define RISC_PSR_HOST_INT 0x0004 58735388Smjacob#define RISC_PSR_INT_PENDING 0x0002 58835388Smjacob#define RISC_PSR_FORCE_FALSE 0x0001 58935388Smjacob 59035388Smjacob 59135388Smjacob/* Host Command and Control */ 59235388Smjacob#define HCCR_CMD_NOP 0x0000 /* NOP */ 59335388Smjacob#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 59435388Smjacob#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 59535388Smjacob#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 59635388Smjacob#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 59735388Smjacob#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 59835388Smjacob#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 59935388Smjacob#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 60035388Smjacob#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 60135388Smjacob#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 60235388Smjacob#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 60335388Smjacob#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 60435388Smjacob#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 60535388Smjacob 60635388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 60735388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 60835388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 60935388Smjacob#define ISP2100_HCCR_PARITY 0x0001 61035388Smjacob 61135388Smjacob#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 61235388Smjacob#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 61335388Smjacob#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 61435388Smjacob 61535388Smjacob#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 61635388Smjacob#define HCCR_RESET 0x0040 /* R : reset in progress */ 61735388Smjacob#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 61835388Smjacob 61935388Smjacob#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 62039235Sgibbs 62139235Sgibbs/* 62246967Smjacob * NVRAM Definitions (PCI cards only) 62346967Smjacob */ 62446967Smjacob 62546967Smjacob#define ISPBSMX(c, byte, shift, mask) \ 62646967Smjacob (((c)[(byte)] >> (shift)) & (mask)) 62746967Smjacob/* 62846967Smjacob * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 62939235Sgibbs * 63039235Sgibbs * Some portion of the front of this is for general host adapter properties 63139235Sgibbs * This is followed by an array of per-target parameters, and is tailed off 63239235Sgibbs * with a checksum xor byte at offset 127. For non-byte entities data is 63339235Sgibbs * stored in Little Endian order. 63439235Sgibbs */ 63539235Sgibbs 63639235Sgibbs#define ISP_NVRAM_SIZE 128 63745040Smjacob 63839235Sgibbs#define ISP_NVRAM_VERSION(c) (c)[4] 63939235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 64039235Sgibbs#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 64139235Sgibbs#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 64239235Sgibbs#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 64339235Sgibbs#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 64439235Sgibbs#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 64539235Sgibbs#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 64639235Sgibbs#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 64739235Sgibbs#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 64839235Sgibbs#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 64939235Sgibbs#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 65039235Sgibbs#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 65139235Sgibbs#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 65239235Sgibbs#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 65339235Sgibbs#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 65439235Sgibbs#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 65539235Sgibbs#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 65639235Sgibbs#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 65739235Sgibbs#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 65839235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 65939235Sgibbs#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 66039235Sgibbs#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 66139235Sgibbs#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 66239235Sgibbs#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 66339235Sgibbs#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 66439235Sgibbs#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 66539235Sgibbs#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 66639235Sgibbs#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 66739235Sgibbs#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 66839235Sgibbs 66939235Sgibbs#define ISP_NVRAM_TARGOFF 28 67039235Sgibbs#define ISP_NVARM_TARGSIZE 6 67139235Sgibbs#define _IxT(tgt, tidx) \ 67239235Sgibbs (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 67339235Sgibbs#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 67439235Sgibbs#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 67539235Sgibbs#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 67639235Sgibbs#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 67739235Sgibbs#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 67839235Sgibbs#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 67939235Sgibbs#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 68039235Sgibbs#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 68139235Sgibbs#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 68239235Sgibbs#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 68339235Sgibbs#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 68439235Sgibbs#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 68539235Sgibbs#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 68639235Sgibbs 68739235Sgibbs/* 68846967Smjacob * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 68946967Smjacob * 69046967Smjacob * Some portion of the front of this is for general host adapter properties 69146967Smjacob * This is followed by an array of per-target parameters, and is tailed off 69246967Smjacob * with a checksum xor byte at offset 256. For non-byte entities data is 69346967Smjacob * stored in Little Endian order. 69446967Smjacob */ 69546967Smjacob 69646967Smjacob#define ISP1080_NVRAM_SIZE 256 69746967Smjacob 69846967Smjacob#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 69946967Smjacob 70046967Smjacob/* Offset 5 */ 70146967Smjacob/* 70261769Smjacob u_int8_t bios_configuration_mode :2; 70361769Smjacob u_int8_t bios_disable :1; 70461769Smjacob u_int8_t selectable_scsi_boot_enable :1; 70561769Smjacob u_int8_t cd_rom_boot_enable :1; 70661769Smjacob u_int8_t disable_loading_risc_code :1; 70761769Smjacob u_int8_t enable_64bit_addressing :1; 70861769Smjacob u_int8_t unused_7 :1; 70946967Smjacob */ 71046967Smjacob 71146967Smjacob/* Offsets 6, 7 */ 71246967Smjacob/* 71361769Smjacob u_int8_t boot_lun_number :5; 71461769Smjacob u_int8_t scsi_bus_number :1; 71561769Smjacob u_int8_t unused_6 :1; 71661769Smjacob u_int8_t unused_7 :1; 71761769Smjacob u_int8_t boot_target_number :4; 71861769Smjacob u_int8_t unused_12 :1; 71961769Smjacob u_int8_t unused_13 :1; 72061769Smjacob u_int8_t unused_14 :1; 72161769Smjacob u_int8_t unused_15 :1; 72246967Smjacob */ 72346967Smjacob 72446967Smjacob#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 72546967Smjacob 72646967Smjacob#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 72746967Smjacob#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 72846967Smjacob 72946967Smjacob#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 73046967Smjacob#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 73146967Smjacob#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 73246967Smjacob 73346967Smjacob#define ISP1080_ISP_PARAMETER(c) \ 73446967Smjacob (((c)[18]) | ((c)[19] << 8)) 73546967Smjacob 73657148Smjacob#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 73757148Smjacob#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 73846967Smjacob 73946967Smjacob#define ISP1080_BUS1_OFF 112 74046967Smjacob 74146967Smjacob#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 74246967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 74346967Smjacob#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 74446967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 74546967Smjacob#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 74646967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 74746967Smjacob#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 74846967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 74946967Smjacob 75046967Smjacob#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 75146967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 75246967Smjacob#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 75346967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 75446967Smjacob#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 75546967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 75646967Smjacob#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 75746967Smjacob (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 75846967Smjacob ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 75946967Smjacob#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 76046967Smjacob (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 76146967Smjacob ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 76246967Smjacob 76346967Smjacob#define ISP1080_NVRAM_TARGOFF(b) \ 76446967Smjacob ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 76546967Smjacob#define ISP1080_NVRAM_TARGSIZE 6 76646967Smjacob#define _IxT8(tgt, tidx, b) \ 76746967Smjacob (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 76846967Smjacob 76946967Smjacob#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 77046967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 77146967Smjacob#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 77246967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 77346967Smjacob#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 77446967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 77546967Smjacob#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 77646967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 77746967Smjacob#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 77846967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 77946967Smjacob#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 78046967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 78146967Smjacob#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 78246967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 78346967Smjacob#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 78446967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 78546967Smjacob#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 78646967Smjacob ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 78746967Smjacob#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 78846967Smjacob ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 78946967Smjacob#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 79046967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 79146967Smjacob#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 79246967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 79346967Smjacob#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 79446967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 79546967Smjacob 79657148Smjacob#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 79757148Smjacob#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 79857148Smjacob#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 79957148Smjacob#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 80057148Smjacob#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 80157148Smjacob#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 80257148Smjacob#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 80357148Smjacob#define ISP12160_FAST_POST ISP1080_FAST_POST 80457148Smjacob#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 80557148Smjacob 80657148Smjacob#define ISP12160_NVRAM_INITIATOR_ID \ 80757148Smjacob ISP1080_NVRAM_INITIATOR_ID 80857148Smjacob#define ISP12160_NVRAM_BUS_RESET_DELAY \ 80957148Smjacob ISP1080_NVRAM_BUS_RESET_DELAY 81057148Smjacob#define ISP12160_NVRAM_BUS_RETRY_COUNT \ 81157148Smjacob ISP1080_NVRAM_BUS_RETRY_COUNT 81257148Smjacob#define ISP12160_NVRAM_BUS_RETRY_DELAY \ 81357148Smjacob ISP1080_NVRAM_BUS_RETRY_DELAY 81457148Smjacob#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 81557148Smjacob ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 81657148Smjacob#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 81757148Smjacob ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 81857148Smjacob#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 81957148Smjacob ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 82057148Smjacob#define ISP12160_NVRAM_SELECTION_TIMEOUT \ 82157148Smjacob ISP1080_NVRAM_SELECTION_TIMEOUT 82257148Smjacob#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 82357148Smjacob ISP1080_NVRAM_MAX_QUEUE_DEPTH 82457148Smjacob 82557148Smjacob 82657148Smjacob#define ISP12160_BUS0_OFF 24 82757148Smjacob#define ISP12160_BUS1_OFF 136 82857148Smjacob 82957148Smjacob#define ISP12160_NVRAM_TARGOFF(b) \ 83057148Smjacob (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 83157148Smjacob 83257148Smjacob#define ISP12160_NVRAM_TARGSIZE 6 83357148Smjacob#define _IxT16(tgt, tidx, b) \ 83457148Smjacob (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 83557148Smjacob 83657148Smjacob#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 83757148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 83857148Smjacob#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 83957148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 84057148Smjacob#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 84157148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 84257148Smjacob#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 84357148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 84457148Smjacob#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 84557148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 84657148Smjacob#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 84757148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 84857148Smjacob#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 84957148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 85057148Smjacob#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 85157148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 85257148Smjacob 85357148Smjacob#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 85457148Smjacob ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 85557148Smjacob#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 85657148Smjacob ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 85757148Smjacob 85857148Smjacob#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 85957148Smjacob ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 86057148Smjacob#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 86157148Smjacob ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 86257148Smjacob 86357148Smjacob#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 86457148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 86557148Smjacob#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 86657148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 86757148Smjacob#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 86857148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 86957148Smjacob 87046967Smjacob/* 87139235Sgibbs * Qlogic 2XXX NVRAM is an array of 256 bytes. 87239235Sgibbs * 87339235Sgibbs * Some portion of the front of this is for general RISC engine parameters, 87439235Sgibbs * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 87539235Sgibbs * 87639235Sgibbs * This is followed by some general host adapter parameters, and ends with 87739235Sgibbs * a checksum xor byte at offset 255. For non-byte entities data is stored 87839235Sgibbs * in Little Endian order. 87939235Sgibbs */ 88039235Sgibbs#define ISP2100_NVRAM_SIZE 256 88139235Sgibbs/* ISP_NVRAM_VERSION is in same overall place */ 88239235Sgibbs#define ISP2100_NVRAM_RISCVER(c) (c)[6] 88343792Smjacob#define ISP2100_NVRAM_OPTIONS(c) (c)[8] 88439235Sgibbs#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 88539235Sgibbs#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 88639235Sgibbs#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 88739235Sgibbs#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 88839235Sgibbs#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 88939235Sgibbs 89060218Smjacob#define ISP2100_NVRAM_PORT_NAME(c) (\ 89139235Sgibbs (((u_int64_t)(c)[18]) << 56) | \ 89239235Sgibbs (((u_int64_t)(c)[19]) << 48) | \ 89339235Sgibbs (((u_int64_t)(c)[20]) << 40) | \ 89439235Sgibbs (((u_int64_t)(c)[21]) << 32) | \ 89539235Sgibbs (((u_int64_t)(c)[22]) << 24) | \ 89639235Sgibbs (((u_int64_t)(c)[23]) << 16) | \ 89739235Sgibbs (((u_int64_t)(c)[24]) << 8) | \ 89839235Sgibbs (((u_int64_t)(c)[25]) << 0)) 89960218Smjacob 90041518Smjacob#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 90139235Sgibbs 90260218Smjacob#define ISP2100_NVRAM_NODE_NAME(c) (\ 90360218Smjacob (((u_int64_t)(c)[30]) << 56) | \ 90460218Smjacob (((u_int64_t)(c)[31]) << 48) | \ 90560218Smjacob (((u_int64_t)(c)[32]) << 40) | \ 90660218Smjacob (((u_int64_t)(c)[33]) << 32) | \ 90760218Smjacob (((u_int64_t)(c)[34]) << 24) | \ 90860218Smjacob (((u_int64_t)(c)[35]) << 16) | \ 90960218Smjacob (((u_int64_t)(c)[36]) << 8) | \ 91060218Smjacob (((u_int64_t)(c)[37]) << 0)) 91160218Smjacob 91243792Smjacob#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 91339235Sgibbs#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 91439235Sgibbs#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 91539235Sgibbs#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 91639235Sgibbs#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 91739235Sgibbs#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 91839235Sgibbs#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 91939235Sgibbs 92045040Smjacob#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 92139235Sgibbs (((u_int64_t)(c)[72]) << 56) | \ 92239235Sgibbs (((u_int64_t)(c)[73]) << 48) | \ 92339235Sgibbs (((u_int64_t)(c)[74]) << 40) | \ 92439235Sgibbs (((u_int64_t)(c)[75]) << 32) | \ 92539235Sgibbs (((u_int64_t)(c)[76]) << 24) | \ 92639235Sgibbs (((u_int64_t)(c)[77]) << 16) | \ 92739235Sgibbs (((u_int64_t)(c)[78]) << 8) | \ 92839235Sgibbs (((u_int64_t)(c)[79]) << 0)) 92943792Smjacob 93039235Sgibbs#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 93139235Sgibbs 93235388Smjacob#endif /* _ISPREG_H */ 933