ispreg.h revision 46967
1/* $Id: ispreg.h,v 1.8 1999/03/25 22:52:45 mjacob Exp $ */ 2/* release_5_11_99 */ 3/* 4 * Machine Independent (well, as best as possible) register 5 * definitions for Qlogic ISP SCSI adapters. 6 * 7 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35#ifndef _ISPREG_H 36#define _ISPREG_H 37 38/* 39 * Hardware definitions for the Qlogic ISP registers. 40 */ 41 42/* 43 * This defines types of access to various registers. 44 * 45 * R: Read Only 46 * W: Write Only 47 * RW: Read/Write 48 * 49 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 50 * if RISC processor in ISP is paused. 51 */ 52 53/* 54 * Offsets for various register blocks. 55 * 56 * Sad but true, different architectures have different offsets. 57 * 58 * Don't be alarmed if none of this makes sense. The original register 59 * layout set some defines in a certain pattern. Everything else has been 60 * grafted on since. For example, the ISP1080 manual will state that DMA 61 * registers start at 0x80 from the base of the register address space. 62 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 63 * to start at offset 0x60 because the DMA registers are all defined to 64 * be DMA_BLOCK+0x20 and so on. Clear? 65 */ 66 67#define BIU_REGS_OFF 0x00 68 69#define PCI_MBOX_REGS_OFF 0x70 70#define PCI_MBOX_REGS2100_OFF 0x10 71#define SBUS_MBOX_REGS_OFF 0x80 72 73#define PCI_SXP_REGS_OFF 0x80 74#define SBUS_SXP_REGS_OFF 0x200 75 76#define PCI_RISC_REGS_OFF 0x80 77#define SBUS_RISC_REGS_OFF 0x400 78 79/* Bless me! Chip designers have putzed it again! */ 80#define ISP1080_DMA_REGS_OFF 0x60 81#define DMA_REGS_OFF 0x00 /* same as BIU block */ 82 83/* 84 * NB: The *_BLOCK definitions have no specific hardware meaning. 85 * They serve simply to note to the MD layer which block of 86 * registers offsets are being accessed. 87 */ 88#define _NREG_BLKS 5 89#define _BLK_REG_SHFT 13 90#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 91#define BIU_BLOCK (0 << _BLK_REG_SHFT) 92#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 93#define SXP_BLOCK (2 << _BLK_REG_SHFT) 94#define RISC_BLOCK (3 << _BLK_REG_SHFT) 95#define DMA_BLOCK (4 << _BLK_REG_SHFT) 96 97/* 98 * Bus Interface Block Register Offsets 99 */ 100 101#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 102#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 103#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 104#define BIU2100_FLASH_DATA BIU_BLOCK+0x2 105#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 106#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 107#define BIU2100_CSR BIU_BLOCK+0x6 108#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 109#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 110#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 111#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 112#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 113#define RDMA2100_CONTROL DFIFO_COMMAND 114#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 115 116/* 117 * Putzed DMA register layouts. 118 */ 119#define CDMA_CONF DMA_BLOCK+0x20 /* RW*: DMA Configuration */ 120#define CDMA2100_CONTROL CDMA_CONF 121#define CDMA_CONTROL DMA_BLOCK+0x22 /* RW*: DMA Control */ 122#define CDMA_STATUS DMA_BLOCK+0x24 /* R : DMA Status */ 123#define CDMA_FIFO_STS DMA_BLOCK+0x26 /* R : DMA FIFO Status */ 124#define CDMA_COUNT DMA_BLOCK+0x28 /* RW*: DMA Transfer Count */ 125#define CDMA_ADDR0 DMA_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 126#define CDMA_ADDR1 DMA_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 127#define CDMA_ADDR2 DMA_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 128#define CDMA_ADDR3 DMA_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 129 130#define DDMA_CONF DMA_BLOCK+0x40 /* RW*: DMA Configuration */ 131#define TDMA2100_CONTROL DDMA_CONF 132#define DDMA_CONTROL DMA_BLOCK+0x42 /* RW*: DMA Control */ 133#define DDMA_STATUS DMA_BLOCK+0x44 /* R : DMA Status */ 134#define DDMA_FIFO_STS DMA_BLOCK+0x46 /* R : DMA FIFO Status */ 135#define DDMA_COUNT_LO DMA_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 136#define DDMA_COUNT_HI DMA_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 137#define DDMA_ADDR0 DMA_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 138#define DDMA_ADDR1 DMA_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 139/* these are for the 1040A cards */ 140#define DDMA_ADDR2 DMA_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 141#define DDMA_ADDR3 DMA_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 142 143 144/* 145 * Bus Interface Block Register Definitions 146 */ 147/* BUS CONFIGURATION REGISTER #0 */ 148#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 149/* BUS CONFIGURATION REGISTER #1 */ 150 151#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 152#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 153 154#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 155#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 156#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 157#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 158#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 159#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 160#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 161#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 162#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 163#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 164#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 165 166#define BIU_PCI1080_CONF1_SXP 0x0100 /* SXP bank select */ 167#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 168 169/* ISP2100 Bus Control/Status Register */ 170 171#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 172#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 173#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 174#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 175#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 176#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 177#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 178#define BIU2100_SOFT_RESET 0x01 179/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 180 181 182/* BUS CONTROL REGISTER */ 183#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 184#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 185#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 186#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 187#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 188#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 189 190#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 191#define BIU2100_ICR_ENA_FPM_INT 0x0020 192#define BIU2100_ICR_ENA_FB_INT 0x0010 193#define BIU2100_ICR_ENA_RISC_INT 0x0008 194#define BIU2100_ICR_ENA_CDMA_INT 0x0004 195#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 196#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 197#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 198 199#define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 200 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 201 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 202 203#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 204 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 205 (ISP_READ(isp, BIU_ICR) & \ 206 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 207 208#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 209 210/* BUS STATUS REGISTER */ 211#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 212#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 213#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 214#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 215#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 216 217#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 218#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 219#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 220#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 221#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 222#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 223#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 224 225 226/* BUS SEMAPHORE REGISTER */ 227#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 228#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 229 230/* NVRAM SEMAPHORE REGISTER */ 231#define BIU_NVRAM_CLOCK 0x0001 232#define BIU_NVRAM_SELECT 0x0002 233#define BIU_NVRAM_DATAOUT 0x0004 234#define BIU_NVRAM_DATAIN 0x0008 235#define ISP_NVRAM_READ 6 236 237/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 238#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 239#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 240#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 241#define DMA_DMA_DIRECTION 0x0001 /* 242 * Set DMA direction: 243 * 0 - DMA FIFO to host 244 * 1 - Host to DMA FIFO 245 */ 246 247/* COMMAND && DATA DMA CONTROL REGISTER */ 248#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 249#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 250 * Clear FIFO and DMA Channel, 251 * reset DMA registers 252 */ 253#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 254#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 255#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 256 257/* 258 * Variants of same for 2100 259 */ 260#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 261#define DMA_CNTRL2100_RESET_INT 0x0002 262 263 264 265/* DMA STATUS REGISTER */ 266#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 267#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 268#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 269#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 270#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 271#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 272 273#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 274#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 275#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 276#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 277#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 278#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 279#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 280#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 281#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 282#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 283#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 284 285/* DMA Status Register, pipeline status bits */ 286#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 287#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 288#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 289 * Pipeline stage 1 Loaded, 290 * stage 2 empty 291 */ 292#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 293#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 294#define DMA_PCI_PIPE_STAGE1 0x0001 /* 295 * Pipeline stage 1 Loaded, 296 * stage 2 empty 297 */ 298#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 299 300/* DMA Status Register, channel status bits */ 301#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 302#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 303#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 304#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 305#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 306#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 307#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 308 309 310/* DMA FIFO STATUS REGISTER */ 311#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 312#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 313#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 314#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 315 316/* 317 * Mailbox Block Register Offsets 318 */ 319 320#define INMAILBOX0 MBOX_BLOCK+0x0 321#define INMAILBOX1 MBOX_BLOCK+0x2 322#define INMAILBOX2 MBOX_BLOCK+0x4 323#define INMAILBOX3 MBOX_BLOCK+0x6 324#define INMAILBOX4 MBOX_BLOCK+0x8 325#define INMAILBOX5 MBOX_BLOCK+0xA 326#define INMAILBOX6 MBOX_BLOCK+0xC 327#define INMAILBOX7 MBOX_BLOCK+0xE 328 329#define OUTMAILBOX0 MBOX_BLOCK+0x0 330#define OUTMAILBOX1 MBOX_BLOCK+0x2 331#define OUTMAILBOX2 MBOX_BLOCK+0x4 332#define OUTMAILBOX3 MBOX_BLOCK+0x6 333#define OUTMAILBOX4 MBOX_BLOCK+0x8 334#define OUTMAILBOX5 MBOX_BLOCK+0xA 335#define OUTMAILBOX6 MBOX_BLOCK+0xC 336#define OUTMAILBOX7 MBOX_BLOCK+0xE 337 338#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 339#define NMBOX(isp) \ 340 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 341 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 342 343/* 344 * SXP Block Register Offsets 345 */ 346#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 347#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 348#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 349#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 350#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 351#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 352#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 353#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 354#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 355#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 356#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 357#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 358#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 359#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 360#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 361#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 362#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 363#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 364#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 365#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 366#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 367#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 368#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 369#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 370#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 371#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 372#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 373#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 374#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 375#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 376#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 377#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 378#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 379#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 380#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 381#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 382#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 383#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 384#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 385 386 387/* SXP CONF1 REGISTER */ 388#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 389#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 390#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 391#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 392#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 393 394/* SXP CONF2 REGISTER */ 395#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 396#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 397#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 398#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 399#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 400#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 401 402/* SXP INTERRUPT REGISTER */ 403#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 404#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 405#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 406#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 407#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 408#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 409#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 410#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 411#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 412#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 413 414 415/* SXP GROSS ERROR REGISTER */ 416#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 417#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 418#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 419#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 420#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 421#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 422#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 423 424/* SXP EXCEPTION REGISTER */ 425#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 426#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 427#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 428#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 429#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 430#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 431#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 432#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 433#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 434#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 435 436 /* SXP OVERRIDE REGISTER */ 437#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 438#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 439#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 440#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 441#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 442#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 443#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 444#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 445#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 446#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 447#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 448#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 449#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 450 451/* SXP COMMANDS */ 452#define SXP_RESET_BUS_CMD 0x300b 453 454/* SXP SCSI ID REGISTER */ 455#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 456#define SXP_SELECT_ID 0x000F /* Select id */ 457 458/* SXP DEV CONFIG1 REGISTER */ 459#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 460#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 461#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 462 463 464/* SXP DEV CONFIG2 REGISTER */ 465#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 466#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 467#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 468#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 469#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 470 471 472/* SXP PHASE POINTER REGISTER */ 473#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 474#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 475#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 476#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 477 478 479/* SXP FIFO STATUS REGISTER */ 480#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 481#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 482#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 483#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 484 485 486/* SXP CONTROL PINS REGISTER */ 487#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 488#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 489#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 490#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 491#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 492#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 493#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 494#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 495#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 496#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 497#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 498#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 499 500/* 501 * Set the hold time for the SCSI Bus Reset to be 250 ms 502 */ 503#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 504 505/* SXP DIFF PINS REGISTER */ 506#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 507#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 508#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 509#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 510#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 511#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 512 513/* 1080 only */ 514#define SXP_PINS_LVD_MODE 0x1000 515#define SXP_PINS_HVD_MODE 0x0800 516#define SXP_PINS_SE_MODE 0x0400 517 518/* The above have to be put together with the DIFFM pin to make sense */ 519#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 520#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 521#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 522#define ISP1080_MODE_MASK \ 523 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 524 525/* 526 * RISC and Host Command and Control Block Register Offsets 527 */ 528 529#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 530#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 531#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 532#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 533#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 534#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 535#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 536#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 537#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 538#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 539#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 540#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 541#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 542#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 543#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 544#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 545#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 546#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 547#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 548#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 549#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 550#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 551#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 552#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 553#define RISC_MTR2100 RISC_BLOCK+0x30 554 555#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 556#define DUAL_BANK 8 557#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 558#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 559#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 560#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 561#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 562#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 563#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 564 565 566/* PROCESSOR STATUS REGISTER */ 567#define RISC_PSR_FORCE_TRUE 0x8000 568#define RISC_PSR_LOOP_COUNT_DONE 0x4000 569#define RISC_PSR_RISC_INT 0x2000 570#define RISC_PSR_TIMER_ROLLOVER 0x1000 571#define RISC_PSR_ALU_OVERFLOW 0x0800 572#define RISC_PSR_ALU_MSB 0x0400 573#define RISC_PSR_ALU_CARRY 0x0200 574#define RISC_PSR_ALU_ZERO 0x0100 575 576#define RISC_PSR_PCI_ULTRA 0x0080 577#define RISC_PSR_SBUS_ULTRA 0x0020 578 579#define RISC_PSR_DMA_INT 0x0010 580#define RISC_PSR_SXP_INT 0x0008 581#define RISC_PSR_HOST_INT 0x0004 582#define RISC_PSR_INT_PENDING 0x0002 583#define RISC_PSR_FORCE_FALSE 0x0001 584 585 586/* Host Command and Control */ 587#define HCCR_CMD_NOP 0x0000 /* NOP */ 588#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 589#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 590#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 591#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 592#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 593#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 594#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 595#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 596#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 597#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 598#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 599#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 600 601#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 602#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 603#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 604#define ISP2100_HCCR_PARITY 0x0001 605 606#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 607#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 608#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 609 610#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 611#define HCCR_RESET 0x0040 /* R : reset in progress */ 612#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 613 614#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 615 616/* 617 * NVRAM Definitions (PCI cards only) 618 */ 619 620#define ISPBSMX(c, byte, shift, mask) \ 621 (((c)[(byte)] >> (shift)) & (mask)) 622/* 623 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 624 * 625 * Some portion of the front of this is for general host adapter properties 626 * This is followed by an array of per-target parameters, and is tailed off 627 * with a checksum xor byte at offset 127. For non-byte entities data is 628 * stored in Little Endian order. 629 */ 630 631#define ISP_NVRAM_SIZE 128 632 633#define ISP_NVRAM_VERSION(c) (c)[4] 634#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 635#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 636#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 637#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 638#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 639#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 640#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 641#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 642#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 643#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 644#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 645#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 646#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 647#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 648#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 649#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 650#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 651#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 652#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 653#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 654#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 655#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 656#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 657#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 658#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 659#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 660#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 661#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 662#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 663 664#define ISP_NVRAM_TARGOFF 28 665#define ISP_NVARM_TARGSIZE 6 666#define _IxT(tgt, tidx) \ 667 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 668#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 669#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 670#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 671#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 672#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 673#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 674#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 675#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 676#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 677#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 678#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 679#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 680#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 681 682/* 683 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 684 * 685 * Some portion of the front of this is for general host adapter properties 686 * This is followed by an array of per-target parameters, and is tailed off 687 * with a checksum xor byte at offset 256. For non-byte entities data is 688 * stored in Little Endian order. 689 */ 690 691#define ISP1080_NVRAM_SIZE 256 692 693#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 694 695/* Offset 5 */ 696/* 697 uint8_t bios_configuration_mode :2; 698 uint8_t bios_disable :1; 699 uint8_t selectable_scsi_boot_enable :1; 700 uint8_t cd_rom_boot_enable :1; 701 uint8_t disable_loading_risc_code :1; 702 uint8_t enable_64bit_addressing :1; 703 uint8_t unused_7 :1; 704 */ 705 706/* Offsets 6, 7 */ 707/* 708 uint8_t boot_lun_number :5; 709 uint8_t scsi_bus_number :1; 710 uint8_t unused_6 :1; 711 uint8_t unused_7 :1; 712 uint8_t boot_target_number :4; 713 uint8_t unused_12 :1; 714 uint8_t unused_13 :1; 715 uint8_t unused_14 :1; 716 uint8_t unused_15 :1; 717 */ 718 719#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 720 721#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 722#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 723 724#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 725#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 726#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 727 728#define ISP1080_ISP_PARAMETER(c) \ 729 (((c)[18]) | ((c)[19] << 8)) 730 731#define ISP1080_FAST_POST ISPBSMX(c, 20, 0, 0x01) 732#define ISP1080_REPORT_LVD_TRANSITION ISPBSMX(c, 20, 1, 0x01) 733 734#define ISP1080_BUS1_OFF 112 735 736#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 737 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 738#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 739 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 740#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 741 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 742#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 743 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 744 745#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 746 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 747#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 748 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 749#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 750 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 751#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 752 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 753 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 754#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 755 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 756 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 757 758#define ISP1080_NVRAM_TARGOFF(b) \ 759 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 760#define ISP1080_NVRAM_TARGSIZE 6 761#define _IxT8(tgt, tidx, b) \ 762 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 763 764#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 765 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 766#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 767 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 768#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 769 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 770#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 771 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 772#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 773 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 774#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 775 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 776#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 777 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 778#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 779 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 780#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 781 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 782#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 783 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 784#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 785 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 786#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 787 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 788#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 789 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 790 791/* 792 * Qlogic 2XXX NVRAM is an array of 256 bytes. 793 * 794 * Some portion of the front of this is for general RISC engine parameters, 795 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 796 * 797 * This is followed by some general host adapter parameters, and ends with 798 * a checksum xor byte at offset 255. For non-byte entities data is stored 799 * in Little Endian order. 800 */ 801#define ISP2100_NVRAM_SIZE 256 802/* ISP_NVRAM_VERSION is in same overall place */ 803#define ISP2100_NVRAM_RISCVER(c) (c)[6] 804#define ISP2100_NVRAM_OPTIONS(c) (c)[8] 805#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 806#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 807#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 808#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 809#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 810 811#define ISP2100_NVRAM_NODE_NAME(c) (\ 812 (((u_int64_t)(c)[18]) << 56) | \ 813 (((u_int64_t)(c)[19]) << 48) | \ 814 (((u_int64_t)(c)[20]) << 40) | \ 815 (((u_int64_t)(c)[21]) << 32) | \ 816 (((u_int64_t)(c)[22]) << 24) | \ 817 (((u_int64_t)(c)[23]) << 16) | \ 818 (((u_int64_t)(c)[24]) << 8) | \ 819 (((u_int64_t)(c)[25]) << 0)) 820#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 821 822#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 823#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 824#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 825#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 826#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 827#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 828#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 829 830#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 831 (((u_int64_t)(c)[72]) << 56) | \ 832 (((u_int64_t)(c)[73]) << 48) | \ 833 (((u_int64_t)(c)[74]) << 40) | \ 834 (((u_int64_t)(c)[75]) << 32) | \ 835 (((u_int64_t)(c)[76]) << 24) | \ 836 (((u_int64_t)(c)[77]) << 16) | \ 837 (((u_int64_t)(c)[78]) << 8) | \ 838 (((u_int64_t)(c)[79]) << 0)) 839 840#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 841 842#endif /* _ISPREG_H */ 843