ispreg.h revision 43792
143792Smjacob/* $Id: ispreg.h,v 1.5 1999/01/30 07:29:00 mjacob Exp $ */ 243792Smjacob/* release_02_05_99 */ 335388Smjacob/* 435388Smjacob * Machine Independent (well, as best as possible) register 535388Smjacob * definitions for Qlogic ISP SCSI adapters. 635388Smjacob * 735388Smjacob *--------------------------------------- 835388Smjacob * Copyright (c) 1997 by Matthew Jacob 935388Smjacob * NASA/Ames Research Center 1035388Smjacob * All rights reserved. 1135388Smjacob *--------------------------------------- 1235388Smjacob * Redistribution and use in source and binary forms, with or without 1335388Smjacob * modification, are permitted provided that the following conditions 1435388Smjacob * are met: 1535388Smjacob * 1. Redistributions of source code must retain the above copyright 1635388Smjacob * notice immediately at the beginning of the file, without modification, 1735388Smjacob * this list of conditions, and the following disclaimer. 1835388Smjacob * 2. Redistributions in binary form must reproduce the above copyright 1935388Smjacob * notice, this list of conditions and the following disclaimer in the 2035388Smjacob * documentation and/or other materials provided with the distribution. 2135388Smjacob * 3. The name of the author may not be used to endorse or promote products 2235388Smjacob * derived from this software without specific prior written permission. 2335388Smjacob * 2435388Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2535388Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2635388Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2735388Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2835388Smjacob * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2935388Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3035388Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3135388Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3235388Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3335388Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3435388Smjacob * SUCH DAMAGE. 3535388Smjacob */ 3635388Smjacob#ifndef _ISPREG_H 3735388Smjacob#define _ISPREG_H 3835388Smjacob 3935388Smjacob/* 4035388Smjacob * Hardware definitions for the Qlogic ISP registers. 4135388Smjacob */ 4235388Smjacob 4335388Smjacob/* 4435388Smjacob * This defines types of access to various registers. 4535388Smjacob * 4635388Smjacob * R: Read Only 4735388Smjacob * W: Write Only 4835388Smjacob * RW: Read/Write 4935388Smjacob * 5035388Smjacob * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 5135388Smjacob * if RISC processor in ISP is paused. 5235388Smjacob */ 5335388Smjacob 5435388Smjacob/* 5535388Smjacob * Offsets for various register blocks. 5635388Smjacob * 5735388Smjacob * Sad but true, different architectures have different offsets. 5835388Smjacob */ 5935388Smjacob 6035388Smjacob#define BIU_REGS_OFF 0x00 6135388Smjacob 6235388Smjacob#define PCI_MBOX_REGS_OFF 0x70 6335388Smjacob#define PCI_MBOX_REGS2100_OFF 0x10 6435388Smjacob#define SBUS_MBOX_REGS_OFF 0x80 6535388Smjacob 6635388Smjacob#define PCI_SXP_REGS_OFF 0x80 6735388Smjacob#define SBUS_SXP_REGS_OFF 0x200 6835388Smjacob 6935388Smjacob#define PCI_RISC_REGS_OFF 0x80 7035388Smjacob#define SBUS_RISC_REGS_OFF 0x400 7135388Smjacob 7235388Smjacob/* 7335388Smjacob * NB: The *_BLOCK definitions have no specific hardware meaning. 7435388Smjacob * They serve simply to note to the MD layer which block of 7535388Smjacob * registers offsets are being accessed. 7635388Smjacob */ 7735388Smjacob 7835388Smjacob/* 7935388Smjacob * Bus Interface Block Register Offsets 8035388Smjacob */ 8135388Smjacob#define BIU_BLOCK 0x0100 8235388Smjacob#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 8335388Smjacob#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 8435388Smjacob#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 8535388Smjacob#define BIU2100_FLASH_DATA BIU_BLOCK+0x2 8635388Smjacob#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 8735388Smjacob#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 8835388Smjacob#define BIU2100_CSR BIU_BLOCK+0x6 8935388Smjacob#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 9035388Smjacob#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 9135388Smjacob#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 9235388Smjacob#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 9335388Smjacob#define CDMA_CONF BIU_BLOCK+0x20 /* RW*: DMA Configuration */ 9435388Smjacob#define CDMA2100_CONTROL CDMA_CONF 9535388Smjacob#define CDMA_CONTROL BIU_BLOCK+0x22 /* RW*: DMA Control */ 9635388Smjacob#define CDMA_STATUS BIU_BLOCK+0x24 /* R : DMA Status */ 9735388Smjacob#define CDMA_FIFO_STS BIU_BLOCK+0x26 /* R : DMA FIFO Status */ 9835388Smjacob#define CDMA_COUNT BIU_BLOCK+0x28 /* RW*: DMA Transfer Count */ 9935388Smjacob#define CDMA_ADDR0 BIU_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 10035388Smjacob#define CDMA_ADDR1 BIU_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 10135388Smjacob/* these are for the 1040A cards */ 10235388Smjacob#define CDMA_ADDR2 BIU_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 10335388Smjacob#define CDMA_ADDR3 BIU_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 10435388Smjacob 10535388Smjacob#define DDMA_CONF BIU_BLOCK+0x40 /* RW*: DMA Configuration */ 10635388Smjacob#define TDMA2100_CONTROL DDMA_CONF 10735388Smjacob#define DDMA_CONTROL BIU_BLOCK+0x42 /* RW*: DMA Control */ 10835388Smjacob#define DDMA_STATUS BIU_BLOCK+0x44 /* R : DMA Status */ 10935388Smjacob#define DDMA_FIFO_STS BIU_BLOCK+0x46 /* R : DMA FIFO Status */ 11035388Smjacob#define DDMA_COUNT_LO BIU_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 11135388Smjacob#define DDMA_COUNT_HI BIU_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 11235388Smjacob#define DDMA_ADDR0 BIU_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 11335388Smjacob#define DDMA_ADDR1 BIU_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 11435388Smjacob/* these are for the 1040A cards */ 11535388Smjacob#define DDMA_ADDR2 BIU_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 11635388Smjacob#define DDMA_ADDR3 BIU_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 11735388Smjacob 11835388Smjacob#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 11935388Smjacob#define RDMA2100_CONTROL DFIFO_COMMAND 12035388Smjacob#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 12135388Smjacob 12235388Smjacob/* 12335388Smjacob * Bus Interface Block Register Definitions 12435388Smjacob */ 12535388Smjacob/* BUS CONFIGURATION REGISTER #0 */ 12635388Smjacob#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 12735388Smjacob/* BUS CONFIGURATION REGISTER #1 */ 12835388Smjacob 12935388Smjacob#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 13035388Smjacob#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 13135388Smjacob 13235388Smjacob#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 13335388Smjacob#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 13435388Smjacob#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 13535388Smjacob#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 13635388Smjacob#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 13735388Smjacob#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 13835388Smjacob#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 13935388Smjacob#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 14035388Smjacob#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 14135388Smjacob#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 14235388Smjacob#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 14335388Smjacob 14435388Smjacob /* ISP2100 Bus Control/Status Register */ 14535388Smjacob 14635388Smjacob#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 14735388Smjacob#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 14835388Smjacob#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 14935388Smjacob#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 15035388Smjacob#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 15135388Smjacob#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 15235388Smjacob#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 15335388Smjacob#define BIU2100_SOFT_RESET 0x01 15435388Smjacob/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 15535388Smjacob 15635388Smjacob 15735388Smjacob/* BUS CONTROL REGISTER */ 15835388Smjacob#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 15935388Smjacob#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 16035388Smjacob#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 16135388Smjacob#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 16235388Smjacob#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 16335388Smjacob#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 16435388Smjacob 16535388Smjacob#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 16635388Smjacob#define BIU2100_ICR_ENA_FPM_INT 0x0020 16735388Smjacob#define BIU2100_ICR_ENA_FB_INT 0x0010 16835388Smjacob#define BIU2100_ICR_ENA_RISC_INT 0x0008 16935388Smjacob#define BIU2100_ICR_ENA_CDMA_INT 0x0004 17035388Smjacob#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 17135388Smjacob#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 17235388Smjacob#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 17335388Smjacob 17435388Smjacob#define ENABLE_INTS(isp) (isp->isp_type & ISP_HA_SCSI)? \ 17535388Smjacob ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 17635388Smjacob ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 17735388Smjacob 17835388Smjacob#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 17935388Smjacob 18035388Smjacob/* BUS STATUS REGISTER */ 18135388Smjacob#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 18235388Smjacob#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 18335388Smjacob#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 18435388Smjacob#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 18535388Smjacob#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 18635388Smjacob 18735388Smjacob#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 18835388Smjacob#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 18935388Smjacob#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 19035388Smjacob#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 19135388Smjacob#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 19235388Smjacob#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 19335388Smjacob#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 19435388Smjacob 19535388Smjacob 19635388Smjacob/* BUS SEMAPHORE REGISTER */ 19735388Smjacob#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 19835388Smjacob#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 19935388Smjacob 20039235Sgibbs/* NVRAM SEMAPHORE REGISTER */ 20139235Sgibbs#define BIU_NVRAM_CLOCK 0x0001 20239235Sgibbs#define BIU_NVRAM_SELECT 0x0002 20339235Sgibbs#define BIU_NVRAM_DATAOUT 0x0004 20439235Sgibbs#define BIU_NVRAM_DATAIN 0x0008 20539235Sgibbs#define ISP_NVRAM_READ 6 20635388Smjacob 20735388Smjacob/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 20835388Smjacob#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 20935388Smjacob#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 21035388Smjacob#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 21135388Smjacob#define DMA_DMA_DIRECTION 0x0001 /* 21235388Smjacob * Set DMA direction: 21335388Smjacob * 0 - DMA FIFO to host 21435388Smjacob * 1 - Host to DMA FIFO 21535388Smjacob */ 21635388Smjacob 21735388Smjacob/* COMMAND && DATA DMA CONTROL REGISTER */ 21835388Smjacob#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 21935388Smjacob#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 22035388Smjacob * Clear FIFO and DMA Channel, 22135388Smjacob * reset DMA registers 22235388Smjacob */ 22335388Smjacob#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 22435388Smjacob#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 22535388Smjacob#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 22635388Smjacob 22735388Smjacob/* 22835388Smjacob * Variants of same for 2100 22935388Smjacob */ 23035388Smjacob#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 23135388Smjacob#define DMA_CNTRL2100_RESET_INT 0x0002 23235388Smjacob 23335388Smjacob 23435388Smjacob 23535388Smjacob/* DMA STATUS REGISTER */ 23635388Smjacob#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 23735388Smjacob#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 23835388Smjacob#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 23935388Smjacob#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 24035388Smjacob#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 24135388Smjacob#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 24235388Smjacob 24335388Smjacob#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 24435388Smjacob#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 24535388Smjacob#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 24635388Smjacob#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 24735388Smjacob#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 24835388Smjacob#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 24935388Smjacob#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 25035388Smjacob#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 25135388Smjacob#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 25235388Smjacob#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 25335388Smjacob#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 25435388Smjacob 25535388Smjacob/* DMA Status Register, pipeline status bits */ 25635388Smjacob#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 25735388Smjacob#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 25835388Smjacob#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 25935388Smjacob * Pipeline stage 1 Loaded, 26035388Smjacob * stage 2 empty 26135388Smjacob */ 26235388Smjacob#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 26335388Smjacob#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 26435388Smjacob#define DMA_PCI_PIPE_STAGE1 0x0001 /* 26535388Smjacob * Pipeline stage 1 Loaded, 26635388Smjacob * stage 2 empty 26735388Smjacob */ 26835388Smjacob#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 26935388Smjacob 27035388Smjacob/* DMA Status Register, channel status bits */ 27135388Smjacob#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 27235388Smjacob#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 27335388Smjacob#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 27435388Smjacob#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 27535388Smjacob#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 27635388Smjacob#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 27735388Smjacob#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 27835388Smjacob 27935388Smjacob 28035388Smjacob/* DMA FIFO STATUS REGISTER */ 28135388Smjacob#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 28235388Smjacob#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 28335388Smjacob#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 28435388Smjacob#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 28535388Smjacob 28635388Smjacob/* 28735388Smjacob * Mailbox Block Register Offsets 28835388Smjacob */ 28935388Smjacob 29035388Smjacob#define MBOX_BLOCK 0x0200 29135388Smjacob#define INMAILBOX0 MBOX_BLOCK+0x0 29235388Smjacob#define INMAILBOX1 MBOX_BLOCK+0x2 29335388Smjacob#define INMAILBOX2 MBOX_BLOCK+0x4 29435388Smjacob#define INMAILBOX3 MBOX_BLOCK+0x6 29535388Smjacob#define INMAILBOX4 MBOX_BLOCK+0x8 29635388Smjacob#define INMAILBOX5 MBOX_BLOCK+0xA 29735388Smjacob#define INMAILBOX6 MBOX_BLOCK+0xC 29835388Smjacob#define INMAILBOX7 MBOX_BLOCK+0xE 29935388Smjacob 30035388Smjacob#define OUTMAILBOX0 MBOX_BLOCK+0x0 30135388Smjacob#define OUTMAILBOX1 MBOX_BLOCK+0x2 30235388Smjacob#define OUTMAILBOX2 MBOX_BLOCK+0x4 30335388Smjacob#define OUTMAILBOX3 MBOX_BLOCK+0x6 30435388Smjacob#define OUTMAILBOX4 MBOX_BLOCK+0x8 30535388Smjacob#define OUTMAILBOX5 MBOX_BLOCK+0xA 30635388Smjacob#define OUTMAILBOX6 MBOX_BLOCK+0xC 30735388Smjacob#define OUTMAILBOX7 MBOX_BLOCK+0xE 30835388Smjacob 30935388Smjacob#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 31035388Smjacob#define NMBOX(isp) \ 31135388Smjacob (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 31235388Smjacob ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 31335388Smjacob 31435388Smjacob/* 31535388Smjacob * SXP Block Register Offsets 31635388Smjacob */ 31735388Smjacob#define SXP_BLOCK 0x0400 31835388Smjacob#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 31935388Smjacob#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 32035388Smjacob#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 32135388Smjacob#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 32235388Smjacob#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 32335388Smjacob#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 32435388Smjacob#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 32535388Smjacob#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 32635388Smjacob#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 32735388Smjacob#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 32835388Smjacob#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 32935388Smjacob#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 33035388Smjacob#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 33135388Smjacob#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 33235388Smjacob#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 33335388Smjacob#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 33435388Smjacob#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 33535388Smjacob#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 33635388Smjacob#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 33735388Smjacob#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 33835388Smjacob#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 33935388Smjacob#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 34035388Smjacob#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 34135388Smjacob#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 34235388Smjacob#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 34335388Smjacob#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 34435388Smjacob#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 34535388Smjacob#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 34635388Smjacob#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 34735388Smjacob#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 34835388Smjacob#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 34935388Smjacob#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 35035388Smjacob#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 35135388Smjacob#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 35235388Smjacob#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 35335388Smjacob#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 35435388Smjacob#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 35535388Smjacob#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 35635388Smjacob#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 35735388Smjacob 35835388Smjacob 35935388Smjacob/* SXP CONF1 REGISTER */ 36035388Smjacob#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 36135388Smjacob#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 36235388Smjacob#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 36335388Smjacob#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 36435388Smjacob#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 36535388Smjacob 36635388Smjacob/* SXP CONF2 REGISTER */ 36735388Smjacob#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 36835388Smjacob#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 36935388Smjacob#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 37035388Smjacob#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 37135388Smjacob#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 37235388Smjacob#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 37335388Smjacob 37435388Smjacob/* SXP INTERRUPT REGISTER */ 37535388Smjacob#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 37635388Smjacob#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 37735388Smjacob#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 37835388Smjacob#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 37935388Smjacob#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 38035388Smjacob#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 38135388Smjacob#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 38235388Smjacob#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 38335388Smjacob#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 38435388Smjacob#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 38535388Smjacob 38635388Smjacob 38735388Smjacob/* SXP GROSS ERROR REGISTER */ 38835388Smjacob#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 38935388Smjacob#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 39035388Smjacob#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 39135388Smjacob#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 39235388Smjacob#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 39335388Smjacob#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 39435388Smjacob#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 39535388Smjacob 39635388Smjacob/* SXP EXCEPTION REGISTER */ 39735388Smjacob#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 39835388Smjacob#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 39935388Smjacob#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 40035388Smjacob#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 40135388Smjacob#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 40235388Smjacob#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 40335388Smjacob#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 40435388Smjacob#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 40535388Smjacob#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 40635388Smjacob#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 40735388Smjacob 40835388Smjacob /* SXP OVERRIDE REGISTER */ 40935388Smjacob#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 41035388Smjacob#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 41135388Smjacob#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 41235388Smjacob#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 41335388Smjacob#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 41435388Smjacob#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 41535388Smjacob#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 41635388Smjacob#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 41735388Smjacob#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 41835388Smjacob#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 41935388Smjacob#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 42035388Smjacob#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 42135388Smjacob#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 42235388Smjacob 42335388Smjacob/* SXP COMMANDS */ 42435388Smjacob#define SXP_RESET_BUS_CMD 0x300b 42535388Smjacob 42635388Smjacob/* SXP SCSI ID REGISTER */ 42735388Smjacob#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 42835388Smjacob#define SXP_SELECT_ID 0x000F /* Select id */ 42935388Smjacob 43035388Smjacob/* SXP DEV CONFIG1 REGISTER */ 43135388Smjacob#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 43235388Smjacob#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 43335388Smjacob#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 43435388Smjacob 43535388Smjacob 43635388Smjacob/* SXP DEV CONFIG2 REGISTER */ 43735388Smjacob#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 43835388Smjacob#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 43935388Smjacob#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 44035388Smjacob#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 44135388Smjacob#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 44235388Smjacob 44335388Smjacob 44435388Smjacob/* SXP PHASE POINTER REGISTER */ 44535388Smjacob#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 44635388Smjacob#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 44735388Smjacob#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 44835388Smjacob#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 44935388Smjacob 45035388Smjacob 45135388Smjacob/* SXP FIFO STATUS REGISTER */ 45235388Smjacob#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 45335388Smjacob#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 45435388Smjacob#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 45535388Smjacob#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 45635388Smjacob 45735388Smjacob 45835388Smjacob/* SXP CONTROL PINS REGISTER */ 45935388Smjacob#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 46035388Smjacob#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 46135388Smjacob#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 46235388Smjacob#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 46335388Smjacob#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 46435388Smjacob#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 46535388Smjacob#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 46635388Smjacob#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 46735388Smjacob#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 46835388Smjacob#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 46935388Smjacob#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 47035388Smjacob#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 47135388Smjacob 47235388Smjacob/* 47335388Smjacob * Set the hold time for the SCSI Bus Reset to be 250 ms 47435388Smjacob */ 47535388Smjacob#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 47635388Smjacob 47735388Smjacob/* SXP DIFF PINS REGISTER */ 47835388Smjacob#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 47935388Smjacob#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 48035388Smjacob#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 48135388Smjacob#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 48235388Smjacob#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 48335388Smjacob#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 48435388Smjacob 48535388Smjacob/* 48635388Smjacob * RISC and Host Command and Control Block Register Offsets 48735388Smjacob */ 48835388Smjacob#define RISC_BLOCK 0x0800 48935388Smjacob 49035388Smjacob#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 49135388Smjacob#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 49235388Smjacob#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 49335388Smjacob#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 49435388Smjacob#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 49535388Smjacob#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 49635388Smjacob#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 49735388Smjacob#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 49835388Smjacob#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 49935388Smjacob#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 50035388Smjacob#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 50135388Smjacob#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 50235388Smjacob#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 50335388Smjacob#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 50435388Smjacob#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 50535388Smjacob#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 50635388Smjacob#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 50735388Smjacob#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 50835388Smjacob#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 50935388Smjacob#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 51035388Smjacob#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 51135388Smjacob#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 51235388Smjacob#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 51335388Smjacob#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 51435388Smjacob#define RISC_MTR2100 RISC_BLOCK+0x30 51535388Smjacob 51635388Smjacob#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 51743420Smjacob#define DUAL_BANK 8 51835388Smjacob#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 51935388Smjacob#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 52035388Smjacob#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 52135388Smjacob#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 52235388Smjacob#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 52335388Smjacob#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 52435388Smjacob#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 52535388Smjacob 52635388Smjacob 52735388Smjacob/* PROCESSOR STATUS REGISTER */ 52835388Smjacob#define RISC_PSR_FORCE_TRUE 0x8000 52935388Smjacob#define RISC_PSR_LOOP_COUNT_DONE 0x4000 53035388Smjacob#define RISC_PSR_RISC_INT 0x2000 53135388Smjacob#define RISC_PSR_TIMER_ROLLOVER 0x1000 53235388Smjacob#define RISC_PSR_ALU_OVERFLOW 0x0800 53335388Smjacob#define RISC_PSR_ALU_MSB 0x0400 53435388Smjacob#define RISC_PSR_ALU_CARRY 0x0200 53535388Smjacob#define RISC_PSR_ALU_ZERO 0x0100 53639235Sgibbs 53739235Sgibbs#define RISC_PSR_PCI_ULTRA 0x0080 53839235Sgibbs#define RISC_PSR_SBUS_ULTRA 0x0020 53939235Sgibbs 54035388Smjacob#define RISC_PSR_DMA_INT 0x0010 54135388Smjacob#define RISC_PSR_SXP_INT 0x0008 54235388Smjacob#define RISC_PSR_HOST_INT 0x0004 54335388Smjacob#define RISC_PSR_INT_PENDING 0x0002 54435388Smjacob#define RISC_PSR_FORCE_FALSE 0x0001 54535388Smjacob 54635388Smjacob 54735388Smjacob/* Host Command and Control */ 54835388Smjacob#define HCCR_CMD_NOP 0x0000 /* NOP */ 54935388Smjacob#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 55035388Smjacob#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 55135388Smjacob#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 55235388Smjacob#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 55335388Smjacob#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 55435388Smjacob#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 55535388Smjacob#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 55635388Smjacob#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 55735388Smjacob#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 55835388Smjacob#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 55935388Smjacob#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 56035388Smjacob#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 56135388Smjacob 56235388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 56335388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 56435388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 56535388Smjacob#define ISP2100_HCCR_PARITY 0x0001 56635388Smjacob 56735388Smjacob#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 56835388Smjacob#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 56935388Smjacob#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 57035388Smjacob 57135388Smjacob#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 57235388Smjacob#define HCCR_RESET 0x0040 /* R : reset in progress */ 57335388Smjacob#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 57435388Smjacob 57535388Smjacob#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 57639235Sgibbs 57739235Sgibbs/* 57839235Sgibbs * Qlogic 1XXX NVRAM is an array of 128 bytes. 57939235Sgibbs * 58039235Sgibbs * Some portion of the front of this is for general host adapter properties 58139235Sgibbs * This is followed by an array of per-target parameters, and is tailed off 58239235Sgibbs * with a checksum xor byte at offset 127. For non-byte entities data is 58339235Sgibbs * stored in Little Endian order. 58439235Sgibbs */ 58539235Sgibbs 58639235Sgibbs#define ISP_NVRAM_SIZE 128 58739235Sgibbs 58839235Sgibbs#define ISPBSMX(c, byte, shift, mask) \ 58939235Sgibbs (((c)[(byte)] >> (shift)) & (mask)) 59039235Sgibbs 59139235Sgibbs#define ISP_NVRAM_VERSION(c) (c)[4] 59239235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 59339235Sgibbs#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 59439235Sgibbs#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 59539235Sgibbs#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 59639235Sgibbs#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 59739235Sgibbs#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 59839235Sgibbs#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 59939235Sgibbs#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 60039235Sgibbs#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 60139235Sgibbs#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 60239235Sgibbs#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 60339235Sgibbs#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 60439235Sgibbs#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 60539235Sgibbs#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 60639235Sgibbs#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 60739235Sgibbs#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 60839235Sgibbs#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 60939235Sgibbs#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 61039235Sgibbs#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 61139235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 61239235Sgibbs#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 61339235Sgibbs#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 61439235Sgibbs#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 61539235Sgibbs#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 61639235Sgibbs#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 61739235Sgibbs#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 61839235Sgibbs#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 61939235Sgibbs#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 62039235Sgibbs#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 62139235Sgibbs 62239235Sgibbs#define ISP_NVRAM_TARGOFF 28 62339235Sgibbs#define ISP_NVARM_TARGSIZE 6 62439235Sgibbs#define _IxT(tgt, tidx) \ 62539235Sgibbs (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 62639235Sgibbs#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 62739235Sgibbs#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 62839235Sgibbs#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 62939235Sgibbs#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 63039235Sgibbs#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 63139235Sgibbs#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 63239235Sgibbs#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 63339235Sgibbs#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 63439235Sgibbs#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 63539235Sgibbs#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 63639235Sgibbs#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 63739235Sgibbs#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 63839235Sgibbs#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 63939235Sgibbs 64039235Sgibbs/* 64139235Sgibbs * Qlogic 2XXX NVRAM is an array of 256 bytes. 64239235Sgibbs * 64339235Sgibbs * Some portion of the front of this is for general RISC engine parameters, 64439235Sgibbs * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 64539235Sgibbs * 64639235Sgibbs * This is followed by some general host adapter parameters, and ends with 64739235Sgibbs * a checksum xor byte at offset 255. For non-byte entities data is stored 64839235Sgibbs * in Little Endian order. 64939235Sgibbs */ 65039235Sgibbs#define ISP2100_NVRAM_SIZE 256 65139235Sgibbs/* ISP_NVRAM_VERSION is in same overall place */ 65239235Sgibbs#define ISP2100_NVRAM_RISCVER(c) (c)[6] 65343792Smjacob#define ISP2100_NVRAM_OPTIONS(c) (c)[8] 65439235Sgibbs#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 65539235Sgibbs#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 65639235Sgibbs#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 65739235Sgibbs#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 65839235Sgibbs#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 65939235Sgibbs 66039235Sgibbs#define ISP2100_NVRAM_NODE_NAME(c) ( \ 66139235Sgibbs (((u_int64_t)(c)[18]) << 56) | \ 66239235Sgibbs (((u_int64_t)(c)[19]) << 48) | \ 66339235Sgibbs (((u_int64_t)(c)[20]) << 40) | \ 66439235Sgibbs (((u_int64_t)(c)[21]) << 32) | \ 66539235Sgibbs (((u_int64_t)(c)[22]) << 24) | \ 66639235Sgibbs (((u_int64_t)(c)[23]) << 16) | \ 66739235Sgibbs (((u_int64_t)(c)[24]) << 8) | \ 66839235Sgibbs (((u_int64_t)(c)[25]) << 0)) 66941518Smjacob#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 67039235Sgibbs 67143792Smjacob#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 67239235Sgibbs#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 67339235Sgibbs#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 67439235Sgibbs#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 67539235Sgibbs#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 67639235Sgibbs#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 67739235Sgibbs#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 67839235Sgibbs 67939235Sgibbs#define ISP2100_NVRAM_BOOT_NODE_NAME(c) ( \ 68039235Sgibbs (((u_int64_t)(c)[72]) << 56) | \ 68139235Sgibbs (((u_int64_t)(c)[73]) << 48) | \ 68239235Sgibbs (((u_int64_t)(c)[74]) << 40) | \ 68339235Sgibbs (((u_int64_t)(c)[75]) << 32) | \ 68439235Sgibbs (((u_int64_t)(c)[76]) << 24) | \ 68539235Sgibbs (((u_int64_t)(c)[77]) << 16) | \ 68639235Sgibbs (((u_int64_t)(c)[78]) << 8) | \ 68739235Sgibbs (((u_int64_t)(c)[79]) << 0)) 68843792Smjacob 68939235Sgibbs#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 69039235Sgibbs 69135388Smjacob#endif /* _ISPREG_H */ 692