150477Speter/* $FreeBSD: releng/10.3/sys/dev/isp/ispreg.h 291500 2015-11-30 21:30:18Z mav $ */ 2139749Simp/*- 3196008Smjacob * Copyright (c) 1997-2009 by Matthew Jacob 4167403Smjacob * All rights reserved. 5167403Smjacob * 6167403Smjacob * Redistribution and use in source and binary forms, with or without 7167403Smjacob * modification, are permitted provided that the following conditions 8167403Smjacob * are met: 9167403Smjacob * 10167403Smjacob * 1. Redistributions of source code must retain the above copyright 11167403Smjacob * notice, this list of conditions and the following disclaimer. 12167403Smjacob * 2. Redistributions in binary form must reproduce the above copyright 13167403Smjacob * notice, this list of conditions and the following disclaimer in the 14167403Smjacob * documentation and/or other materials provided with the distribution. 15167403Smjacob * 16167403Smjacob * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17167403Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18167403Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19167403Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20167403Smjacob * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21167403Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22167403Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23167403Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24167403Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25167403Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26167403Smjacob * SUCH DAMAGE. 27196008Smjacob * 28167403Smjacob */ 29167403Smjacob/* 3035388Smjacob * Machine Independent (well, as best as possible) register 3135388Smjacob * definitions for Qlogic ISP SCSI adapters. 3235388Smjacob */ 3335388Smjacob#ifndef _ISPREG_H 3435388Smjacob#define _ISPREG_H 3535388Smjacob 3635388Smjacob/* 3735388Smjacob * Hardware definitions for the Qlogic ISP registers. 3835388Smjacob */ 3935388Smjacob 4035388Smjacob/* 4135388Smjacob * This defines types of access to various registers. 4235388Smjacob * 4335388Smjacob * R: Read Only 4435388Smjacob * W: Write Only 4535388Smjacob * RW: Read/Write 4635388Smjacob * 4735388Smjacob * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 4835388Smjacob * if RISC processor in ISP is paused. 4935388Smjacob */ 5035388Smjacob 5135388Smjacob/* 5235388Smjacob * Offsets for various register blocks. 5335388Smjacob * 5435388Smjacob * Sad but true, different architectures have different offsets. 5546967Smjacob * 5646967Smjacob * Don't be alarmed if none of this makes sense. The original register 5746967Smjacob * layout set some defines in a certain pattern. Everything else has been 5846967Smjacob * grafted on since. For example, the ISP1080 manual will state that DMA 5946967Smjacob * registers start at 0x80 from the base of the register address space. 6046967Smjacob * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 6146967Smjacob * to start at offset 0x60 because the DMA registers are all defined to 6246967Smjacob * be DMA_BLOCK+0x20 and so on. Clear? 6335388Smjacob */ 6435388Smjacob 6544819Smjacob#define BIU_REGS_OFF 0x00 6635388Smjacob 6744819Smjacob#define PCI_MBOX_REGS_OFF 0x70 6844819Smjacob#define PCI_MBOX_REGS2100_OFF 0x10 6982689Smjacob#define PCI_MBOX_REGS2300_OFF 0x40 70163899Smjacob#define PCI_MBOX_REGS2400_OFF 0x80 7135388Smjacob#define SBUS_MBOX_REGS_OFF 0x80 7235388Smjacob 7344819Smjacob#define PCI_SXP_REGS_OFF 0x80 7435388Smjacob#define SBUS_SXP_REGS_OFF 0x200 7535388Smjacob 7644819Smjacob#define PCI_RISC_REGS_OFF 0x80 7735388Smjacob#define SBUS_RISC_REGS_OFF 0x400 7835388Smjacob 7944819Smjacob/* Bless me! Chip designers have putzed it again! */ 8044819Smjacob#define ISP1080_DMA_REGS_OFF 0x60 8144819Smjacob#define DMA_REGS_OFF 0x00 /* same as BIU block */ 8244819Smjacob 8364088Smjacob#define SBUS_REGSIZE 0x450 8464088Smjacob#define PCI_REGSIZE 0x100 8564088Smjacob 8635388Smjacob/* 8735388Smjacob * NB: The *_BLOCK definitions have no specific hardware meaning. 8835388Smjacob * They serve simply to note to the MD layer which block of 8935388Smjacob * registers offsets are being accessed. 9035388Smjacob */ 9144819Smjacob#define _NREG_BLKS 5 9244819Smjacob#define _BLK_REG_SHFT 13 9344819Smjacob#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 9444819Smjacob#define BIU_BLOCK (0 << _BLK_REG_SHFT) 9544819Smjacob#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 9644819Smjacob#define SXP_BLOCK (2 << _BLK_REG_SHFT) 9744819Smjacob#define RISC_BLOCK (3 << _BLK_REG_SHFT) 9844819Smjacob#define DMA_BLOCK (4 << _BLK_REG_SHFT) 9935388Smjacob 10035388Smjacob/* 10135388Smjacob * Bus Interface Block Register Offsets 10235388Smjacob */ 10344819Smjacob 10454671Smjacob#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 10554671Smjacob#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 10654671Smjacob#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 10754671Smjacob#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 10854671Smjacob#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 10954671Smjacob#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 11054671Smjacob#define BIU2100_CSR (BIU_BLOCK+0x6) 11154671Smjacob#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 11254671Smjacob#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 11354671Smjacob#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 11454671Smjacob#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 11582689Smjacob/* 11682689Smjacob * These are specific to the 2300. 11782689Smjacob */ 11882689Smjacob#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 11982689Smjacob#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 12082689Smjacob#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 12182689Smjacob#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 12282689Smjacob 12382689Smjacob#define BIU_R2HSTSLO (BIU_BLOCK+0x18) 12482689Smjacob#define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 12582689Smjacob 12682689Smjacob#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 12782689Smjacob#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 128290785Smav#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */ 12982689Smjacob#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 13082689Smjacob#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 13182689Smjacob#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 13282689Smjacob#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 13382689Smjacob#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 13482689Smjacob#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 135290785Smav#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */ 13682689Smjacob#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 13782689Smjacob#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 13882689Smjacob#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 139290785Smav#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */ 140290785Smav#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */ 141290785Smav#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */ 14282689Smjacob 143163899Smjacob/* fifo command stuff- mostly for SPI */ 14454671Smjacob#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 14544819Smjacob#define RDMA2100_CONTROL DFIFO_COMMAND 14654671Smjacob#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 14744819Smjacob 14844819Smjacob/* 14944819Smjacob * Putzed DMA register layouts. 15044819Smjacob */ 15154671Smjacob#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 15235388Smjacob#define CDMA2100_CONTROL CDMA_CONF 15354671Smjacob#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 15454671Smjacob#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 15554671Smjacob#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 15654671Smjacob#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 15754671Smjacob#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 15854671Smjacob#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 15954671Smjacob#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 16054671Smjacob#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 16135388Smjacob 16254671Smjacob#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 16335388Smjacob#define TDMA2100_CONTROL DDMA_CONF 16454671Smjacob#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 16554671Smjacob#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 16654671Smjacob#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 16754671Smjacob#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 16854671Smjacob#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 16954671Smjacob#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 17054671Smjacob#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 17135388Smjacob/* these are for the 1040A cards */ 17254671Smjacob#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 17354671Smjacob#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 17435388Smjacob 17535388Smjacob 17635388Smjacob/* 17735388Smjacob * Bus Interface Block Register Definitions 17835388Smjacob */ 17935388Smjacob/* BUS CONFIGURATION REGISTER #0 */ 18035388Smjacob#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 18135388Smjacob/* BUS CONFIGURATION REGISTER #1 */ 18235388Smjacob 18335388Smjacob#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 18435388Smjacob#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 18535388Smjacob 18635388Smjacob#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 18735388Smjacob#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 18835388Smjacob#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 18935388Smjacob#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 19035388Smjacob#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 19135388Smjacob#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 19235388Smjacob#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 19335388Smjacob#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 19435388Smjacob#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 19535388Smjacob#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 19635388Smjacob#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 19735388Smjacob 19854671Smjacob#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 19954671Smjacob#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 20044819Smjacob#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 20144819Smjacob 20245040Smjacob/* ISP2100 Bus Control/Status Register */ 20335388Smjacob 20435388Smjacob#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 20535388Smjacob#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 20635388Smjacob#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 20735388Smjacob#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 20835388Smjacob#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 209160080Smjacob#define BIU2100_NVRAM_OFFSET (1 << 14) 210160080Smjacob#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */ 21135388Smjacob#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 21235388Smjacob#define BIU2100_SOFT_RESET 0x01 21335388Smjacob/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 21435388Smjacob 21535388Smjacob 21635388Smjacob/* BUS CONTROL REGISTER */ 21735388Smjacob#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 21835388Smjacob#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 21935388Smjacob#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 22035388Smjacob#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 22135388Smjacob#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 22235388Smjacob#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 22335388Smjacob 224163899Smjacob#define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS) 225163899Smjacob 22635388Smjacob#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 22735388Smjacob#define BIU2100_ICR_ENA_FPM_INT 0x0020 22835388Smjacob#define BIU2100_ICR_ENA_FB_INT 0x0010 22935388Smjacob#define BIU2100_ICR_ENA_RISC_INT 0x0008 23035388Smjacob#define BIU2100_ICR_ENA_CDMA_INT 0x0004 23135388Smjacob#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 23235388Smjacob#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 23335388Smjacob#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 23435388Smjacob 235163899Smjacob#define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS) 23635388Smjacob 23735388Smjacob/* BUS STATUS REGISTER */ 23835388Smjacob#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 23935388Smjacob#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 24035388Smjacob#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 24135388Smjacob#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 24235388Smjacob#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 24335388Smjacob 24435388Smjacob#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 24535388Smjacob#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 24635388Smjacob#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 24735388Smjacob#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 24835388Smjacob#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 24935388Smjacob#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 25035388Smjacob#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 25135388Smjacob 25262170Smjacob#define INT_PENDING_MASK(isp) \ 253163899Smjacob (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \ 254163899Smjacob (BIU_ISR_RISC_INT)) 25562170Smjacob 25635388Smjacob/* BUS SEMAPHORE REGISTER */ 25735388Smjacob#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 25835388Smjacob#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 25935388Smjacob 26039235Sgibbs/* NVRAM SEMAPHORE REGISTER */ 26139235Sgibbs#define BIU_NVRAM_CLOCK 0x0001 26239235Sgibbs#define BIU_NVRAM_SELECT 0x0002 26339235Sgibbs#define BIU_NVRAM_DATAOUT 0x0004 26439235Sgibbs#define BIU_NVRAM_DATAIN 0x0008 265160080Smjacob#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */ 26639235Sgibbs#define ISP_NVRAM_READ 6 26735388Smjacob 26835388Smjacob/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 26935388Smjacob#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 27035388Smjacob#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 27135388Smjacob#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 27235388Smjacob#define DMA_DMA_DIRECTION 0x0001 /* 27335388Smjacob * Set DMA direction: 27435388Smjacob * 0 - DMA FIFO to host 27535388Smjacob * 1 - Host to DMA FIFO 27635388Smjacob */ 27735388Smjacob 27835388Smjacob/* COMMAND && DATA DMA CONTROL REGISTER */ 27935388Smjacob#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 28035388Smjacob#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 28135388Smjacob * Clear FIFO and DMA Channel, 28235388Smjacob * reset DMA registers 28335388Smjacob */ 28435388Smjacob#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 28535388Smjacob#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 28635388Smjacob#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 28735388Smjacob 28835388Smjacob/* 28935388Smjacob * Variants of same for 2100 29035388Smjacob */ 29135388Smjacob#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 29235388Smjacob#define DMA_CNTRL2100_RESET_INT 0x0002 29335388Smjacob 29435388Smjacob 29535388Smjacob 29635388Smjacob/* DMA STATUS REGISTER */ 29735388Smjacob#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 29835388Smjacob#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 29935388Smjacob#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 30035388Smjacob#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 30135388Smjacob#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 30235388Smjacob#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 30335388Smjacob 30435388Smjacob#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 30535388Smjacob#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 30635388Smjacob#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 30735388Smjacob#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 30835388Smjacob#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 30935388Smjacob#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 31035388Smjacob#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 31135388Smjacob#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 31235388Smjacob#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 31335388Smjacob#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 31435388Smjacob#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 31535388Smjacob 31635388Smjacob/* DMA Status Register, pipeline status bits */ 31735388Smjacob#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 31835388Smjacob#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 31935388Smjacob#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 32035388Smjacob * Pipeline stage 1 Loaded, 32135388Smjacob * stage 2 empty 32235388Smjacob */ 32335388Smjacob#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 32435388Smjacob#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 32535388Smjacob#define DMA_PCI_PIPE_STAGE1 0x0001 /* 32635388Smjacob * Pipeline stage 1 Loaded, 32735388Smjacob * stage 2 empty 32835388Smjacob */ 32935388Smjacob#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 33035388Smjacob 33135388Smjacob/* DMA Status Register, channel status bits */ 33235388Smjacob#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 33335388Smjacob#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 33435388Smjacob#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 33535388Smjacob#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 33635388Smjacob#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 33735388Smjacob#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 33835388Smjacob#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 33935388Smjacob 34035388Smjacob 34135388Smjacob/* DMA FIFO STATUS REGISTER */ 34235388Smjacob#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 34335388Smjacob#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 34435388Smjacob#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 34535388Smjacob#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 34635388Smjacob 34735388Smjacob/* 348163899Smjacob * 2400 Interface Offsets and Register Definitions 349163899Smjacob * 350163899Smjacob * The 2400 looks quite different in terms of registers from other QLogic cards. 351163899Smjacob * It is getting to be a genuine pain and challenge to keep the same model 352163899Smjacob * for all. 353163899Smjacob */ 354163899Smjacob#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) 355163899Smjacob#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) 356163899Smjacob#define BIU2400_CSR (BIU_BLOCK+0x08) 357163899Smjacob#define BIU2400_ICR (BIU_BLOCK+0x0C) 358163899Smjacob#define BIU2400_ISR (BIU_BLOCK+0x10) 359163899Smjacob 360163899Smjacob#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */ 361163899Smjacob#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */ 362163899Smjacob#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */ 363163899Smjacob#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */ 364163899Smjacob 365196008Smjacob#define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */ 366196008Smjacob#define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */ 367163899Smjacob 368196008Smjacob#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */ 369196008Smjacob#define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */ 370196008Smjacob 371163899Smjacob#define BIU2400_R2HSTSLO (BIU_BLOCK+0x44) 372163899Smjacob#define BIU2400_R2HSTSHI (BIU_BLOCK+0x46) 373163899Smjacob 374163899Smjacob#define BIU2400_HCCR (BIU_BLOCK+0x48) 375163899Smjacob#define BIU2400_GPIOD (BIU_BLOCK+0x4C) 376163899Smjacob#define BIU2400_GPIOE (BIU_BLOCK+0x50) 377163899Smjacob#define BIU2400_HSEMA (BIU_BLOCK+0x58) 378163899Smjacob 379163899Smjacob/* BIU2400_FLASH_ADDR definitions */ 380163899Smjacob#define BIU2400_FLASH_DFLAG (1 << 30) 381163899Smjacob 382163899Smjacob/* BIU2400_CSR definitions */ 383163899Smjacob#define BIU2400_NVERR (1 << 18) 384163899Smjacob#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */ 385163899Smjacob#define BIU2400_DMA_STOP (1 << 16) 386163899Smjacob#define BIU2400_FUNCTION (1 << 15) /* RO */ 387163899Smjacob#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */ 388163899Smjacob#define BIU2400_CSR_64BIT (1 << 2) /* RO */ 389163899Smjacob#define BIU2400_FLASH_ENABLE (1 << 1) 390163899Smjacob#define BIU2400_SOFT_RESET (1 << 0) 391163899Smjacob 392163899Smjacob/* BIU2400_ICR definitions */ 393163899Smjacob#define BIU2400_ICR_ENA_RISC_INT 0x8 394163899Smjacob#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT) 395163899Smjacob 396163899Smjacob/* BIU2400_ISR definitions */ 397163899Smjacob#define BIU2400_ISR_RISC_INT 0x8 398163899Smjacob 399163899Smjacob/* BIU2400_HCCR definitions */ 400163899Smjacob 401166929Smjacob#define HCCR_2400_CMD_NOP 0x00000000 402166929Smjacob#define HCCR_2400_CMD_RESET 0x10000000 403166929Smjacob#define HCCR_2400_CMD_CLEAR_RESET 0x20000000 404166929Smjacob#define HCCR_2400_CMD_PAUSE 0x30000000 405166929Smjacob#define HCCR_2400_CMD_RELEASE 0x40000000 406166929Smjacob#define HCCR_2400_CMD_SET_HOST_INT 0x50000000 407166929Smjacob#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 408166929Smjacob#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 409163899Smjacob 410163899Smjacob#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 411163899Smjacob#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 412163899Smjacob#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 413163899Smjacob 414163899Smjacob 415163899Smjacob/* 41635388Smjacob * Mailbox Block Register Offsets 41735388Smjacob */ 41835388Smjacob 41954671Smjacob#define INMAILBOX0 (MBOX_BLOCK+0x0) 42054671Smjacob#define INMAILBOX1 (MBOX_BLOCK+0x2) 42154671Smjacob#define INMAILBOX2 (MBOX_BLOCK+0x4) 42254671Smjacob#define INMAILBOX3 (MBOX_BLOCK+0x6) 42354671Smjacob#define INMAILBOX4 (MBOX_BLOCK+0x8) 42454671Smjacob#define INMAILBOX5 (MBOX_BLOCK+0xA) 42554671Smjacob#define INMAILBOX6 (MBOX_BLOCK+0xC) 42654671Smjacob#define INMAILBOX7 (MBOX_BLOCK+0xE) 42735388Smjacob 42854671Smjacob#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 42954671Smjacob#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 43054671Smjacob#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 43154671Smjacob#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 43254671Smjacob#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 43354671Smjacob#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 43454671Smjacob#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 43554671Smjacob#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 43635388Smjacob 437154704Smjacob/* 438154704Smjacob * Strictly speaking, it's 439154704Smjacob * SCSI && 2100 : 8 MBOX registers 440154704Smjacob * 2200: 24 MBOX registers 441163899Smjacob * 2300/2400: 32 MBOX registers 442154704Smjacob */ 44362170Smjacob#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 444237210Smjacob#define ISP_NMBOX(isp) ((IS_24XX(isp) || IS_23XX(isp))? 32 : (IS_2200(isp) ? 24 : 8)) 445237210Smjacob#define ISP_NMBOX_BMASK(isp) \ 446237210Smjacob ((IS_24XX(isp) || IS_23XX(isp))? 0xffffffff : (IS_2200(isp)? 0x00ffffff : 0xff)) 447237210Smjacob#define MAX_MAILBOX 32 448163899Smjacob/* if timeout == 0, then default timeout is picked */ 449163899Smjacob#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 450154704Smjacobtypedef struct { 451237210Smjacob uint16_t param[MAX_MAILBOX]; 452253330Smjacob uint32_t ibits; /* bits to add for register copyin */ 453253330Smjacob uint32_t obits; /* bits to add for register copyout */ 454253330Smjacob uint32_t ibitm; /* bits to mask for register copyin */ 455253330Smjacob uint32_t obitm; /* bits to mask for register copyout */ 456291500Smav uint32_t logval; /* Bitmask of status codes to log */ 457163899Smjacob uint32_t timeout; 458291500Smav uint32_t lineno; 459196008Smjacob const char *func; 460154704Smjacob} mbreg_t; 461196008Smjacob#define MBSINIT(mbxp, code, loglev, timo) \ 462196008Smjacob ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \ 463253330Smjacob (mbxp)->ibitm = ~0; \ 464253330Smjacob (mbxp)->obitm = ~0; \ 465196008Smjacob (mbxp)->param[0] = code; \ 466196008Smjacob (mbxp)->lineno = __LINE__; \ 467196008Smjacob (mbxp)->func = __func__; \ 468196008Smjacob (mbxp)->logval = loglev; \ 469196008Smjacob (mbxp)->timeout = timo 47062170Smjacob 471196008Smjacob 47235388Smjacob/* 47371078Smjacob * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 47471078Smjacob * NB: The RISC processor must be paused and the appropriate register 47571078Smjacob * bank selected via BIU2100_CSR bits. 47671078Smjacob */ 47771078Smjacob 47871078Smjacob#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 47971078Smjacob#define FPM_SOFT_RESET 0x0100 48071078Smjacob 48171078Smjacob#define FBM_CMD (BIU_BLOCK + 0xB8) 48271078Smjacob#define FBMCMD_FIFO_RESET_ALL 0xA000 48371078Smjacob 48471078Smjacob 48571078Smjacob/* 48635388Smjacob * SXP Block Register Offsets 48735388Smjacob */ 48854671Smjacob#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 48954671Smjacob#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 49054671Smjacob#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 49154671Smjacob#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 49254671Smjacob#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 49354671Smjacob#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 49454671Smjacob#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 49554671Smjacob#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 49654671Smjacob#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 49754671Smjacob#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 49854671Smjacob#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 49954671Smjacob#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 50054671Smjacob#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 50154671Smjacob#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 50254671Smjacob#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 50354671Smjacob#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 50454671Smjacob#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 50554671Smjacob#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 50654671Smjacob#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 50754671Smjacob#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 50854671Smjacob#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 50954671Smjacob#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 51054671Smjacob#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 51154671Smjacob#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 51254671Smjacob#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 51354671Smjacob#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 51454671Smjacob#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 51554671Smjacob#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 51654671Smjacob#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 51754671Smjacob#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 51854671Smjacob#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 51954671Smjacob#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 52054671Smjacob#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 52154671Smjacob#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 52254671Smjacob#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 52354671Smjacob#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 52454671Smjacob#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 52554671Smjacob#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 52654671Smjacob#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 52735388Smjacob 52854671Smjacob/* for 1080/1280/1240 only */ 52954671Smjacob#define SXP_BANK1_SELECT 0x100 53035388Smjacob 53154671Smjacob 53235388Smjacob/* SXP CONF1 REGISTER */ 53335388Smjacob#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 53435388Smjacob#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 53535388Smjacob#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 53635388Smjacob#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 53735388Smjacob#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 53835388Smjacob 53935388Smjacob/* SXP CONF2 REGISTER */ 54035388Smjacob#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 54135388Smjacob#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 54235388Smjacob#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 54335388Smjacob#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 54435388Smjacob#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 54535388Smjacob#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 54635388Smjacob 54735388Smjacob/* SXP INTERRUPT REGISTER */ 54835388Smjacob#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 54935388Smjacob#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 55035388Smjacob#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 55135388Smjacob#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 55235388Smjacob#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 55335388Smjacob#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 55435388Smjacob#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 55535388Smjacob#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 55635388Smjacob#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 55735388Smjacob#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 55835388Smjacob 55935388Smjacob 56035388Smjacob/* SXP GROSS ERROR REGISTER */ 56135388Smjacob#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 56235388Smjacob#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 56335388Smjacob#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 56435388Smjacob#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 56535388Smjacob#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 56635388Smjacob#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 56735388Smjacob#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 56835388Smjacob 56935388Smjacob/* SXP EXCEPTION REGISTER */ 57035388Smjacob#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 57135388Smjacob#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 57235388Smjacob#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 57335388Smjacob#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 57435388Smjacob#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 57535388Smjacob#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 57635388Smjacob#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 57735388Smjacob#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 57835388Smjacob#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 57935388Smjacob#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 58035388Smjacob 58135388Smjacob /* SXP OVERRIDE REGISTER */ 58235388Smjacob#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 58335388Smjacob#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 58435388Smjacob#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 58535388Smjacob#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 58635388Smjacob#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 58735388Smjacob#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 58835388Smjacob#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 58935388Smjacob#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 59035388Smjacob#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 59135388Smjacob#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 59235388Smjacob#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 59335388Smjacob#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 59435388Smjacob#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 59535388Smjacob 59635388Smjacob/* SXP COMMANDS */ 59735388Smjacob#define SXP_RESET_BUS_CMD 0x300b 59835388Smjacob 59935388Smjacob/* SXP SCSI ID REGISTER */ 60035388Smjacob#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 60135388Smjacob#define SXP_SELECT_ID 0x000F /* Select id */ 60235388Smjacob 60335388Smjacob/* SXP DEV CONFIG1 REGISTER */ 60435388Smjacob#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 60535388Smjacob#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 60635388Smjacob#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 60735388Smjacob 60835388Smjacob 60935388Smjacob/* SXP DEV CONFIG2 REGISTER */ 61035388Smjacob#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 61135388Smjacob#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 61235388Smjacob#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 61335388Smjacob#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 61435388Smjacob#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 61535388Smjacob 61635388Smjacob 61735388Smjacob/* SXP PHASE POINTER REGISTER */ 61835388Smjacob#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 61935388Smjacob#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 62035388Smjacob#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 62135388Smjacob#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 62235388Smjacob 62335388Smjacob 62435388Smjacob/* SXP FIFO STATUS REGISTER */ 62535388Smjacob#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 62635388Smjacob#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 62735388Smjacob#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 62835388Smjacob#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 62935388Smjacob 63035388Smjacob 63135388Smjacob/* SXP CONTROL PINS REGISTER */ 63235388Smjacob#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 63335388Smjacob#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 63435388Smjacob#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 63535388Smjacob#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 63635388Smjacob#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 63735388Smjacob#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 63835388Smjacob#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 63935388Smjacob#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 64035388Smjacob#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 64135388Smjacob#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 64235388Smjacob#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 64335388Smjacob#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 64435388Smjacob 64535388Smjacob/* 64635388Smjacob * Set the hold time for the SCSI Bus Reset to be 250 ms 64735388Smjacob */ 64835388Smjacob#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 64935388Smjacob 65035388Smjacob/* SXP DIFF PINS REGISTER */ 65135388Smjacob#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 65235388Smjacob#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 65335388Smjacob#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 65435388Smjacob#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 65535388Smjacob#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 65635388Smjacob#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 65735388Smjacob 65854671Smjacob/* Ultra2 only */ 65945040Smjacob#define SXP_PINS_LVD_MODE 0x1000 66045040Smjacob#define SXP_PINS_HVD_MODE 0x0800 66145040Smjacob#define SXP_PINS_SE_MODE 0x0400 662204397Smjacob#define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE) 66345040Smjacob 66445040Smjacob/* The above have to be put together with the DIFFM pin to make sense */ 66545040Smjacob#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 66645040Smjacob#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 66745040Smjacob#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 668204397Smjacob#define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE) 66945040Smjacob 67035388Smjacob/* 67135388Smjacob * RISC and Host Command and Control Block Register Offsets 67235388Smjacob */ 67335388Smjacob 67435388Smjacob#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 67535388Smjacob#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 67635388Smjacob#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 67735388Smjacob#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 67835388Smjacob#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 67935388Smjacob#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 68035388Smjacob#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 68135388Smjacob#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 68235388Smjacob#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 68335388Smjacob#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 68435388Smjacob#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 68535388Smjacob#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 68635388Smjacob#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 68735388Smjacob#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 68835388Smjacob#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 68935388Smjacob#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 69035388Smjacob#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 69135388Smjacob#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 69235388Smjacob#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 69335388Smjacob#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 69435388Smjacob#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 69535388Smjacob#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 69635388Smjacob#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 69735388Smjacob#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 69835388Smjacob#define RISC_MTR2100 RISC_BLOCK+0x30 69935388Smjacob 70035388Smjacob#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 70143420Smjacob#define DUAL_BANK 8 70235388Smjacob#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 70335388Smjacob#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 70435388Smjacob#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 70535388Smjacob#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 70635388Smjacob#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 70735388Smjacob#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 70835388Smjacob#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 70935388Smjacob 71035388Smjacob 71135388Smjacob/* PROCESSOR STATUS REGISTER */ 71235388Smjacob#define RISC_PSR_FORCE_TRUE 0x8000 71335388Smjacob#define RISC_PSR_LOOP_COUNT_DONE 0x4000 71435388Smjacob#define RISC_PSR_RISC_INT 0x2000 71535388Smjacob#define RISC_PSR_TIMER_ROLLOVER 0x1000 71635388Smjacob#define RISC_PSR_ALU_OVERFLOW 0x0800 71735388Smjacob#define RISC_PSR_ALU_MSB 0x0400 71835388Smjacob#define RISC_PSR_ALU_CARRY 0x0200 71935388Smjacob#define RISC_PSR_ALU_ZERO 0x0100 72039235Sgibbs 72139235Sgibbs#define RISC_PSR_PCI_ULTRA 0x0080 72239235Sgibbs#define RISC_PSR_SBUS_ULTRA 0x0020 72339235Sgibbs 72435388Smjacob#define RISC_PSR_DMA_INT 0x0010 72535388Smjacob#define RISC_PSR_SXP_INT 0x0008 72635388Smjacob#define RISC_PSR_HOST_INT 0x0004 72735388Smjacob#define RISC_PSR_INT_PENDING 0x0002 72835388Smjacob#define RISC_PSR_FORCE_FALSE 0x0001 72935388Smjacob 73035388Smjacob 73135388Smjacob/* Host Command and Control */ 73235388Smjacob#define HCCR_CMD_NOP 0x0000 /* NOP */ 73335388Smjacob#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 73435388Smjacob#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 73535388Smjacob#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 73635388Smjacob#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 73771078Smjacob#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 73871078Smjacob * Disable RISC pause on FPM 73971078Smjacob * parity error. 74071078Smjacob */ 74135388Smjacob#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 74235388Smjacob#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 74335388Smjacob#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 74435388Smjacob#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 74535388Smjacob#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 74635388Smjacob#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 74735388Smjacob#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 74835388Smjacob#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 74935388Smjacob 750163899Smjacob 75135388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 75235388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 75335388Smjacob#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 75435388Smjacob#define ISP2100_HCCR_PARITY 0x0001 75535388Smjacob 75635388Smjacob#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 75735388Smjacob#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 75835388Smjacob#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 75935388Smjacob 76035388Smjacob#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 76135388Smjacob#define HCCR_RESET 0x0040 /* R : reset in progress */ 76235388Smjacob#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 76335388Smjacob 76435388Smjacob#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 76539235Sgibbs 76639235Sgibbs/* 767163899Smjacob * Defines for Interrupts 768163899Smjacob */ 769163899Smjacob#define ISP_INTS_ENABLED(isp) \ 770163899Smjacob ((IS_SCSI(isp))? \ 771163899Smjacob (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ 772163899Smjacob (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ 773163899Smjacob (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) 774163899Smjacob 775163899Smjacob#define ISP_ENABLE_INTS(isp) \ 776163899Smjacob (IS_SCSI(isp) ? \ 777163899Smjacob ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ 778163899Smjacob (IS_24XX(isp) ? \ 779163899Smjacob (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ 780163899Smjacob (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) 781163899Smjacob 782163899Smjacob#define ISP_DISABLE_INTS(isp) \ 783163899Smjacob IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) 784163899Smjacob 785163899Smjacob/* 78646967Smjacob * NVRAM Definitions (PCI cards only) 78746967Smjacob */ 78846967Smjacob 78946967Smjacob#define ISPBSMX(c, byte, shift, mask) \ 79046967Smjacob (((c)[(byte)] >> (shift)) & (mask)) 79146967Smjacob/* 79246967Smjacob * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 79339235Sgibbs * 79439235Sgibbs * Some portion of the front of this is for general host adapter properties 79539235Sgibbs * This is followed by an array of per-target parameters, and is tailed off 79639235Sgibbs * with a checksum xor byte at offset 127. For non-byte entities data is 79739235Sgibbs * stored in Little Endian order. 79839235Sgibbs */ 79939235Sgibbs 80039235Sgibbs#define ISP_NVRAM_SIZE 128 80145040Smjacob 80239235Sgibbs#define ISP_NVRAM_VERSION(c) (c)[4] 80339235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 80439235Sgibbs#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 80539235Sgibbs#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 80639235Sgibbs#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 80739235Sgibbs#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 80839235Sgibbs#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 80939235Sgibbs#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 81039235Sgibbs#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 81139235Sgibbs#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 81239235Sgibbs#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 81339235Sgibbs#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 81439235Sgibbs#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 81539235Sgibbs#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 81639235Sgibbs#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 81739235Sgibbs#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 81839235Sgibbs#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 81939235Sgibbs#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 82039235Sgibbs#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 82139235Sgibbs#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 82239235Sgibbs#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 82339235Sgibbs#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 82439235Sgibbs#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 82539235Sgibbs#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 82639235Sgibbs#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 82739235Sgibbs#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 82839235Sgibbs#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 82939235Sgibbs#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 83039235Sgibbs#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 83139235Sgibbs#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 83239235Sgibbs 83339235Sgibbs#define ISP_NVRAM_TARGOFF 28 834163899Smjacob#define ISP_NVRAM_TARGSIZE 6 83539235Sgibbs#define _IxT(tgt, tidx) \ 836163899Smjacob (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) 83739235Sgibbs#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 83839235Sgibbs#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 83939235Sgibbs#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 84039235Sgibbs#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 84139235Sgibbs#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 84239235Sgibbs#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 84339235Sgibbs#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 84439235Sgibbs#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 84539235Sgibbs#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 84639235Sgibbs#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 84739235Sgibbs#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 84839235Sgibbs#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 84939235Sgibbs#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 85039235Sgibbs 85139235Sgibbs/* 85246967Smjacob * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 85346967Smjacob * 85446967Smjacob * Some portion of the front of this is for general host adapter properties 85546967Smjacob * This is followed by an array of per-target parameters, and is tailed off 85646967Smjacob * with a checksum xor byte at offset 256. For non-byte entities data is 85746967Smjacob * stored in Little Endian order. 85846967Smjacob */ 85946967Smjacob 86046967Smjacob#define ISP1080_NVRAM_SIZE 256 86146967Smjacob 86246967Smjacob#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 86346967Smjacob 86446967Smjacob/* Offset 5 */ 86546967Smjacob/* 866155704Smjacob uint8_t bios_configuration_mode :2; 867155704Smjacob uint8_t bios_disable :1; 868155704Smjacob uint8_t selectable_scsi_boot_enable :1; 869155704Smjacob uint8_t cd_rom_boot_enable :1; 870155704Smjacob uint8_t disable_loading_risc_code :1; 871155704Smjacob uint8_t enable_64bit_addressing :1; 872155704Smjacob uint8_t unused_7 :1; 87346967Smjacob */ 87446967Smjacob 87546967Smjacob/* Offsets 6, 7 */ 87646967Smjacob/* 877155704Smjacob uint8_t boot_lun_number :5; 878155704Smjacob uint8_t scsi_bus_number :1; 879155704Smjacob uint8_t unused_6 :1; 880155704Smjacob uint8_t unused_7 :1; 881155704Smjacob uint8_t boot_target_number :4; 882155704Smjacob uint8_t unused_12 :1; 883155704Smjacob uint8_t unused_13 :1; 884155704Smjacob uint8_t unused_14 :1; 885155704Smjacob uint8_t unused_15 :1; 88646967Smjacob */ 88746967Smjacob 88846967Smjacob#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 88946967Smjacob 89046967Smjacob#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 89146967Smjacob#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 89246967Smjacob 89346967Smjacob#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 89446967Smjacob#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 89546967Smjacob#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 89646967Smjacob 89746967Smjacob#define ISP1080_ISP_PARAMETER(c) \ 89846967Smjacob (((c)[18]) | ((c)[19] << 8)) 89946967Smjacob 90057148Smjacob#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 90157148Smjacob#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 90246967Smjacob 90346967Smjacob#define ISP1080_BUS1_OFF 112 90446967Smjacob 90546967Smjacob#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 90646967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 90746967Smjacob#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 90846967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 90946967Smjacob#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 91046967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 91146967Smjacob#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 91246967Smjacob (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 91346967Smjacob 91446967Smjacob#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 91546967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 91646967Smjacob#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 91746967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 91846967Smjacob#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 91946967Smjacob ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 92046967Smjacob#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 92146967Smjacob (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 92246967Smjacob ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 92346967Smjacob#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 92446967Smjacob (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 92546967Smjacob ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 92646967Smjacob 92746967Smjacob#define ISP1080_NVRAM_TARGOFF(b) \ 92846967Smjacob ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 92946967Smjacob#define ISP1080_NVRAM_TARGSIZE 6 93046967Smjacob#define _IxT8(tgt, tidx, b) \ 93146967Smjacob (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 93246967Smjacob 93346967Smjacob#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 93446967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 93546967Smjacob#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 93646967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 93746967Smjacob#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 93846967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 93946967Smjacob#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 94046967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 94146967Smjacob#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 94246967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 94346967Smjacob#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 94446967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 94546967Smjacob#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 94646967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 94746967Smjacob#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 94846967Smjacob ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 94946967Smjacob#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 95046967Smjacob ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 95146967Smjacob#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 95246967Smjacob ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 95346967Smjacob#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 95446967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 95546967Smjacob#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 95646967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 95746967Smjacob#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 95846967Smjacob ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 95946967Smjacob 96057148Smjacob#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 96157148Smjacob#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 96257148Smjacob#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 96357148Smjacob#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 96457148Smjacob#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 96557148Smjacob#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 96657148Smjacob#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 96757148Smjacob#define ISP12160_FAST_POST ISP1080_FAST_POST 96857148Smjacob#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 96957148Smjacob 97057148Smjacob#define ISP12160_NVRAM_INITIATOR_ID \ 97157148Smjacob ISP1080_NVRAM_INITIATOR_ID 97257148Smjacob#define ISP12160_NVRAM_BUS_RESET_DELAY \ 97357148Smjacob ISP1080_NVRAM_BUS_RESET_DELAY 97457148Smjacob#define ISP12160_NVRAM_BUS_RETRY_COUNT \ 97557148Smjacob ISP1080_NVRAM_BUS_RETRY_COUNT 97657148Smjacob#define ISP12160_NVRAM_BUS_RETRY_DELAY \ 97757148Smjacob ISP1080_NVRAM_BUS_RETRY_DELAY 97857148Smjacob#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 97957148Smjacob ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 98057148Smjacob#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 98157148Smjacob ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 98257148Smjacob#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 98357148Smjacob ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 98457148Smjacob#define ISP12160_NVRAM_SELECTION_TIMEOUT \ 98557148Smjacob ISP1080_NVRAM_SELECTION_TIMEOUT 98657148Smjacob#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 98757148Smjacob ISP1080_NVRAM_MAX_QUEUE_DEPTH 98857148Smjacob 98957148Smjacob 99057148Smjacob#define ISP12160_BUS0_OFF 24 99157148Smjacob#define ISP12160_BUS1_OFF 136 99257148Smjacob 99357148Smjacob#define ISP12160_NVRAM_TARGOFF(b) \ 99457148Smjacob (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 99557148Smjacob 99657148Smjacob#define ISP12160_NVRAM_TARGSIZE 6 99757148Smjacob#define _IxT16(tgt, tidx, b) \ 99857148Smjacob (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 99957148Smjacob 100057148Smjacob#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 100157148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 100257148Smjacob#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 100357148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 100457148Smjacob#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 100557148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 100657148Smjacob#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 100757148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 100857148Smjacob#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 100957148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 101057148Smjacob#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 101157148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 101257148Smjacob#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 101357148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 101457148Smjacob#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 101557148Smjacob ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 101657148Smjacob 101757148Smjacob#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 101857148Smjacob ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 101957148Smjacob#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 102057148Smjacob ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 102157148Smjacob 102257148Smjacob#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 102357148Smjacob ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 102457148Smjacob#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 102557148Smjacob ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 102657148Smjacob 102757148Smjacob#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 102857148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 102957148Smjacob#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 103057148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 103157148Smjacob#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 103257148Smjacob ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 103357148Smjacob 103446967Smjacob/* 1035163899Smjacob * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. 103639235Sgibbs * 103739235Sgibbs * Some portion of the front of this is for general RISC engine parameters, 103839235Sgibbs * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 103939235Sgibbs * 104039235Sgibbs * This is followed by some general host adapter parameters, and ends with 104139235Sgibbs * a checksum xor byte at offset 255. For non-byte entities data is stored 104239235Sgibbs * in Little Endian order. 104339235Sgibbs */ 104439235Sgibbs#define ISP2100_NVRAM_SIZE 256 104539235Sgibbs/* ISP_NVRAM_VERSION is in same overall place */ 104639235Sgibbs#define ISP2100_NVRAM_RISCVER(c) (c)[6] 1047160080Smjacob#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) 104839235Sgibbs#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 104939235Sgibbs#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 105039235Sgibbs#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 105139235Sgibbs#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 105239235Sgibbs#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 105339235Sgibbs 105460218Smjacob#define ISP2100_NVRAM_PORT_NAME(c) (\ 1055155704Smjacob (((uint64_t)(c)[18]) << 56) | \ 1056155704Smjacob (((uint64_t)(c)[19]) << 48) | \ 1057155704Smjacob (((uint64_t)(c)[20]) << 40) | \ 1058155704Smjacob (((uint64_t)(c)[21]) << 32) | \ 1059155704Smjacob (((uint64_t)(c)[22]) << 24) | \ 1060155704Smjacob (((uint64_t)(c)[23]) << 16) | \ 1061155704Smjacob (((uint64_t)(c)[24]) << 8) | \ 1062155704Smjacob (((uint64_t)(c)[25]) << 0)) 106360218Smjacob 1064160080Smjacob#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 1065160080Smjacob#define ISP2100_NVRAM_TOV(c) ((c)[29]) 106639235Sgibbs 1067160080Smjacob#define ISP2100_NVRAM_NODE_NAME(c) (\ 1068155704Smjacob (((uint64_t)(c)[30]) << 56) | \ 1069155704Smjacob (((uint64_t)(c)[31]) << 48) | \ 1070155704Smjacob (((uint64_t)(c)[32]) << 40) | \ 1071155704Smjacob (((uint64_t)(c)[33]) << 32) | \ 1072155704Smjacob (((uint64_t)(c)[34]) << 24) | \ 1073155704Smjacob (((uint64_t)(c)[35]) << 16) | \ 1074155704Smjacob (((uint64_t)(c)[36]) << 8) | \ 1075155704Smjacob (((uint64_t)(c)[37]) << 0)) 107660218Smjacob 1077160080Smjacob#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 1078160080Smjacob 1079160080Smjacob#define ISP2100_RACC_TIMER(c) (c)[40] 1080160080Smjacob#define ISP2100_IDELAY_TIMER(c) (c)[41] 1081160080Smjacob 1082160080Smjacob#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 1083160080Smjacob 1084160080Smjacob#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 1085160080Smjacob 1086160080Smjacob#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) 108739235Sgibbs#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 108839235Sgibbs#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 108939235Sgibbs#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 109039235Sgibbs#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 109139235Sgibbs#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 109239235Sgibbs#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 109339235Sgibbs 109445040Smjacob#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1095155704Smjacob (((uint64_t)(c)[72]) << 56) | \ 1096155704Smjacob (((uint64_t)(c)[73]) << 48) | \ 1097155704Smjacob (((uint64_t)(c)[74]) << 40) | \ 1098155704Smjacob (((uint64_t)(c)[75]) << 32) | \ 1099155704Smjacob (((uint64_t)(c)[76]) << 24) | \ 1100155704Smjacob (((uint64_t)(c)[77]) << 16) | \ 1101155704Smjacob (((uint64_t)(c)[78]) << 8) | \ 1102155704Smjacob (((uint64_t)(c)[79]) << 0)) 110343792Smjacob 110439235Sgibbs#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1105160080Smjacob#define ISP2100_RESET_DELAY(c) (c)[81] 110639235Sgibbs 1107160080Smjacob#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) 110890754Smjacob 110990754Smjacob/* 1110163899Smjacob * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 1111163899Smjacob */ 1112163899Smjacob#define ISP2400_NVRAM_PORT0_ADDR 0x80 1113163899Smjacob#define ISP2400_NVRAM_PORT1_ADDR 0x180 1114163899Smjacob#define ISP2400_NVRAM_SIZE 512 1115163899Smjacob 1116163899Smjacob#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 1117163899Smjacob#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 1118163899Smjacob#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1119163899Smjacob#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) 1120163899Smjacob#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 1121163899Smjacob 1122163899Smjacob#define ISP2400_NVRAM_PORT_NAME(c) (\ 1123163899Smjacob (((uint64_t)(c)[20]) << 56) | \ 1124163899Smjacob (((uint64_t)(c)[21]) << 48) | \ 1125163899Smjacob (((uint64_t)(c)[22]) << 40) | \ 1126163899Smjacob (((uint64_t)(c)[23]) << 32) | \ 1127163899Smjacob (((uint64_t)(c)[24]) << 24) | \ 1128163899Smjacob (((uint64_t)(c)[25]) << 16) | \ 1129163899Smjacob (((uint64_t)(c)[26]) << 8) | \ 1130163899Smjacob (((uint64_t)(c)[27]) << 0)) 1131163899Smjacob 1132163899Smjacob#define ISP2400_NVRAM_NODE_NAME(c) (\ 1133163899Smjacob (((uint64_t)(c)[28]) << 56) | \ 1134163899Smjacob (((uint64_t)(c)[29]) << 48) | \ 1135163899Smjacob (((uint64_t)(c)[30]) << 40) | \ 1136163899Smjacob (((uint64_t)(c)[31]) << 32) | \ 1137163899Smjacob (((uint64_t)(c)[32]) << 24) | \ 1138163899Smjacob (((uint64_t)(c)[33]) << 16) | \ 1139163899Smjacob (((uint64_t)(c)[34]) << 8) | \ 1140163899Smjacob (((uint64_t)(c)[35]) << 0)) 1141163899Smjacob 1142163899Smjacob#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 1143163899Smjacob#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 1144163899Smjacob#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 1145163899Smjacob#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 1146163899Smjacob 1147163899Smjacob#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 1148163899Smjacob ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 1149163899Smjacob#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 1150163899Smjacob ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 1151163899Smjacob#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 1152163899Smjacob ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 1153163899Smjacob 1154163899Smjacob/* 115590754Smjacob * Firmware Crash Dump 115690754Smjacob * 115790754Smjacob * QLogic needs specific information format when they look at firmware crashes. 115890754Smjacob * 115990754Smjacob * This is incredibly kernel memory consumptive (to say the least), so this 116090754Smjacob * code is only compiled in when needed. 116190754Smjacob */ 116290754Smjacob 116390754Smjacob#define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1164155704Smjacob (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1165155704Smjacob (352 * sizeof (uint16_t)) + /* RISC registers */ \ 1166155704Smjacob (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 116790754Smjacob#define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1168155704Smjacob (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1169155704Smjacob (464 * sizeof (uint16_t)) + /* RISC registers */ \ 1170155704Smjacob (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1171155704Smjacob (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1172155704Smjacob (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 117390754Smjacob/* the larger of the two */ 117490754Smjacob#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 117535388Smjacob#endif /* _ISPREG_H */ 1176