isp_pci.c revision 239218
1/*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26/* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/isp/isp_pci.c 239218 2012-08-12 20:45:47Z mjacob $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/linker.h> 38#include <sys/firmware.h> 39#include <sys/bus.h> 40#include <sys/stdint.h> 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46#include <sys/malloc.h> 47#include <sys/uio.h> 48 49#ifdef __sparc64__ 50#include <dev/ofw/openfirm.h> 51#include <machine/ofw_machdep.h> 52#endif 53 54#include <dev/isp/isp_freebsd.h> 55 56static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 63static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 64static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 65static int isp_pci_mbxdma(ispsoftc_t *); 66static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69static void isp_pci_reset0(ispsoftc_t *); 70static void isp_pci_reset1(ispsoftc_t *); 71static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85}; 86 87static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99}; 100 101static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113}; 114 115static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125}; 126 127static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137}; 138 139static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149}; 150 151static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161}; 162 163static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173}; 174 175#ifndef PCIM_CMD_INVEN 176#define PCIM_CMD_INVEN 0x10 177#endif 178#ifndef PCIM_CMD_BUSMASTEREN 179#define PCIM_CMD_BUSMASTEREN 0x0004 180#endif 181#ifndef PCIM_CMD_PERRESPEN 182#define PCIM_CMD_PERRESPEN 0x0040 183#endif 184#ifndef PCIM_CMD_SEREN 185#define PCIM_CMD_SEREN 0x0100 186#endif 187#ifndef PCIM_CMD_INTX_DISABLE 188#define PCIM_CMD_INTX_DISABLE 0x0400 189#endif 190 191#ifndef PCIR_COMMAND 192#define PCIR_COMMAND 0x04 193#endif 194 195#ifndef PCIR_CACHELNSZ 196#define PCIR_CACHELNSZ 0x0c 197#endif 198 199#ifndef PCIR_LATTIMER 200#define PCIR_LATTIMER 0x0d 201#endif 202 203#ifndef PCIR_ROMADDR 204#define PCIR_ROMADDR 0x30 205#endif 206 207#ifndef PCI_VENDOR_QLOGIC 208#define PCI_VENDOR_QLOGIC 0x1077 209#endif 210 211#ifndef PCI_PRODUCT_QLOGIC_ISP1020 212#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213#endif 214 215#ifndef PCI_PRODUCT_QLOGIC_ISP1080 216#define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217#endif 218 219#ifndef PCI_PRODUCT_QLOGIC_ISP10160 220#define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221#endif 222 223#ifndef PCI_PRODUCT_QLOGIC_ISP12160 224#define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225#endif 226 227#ifndef PCI_PRODUCT_QLOGIC_ISP1240 228#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229#endif 230 231#ifndef PCI_PRODUCT_QLOGIC_ISP1280 232#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233#endif 234 235#ifndef PCI_PRODUCT_QLOGIC_ISP2100 236#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237#endif 238 239#ifndef PCI_PRODUCT_QLOGIC_ISP2200 240#define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241#endif 242 243#ifndef PCI_PRODUCT_QLOGIC_ISP2300 244#define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245#endif 246 247#ifndef PCI_PRODUCT_QLOGIC_ISP2312 248#define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249#endif 250 251#ifndef PCI_PRODUCT_QLOGIC_ISP2322 252#define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253#endif 254 255#ifndef PCI_PRODUCT_QLOGIC_ISP2422 256#define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257#endif 258 259#ifndef PCI_PRODUCT_QLOGIC_ISP2432 260#define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261#endif 262 263#ifndef PCI_PRODUCT_QLOGIC_ISP2532 264#define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265#endif 266 267#ifndef PCI_PRODUCT_QLOGIC_ISP6312 268#define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269#endif 270 271#ifndef PCI_PRODUCT_QLOGIC_ISP6322 272#define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273#endif 274 275#ifndef PCI_PRODUCT_QLOGIC_ISP5432 276#define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277#endif 278 279#define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282#define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285#define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288#define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291#define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294#define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297#define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300#define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303#define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306#define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309#define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312#define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315#define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318#define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321#define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324#define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327#define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330/* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333#define AMI_RAID_SUBVENDOR_ID 0x101e 334 335#define IO_MAP_REG 0x10 336#define MEM_MAP_REG 0x14 337 338#define PCI_DFLT_LTNCY 0x40 339#define PCI_DFLT_LNSZ 0x10 340 341static int isp_pci_probe (device_t); 342static int isp_pci_attach (device_t); 343static int isp_pci_detach (device_t); 344 345 346#define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359}; 360 361 362static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368}; 369 370static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372}; 373static devclass_t isp_devclass; 374DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375MODULE_DEPEND(isp, cam, 1, 1, 1); 376MODULE_DEPEND(isp, firmware, 1, 1, 1); 377static int isp_nvports = 0; 378 379static int 380isp_pci_probe(device_t dev) 381{ 382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 383 case PCI_QLOGIC_ISP1020: 384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP1080: 387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 388 break; 389 case PCI_QLOGIC_ISP1240: 390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 391 break; 392 case PCI_QLOGIC_ISP1280: 393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 394 break; 395 case PCI_QLOGIC_ISP10160: 396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 397 break; 398 case PCI_QLOGIC_ISP12160: 399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 400 return (ENXIO); 401 } 402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2100: 405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2200: 408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP2300: 411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP2312: 414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 415 break; 416 case PCI_QLOGIC_ISP2322: 417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 418 break; 419 case PCI_QLOGIC_ISP2422: 420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 421 break; 422 case PCI_QLOGIC_ISP2432: 423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 424 break; 425 case PCI_QLOGIC_ISP2532: 426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 427 break; 428 case PCI_QLOGIC_ISP5432: 429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP6312: 432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP6322: 435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 436 break; 437 default: 438 return (ENXIO); 439 } 440 if (isp_announced == 0 && bootverbose) { 441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 442 "Core Version %d.%d\n", 443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 445 isp_announced++; 446 } 447 /* 448 * XXXX: Here is where we might load the f/w module 449 * XXXX: (or increase a reference count to it). 450 */ 451 return (BUS_PROBE_DEFAULT); 452} 453 454static void 455isp_get_generic_options(device_t dev, ispsoftc_t *isp) 456{ 457 int tval; 458 459 /* 460 * Figure out if we're supposed to skip this one. 461 */ 462 tval = 0; 463 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 464 device_printf(dev, "disabled at user request\n"); 465 isp->isp_osinfo.disabled = 1; 466 return; 467 } 468 469 tval = 0; 470 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 471 isp->isp_confopts |= ISP_CFG_NORELOAD; 472 } 473 tval = 0; 474 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 475 isp->isp_confopts |= ISP_CFG_NONVRAM; 476 } 477 tval = 0; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 479 if (tval) { 480 isp->isp_dblev = tval; 481 } else { 482 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 483 } 484 if (bootverbose) { 485 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 486 } 487 tval = -1; 488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 489 if (tval > 0 && tval < 127) { 490 isp_nvports = tval; 491 } 492 tval = 1; 493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 494 isp_autoconfig = tval; 495 tval = 7; 496 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 497 isp_quickboot_time = tval; 498} 499 500static void 501isp_get_pci_options(device_t dev, int *m1, int *m2) 502{ 503 int tval; 504 /* 505 * Which we should try first - memory mapping or i/o mapping? 506 * 507 * We used to try memory first followed by i/o on alpha, otherwise 508 * the reverse, but we should just try memory first all the time now. 509 */ 510 *m1 = PCIM_CMD_MEMEN; 511 *m2 = PCIM_CMD_PORTEN; 512 513 tval = 0; 514 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 515 *m1 = PCIM_CMD_PORTEN; 516 *m2 = PCIM_CMD_MEMEN; 517 } 518 tval = 0; 519 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 520 *m1 = PCIM_CMD_MEMEN; 521 *m2 = PCIM_CMD_PORTEN; 522 } 523} 524 525static void 526isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 527{ 528 const char *sptr; 529 int tval = 0; 530 531 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 532 if (IS_FC(isp)) { 533 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 534 } else { 535#ifdef __sparc64__ 536 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 537#else 538 ISP_SPI_PC(isp, chan)->iid = 7; 539#endif 540 } 541 } else { 542 if (IS_FC(isp)) { 543 ISP_FC_PC(isp, chan)->default_id = tval - chan; 544 } else { 545 ISP_SPI_PC(isp, chan)->iid = tval; 546 } 547 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 548 } 549 550 tval = -1; 551 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 552 switch (tval) { 553 case ISP_ROLE_NONE: 554 case ISP_ROLE_INITIATOR: 555 case ISP_ROLE_TARGET: 556 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 557 device_printf(dev, "setting role to 0x%x\n", tval); 558 break; 559 default: 560 tval = -1; 561 break; 562 } 563 } 564 if (tval == -1) { 565 tval = ISP_DEFAULT_ROLES; 566 } 567 568 if (IS_SCSI(isp)) { 569 ISP_SPI_PC(isp, chan)->def_role = tval; 570 return; 571 } 572 ISP_FC_PC(isp, chan)->def_role = tval; 573 574 tval = 0; 575 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 576 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 577 } 578 sptr = 0; 579 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 580 if (strcmp(sptr, "lport") == 0) { 581 isp->isp_confopts |= ISP_CFG_LPORT; 582 } else if (strcmp(sptr, "nport") == 0) { 583 isp->isp_confopts |= ISP_CFG_NPORT; 584 } else if (strcmp(sptr, "lport-only") == 0) { 585 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 586 } else if (strcmp(sptr, "nport-only") == 0) { 587 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 588 } 589 } 590 591 tval = 0; 592 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "nofctape", &tval); 593 if (tval) { 594 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 595 } 596 597 tval = 0; 598 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "fctape", &tval); 599 if (tval) { 600 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 601 isp->isp_confopts |= ISP_CFG_FCTAPE; 602 } 603 604 605 /* 606 * Because the resource_*_value functions can neither return 607 * 64 bit integer values, nor can they be directly coerced 608 * to interpret the right hand side of the assignment as 609 * you want them to interpret it, we have to force WWN 610 * hint replacement to specify WWN strings with a leading 611 * 'w' (e..g w50000000aaaa0001). Sigh. 612 */ 613 sptr = 0; 614 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 615 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 616 char *eptr = 0; 617 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 618 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 619 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 620 ISP_FC_PC(isp, chan)->def_wwpn = 0; 621 } 622 } 623 624 sptr = 0; 625 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 626 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 627 char *eptr = 0; 628 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 629 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 630 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 631 ISP_FC_PC(isp, chan)->def_wwnn = 0; 632 } 633 } 634 635 tval = 0; 636 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 637 if (tval >= 0 && tval < 256) { 638 ISP_FC_PC(isp, chan)->hysteresis = tval; 639 } else { 640 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 641 } 642 643 tval = -1; 644 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 645 if (tval >= 0 && tval < 0xffff) { 646 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 647 } else { 648 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 649 } 650 651 tval = -1; 652 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 653 if (tval >= 0 && tval < 0xffff) { 654 ISP_FC_PC(isp, chan)->gone_device_time = tval; 655 } else { 656 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 657 } 658} 659 660static int 661isp_pci_attach(device_t dev) 662{ 663 int i, m1, m2, locksetup = 0; 664 uint32_t data, cmd, linesz, did; 665 struct isp_pcisoftc *pcs; 666 ispsoftc_t *isp; 667 size_t psize, xsize; 668 char fwname[32]; 669 670 pcs = device_get_softc(dev); 671 if (pcs == NULL) { 672 device_printf(dev, "cannot get softc\n"); 673 return (ENOMEM); 674 } 675 memset(pcs, 0, sizeof (*pcs)); 676 677 pcs->pci_dev = dev; 678 isp = &pcs->pci_isp; 679 isp->isp_dev = dev; 680 isp->isp_nchan = 1; 681 if (sizeof (bus_addr_t) > 4) 682 isp->isp_osinfo.sixtyfourbit = 1; 683 684 /* 685 * Get Generic Options 686 */ 687 isp_nvports = 0; 688 isp_get_generic_options(dev, isp); 689 690 /* 691 * Check to see if options have us disabled 692 */ 693 if (isp->isp_osinfo.disabled) { 694 /* 695 * But return zero to preserve unit numbering 696 */ 697 return (0); 698 } 699 700 /* 701 * Get PCI options- which in this case are just mapping preferences. 702 */ 703 isp_get_pci_options(dev, &m1, &m2); 704 705 linesz = PCI_DFLT_LNSZ; 706 pcs->irq = pcs->regs = NULL; 707 pcs->rgd = pcs->rtp = pcs->iqd = 0; 708 709 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 710 if (cmd & m1) { 711 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 712 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 713 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 714 } 715 if (pcs->regs == NULL && (cmd & m2)) { 716 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 717 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 718 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 719 } 720 if (pcs->regs == NULL) { 721 device_printf(dev, "unable to map any ports\n"); 722 goto bad; 723 } 724 if (bootverbose) { 725 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 726 } 727 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 728 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 729 730 pcs->pci_dev = dev; 731 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 732 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 733 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 734 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 735 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 736 737 switch (pci_get_devid(dev)) { 738 case PCI_QLOGIC_ISP1020: 739 did = 0x1040; 740 isp->isp_mdvec = &mdvec; 741 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 742 break; 743 case PCI_QLOGIC_ISP1080: 744 did = 0x1080; 745 isp->isp_mdvec = &mdvec_1080; 746 isp->isp_type = ISP_HA_SCSI_1080; 747 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 748 break; 749 case PCI_QLOGIC_ISP1240: 750 did = 0x1080; 751 isp->isp_mdvec = &mdvec_1080; 752 isp->isp_type = ISP_HA_SCSI_1240; 753 isp->isp_nchan = 2; 754 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 755 break; 756 case PCI_QLOGIC_ISP1280: 757 did = 0x1080; 758 isp->isp_mdvec = &mdvec_1080; 759 isp->isp_type = ISP_HA_SCSI_1280; 760 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 761 break; 762 case PCI_QLOGIC_ISP10160: 763 did = 0x12160; 764 isp->isp_mdvec = &mdvec_12160; 765 isp->isp_type = ISP_HA_SCSI_10160; 766 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 767 break; 768 case PCI_QLOGIC_ISP12160: 769 did = 0x12160; 770 isp->isp_nchan = 2; 771 isp->isp_mdvec = &mdvec_12160; 772 isp->isp_type = ISP_HA_SCSI_12160; 773 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 774 break; 775 case PCI_QLOGIC_ISP2100: 776 did = 0x2100; 777 isp->isp_mdvec = &mdvec_2100; 778 isp->isp_type = ISP_HA_FC_2100; 779 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 780 if (pci_get_revid(dev) < 3) { 781 /* 782 * XXX: Need to get the actual revision 783 * XXX: number of the 2100 FB. At any rate, 784 * XXX: lower cache line size for early revision 785 * XXX; boards. 786 */ 787 linesz = 1; 788 } 789 break; 790 case PCI_QLOGIC_ISP2200: 791 did = 0x2200; 792 isp->isp_mdvec = &mdvec_2200; 793 isp->isp_type = ISP_HA_FC_2200; 794 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 795 break; 796 case PCI_QLOGIC_ISP2300: 797 did = 0x2300; 798 isp->isp_mdvec = &mdvec_2300; 799 isp->isp_type = ISP_HA_FC_2300; 800 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 801 break; 802 case PCI_QLOGIC_ISP2312: 803 case PCI_QLOGIC_ISP6312: 804 did = 0x2300; 805 isp->isp_mdvec = &mdvec_2300; 806 isp->isp_type = ISP_HA_FC_2312; 807 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 808 break; 809 case PCI_QLOGIC_ISP2322: 810 case PCI_QLOGIC_ISP6322: 811 did = 0x2322; 812 isp->isp_mdvec = &mdvec_2300; 813 isp->isp_type = ISP_HA_FC_2322; 814 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 815 break; 816 case PCI_QLOGIC_ISP2422: 817 case PCI_QLOGIC_ISP2432: 818 did = 0x2400; 819 isp->isp_nchan += isp_nvports; 820 isp->isp_mdvec = &mdvec_2400; 821 isp->isp_type = ISP_HA_FC_2400; 822 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 823 break; 824 case PCI_QLOGIC_ISP2532: 825 did = 0x2500; 826 isp->isp_nchan += isp_nvports; 827 isp->isp_mdvec = &mdvec_2500; 828 isp->isp_type = ISP_HA_FC_2500; 829 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 830 break; 831 case PCI_QLOGIC_ISP5432: 832 did = 0x2500; 833 isp->isp_mdvec = &mdvec_2500; 834 isp->isp_type = ISP_HA_FC_2500; 835 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 836 break; 837 default: 838 device_printf(dev, "unknown device type\n"); 839 goto bad; 840 break; 841 } 842 isp->isp_revision = pci_get_revid(dev); 843 844 if (IS_FC(isp)) { 845 psize = sizeof (fcparam); 846 xsize = sizeof (struct isp_fc); 847 } else { 848 psize = sizeof (sdparam); 849 xsize = sizeof (struct isp_spi); 850 } 851 psize *= isp->isp_nchan; 852 xsize *= isp->isp_nchan; 853 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 854 if (isp->isp_param == NULL) { 855 device_printf(dev, "cannot allocate parameter data\n"); 856 goto bad; 857 } 858 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 859 if (isp->isp_osinfo.pc.ptr == NULL) { 860 device_printf(dev, "cannot allocate parameter data\n"); 861 goto bad; 862 } 863 864 /* 865 * Now that we know who we are (roughly) get/set specific options 866 */ 867 for (i = 0; i < isp->isp_nchan; i++) { 868 isp_get_specific_options(dev, i, isp); 869 } 870 871 /* 872 * The 'it' suffix really only matters for SCSI cards in target mode. 873 */ 874 isp->isp_osinfo.fw = NULL; 875 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 876 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 877 isp->isp_osinfo.fw = firmware_get(fwname); 878 } else if (IS_24XX(isp)) { 879 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 880 isp->isp_osinfo.fw = firmware_get(fwname); 881 } 882 if (isp->isp_osinfo.fw == NULL) { 883 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 884 isp->isp_osinfo.fw = firmware_get(fwname); 885 } 886 if (isp->isp_osinfo.fw != NULL) { 887 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 888 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 889 } 890 891 /* 892 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 893 */ 894 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 895 if (IS_2300(isp)) { /* per QLogic errata */ 896 cmd &= ~PCIM_CMD_INVEN; 897 } 898 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 899 cmd &= ~PCIM_CMD_INTX_DISABLE; 900 } 901 if (IS_24XX(isp)) { 902 cmd &= ~PCIM_CMD_INTX_DISABLE; 903 } 904 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 905 906 /* 907 * Make sure the Cache Line Size register is set sensibly. 908 */ 909 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 910 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 911 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 912 data = linesz; 913 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 914 } 915 916 /* 917 * Make sure the Latency Timer is sane. 918 */ 919 data = pci_read_config(dev, PCIR_LATTIMER, 1); 920 if (data < PCI_DFLT_LTNCY) { 921 data = PCI_DFLT_LTNCY; 922 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 923 pci_write_config(dev, PCIR_LATTIMER, data, 1); 924 } 925 926 /* 927 * Make sure we've disabled the ROM. 928 */ 929 data = pci_read_config(dev, PCIR_ROMADDR, 4); 930 data &= ~1; 931 pci_write_config(dev, PCIR_ROMADDR, data, 4); 932 933 /* 934 * Do MSI 935 * 936 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 937 */ 938 if (IS_24XX(isp) || IS_2322(isp)) { 939 pcs->msicount = pci_msi_count(dev); 940 if (pcs->msicount > 1) { 941 pcs->msicount = 1; 942 } 943 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 944 pcs->iqd = 1; 945 } else { 946 pcs->iqd = 0; 947 } 948 } 949 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 950 if (pcs->irq == NULL) { 951 device_printf(dev, "could not allocate interrupt\n"); 952 goto bad; 953 } 954 955 /* Make sure the lock is set up. */ 956 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 957 locksetup++; 958 959 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 960 device_printf(dev, "could not setup interrupt\n"); 961 goto bad; 962 } 963 964 /* 965 * Last minute checks... 966 */ 967 if (IS_23XX(isp) || IS_24XX(isp)) { 968 isp->isp_port = pci_get_function(dev); 969 } 970 971 /* 972 * Make sure we're in reset state. 973 */ 974 ISP_LOCK(isp); 975 isp_reset(isp, 1); 976 if (isp->isp_state != ISP_RESETSTATE) { 977 ISP_UNLOCK(isp); 978 goto bad; 979 } 980 isp_init(isp); 981 if (isp->isp_state == ISP_INITSTATE) { 982 isp->isp_state = ISP_RUNSTATE; 983 } 984 ISP_UNLOCK(isp); 985 if (isp_attach(isp)) { 986 ISP_LOCK(isp); 987 isp_uninit(isp); 988 ISP_UNLOCK(isp); 989 goto bad; 990 } 991 return (0); 992 993bad: 994 if (pcs->ih) { 995 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 996 } 997 if (locksetup) { 998 mtx_destroy(&isp->isp_osinfo.lock); 999 } 1000 if (pcs->irq) { 1001 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1002 } 1003 if (pcs->msicount) { 1004 pci_release_msi(dev); 1005 } 1006 if (pcs->regs) { 1007 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1008 } 1009 if (pcs->pci_isp.isp_param) { 1010 free(pcs->pci_isp.isp_param, M_DEVBUF); 1011 pcs->pci_isp.isp_param = NULL; 1012 } 1013 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1014 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1015 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1016 } 1017 return (ENXIO); 1018} 1019 1020static int 1021isp_pci_detach(device_t dev) 1022{ 1023 struct isp_pcisoftc *pcs; 1024 ispsoftc_t *isp; 1025 int status; 1026 1027 pcs = device_get_softc(dev); 1028 if (pcs == NULL) { 1029 return (ENXIO); 1030 } 1031 isp = (ispsoftc_t *) pcs; 1032 status = isp_detach(isp); 1033 if (status) 1034 return (status); 1035 ISP_LOCK(isp); 1036 isp_uninit(isp); 1037 if (pcs->ih) { 1038 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1039 } 1040 ISP_UNLOCK(isp); 1041 mtx_destroy(&isp->isp_osinfo.lock); 1042 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1043 if (pcs->msicount) { 1044 pci_release_msi(dev); 1045 } 1046 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1047 /* 1048 * XXX: THERE IS A LOT OF LEAKAGE HERE 1049 */ 1050 if (pcs->pci_isp.isp_param) { 1051 free(pcs->pci_isp.isp_param, M_DEVBUF); 1052 pcs->pci_isp.isp_param = NULL; 1053 } 1054 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1055 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1056 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1057 } 1058 return (0); 1059} 1060 1061#define IspVirt2Off(a, x) \ 1062 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1063 _BLK_REG_SHFT] + ((x) & 0xfff)) 1064 1065#define BXR2(isp, off) \ 1066 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1067#define BXW2(isp, off, v) \ 1068 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1069#define BXR4(isp, off) \ 1070 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1071#define BXW4(isp, off, v) \ 1072 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1073 1074 1075static ISP_INLINE int 1076isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1077{ 1078 uint32_t val0, val1; 1079 int i = 0; 1080 1081 do { 1082 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1083 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1084 } while (val0 != val1 && ++i < 1000); 1085 if (val0 != val1) { 1086 return (1); 1087 } 1088 *rp = val0; 1089 return (0); 1090} 1091 1092static int 1093isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1094{ 1095 uint16_t isr, sema; 1096 1097 if (IS_2100(isp)) { 1098 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1099 return (0); 1100 } 1101 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1102 return (0); 1103 } 1104 } else { 1105 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1106 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1107 } 1108 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1109 isr &= INT_PENDING_MASK(isp); 1110 sema &= BIU_SEMA_LOCK; 1111 if (isr == 0 && sema == 0) { 1112 return (0); 1113 } 1114 *isrp = isr; 1115 if ((*semap = sema) != 0) { 1116 if (IS_2100(isp)) { 1117 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1118 return (0); 1119 } 1120 } else { 1121 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1122 } 1123 } 1124 return (1); 1125} 1126 1127static int 1128isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1129{ 1130 uint32_t hccr; 1131 uint32_t r2hisr; 1132 1133 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1134 *isrp = 0; 1135 return (0); 1136 } 1137 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1138 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1139 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1140 *isrp = 0; 1141 return (0); 1142 } 1143 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1144 case ISPR2HST_ROM_MBX_OK: 1145 case ISPR2HST_ROM_MBX_FAIL: 1146 case ISPR2HST_MBX_OK: 1147 case ISPR2HST_MBX_FAIL: 1148 case ISPR2HST_ASYNC_EVENT: 1149 *isrp = r2hisr & 0xffff; 1150 *mbox0p = (r2hisr >> 16); 1151 *semap = 1; 1152 return (1); 1153 case ISPR2HST_RIO_16: 1154 *isrp = r2hisr & 0xffff; 1155 *mbox0p = ASYNC_RIO16_1; 1156 *semap = 1; 1157 return (1); 1158 case ISPR2HST_FPOST: 1159 *isrp = r2hisr & 0xffff; 1160 *mbox0p = ASYNC_CMD_CMPLT; 1161 *semap = 1; 1162 return (1); 1163 case ISPR2HST_FPOST_CTIO: 1164 *isrp = r2hisr & 0xffff; 1165 *mbox0p = ASYNC_CTIO_DONE; 1166 *semap = 1; 1167 return (1); 1168 case ISPR2HST_RSPQ_UPDATE: 1169 *isrp = r2hisr & 0xffff; 1170 *mbox0p = 0; 1171 *semap = 0; 1172 return (1); 1173 default: 1174 hccr = ISP_READ(isp, HCCR); 1175 if (hccr & HCCR_PAUSE) { 1176 ISP_WRITE(isp, HCCR, HCCR_RESET); 1177 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1178 ISP_WRITE(isp, BIU_ICR, 0); 1179 } else { 1180 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1181 } 1182 return (0); 1183 } 1184} 1185 1186static int 1187isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1188{ 1189 uint32_t r2hisr; 1190 1191 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1192 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1193 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1194 *isrp = 0; 1195 return (0); 1196 } 1197 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1198 case ISP2400R2HST_ROM_MBX_OK: 1199 case ISP2400R2HST_ROM_MBX_FAIL: 1200 case ISP2400R2HST_MBX_OK: 1201 case ISP2400R2HST_MBX_FAIL: 1202 case ISP2400R2HST_ASYNC_EVENT: 1203 *isrp = r2hisr & 0xffff; 1204 *mbox0p = (r2hisr >> 16); 1205 *semap = 1; 1206 return (1); 1207 case ISP2400R2HST_RSPQ_UPDATE: 1208 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1209 case ISP2400R2HST_ATIO_RQST_UPDATE: 1210 *isrp = r2hisr & 0xffff; 1211 *mbox0p = 0; 1212 *semap = 0; 1213 return (1); 1214 default: 1215 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1216 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1217 return (0); 1218 } 1219} 1220 1221static uint32_t 1222isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1223{ 1224 uint16_t rv; 1225 int oldconf = 0; 1226 1227 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1228 /* 1229 * We will assume that someone has paused the RISC processor. 1230 */ 1231 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1232 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1233 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1234 } 1235 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1236 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1237 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1238 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1239 } 1240 return (rv); 1241} 1242 1243static void 1244isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1245{ 1246 int oldconf = 0; 1247 1248 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1249 /* 1250 * We will assume that someone has paused the RISC processor. 1251 */ 1252 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1253 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1254 oldconf | BIU_PCI_CONF1_SXP); 1255 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1256 } 1257 BXW2(isp, IspVirt2Off(isp, regoff), val); 1258 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1259 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1260 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1261 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1262 } 1263 1264} 1265 1266static uint32_t 1267isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1268{ 1269 uint32_t rv, oc = 0; 1270 1271 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1272 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1273 uint32_t tc; 1274 /* 1275 * We will assume that someone has paused the RISC processor. 1276 */ 1277 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1278 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1279 if (regoff & SXP_BANK1_SELECT) 1280 tc |= BIU_PCI1080_CONF1_SXP1; 1281 else 1282 tc |= BIU_PCI1080_CONF1_SXP0; 1283 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1284 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1285 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1286 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1287 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1288 oc | BIU_PCI1080_CONF1_DMA); 1289 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1290 } 1291 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1292 if (oc) { 1293 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1294 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1295 } 1296 return (rv); 1297} 1298 1299static void 1300isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1301{ 1302 int oc = 0; 1303 1304 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1305 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1306 uint32_t tc; 1307 /* 1308 * We will assume that someone has paused the RISC processor. 1309 */ 1310 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1311 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1312 if (regoff & SXP_BANK1_SELECT) 1313 tc |= BIU_PCI1080_CONF1_SXP1; 1314 else 1315 tc |= BIU_PCI1080_CONF1_SXP0; 1316 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1317 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1318 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1319 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1320 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1321 oc | BIU_PCI1080_CONF1_DMA); 1322 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1323 } 1324 BXW2(isp, IspVirt2Off(isp, regoff), val); 1325 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1326 if (oc) { 1327 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1328 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1329 } 1330} 1331 1332static uint32_t 1333isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1334{ 1335 uint32_t rv; 1336 int block = regoff & _BLK_REG_MASK; 1337 1338 switch (block) { 1339 case BIU_BLOCK: 1340 break; 1341 case MBOX_BLOCK: 1342 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1343 case SXP_BLOCK: 1344 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1345 return (0xffffffff); 1346 case RISC_BLOCK: 1347 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1348 return (0xffffffff); 1349 case DMA_BLOCK: 1350 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1351 return (0xffffffff); 1352 default: 1353 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1354 return (0xffffffff); 1355 } 1356 1357 1358 switch (regoff) { 1359 case BIU2400_FLASH_ADDR: 1360 case BIU2400_FLASH_DATA: 1361 case BIU2400_ICR: 1362 case BIU2400_ISR: 1363 case BIU2400_CSR: 1364 case BIU2400_REQINP: 1365 case BIU2400_REQOUTP: 1366 case BIU2400_RSPINP: 1367 case BIU2400_RSPOUTP: 1368 case BIU2400_PRI_REQINP: 1369 case BIU2400_PRI_REQOUTP: 1370 case BIU2400_ATIO_RSPINP: 1371 case BIU2400_ATIO_RSPOUTP: 1372 case BIU2400_HCCR: 1373 case BIU2400_GPIOD: 1374 case BIU2400_GPIOE: 1375 case BIU2400_HSEMA: 1376 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1377 break; 1378 case BIU2400_R2HSTSLO: 1379 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1380 break; 1381 case BIU2400_R2HSTSHI: 1382 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1383 break; 1384 default: 1385 isp_prt(isp, ISP_LOGERR, 1386 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1387 rv = 0xffffffff; 1388 break; 1389 } 1390 return (rv); 1391} 1392 1393static void 1394isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1395{ 1396 int block = regoff & _BLK_REG_MASK; 1397 1398 switch (block) { 1399 case BIU_BLOCK: 1400 break; 1401 case MBOX_BLOCK: 1402 BXW2(isp, IspVirt2Off(isp, regoff), val); 1403 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1404 return; 1405 case SXP_BLOCK: 1406 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1407 return; 1408 case RISC_BLOCK: 1409 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1410 return; 1411 case DMA_BLOCK: 1412 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1413 return; 1414 default: 1415 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1416 regoff); 1417 break; 1418 } 1419 1420 switch (regoff) { 1421 case BIU2400_FLASH_ADDR: 1422 case BIU2400_FLASH_DATA: 1423 case BIU2400_ICR: 1424 case BIU2400_ISR: 1425 case BIU2400_CSR: 1426 case BIU2400_REQINP: 1427 case BIU2400_REQOUTP: 1428 case BIU2400_RSPINP: 1429 case BIU2400_RSPOUTP: 1430 case BIU2400_PRI_REQINP: 1431 case BIU2400_PRI_REQOUTP: 1432 case BIU2400_ATIO_RSPINP: 1433 case BIU2400_ATIO_RSPOUTP: 1434 case BIU2400_HCCR: 1435 case BIU2400_GPIOD: 1436 case BIU2400_GPIOE: 1437 case BIU2400_HSEMA: 1438 BXW4(isp, IspVirt2Off(isp, regoff), val); 1439 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1440 break; 1441 default: 1442 isp_prt(isp, ISP_LOGERR, 1443 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1444 break; 1445 } 1446} 1447 1448 1449struct imush { 1450 ispsoftc_t *isp; 1451 caddr_t vbase; 1452 int chan; 1453 int error; 1454}; 1455 1456static void imc(void *, bus_dma_segment_t *, int, int); 1457static void imc1(void *, bus_dma_segment_t *, int, int); 1458 1459static void 1460imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1461{ 1462 struct imush *imushp = (struct imush *) arg; 1463 isp_ecmd_t *ecmd; 1464 1465 if (error) { 1466 imushp->error = error; 1467 return; 1468 } 1469 if (nseg != 1) { 1470 imushp->error = EINVAL; 1471 return; 1472 } 1473 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1474 1475 imushp->isp->isp_rquest = imushp->vbase; 1476 imushp->isp->isp_rquest_dma = segs->ds_addr; 1477 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1478 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1479 1480 imushp->isp->isp_result_dma = segs->ds_addr; 1481 imushp->isp->isp_result = imushp->vbase; 1482 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1483 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1484 1485 if (imushp->isp->isp_type >= ISP_HA_FC_2300) { 1486 imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr; 1487 imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase; 1488 imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free; 1489 for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1490 if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) { 1491 ecmd->next = NULL; 1492 } else { 1493 ecmd->next = ecmd + 1; 1494 } 1495 } 1496 } 1497#ifdef ISP_TARGET_MODE 1498 segs->ds_addr += (N_XCMDS * XCMD_SIZE); 1499 imushp->vbase += (N_XCMDS * XCMD_SIZE); 1500 if (IS_24XX(imushp->isp)) { 1501 imushp->isp->isp_atioq_dma = segs->ds_addr; 1502 imushp->isp->isp_atioq = imushp->vbase; 1503 } 1504#endif 1505} 1506 1507static void 1508imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1509{ 1510 struct imush *imushp = (struct imush *) arg; 1511 if (error) { 1512 imushp->error = error; 1513 return; 1514 } 1515 if (nseg != 1) { 1516 imushp->error = EINVAL; 1517 return; 1518 } 1519 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1520 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1521 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1522} 1523 1524static int 1525isp_pci_mbxdma(ispsoftc_t *isp) 1526{ 1527 caddr_t base; 1528 uint32_t len; 1529 int i, error, ns, cmap = 0; 1530 bus_size_t slim; /* segment size */ 1531 bus_addr_t llim; /* low limit of unavailable dma */ 1532 bus_addr_t hlim; /* high limit of unavailable dma */ 1533 struct imush im; 1534 1535 /* 1536 * Already been here? If so, leave... 1537 */ 1538 if (isp->isp_rquest) { 1539 return (0); 1540 } 1541 ISP_UNLOCK(isp); 1542 1543 if (isp->isp_maxcmds == 0) { 1544 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1545 ISP_LOCK(isp); 1546 return (1); 1547 } 1548 1549 hlim = BUS_SPACE_MAXADDR; 1550 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1551 if (sizeof (bus_size_t) > 4) { 1552 slim = (bus_size_t) (1ULL << 32); 1553 } else { 1554 slim = (bus_size_t) (1UL << 31); 1555 } 1556 llim = BUS_SPACE_MAXADDR; 1557 } else { 1558 llim = BUS_SPACE_MAXADDR_32BIT; 1559 slim = (1UL << 24); 1560 } 1561 1562 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1563 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1564 if (isp->isp_osinfo.pcmd_pool == NULL) { 1565 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1566 ISP_LOCK(isp); 1567 return (1); 1568 } 1569 1570#ifdef ISP_TARGET_MODE 1571 /* 1572 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1573 */ 1574 if (IS_SCSI(isp) && isp->isp_osinfo.sixtyfourbit) { 1575 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1576 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1577 ISP_LOCK(isp); 1578 return (1); 1579 } 1580#endif 1581 1582 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1583 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1584 ISP_LOCK(isp); 1585 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1586 return (1); 1587 } 1588 1589 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1590 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1591 if (isp->isp_xflist == NULL) { 1592 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1593 ISP_LOCK(isp); 1594 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1595 return (1); 1596 } 1597 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1598 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1599 } 1600 isp->isp_xffree = isp->isp_xflist; 1601#ifdef ISP_TARGET_MODE 1602 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1603 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1604 if (isp->isp_tgtlist == NULL) { 1605 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1606 free(isp->isp_xflist, M_DEVBUF); 1607 ISP_LOCK(isp); 1608 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1609 return (1); 1610 } 1611 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1612 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1613 } 1614 isp->isp_tgtfree = isp->isp_tgtlist; 1615#endif 1616 1617 /* 1618 * Allocate and map the request and result queues (and ATIO queue 1619 * if we're a 2400 supporting target mode), and a region for 1620 * external dma addressable command/status structures (23XX and 1621 * later). 1622 */ 1623 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1624 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1625#ifdef ISP_TARGET_MODE 1626 if (IS_24XX(isp)) { 1627 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1628 } 1629#endif 1630 if (isp->isp_type >= ISP_HA_FC_2300) { 1631 len += (N_XCMDS * XCMD_SIZE); 1632 } 1633 ns = (len / PAGE_SIZE) + 1; 1634 1635 /* 1636 * Create a tag for the control spaces. We don't always need this 1637 * to be 32 bits, but we do this for simplicity and speed's sake. 1638 */ 1639 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1640 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1641 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1642 free(isp->isp_xflist, M_DEVBUF); 1643#ifdef ISP_TARGET_MODE 1644 free(isp->isp_tgtlist, M_DEVBUF); 1645#endif 1646 ISP_LOCK(isp); 1647 return (1); 1648 } 1649 1650 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1651 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1652 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1653 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1654 free(isp->isp_xflist, M_DEVBUF); 1655#ifdef ISP_TARGET_MODE 1656 free(isp->isp_tgtlist, M_DEVBUF); 1657#endif 1658 ISP_LOCK(isp); 1659 return (1); 1660 } 1661 1662 im.isp = isp; 1663 im.chan = 0; 1664 im.vbase = base; 1665 im.error = 0; 1666 1667 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1668 if (im.error) { 1669 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1670 goto bad; 1671 } 1672 1673 if (IS_FC(isp)) { 1674 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1675 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1676 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1677 goto bad; 1678 } 1679 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1680 bus_dma_tag_destroy(fc->tdmat); 1681 goto bad; 1682 } 1683 im.isp = isp; 1684 im.chan = cmap; 1685 im.vbase = base; 1686 im.error = 0; 1687 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1688 if (im.error) { 1689 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1690 bus_dma_tag_destroy(fc->tdmat); 1691 goto bad; 1692 } 1693 if (isp->isp_type >= ISP_HA_FC_2300) { 1694 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1695 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1696 if (n == NULL) { 1697 while (fc->nexus_free_list) { 1698 n = fc->nexus_free_list; 1699 fc->nexus_free_list = n->next; 1700 free(n, M_DEVBUF); 1701 } 1702 goto bad; 1703 } 1704 n->next = fc->nexus_free_list; 1705 fc->nexus_free_list = n; 1706 } 1707 } 1708 } 1709 } 1710 1711 for (i = 0; i < isp->isp_maxcmds; i++) { 1712 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1713 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1714 if (error) { 1715 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1716 while (--i >= 0) { 1717 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1718 } 1719 goto bad; 1720 } 1721 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1722 if (i == isp->isp_maxcmds-1) { 1723 pcmd->next = NULL; 1724 } else { 1725 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1726 } 1727 } 1728 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1729 ISP_LOCK(isp); 1730 return (0); 1731 1732bad: 1733 while (--cmap >= 0) { 1734 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1735 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1736 bus_dma_tag_destroy(fc->tdmat); 1737 while (fc->nexus_free_list) { 1738 struct isp_nexus *n = fc->nexus_free_list; 1739 fc->nexus_free_list = n->next; 1740 free(n, M_DEVBUF); 1741 } 1742 } 1743 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1744 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1745 free(isp->isp_xflist, M_DEVBUF); 1746#ifdef ISP_TARGET_MODE 1747 free(isp->isp_tgtlist, M_DEVBUF); 1748#endif 1749 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1750 isp->isp_rquest = NULL; 1751 ISP_LOCK(isp); 1752 return (1); 1753} 1754 1755typedef struct { 1756 ispsoftc_t *isp; 1757 void *cmd_token; 1758 void *rq; /* original request */ 1759 int error; 1760 bus_size_t mapsize; 1761} mush_t; 1762 1763#define MUSHERR_NOQENTRIES -2 1764 1765#ifdef ISP_TARGET_MODE 1766static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1767static void tdma2(void *, bus_dma_segment_t *, int, int); 1768 1769static void 1770tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1771{ 1772 mush_t *mp; 1773 mp = (mush_t *)arg; 1774 mp->mapsize = mapsize; 1775 tdma2(arg, dm_segs, nseg, error); 1776} 1777 1778static void 1779tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1780{ 1781 mush_t *mp; 1782 ispsoftc_t *isp; 1783 struct ccb_scsiio *csio; 1784 isp_ddir_t ddir; 1785 ispreq_t *rq; 1786 1787 mp = (mush_t *) arg; 1788 if (error) { 1789 mp->error = error; 1790 return; 1791 } 1792 csio = mp->cmd_token; 1793 isp = mp->isp; 1794 rq = mp->rq; 1795 if (nseg) { 1796 if (isp->isp_osinfo.sixtyfourbit) { 1797 if (nseg >= ISP_NSEG64_MAX) { 1798 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1799 mp->error = EFAULT; 1800 return; 1801 } 1802 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1803 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1804 } 1805 } else { 1806 if (nseg >= ISP_NSEG_MAX) { 1807 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1808 mp->error = EFAULT; 1809 return; 1810 } 1811 } 1812 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1813 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1814 ddir = ISP_TO_DEVICE; 1815 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1816 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1817 ddir = ISP_FROM_DEVICE; 1818 } else { 1819 dm_segs = NULL; 1820 nseg = 0; 1821 ddir = ISP_NOXFR; 1822 } 1823 } else { 1824 dm_segs = NULL; 1825 nseg = 0; 1826 ddir = ISP_NOXFR; 1827 } 1828 1829 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len); 1830 switch (error) { 1831 case CMD_EAGAIN: 1832 mp->error = MUSHERR_NOQENTRIES; 1833 case CMD_QUEUED: 1834 break; 1835 default: 1836 mp->error = EIO; 1837 } 1838} 1839#endif 1840 1841static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1842static void dma2(void *, bus_dma_segment_t *, int, int); 1843 1844static void 1845dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1846{ 1847 mush_t *mp; 1848 mp = (mush_t *)arg; 1849 mp->mapsize = mapsize; 1850 dma2(arg, dm_segs, nseg, error); 1851} 1852 1853static void 1854dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1855{ 1856 mush_t *mp; 1857 ispsoftc_t *isp; 1858 struct ccb_scsiio *csio; 1859 isp_ddir_t ddir; 1860 ispreq_t *rq; 1861 1862 mp = (mush_t *) arg; 1863 if (error) { 1864 mp->error = error; 1865 return; 1866 } 1867 csio = mp->cmd_token; 1868 isp = mp->isp; 1869 rq = mp->rq; 1870 if (nseg) { 1871 if (isp->isp_osinfo.sixtyfourbit) { 1872 if (nseg >= ISP_NSEG64_MAX) { 1873 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1874 mp->error = EFAULT; 1875 return; 1876 } 1877 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1878 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1879 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1880 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1881 } 1882 } else { 1883 if (nseg >= ISP_NSEG_MAX) { 1884 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1885 mp->error = EFAULT; 1886 return; 1887 } 1888 } 1889 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1890 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1891 ddir = ISP_FROM_DEVICE; 1892 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1893 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1894 ddir = ISP_TO_DEVICE; 1895 } else { 1896 ddir = ISP_NOXFR; 1897 } 1898 } else { 1899 dm_segs = NULL; 1900 nseg = 0; 1901 ddir = ISP_NOXFR; 1902 } 1903 1904 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map); 1905 switch (error) { 1906 case CMD_EAGAIN: 1907 mp->error = MUSHERR_NOQENTRIES; 1908 break; 1909 case CMD_QUEUED: 1910 break; 1911 default: 1912 mp->error = EIO; 1913 break; 1914 } 1915} 1916 1917static int 1918isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1919{ 1920 mush_t mush, *mp; 1921 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1922 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1923 1924 mp = &mush; 1925 mp->isp = isp; 1926 mp->cmd_token = csio; 1927 mp->rq = ff; 1928 mp->error = 0; 1929 mp->mapsize = 0; 1930 1931#ifdef ISP_TARGET_MODE 1932 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1933 eptr = tdma2; 1934 eptr2 = tdma2_2; 1935 } else 1936#endif 1937 { 1938 eptr = dma2; 1939 eptr2 = dma2_2; 1940 } 1941 1942 1943 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1944 (*eptr)(mp, NULL, 0, 0); 1945 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1946 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1947 int error; 1948 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1949#if 0 1950 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1951#endif 1952 1953 if (error == EINPROGRESS) { 1954 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1955 mp->error = EINVAL; 1956 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1957 } else if (error && mp->error == 0) { 1958#ifdef DIAGNOSTIC 1959 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1960#endif 1961 mp->error = error; 1962 } 1963 } else { 1964 /* Pointer to physical buffer */ 1965 struct bus_dma_segment seg; 1966 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1967 seg.ds_len = csio->dxfer_len; 1968 (*eptr)(mp, &seg, 1, 0); 1969 } 1970 } else { 1971 struct bus_dma_segment *segs; 1972 1973 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1974 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1975 mp->error = EINVAL; 1976 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1977 struct uio sguio; 1978 int error; 1979 1980 /* 1981 * We're taking advantage of the fact that 1982 * the pointer/length sizes and layout of the iovec 1983 * structure are the same as the bus_dma_segment 1984 * structure. This might be a little dangerous, 1985 * but only if they change the structures, which 1986 * seems unlikely. 1987 */ 1988 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1989 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1990 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1991 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1992 sguio.uio_iovcnt = csio->sglist_cnt; 1993 sguio.uio_resid = csio->dxfer_len; 1994 sguio.uio_segflg = UIO_SYSSPACE; 1995 1996 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1997 1998 if (error != 0 && mp->error == 0) { 1999 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 2000 mp->error = error; 2001 } 2002 } else { 2003 /* Just use the segments provided */ 2004 segs = (struct bus_dma_segment *) csio->data_ptr; 2005 (*eptr)(mp, segs, csio->sglist_cnt, 0); 2006 } 2007 } 2008 if (mp->error) { 2009 int retval = CMD_COMPLETE; 2010 if (mp->error == MUSHERR_NOQENTRIES) { 2011 retval = CMD_EAGAIN; 2012 } else if (mp->error == EFBIG) { 2013 csio->ccb_h.status = CAM_REQ_TOO_BIG; 2014 } else if (mp->error == EINVAL) { 2015 csio->ccb_h.status = CAM_REQ_INVALID; 2016 } else { 2017 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 2018 } 2019 return (retval); 2020 } 2021 return (CMD_QUEUED); 2022} 2023 2024static void 2025isp_pci_reset0(ispsoftc_t *isp) 2026{ 2027 ISP_DISABLE_INTS(isp); 2028} 2029 2030static void 2031isp_pci_reset1(ispsoftc_t *isp) 2032{ 2033 if (!IS_24XX(isp)) { 2034 /* Make sure the BIOS is disabled */ 2035 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 2036 } 2037 /* and enable interrupts */ 2038 ISP_ENABLE_INTS(isp); 2039} 2040 2041static void 2042isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 2043{ 2044 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2045 if (msg) 2046 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 2047 else 2048 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2049 if (IS_SCSI(isp)) 2050 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2051 else 2052 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2053 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2054 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2055 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2056 2057 2058 if (IS_SCSI(isp)) { 2059 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2060 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2061 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2062 ISP_READ(isp, CDMA_FIFO_STS)); 2063 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2064 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2065 ISP_READ(isp, DDMA_FIFO_STS)); 2066 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2067 ISP_READ(isp, SXP_INTERRUPT), 2068 ISP_READ(isp, SXP_GROSS_ERR), 2069 ISP_READ(isp, SXP_PINS_CTRL)); 2070 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2071 } 2072 printf(" mbox regs: %x %x %x %x %x\n", 2073 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2074 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2075 ISP_READ(isp, OUTMAILBOX4)); 2076 printf(" PCI Status Command/Status=%x\n", 2077 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2078} 2079