isp_pci.c revision 203444
1/*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26/* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/isp/isp_pci.c 203444 2010-02-03 21:09:32Z mjacob $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/linker.h> 38#include <sys/firmware.h> 39#include <sys/bus.h> 40#include <sys/stdint.h> 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46#include <sys/malloc.h> 47#include <sys/uio.h> 48 49#include <dev/isp/isp_freebsd.h> 50 51static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 52static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 53static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 54static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 55static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 56static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 57static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 58static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 59static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 60static int isp_pci_mbxdma(ispsoftc_t *); 61static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 62 63 64static void isp_pci_reset0(ispsoftc_t *); 65static void isp_pci_reset1(ispsoftc_t *); 66static void isp_pci_dumpregs(ispsoftc_t *, const char *); 67 68static struct ispmdvec mdvec = { 69 isp_pci_rd_isr, 70 isp_pci_rd_reg, 71 isp_pci_wr_reg, 72 isp_pci_mbxdma, 73 isp_pci_dmasetup, 74 isp_common_dmateardown, 75 isp_pci_reset0, 76 isp_pci_reset1, 77 isp_pci_dumpregs, 78 NULL, 79 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 80}; 81 82static struct ispmdvec mdvec_1080 = { 83 isp_pci_rd_isr, 84 isp_pci_rd_reg_1080, 85 isp_pci_wr_reg_1080, 86 isp_pci_mbxdma, 87 isp_pci_dmasetup, 88 isp_common_dmateardown, 89 isp_pci_reset0, 90 isp_pci_reset1, 91 isp_pci_dumpregs, 92 NULL, 93 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 94}; 95 96static struct ispmdvec mdvec_12160 = { 97 isp_pci_rd_isr, 98 isp_pci_rd_reg_1080, 99 isp_pci_wr_reg_1080, 100 isp_pci_mbxdma, 101 isp_pci_dmasetup, 102 isp_common_dmateardown, 103 isp_pci_reset0, 104 isp_pci_reset1, 105 isp_pci_dumpregs, 106 NULL, 107 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 108}; 109 110static struct ispmdvec mdvec_2100 = { 111 isp_pci_rd_isr, 112 isp_pci_rd_reg, 113 isp_pci_wr_reg, 114 isp_pci_mbxdma, 115 isp_pci_dmasetup, 116 isp_common_dmateardown, 117 isp_pci_reset0, 118 isp_pci_reset1, 119 isp_pci_dumpregs 120}; 121 122static struct ispmdvec mdvec_2200 = { 123 isp_pci_rd_isr, 124 isp_pci_rd_reg, 125 isp_pci_wr_reg, 126 isp_pci_mbxdma, 127 isp_pci_dmasetup, 128 isp_common_dmateardown, 129 isp_pci_reset0, 130 isp_pci_reset1, 131 isp_pci_dumpregs 132}; 133 134static struct ispmdvec mdvec_2300 = { 135 isp_pci_rd_isr_2300, 136 isp_pci_rd_reg, 137 isp_pci_wr_reg, 138 isp_pci_mbxdma, 139 isp_pci_dmasetup, 140 isp_common_dmateardown, 141 isp_pci_reset0, 142 isp_pci_reset1, 143 isp_pci_dumpregs 144}; 145 146static struct ispmdvec mdvec_2400 = { 147 isp_pci_rd_isr_2400, 148 isp_pci_rd_reg_2400, 149 isp_pci_wr_reg_2400, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_common_dmateardown, 153 isp_pci_reset0, 154 isp_pci_reset1, 155 NULL 156}; 157 158static struct ispmdvec mdvec_2500 = { 159 isp_pci_rd_isr_2400, 160 isp_pci_rd_reg_2400, 161 isp_pci_wr_reg_2400, 162 isp_pci_mbxdma, 163 isp_pci_dmasetup, 164 isp_common_dmateardown, 165 isp_pci_reset0, 166 isp_pci_reset1, 167 NULL 168}; 169 170#ifndef PCIM_CMD_INVEN 171#define PCIM_CMD_INVEN 0x10 172#endif 173#ifndef PCIM_CMD_BUSMASTEREN 174#define PCIM_CMD_BUSMASTEREN 0x0004 175#endif 176#ifndef PCIM_CMD_PERRESPEN 177#define PCIM_CMD_PERRESPEN 0x0040 178#endif 179#ifndef PCIM_CMD_SEREN 180#define PCIM_CMD_SEREN 0x0100 181#endif 182#ifndef PCIM_CMD_INTX_DISABLE 183#define PCIM_CMD_INTX_DISABLE 0x0400 184#endif 185 186#ifndef PCIR_COMMAND 187#define PCIR_COMMAND 0x04 188#endif 189 190#ifndef PCIR_CACHELNSZ 191#define PCIR_CACHELNSZ 0x0c 192#endif 193 194#ifndef PCIR_LATTIMER 195#define PCIR_LATTIMER 0x0d 196#endif 197 198#ifndef PCIR_ROMADDR 199#define PCIR_ROMADDR 0x30 200#endif 201 202#ifndef PCI_VENDOR_QLOGIC 203#define PCI_VENDOR_QLOGIC 0x1077 204#endif 205 206#ifndef PCI_PRODUCT_QLOGIC_ISP1020 207#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 208#endif 209 210#ifndef PCI_PRODUCT_QLOGIC_ISP1080 211#define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 212#endif 213 214#ifndef PCI_PRODUCT_QLOGIC_ISP10160 215#define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 216#endif 217 218#ifndef PCI_PRODUCT_QLOGIC_ISP12160 219#define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 220#endif 221 222#ifndef PCI_PRODUCT_QLOGIC_ISP1240 223#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 224#endif 225 226#ifndef PCI_PRODUCT_QLOGIC_ISP1280 227#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 228#endif 229 230#ifndef PCI_PRODUCT_QLOGIC_ISP2100 231#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 232#endif 233 234#ifndef PCI_PRODUCT_QLOGIC_ISP2200 235#define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 236#endif 237 238#ifndef PCI_PRODUCT_QLOGIC_ISP2300 239#define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 240#endif 241 242#ifndef PCI_PRODUCT_QLOGIC_ISP2312 243#define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 244#endif 245 246#ifndef PCI_PRODUCT_QLOGIC_ISP2322 247#define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 248#endif 249 250#ifndef PCI_PRODUCT_QLOGIC_ISP2422 251#define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 252#endif 253 254#ifndef PCI_PRODUCT_QLOGIC_ISP2432 255#define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 256#endif 257 258#ifndef PCI_PRODUCT_QLOGIC_ISP2532 259#define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 260#endif 261 262#ifndef PCI_PRODUCT_QLOGIC_ISP6312 263#define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 264#endif 265 266#ifndef PCI_PRODUCT_QLOGIC_ISP6322 267#define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 268#endif 269 270 271#define PCI_QLOGIC_ISP1020 \ 272 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 273 274#define PCI_QLOGIC_ISP1080 \ 275 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 276 277#define PCI_QLOGIC_ISP10160 \ 278 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 279 280#define PCI_QLOGIC_ISP12160 \ 281 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 282 283#define PCI_QLOGIC_ISP1240 \ 284 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 285 286#define PCI_QLOGIC_ISP1280 \ 287 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 288 289#define PCI_QLOGIC_ISP2100 \ 290 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 291 292#define PCI_QLOGIC_ISP2200 \ 293 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 294 295#define PCI_QLOGIC_ISP2300 \ 296 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 297 298#define PCI_QLOGIC_ISP2312 \ 299 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 300 301#define PCI_QLOGIC_ISP2322 \ 302 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 303 304#define PCI_QLOGIC_ISP2422 \ 305 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 306 307#define PCI_QLOGIC_ISP2432 \ 308 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 309 310#define PCI_QLOGIC_ISP2532 \ 311 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 312 313#define PCI_QLOGIC_ISP6312 \ 314 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 315 316#define PCI_QLOGIC_ISP6322 \ 317 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 318 319/* 320 * Odd case for some AMI raid cards... We need to *not* attach to this. 321 */ 322#define AMI_RAID_SUBVENDOR_ID 0x101e 323 324#define IO_MAP_REG 0x10 325#define MEM_MAP_REG 0x14 326 327#define PCI_DFLT_LTNCY 0x40 328#define PCI_DFLT_LNSZ 0x10 329 330static int isp_pci_probe (device_t); 331static int isp_pci_attach (device_t); 332static int isp_pci_detach (device_t); 333 334 335#define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 336struct isp_pcisoftc { 337 ispsoftc_t pci_isp; 338 device_t pci_dev; 339 struct resource * pci_reg; 340 void * ih; 341 int16_t pci_poff[_NREG_BLKS]; 342 bus_dma_tag_t dmat; 343 int msicount; 344}; 345 346 347static device_method_t isp_pci_methods[] = { 348 /* Device interface */ 349 DEVMETHOD(device_probe, isp_pci_probe), 350 DEVMETHOD(device_attach, isp_pci_attach), 351 DEVMETHOD(device_detach, isp_pci_detach), 352 { 0, 0 } 353}; 354 355static driver_t isp_pci_driver = { 356 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 357}; 358static devclass_t isp_devclass; 359DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 360 361static int 362isp_pci_probe(device_t dev) 363{ 364 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 365 case PCI_QLOGIC_ISP1020: 366 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 367 break; 368 case PCI_QLOGIC_ISP1080: 369 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 370 break; 371 case PCI_QLOGIC_ISP1240: 372 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 373 break; 374 case PCI_QLOGIC_ISP1280: 375 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 376 break; 377 case PCI_QLOGIC_ISP10160: 378 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 379 break; 380 case PCI_QLOGIC_ISP12160: 381 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 382 return (ENXIO); 383 } 384 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP2100: 387 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 388 break; 389 case PCI_QLOGIC_ISP2200: 390 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 391 break; 392 case PCI_QLOGIC_ISP2300: 393 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 394 break; 395 case PCI_QLOGIC_ISP2312: 396 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 397 break; 398 case PCI_QLOGIC_ISP2322: 399 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 400 break; 401 case PCI_QLOGIC_ISP2422: 402 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2432: 405 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2532: 408 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP6312: 411 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP6322: 414 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 415 break; 416 default: 417 return (ENXIO); 418 } 419 if (isp_announced == 0 && bootverbose) { 420 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 421 "Core Version %d.%d\n", 422 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 423 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 424 isp_announced++; 425 } 426 /* 427 * XXXX: Here is where we might load the f/w module 428 * XXXX: (or increase a reference count to it). 429 */ 430 return (BUS_PROBE_DEFAULT); 431} 432 433static void 434isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 435{ 436 int tval; 437 438 /* 439 * Figure out if we're supposed to skip this one. 440 */ 441 tval = 0; 442 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 443 device_printf(dev, "disabled at user request\n"); 444 isp->isp_osinfo.disabled = 1; 445 return; 446 } 447 448 tval = 0; 449 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 450 isp->isp_confopts |= ISP_CFG_NORELOAD; 451 } 452 tval = 0; 453 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 454 isp->isp_confopts |= ISP_CFG_NONVRAM; 455 } 456 tval = 0; 457 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 458 if (tval) { 459 isp->isp_dblev = tval; 460 } else { 461 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 462 } 463 if (bootverbose) { 464 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 465 } 466 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 467 if (tval > 0 && tval < 127) { 468 *nvp = tval; 469 } else { 470 *nvp = 0; 471 } 472 tval = 1; 473 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 474 isp_autoconfig = tval; 475 tval = 7; 476 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 477 isp_quickboot_time = tval; 478 479 tval = 0; 480 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) { 481 isp->isp_osinfo.forcemulti = 1; 482 } 483} 484 485static void 486isp_get_pci_options(device_t dev, int *m1, int *m2) 487{ 488 int tval; 489 /* 490 * Which we should try first - memory mapping or i/o mapping? 491 * 492 * We used to try memory first followed by i/o on alpha, otherwise 493 * the reverse, but we should just try memory first all the time now. 494 */ 495 *m1 = PCIM_CMD_MEMEN; 496 *m2 = PCIM_CMD_PORTEN; 497 498 tval = 0; 499 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 500 *m1 = PCIM_CMD_PORTEN; 501 *m2 = PCIM_CMD_MEMEN; 502 } 503 tval = 0; 504 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 505 *m1 = PCIM_CMD_MEMEN; 506 *m2 = PCIM_CMD_PORTEN; 507 } 508} 509 510static void 511isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 512{ 513 const char *sptr; 514 int tval; 515 516 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 517 if (IS_FC(isp)) { 518 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 519 } else { 520 ISP_SPI_PC(isp, chan)->iid = 7; 521 } 522 } else { 523 if (IS_FC(isp)) { 524 ISP_FC_PC(isp, chan)->default_id = tval - chan; 525 } else { 526 ISP_SPI_PC(isp, chan)->iid = tval; 527 } 528 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 529 } 530 531 tval = -1; 532 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 533 switch (tval) { 534 case ISP_ROLE_NONE: 535 case ISP_ROLE_INITIATOR: 536 case ISP_ROLE_TARGET: 537 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 538 device_printf(dev, "setting role to 0x%x\n", tval); 539 break; 540 default: 541 tval = -1; 542 break; 543 } 544 } 545 if (tval == -1) { 546 tval = ISP_DEFAULT_ROLES; 547 } 548 549 if (IS_SCSI(isp)) { 550 ISP_SPI_PC(isp, chan)->role = tval; 551 return; 552 } 553 ISP_FC_PC(isp, chan)->role = tval; 554 555 tval = 0; 556 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 557 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 558 } 559 sptr = 0; 560 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 561 if (strcmp(sptr, "lport") == 0) { 562 isp->isp_confopts |= ISP_CFG_LPORT; 563 } else if (strcmp(sptr, "nport") == 0) { 564 isp->isp_confopts |= ISP_CFG_NPORT; 565 } else if (strcmp(sptr, "lport-only") == 0) { 566 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 567 } else if (strcmp(sptr, "nport-only") == 0) { 568 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 569 } 570 } 571 572 /* 573 * Because the resource_*_value functions can neither return 574 * 64 bit integer values, nor can they be directly coerced 575 * to interpret the right hand side of the assignment as 576 * you want them to interpret it, we have to force WWN 577 * hint replacement to specify WWN strings with a leading 578 * 'w' (e..g w50000000aaaa0001). Sigh. 579 */ 580 sptr = 0; 581 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 582 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 583 char *eptr = 0; 584 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 585 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 586 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 587 ISP_FC_PC(isp, chan)->def_wwpn = 0; 588 } 589 } 590 591 sptr = 0; 592 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 593 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 594 char *eptr = 0; 595 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 596 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 597 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 598 ISP_FC_PC(isp, chan)->def_wwnn = 0; 599 } 600 } 601 602 tval = 0; 603 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 604 if (tval >= 0 && tval < 256) { 605 ISP_FC_PC(isp, chan)->hysteresis = tval; 606 } else { 607 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 608 } 609 610 tval = -1; 611 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 612 if (tval >= 0 && tval < 0xffff) { 613 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 614 } else { 615 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 616 } 617 618 tval = -1; 619 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 620 if (tval >= 0 && tval < 0xffff) { 621 ISP_FC_PC(isp, chan)->gone_device_time = tval; 622 } else { 623 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 624 } 625} 626 627static int 628isp_pci_attach(device_t dev) 629{ 630 struct resource *regs, *irq; 631 int rtp, rgd, iqd, i, m1, m2, locksetup = 0; 632 int isp_nvports = 0; 633 uint32_t data, cmd, linesz, did; 634 struct isp_pcisoftc *pcs; 635 ispsoftc_t *isp = NULL; 636 size_t psize, xsize; 637 char fwname[32]; 638 639 pcs = device_get_softc(dev); 640 if (pcs == NULL) { 641 device_printf(dev, "cannot get softc\n"); 642 return (ENOMEM); 643 } 644 memset(pcs, 0, sizeof (*pcs)); 645 646 pcs->pci_dev = dev; 647 isp = &pcs->pci_isp; 648 isp->isp_dev = dev; 649 isp->isp_nchan = 1; 650 651 /* 652 * Get Generic Options 653 */ 654 isp_get_generic_options(dev, isp, &isp_nvports); 655 656 /* 657 * Check to see if options have us disabled 658 */ 659 if (isp->isp_osinfo.disabled) { 660 /* 661 * But return zero to preserve unit numbering 662 */ 663 return (0); 664 } 665 666 /* 667 * Get PCI options- which in this case are just mapping preferences. 668 */ 669 isp_get_pci_options(dev, &m1, &m2); 670 671 linesz = PCI_DFLT_LNSZ; 672 irq = regs = NULL; 673 rgd = rtp = iqd = 0; 674 675 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 676 if (cmd & m1) { 677 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 678 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 679 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 680 } 681 if (regs == NULL && (cmd & m2)) { 682 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 683 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 684 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 685 } 686 if (regs == NULL) { 687 device_printf(dev, "unable to map any ports\n"); 688 goto bad; 689 } 690 if (bootverbose) { 691 device_printf(dev, "using %s space register mapping\n", (rgd == IO_MAP_REG)? "I/O" : "Memory"); 692 } 693 isp->isp_bus_tag = rman_get_bustag(regs); 694 isp->isp_bus_handle = rman_get_bushandle(regs); 695 696 pcs->pci_dev = dev; 697 pcs->pci_reg = regs; 698 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 699 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 700 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 701 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 702 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 703 704 switch (pci_get_devid(dev)) { 705 case PCI_QLOGIC_ISP1020: 706 did = 0x1040; 707 isp->isp_mdvec = &mdvec; 708 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 709 break; 710 case PCI_QLOGIC_ISP1080: 711 did = 0x1080; 712 isp->isp_mdvec = &mdvec_1080; 713 isp->isp_type = ISP_HA_SCSI_1080; 714 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 715 break; 716 case PCI_QLOGIC_ISP1240: 717 did = 0x1080; 718 isp->isp_mdvec = &mdvec_1080; 719 isp->isp_type = ISP_HA_SCSI_1240; 720 isp->isp_nchan = 2; 721 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 722 break; 723 case PCI_QLOGIC_ISP1280: 724 did = 0x1080; 725 isp->isp_mdvec = &mdvec_1080; 726 isp->isp_type = ISP_HA_SCSI_1280; 727 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 728 break; 729 case PCI_QLOGIC_ISP10160: 730 did = 0x12160; 731 isp->isp_mdvec = &mdvec_12160; 732 isp->isp_type = ISP_HA_SCSI_10160; 733 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 734 break; 735 case PCI_QLOGIC_ISP12160: 736 did = 0x12160; 737 isp->isp_nchan = 2; 738 isp->isp_mdvec = &mdvec_12160; 739 isp->isp_type = ISP_HA_SCSI_12160; 740 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 741 break; 742 case PCI_QLOGIC_ISP2100: 743 did = 0x2100; 744 isp->isp_mdvec = &mdvec_2100; 745 isp->isp_type = ISP_HA_FC_2100; 746 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 747 if (pci_get_revid(dev) < 3) { 748 /* 749 * XXX: Need to get the actual revision 750 * XXX: number of the 2100 FB. At any rate, 751 * XXX: lower cache line size for early revision 752 * XXX; boards. 753 */ 754 linesz = 1; 755 } 756 break; 757 case PCI_QLOGIC_ISP2200: 758 did = 0x2200; 759 isp->isp_mdvec = &mdvec_2200; 760 isp->isp_type = ISP_HA_FC_2200; 761 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 762 break; 763 case PCI_QLOGIC_ISP2300: 764 did = 0x2300; 765 isp->isp_mdvec = &mdvec_2300; 766 isp->isp_type = ISP_HA_FC_2300; 767 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 768 break; 769 case PCI_QLOGIC_ISP2312: 770 case PCI_QLOGIC_ISP6312: 771 did = 0x2300; 772 isp->isp_mdvec = &mdvec_2300; 773 isp->isp_type = ISP_HA_FC_2312; 774 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 775 break; 776 case PCI_QLOGIC_ISP2322: 777 case PCI_QLOGIC_ISP6322: 778 did = 0x2322; 779 isp->isp_mdvec = &mdvec_2300; 780 isp->isp_type = ISP_HA_FC_2322; 781 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 782 break; 783 case PCI_QLOGIC_ISP2422: 784 case PCI_QLOGIC_ISP2432: 785 did = 0x2400; 786 isp->isp_nchan += isp_nvports; 787 isp->isp_mdvec = &mdvec_2400; 788 isp->isp_type = ISP_HA_FC_2400; 789 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 790 break; 791 case PCI_QLOGIC_ISP2532: 792 did = 0x2500; 793 isp->isp_nchan += isp_nvports; 794 isp->isp_mdvec = &mdvec_2500; 795 isp->isp_type = ISP_HA_FC_2500; 796 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 797 break; 798 default: 799 device_printf(dev, "unknown device type\n"); 800 goto bad; 801 break; 802 } 803 isp->isp_revision = pci_get_revid(dev); 804 805 if (IS_FC(isp)) { 806 psize = sizeof (fcparam); 807 xsize = sizeof (struct isp_fc); 808 } else { 809 psize = sizeof (sdparam); 810 xsize = sizeof (struct isp_spi); 811 } 812 psize *= isp->isp_nchan; 813 xsize *= isp->isp_nchan; 814 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 815 if (isp->isp_param == NULL) { 816 device_printf(dev, "cannot allocate parameter data\n"); 817 goto bad; 818 } 819 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 820 if (isp->isp_osinfo.pc.ptr == NULL) { 821 device_printf(dev, "cannot allocate parameter data\n"); 822 goto bad; 823 } 824 825 /* 826 * Now that we know who we are (roughly) get/set specific options 827 */ 828 for (i = 0; i < isp->isp_nchan; i++) { 829 isp_get_specific_options(dev, i, isp); 830 } 831 832 /* 833 * The 'it' suffix really only matters for SCSI cards in target mode. 834 */ 835 isp->isp_osinfo.fw = NULL; 836 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->role & ISP_ROLE_TARGET)) { 837 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 838 isp->isp_osinfo.fw = firmware_get(fwname); 839 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) { 840 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 841 isp->isp_osinfo.fw = firmware_get(fwname); 842 } 843 if (isp->isp_osinfo.fw == NULL) { 844 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 845 isp->isp_osinfo.fw = firmware_get(fwname); 846 } 847 if (isp->isp_osinfo.fw != NULL) { 848 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 849 } 850 851 /* 852 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 853 * are set. 854 */ 855 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 856 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 857 858 if (IS_2300(isp)) { /* per QLogic errata */ 859 cmd &= ~PCIM_CMD_INVEN; 860 } 861 862 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 863 cmd &= ~PCIM_CMD_INTX_DISABLE; 864 } 865 866 if (IS_24XX(isp)) { 867 cmd &= ~PCIM_CMD_INTX_DISABLE; 868 } 869 870 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 871 872 /* 873 * Make sure the Cache Line Size register is set sensibly. 874 */ 875 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 876 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 877 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data); 878 data = linesz; 879 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 880 } 881 882 /* 883 * Make sure the Latency Timer is sane. 884 */ 885 data = pci_read_config(dev, PCIR_LATTIMER, 1); 886 if (data < PCI_DFLT_LTNCY) { 887 data = PCI_DFLT_LTNCY; 888 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 889 pci_write_config(dev, PCIR_LATTIMER, data, 1); 890 } 891 892 /* 893 * Make sure we've disabled the ROM. 894 */ 895 data = pci_read_config(dev, PCIR_ROMADDR, 4); 896 data &= ~1; 897 pci_write_config(dev, PCIR_ROMADDR, data, 4); 898 899 /* 900 * Do MSI 901 * 902 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 903 */ 904 if (IS_24XX(isp) || IS_2322(isp)) { 905 pcs->msicount = pci_msi_count(dev); 906 if (pcs->msicount > 1) { 907 pcs->msicount = 1; 908 } 909 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 910 iqd = 1; 911 } else { 912 iqd = 0; 913 } 914 } 915 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, RF_ACTIVE | RF_SHAREABLE); 916 if (irq == NULL) { 917 device_printf(dev, "could not allocate interrupt\n"); 918 goto bad; 919 } 920 921 /* Make sure the lock is set up. */ 922 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 923 locksetup++; 924 925 if (isp_setup_intr(dev, irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 926 device_printf(dev, "could not setup interrupt\n"); 927 goto bad; 928 } 929 930 /* 931 * Last minute checks... 932 */ 933 if (IS_23XX(isp) || IS_24XX(isp)) { 934 isp->isp_port = pci_get_function(dev); 935 } 936 937 /* 938 * Make sure we're in reset state. 939 */ 940 ISP_LOCK(isp); 941 isp_reset(isp, 1); 942 if (isp->isp_state != ISP_RESETSTATE) { 943 ISP_UNLOCK(isp); 944 goto bad; 945 } 946 isp_init(isp); 947 if (isp->isp_state == ISP_INITSTATE) { 948 isp->isp_state = ISP_RUNSTATE; 949 } 950 ISP_UNLOCK(isp); 951 if (isp_attach(isp)) { 952 ISP_LOCK(isp); 953 isp_uninit(isp); 954 ISP_UNLOCK(isp); 955 goto bad; 956 } 957 return (0); 958 959bad: 960 if (pcs && pcs->ih) { 961 (void) bus_teardown_intr(dev, irq, pcs->ih); 962 } 963 if (locksetup && isp) { 964 mtx_destroy(&isp->isp_osinfo.lock); 965 } 966 if (irq) { 967 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 968 } 969 if (pcs && pcs->msicount) { 970 pci_release_msi(dev); 971 } 972 if (regs) { 973 (void) bus_release_resource(dev, rtp, rgd, regs); 974 } 975 if (pcs) { 976 if (pcs->pci_isp.isp_param) { 977 free(pcs->pci_isp.isp_param, M_DEVBUF); 978 pcs->pci_isp.isp_param = NULL; 979 } 980 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 981 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 982 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 983 } 984 } 985 return (ENXIO); 986} 987 988static int 989isp_pci_detach(device_t dev) 990{ 991 struct isp_pcisoftc *pcs; 992 ispsoftc_t *isp; 993 994 pcs = device_get_softc(dev); 995 if (pcs == NULL) { 996 return (ENXIO); 997 } 998 isp = (ispsoftc_t *) pcs; 999 ISP_DISABLE_INTS(isp); 1000 mtx_destroy(&isp->isp_osinfo.lock); 1001 return (0); 1002} 1003 1004#define IspVirt2Off(a, x) \ 1005 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1006 _BLK_REG_SHFT] + ((x) & 0xfff)) 1007 1008#define BXR2(isp, off) \ 1009 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1010#define BXW2(isp, off, v) \ 1011 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1012#define BXR4(isp, off) \ 1013 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1014#define BXW4(isp, off, v) \ 1015 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1016 1017 1018static ISP_INLINE int 1019isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1020{ 1021 uint32_t val0, val1; 1022 int i = 0; 1023 1024 do { 1025 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1026 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1027 } while (val0 != val1 && ++i < 1000); 1028 if (val0 != val1) { 1029 return (1); 1030 } 1031 *rp = val0; 1032 return (0); 1033} 1034 1035static int 1036isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1037{ 1038 uint16_t isr, sema; 1039 1040 if (IS_2100(isp)) { 1041 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1042 return (0); 1043 } 1044 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1045 return (0); 1046 } 1047 } else { 1048 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1049 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1050 } 1051 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1052 isr &= INT_PENDING_MASK(isp); 1053 sema &= BIU_SEMA_LOCK; 1054 if (isr == 0 && sema == 0) { 1055 return (0); 1056 } 1057 *isrp = isr; 1058 if ((*semap = sema) != 0) { 1059 if (IS_2100(isp)) { 1060 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1061 return (0); 1062 } 1063 } else { 1064 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1065 } 1066 } 1067 return (1); 1068} 1069 1070static int 1071isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, 1072 uint16_t *semap, uint16_t *mbox0p) 1073{ 1074 uint32_t hccr; 1075 uint32_t r2hisr; 1076 1077 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1078 *isrp = 0; 1079 return (0); 1080 } 1081 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1082 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1083 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1084 *isrp = 0; 1085 return (0); 1086 } 1087 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1088 case ISPR2HST_ROM_MBX_OK: 1089 case ISPR2HST_ROM_MBX_FAIL: 1090 case ISPR2HST_MBX_OK: 1091 case ISPR2HST_MBX_FAIL: 1092 case ISPR2HST_ASYNC_EVENT: 1093 *isrp = r2hisr & 0xffff; 1094 *mbox0p = (r2hisr >> 16); 1095 *semap = 1; 1096 return (1); 1097 case ISPR2HST_RIO_16: 1098 *isrp = r2hisr & 0xffff; 1099 *mbox0p = ASYNC_RIO1; 1100 *semap = 1; 1101 return (1); 1102 case ISPR2HST_FPOST: 1103 *isrp = r2hisr & 0xffff; 1104 *mbox0p = ASYNC_CMD_CMPLT; 1105 *semap = 1; 1106 return (1); 1107 case ISPR2HST_FPOST_CTIO: 1108 *isrp = r2hisr & 0xffff; 1109 *mbox0p = ASYNC_CTIO_DONE; 1110 *semap = 1; 1111 return (1); 1112 case ISPR2HST_RSPQ_UPDATE: 1113 *isrp = r2hisr & 0xffff; 1114 *mbox0p = 0; 1115 *semap = 0; 1116 return (1); 1117 default: 1118 hccr = ISP_READ(isp, HCCR); 1119 if (hccr & HCCR_PAUSE) { 1120 ISP_WRITE(isp, HCCR, HCCR_RESET); 1121 isp_prt(isp, ISP_LOGERR, 1122 "RISC paused at interrupt (%x->%x)", hccr, 1123 ISP_READ(isp, HCCR)); 1124 ISP_WRITE(isp, BIU_ICR, 0); 1125 } else { 1126 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", 1127 r2hisr); 1128 } 1129 return (0); 1130 } 1131} 1132 1133static int 1134isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 1135 uint16_t *semap, uint16_t *mbox0p) 1136{ 1137 uint32_t r2hisr; 1138 1139 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1140 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1141 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1142 *isrp = 0; 1143 return (0); 1144 } 1145 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1146 case ISP2400R2HST_ROM_MBX_OK: 1147 case ISP2400R2HST_ROM_MBX_FAIL: 1148 case ISP2400R2HST_MBX_OK: 1149 case ISP2400R2HST_MBX_FAIL: 1150 case ISP2400R2HST_ASYNC_EVENT: 1151 *isrp = r2hisr & 0xffff; 1152 *mbox0p = (r2hisr >> 16); 1153 *semap = 1; 1154 return (1); 1155 case ISP2400R2HST_RSPQ_UPDATE: 1156 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1157 case ISP2400R2HST_ATIO_RQST_UPDATE: 1158 *isrp = r2hisr & 0xffff; 1159 *mbox0p = 0; 1160 *semap = 0; 1161 return (1); 1162 default: 1163 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1164 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1165 return (0); 1166 } 1167} 1168 1169static uint32_t 1170isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1171{ 1172 uint16_t rv; 1173 int oldconf = 0; 1174 1175 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1176 /* 1177 * We will assume that someone has paused the RISC processor. 1178 */ 1179 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1180 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1181 oldconf | BIU_PCI_CONF1_SXP); 1182 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1183 } 1184 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1185 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1186 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1187 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1188 } 1189 return (rv); 1190} 1191 1192static void 1193isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1194{ 1195 int oldconf = 0; 1196 1197 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1198 /* 1199 * We will assume that someone has paused the RISC processor. 1200 */ 1201 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1202 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1203 oldconf | BIU_PCI_CONF1_SXP); 1204 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1205 } 1206 BXW2(isp, IspVirt2Off(isp, regoff), val); 1207 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1208 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1209 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1210 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1211 } 1212 1213} 1214 1215static uint32_t 1216isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1217{ 1218 uint32_t rv, oc = 0; 1219 1220 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1221 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1222 uint32_t tc; 1223 /* 1224 * We will assume that someone has paused the RISC processor. 1225 */ 1226 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1227 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1228 if (regoff & SXP_BANK1_SELECT) 1229 tc |= BIU_PCI1080_CONF1_SXP1; 1230 else 1231 tc |= BIU_PCI1080_CONF1_SXP0; 1232 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1233 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1234 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1235 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1236 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1237 oc | BIU_PCI1080_CONF1_DMA); 1238 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1239 } 1240 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1241 if (oc) { 1242 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1243 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1244 } 1245 return (rv); 1246} 1247 1248static void 1249isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1250{ 1251 int oc = 0; 1252 1253 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1254 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1255 uint32_t tc; 1256 /* 1257 * We will assume that someone has paused the RISC processor. 1258 */ 1259 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1260 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1261 if (regoff & SXP_BANK1_SELECT) 1262 tc |= BIU_PCI1080_CONF1_SXP1; 1263 else 1264 tc |= BIU_PCI1080_CONF1_SXP0; 1265 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1266 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1267 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1268 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1269 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1270 oc | BIU_PCI1080_CONF1_DMA); 1271 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1272 } 1273 BXW2(isp, IspVirt2Off(isp, regoff), val); 1274 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1275 if (oc) { 1276 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1277 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1278 } 1279} 1280 1281static uint32_t 1282isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1283{ 1284 uint32_t rv; 1285 int block = regoff & _BLK_REG_MASK; 1286 1287 switch (block) { 1288 case BIU_BLOCK: 1289 break; 1290 case MBOX_BLOCK: 1291 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1292 case SXP_BLOCK: 1293 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1294 return (0xffffffff); 1295 case RISC_BLOCK: 1296 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1297 return (0xffffffff); 1298 case DMA_BLOCK: 1299 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1300 return (0xffffffff); 1301 default: 1302 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1303 return (0xffffffff); 1304 } 1305 1306 1307 switch (regoff) { 1308 case BIU2400_FLASH_ADDR: 1309 case BIU2400_FLASH_DATA: 1310 case BIU2400_ICR: 1311 case BIU2400_ISR: 1312 case BIU2400_CSR: 1313 case BIU2400_REQINP: 1314 case BIU2400_REQOUTP: 1315 case BIU2400_RSPINP: 1316 case BIU2400_RSPOUTP: 1317 case BIU2400_PRI_REQINP: 1318 case BIU2400_PRI_REQOUTP: 1319 case BIU2400_ATIO_RSPINP: 1320 case BIU2400_ATIO_RSPOUTP: 1321 case BIU2400_HCCR: 1322 case BIU2400_GPIOD: 1323 case BIU2400_GPIOE: 1324 case BIU2400_HSEMA: 1325 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1326 break; 1327 case BIU2400_R2HSTSLO: 1328 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1329 break; 1330 case BIU2400_R2HSTSHI: 1331 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1332 break; 1333 default: 1334 isp_prt(isp, ISP_LOGERR, 1335 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1336 rv = 0xffffffff; 1337 break; 1338 } 1339 return (rv); 1340} 1341 1342static void 1343isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1344{ 1345 int block = regoff & _BLK_REG_MASK; 1346 1347 switch (block) { 1348 case BIU_BLOCK: 1349 break; 1350 case MBOX_BLOCK: 1351 BXW2(isp, IspVirt2Off(isp, regoff), val); 1352 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1353 return; 1354 case SXP_BLOCK: 1355 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1356 return; 1357 case RISC_BLOCK: 1358 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1359 return; 1360 case DMA_BLOCK: 1361 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1362 return; 1363 default: 1364 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1365 regoff); 1366 break; 1367 } 1368 1369 switch (regoff) { 1370 case BIU2400_FLASH_ADDR: 1371 case BIU2400_FLASH_DATA: 1372 case BIU2400_ICR: 1373 case BIU2400_ISR: 1374 case BIU2400_CSR: 1375 case BIU2400_REQINP: 1376 case BIU2400_REQOUTP: 1377 case BIU2400_RSPINP: 1378 case BIU2400_RSPOUTP: 1379 case BIU2400_PRI_REQINP: 1380 case BIU2400_PRI_REQOUTP: 1381 case BIU2400_ATIO_RSPINP: 1382 case BIU2400_ATIO_RSPOUTP: 1383 case BIU2400_HCCR: 1384 case BIU2400_GPIOD: 1385 case BIU2400_GPIOE: 1386 case BIU2400_HSEMA: 1387 BXW4(isp, IspVirt2Off(isp, regoff), val); 1388 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4); 1389 break; 1390 default: 1391 isp_prt(isp, ISP_LOGERR, 1392 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1393 break; 1394 } 1395} 1396 1397 1398struct imush { 1399 ispsoftc_t *isp; 1400 caddr_t vbase; 1401 int chan; 1402 int error; 1403}; 1404 1405static void imc(void *, bus_dma_segment_t *, int, int); 1406static void imc1(void *, bus_dma_segment_t *, int, int); 1407 1408static void 1409imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1410{ 1411 struct imush *imushp = (struct imush *) arg; 1412 1413 if (error) { 1414 imushp->error = error; 1415 return; 1416 } 1417 if (nseg != 1) { 1418 imushp->error = EINVAL; 1419 return; 1420 } 1421 imushp->isp->isp_rquest = imushp->vbase; 1422 imushp->isp->isp_rquest_dma = segs->ds_addr; 1423 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1424 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1425 imushp->isp->isp_result_dma = segs->ds_addr; 1426 imushp->isp->isp_result = imushp->vbase; 1427 1428#ifdef ISP_TARGET_MODE 1429 if (IS_24XX(imushp->isp)) { 1430 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1431 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1432 imushp->isp->isp_atioq_dma = segs->ds_addr; 1433 imushp->isp->isp_atioq = imushp->vbase; 1434 } 1435#endif 1436} 1437 1438static void 1439imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1440{ 1441 struct imush *imushp = (struct imush *) arg; 1442 if (error) { 1443 imushp->error = error; 1444 return; 1445 } 1446 if (nseg != 1) { 1447 imushp->error = EINVAL; 1448 return; 1449 } 1450 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1451 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1452} 1453 1454static int 1455isp_pci_mbxdma(ispsoftc_t *isp) 1456{ 1457 caddr_t base; 1458 uint32_t len; 1459 int i, error, ns, cmap = 0; 1460 bus_size_t slim; /* segment size */ 1461 bus_addr_t llim; /* low limit of unavailable dma */ 1462 bus_addr_t hlim; /* high limit of unavailable dma */ 1463 struct imush im; 1464 1465 /* 1466 * Already been here? If so, leave... 1467 */ 1468 if (isp->isp_rquest) { 1469 return (0); 1470 } 1471 ISP_UNLOCK(isp); 1472 1473 if (isp->isp_maxcmds == 0) { 1474 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1475 ISP_LOCK(isp); 1476 return (1); 1477 } 1478 1479 hlim = BUS_SPACE_MAXADDR; 1480 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1481 if (sizeof (bus_size_t) > 4) { 1482 slim = (bus_size_t) (1ULL << 32); 1483 } else { 1484 slim = (bus_size_t) (1UL << 31); 1485 } 1486 llim = BUS_SPACE_MAXADDR; 1487 } else { 1488 llim = BUS_SPACE_MAXADDR_32BIT; 1489 slim = (1UL << 24); 1490 } 1491 1492 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1493 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1494 if (isp->isp_osinfo.pcmd_pool == NULL) { 1495 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1496 ISP_LOCK(isp); 1497 return (1); 1498 } 1499 1500 /* 1501 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1502 */ 1503#ifdef ISP_TARGET_MODE 1504 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1505 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1506 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1507 ISP_LOCK(isp); 1508 return (1); 1509 } 1510#endif 1511 1512 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1513 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1514 ISP_LOCK(isp); 1515 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1516 return (1); 1517 } 1518 1519 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1520 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1521 if (isp->isp_xflist == NULL) { 1522 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1523 ISP_LOCK(isp); 1524 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1525 return (1); 1526 } 1527 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1528 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1529 } 1530 isp->isp_xffree = isp->isp_xflist; 1531#ifdef ISP_TARGET_MODE 1532 len = sizeof (isp_hdl_t *) * isp->isp_maxcmds; 1533 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1534 if (isp->isp_tgtlist == NULL) { 1535 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1536 free(isp->isp_xflist, M_DEVBUF); 1537 ISP_LOCK(isp); 1538 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1539 return (1); 1540 } 1541 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1542 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1543 } 1544 isp->isp_tgtfree = isp->isp_tgtlist; 1545#endif 1546 1547 /* 1548 * Allocate and map the request and result queues (and ATIO queue 1549 * if we're a 2400 supporting target mode). 1550 */ 1551 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1552 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1553#ifdef ISP_TARGET_MODE 1554 if (IS_24XX(isp)) { 1555 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1556 } 1557#endif 1558 1559 ns = (len / PAGE_SIZE) + 1; 1560 1561 /* 1562 * Create a tag for the control spaces. We don't always need this 1563 * to be 32 bits, but we do this for simplicity and speed's sake. 1564 */ 1565 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1566 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1567 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1568 free(isp->isp_xflist, M_DEVBUF); 1569#ifdef ISP_TARGET_MODE 1570 free(isp->isp_tgtlist, M_DEVBUF); 1571#endif 1572 ISP_LOCK(isp); 1573 return (1); 1574 } 1575 1576 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT, &isp->isp_osinfo.cdmap) != 0) { 1577 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1578 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1579 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1580 free(isp->isp_xflist, M_DEVBUF); 1581#ifdef ISP_TARGET_MODE 1582 free(isp->isp_tgtlist, M_DEVBUF); 1583#endif 1584 ISP_LOCK(isp); 1585 return (1); 1586 } 1587 1588 im.isp = isp; 1589 im.chan = 0; 1590 im.vbase = base; 1591 im.error = 0; 1592 1593 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1594 if (im.error) { 1595 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1596 goto bad; 1597 } 1598 1599 if (IS_FC(isp)) { 1600 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1601 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1602 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1603 goto bad; 1604 } 1605 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT, &fc->tdmap) != 0) { 1606 bus_dma_tag_destroy(fc->tdmat); 1607 goto bad; 1608 } 1609 im.isp = isp; 1610 im.chan = cmap; 1611 im.vbase = base; 1612 im.error = 0; 1613 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1614 if (im.error) { 1615 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1616 bus_dma_tag_destroy(fc->tdmat); 1617 goto bad; 1618 } 1619 } 1620 } 1621 1622 for (i = 0; i < isp->isp_maxcmds; i++) { 1623 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1624 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1625 if (error) { 1626 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1627 while (--i >= 0) { 1628 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1629 } 1630 goto bad; 1631 } 1632 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1633 if (i == isp->isp_maxcmds-1) { 1634 pcmd->next = NULL; 1635 } else { 1636 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1637 } 1638 } 1639 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1640 ISP_LOCK(isp); 1641 return (0); 1642 1643bad: 1644 while (--cmap >= 0) { 1645 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1646 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1647 bus_dma_tag_destroy(fc->tdmat); 1648 } 1649 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1650 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1651 free(isp->isp_xflist, M_DEVBUF); 1652#ifdef ISP_TARGET_MODE 1653 free(isp->isp_tgtlist, M_DEVBUF); 1654#endif 1655 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1656 isp->isp_rquest = NULL; 1657 ISP_LOCK(isp); 1658 return (1); 1659} 1660 1661typedef struct { 1662 ispsoftc_t *isp; 1663 void *cmd_token; 1664 void *rq; /* original request */ 1665 int error; 1666 bus_size_t mapsize; 1667} mush_t; 1668 1669#define MUSHERR_NOQENTRIES -2 1670 1671#ifdef ISP_TARGET_MODE 1672static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1673static void tdma2(void *, bus_dma_segment_t *, int, int); 1674 1675static void 1676tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1677{ 1678 mush_t *mp; 1679 mp = (mush_t *)arg; 1680 mp->mapsize = mapsize; 1681 tdma2(arg, dm_segs, nseg, error); 1682} 1683 1684static void 1685tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1686{ 1687 mush_t *mp; 1688 ispsoftc_t *isp; 1689 struct ccb_scsiio *csio; 1690 isp_ddir_t ddir; 1691 ispreq_t *rq; 1692 1693 mp = (mush_t *) arg; 1694 if (error) { 1695 mp->error = error; 1696 return; 1697 } 1698 csio = mp->cmd_token; 1699 isp = mp->isp; 1700 rq = mp->rq; 1701 if (nseg) { 1702 if (sizeof (bus_addr_t) > 4) { 1703 if (nseg >= ISP_NSEG64_MAX) { 1704 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1705 mp->error = EFAULT; 1706 return; 1707 } 1708 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1709 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1710 } 1711 } else { 1712 if (nseg >= ISP_NSEG_MAX) { 1713 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1714 mp->error = EFAULT; 1715 return; 1716 } 1717 } 1718 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1719 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1720 ddir = ISP_TO_DEVICE; 1721 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1722 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1723 ddir = ISP_FROM_DEVICE; 1724 } else { 1725 ddir = ISP_NOXFR; 1726 } 1727 } else { 1728 dm_segs = NULL; 1729 nseg = 0; 1730 ddir = ISP_NOXFR; 1731 } 1732 1733 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1734 mp->error = MUSHERR_NOQENTRIES; 1735 } 1736} 1737#endif 1738 1739static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1740static void dma2(void *, bus_dma_segment_t *, int, int); 1741 1742static void 1743dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1744{ 1745 mush_t *mp; 1746 mp = (mush_t *)arg; 1747 mp->mapsize = mapsize; 1748 dma2(arg, dm_segs, nseg, error); 1749} 1750 1751static void 1752dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1753{ 1754 mush_t *mp; 1755 ispsoftc_t *isp; 1756 struct ccb_scsiio *csio; 1757 isp_ddir_t ddir; 1758 ispreq_t *rq; 1759 1760 mp = (mush_t *) arg; 1761 if (error) { 1762 mp->error = error; 1763 return; 1764 } 1765 csio = mp->cmd_token; 1766 isp = mp->isp; 1767 rq = mp->rq; 1768 if (nseg) { 1769 if (sizeof (bus_addr_t) > 4) { 1770 if (nseg >= ISP_NSEG64_MAX) { 1771 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1772 mp->error = EFAULT; 1773 return; 1774 } 1775 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1776 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1777 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1778 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1779 } 1780 } else { 1781 if (nseg >= ISP_NSEG_MAX) { 1782 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1783 mp->error = EFAULT; 1784 return; 1785 } 1786 } 1787 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1788 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1789 ddir = ISP_FROM_DEVICE; 1790 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1791 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1792 ddir = ISP_TO_DEVICE; 1793 } else { 1794 ddir = ISP_NOXFR; 1795 } 1796 } else { 1797 dm_segs = NULL; 1798 nseg = 0; 1799 ddir = ISP_NOXFR; 1800 } 1801 1802 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1803 mp->error = MUSHERR_NOQENTRIES; 1804 } 1805} 1806 1807static int 1808isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1809{ 1810 mush_t mush, *mp; 1811 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1812 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1813 1814 mp = &mush; 1815 mp->isp = isp; 1816 mp->cmd_token = csio; 1817 mp->rq = ff; 1818 mp->error = 0; 1819 mp->mapsize = 0; 1820 1821#ifdef ISP_TARGET_MODE 1822 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1823 eptr = tdma2; 1824 eptr2 = tdma2_2; 1825 } else 1826#endif 1827 { 1828 eptr = dma2; 1829 eptr2 = dma2_2; 1830 } 1831 1832 1833 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1834 (*eptr)(mp, NULL, 0, 0); 1835 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1836 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1837 int error; 1838 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1839#if 0 1840 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1841#endif 1842 1843 if (error == EINPROGRESS) { 1844 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1845 mp->error = EINVAL; 1846 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1847 } else if (error && mp->error == 0) { 1848#ifdef DIAGNOSTIC 1849 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1850#endif 1851 mp->error = error; 1852 } 1853 } else { 1854 /* Pointer to physical buffer */ 1855 struct bus_dma_segment seg; 1856 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1857 seg.ds_len = csio->dxfer_len; 1858 (*eptr)(mp, &seg, 1, 0); 1859 } 1860 } else { 1861 struct bus_dma_segment *segs; 1862 1863 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1864 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1865 mp->error = EINVAL; 1866 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1867 struct uio sguio; 1868 int error; 1869 1870 /* 1871 * We're taking advantage of the fact that 1872 * the pointer/length sizes and layout of the iovec 1873 * structure are the same as the bus_dma_segment 1874 * structure. This might be a little dangerous, 1875 * but only if they change the structures, which 1876 * seems unlikely. 1877 */ 1878 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1879 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1880 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1881 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1882 sguio.uio_iovcnt = csio->sglist_cnt; 1883 sguio.uio_resid = csio->dxfer_len; 1884 sguio.uio_segflg = UIO_SYSSPACE; 1885 1886 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1887 1888 if (error != 0 && mp->error == 0) { 1889 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1890 mp->error = error; 1891 } 1892 } else { 1893 /* Just use the segments provided */ 1894 segs = (struct bus_dma_segment *) csio->data_ptr; 1895 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1896 } 1897 } 1898 if (mp->error) { 1899 int retval = CMD_COMPLETE; 1900 if (mp->error == MUSHERR_NOQENTRIES) { 1901 retval = CMD_EAGAIN; 1902 } else if (mp->error == EFBIG) { 1903 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1904 } else if (mp->error == EINVAL) { 1905 XS_SETERR(csio, CAM_REQ_INVALID); 1906 } else { 1907 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1908 } 1909 return (retval); 1910 } 1911 return (CMD_QUEUED); 1912} 1913 1914static void 1915isp_pci_reset0(ispsoftc_t *isp) 1916{ 1917 ISP_DISABLE_INTS(isp); 1918} 1919 1920static void 1921isp_pci_reset1(ispsoftc_t *isp) 1922{ 1923 if (!IS_24XX(isp)) { 1924 /* Make sure the BIOS is disabled */ 1925 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1926 } 1927 /* and enable interrupts */ 1928 ISP_ENABLE_INTS(isp); 1929} 1930 1931static void 1932isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1933{ 1934 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1935 if (msg) 1936 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1937 else 1938 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1939 if (IS_SCSI(isp)) 1940 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1941 else 1942 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1943 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1944 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1945 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1946 1947 1948 if (IS_SCSI(isp)) { 1949 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1950 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1951 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1952 ISP_READ(isp, CDMA_FIFO_STS)); 1953 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1954 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1955 ISP_READ(isp, DDMA_FIFO_STS)); 1956 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1957 ISP_READ(isp, SXP_INTERRUPT), 1958 ISP_READ(isp, SXP_GROSS_ERR), 1959 ISP_READ(isp, SXP_PINS_CTRL)); 1960 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1961 } 1962 printf(" mbox regs: %x %x %x %x %x\n", 1963 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1964 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1965 ISP_READ(isp, OUTMAILBOX4)); 1966 printf(" PCI Status Command/Status=%x\n", 1967 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1968} 1969