scic_sds_port_registers.h revision 231134 
1231200Smm/*-
2231200Smm * This file is provided under a dual BSD/GPLv2 license.  When using or
3231200Smm * redistributing this file, you may do so under either license.
4231200Smm *
5231200Smm * GPL LICENSE SUMMARY
6231200Smm *
7231200Smm * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8231200Smm *
9231200Smm * This program is free software; you can redistribute it and/or modify
10231200Smm * it under the terms of version 2 of the GNU General Public License as
11231200Smm * published by the Free Software Foundation.
12231200Smm *
13231200Smm * This program is distributed in the hope that it will be useful, but
14231200Smm * WITHOUT ANY WARRANTY; without even the implied warranty of
15231200Smm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16231200Smm * General Public License for more details.
17231200Smm *
18231200Smm * You should have received a copy of the GNU General Public License
19231200Smm * along with this program; if not, write to the Free Software
20231200Smm * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21231200Smm * The full GNU General Public License is included in this distribution
22231200Smm * in the file called LICENSE.GPL.
23231200Smm *
24231200Smm * BSD LICENSE
25231200Smm *
26231200Smm * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27231200Smm * All rights reserved.
28231200Smm *
29231200Smm * Redistribution and use in source and binary forms, with or without
30231200Smm * modification, are permitted provided that the following conditions
31231200Smm * are met:
32231200Smm *
33231200Smm *   * Redistributions of source code must retain the above copyright
34231200Smm *     notice, this list of conditions and the following disclaimer.
35231200Smm *   * Redistributions in binary form must reproduce the above copyright
36231200Smm *     notice, this list of conditions and the following disclaimer in
37231200Smm *     the documentation and/or other materials provided with the
38231200Smm *     distribution.
39231200Smm *
40231200Smm * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41231200Smm * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42231200Smm * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43231200Smm * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44231200Smm * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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48231200Smm * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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50231200Smm * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51231200Smm *
52231200Smm * $FreeBSD$
53231200Smm */
54231200Smm#ifndef _SCIC_SDS_PORT_REGISTERS_H_
55231200Smm#define _SCIC_SDS_PORT_REGISTERS_H_
56231200Smm
57231200Smm/**
58231200Smm * @file
59231200Smm *
60231200Smm * @brief This file contains a set of macros that assist in reading the SCU
61231200Smm * hardware registers.
62231200Smm */
63231200Smm
64231200Smm#ifdef __cplusplus
65231200Smmextern "C" {
66231200Smm#endif // __cplusplus
67231200Smm
68231200Smm/**
69231200Smm * Macro to read the port task scheduler register associated with this port
70231200Smm * object
71231200Smm */
72231200Smm#define scu_port_task_scheduler_read(port, reg) \
73231200Smm   scu_register_read( \
74231200Smm      scic_sds_port_get_controller(port), \
75231200Smm      (port)->port_task_scheduler_registers->reg \
76231200Smm   )
77231200Smm
78231200Smm/**
79231200Smm * Macro to write the port task scheduler register associated with this
80231200Smm * port object
81231200Smm */
82231200Smm#define scu_port_task_scheduler_write(port, reg, value) \
83231200Smm   scu_register_write( \
84      scic_sds_port_get_controller(port), \
85      (port)->port_task_scheduler_registers->reg, \
86      (value) \
87   )
88
89#define scu_port_viit_register_write(port, reg, value) \
90   scu_register_write( \
91      scic_sds_port_get_controller(port), \
92      (port)->viit_registers->reg, \
93      (value) \
94   )
95
96//****************************************************************************
97//* Port Task Scheduler registers controlled by the port object
98//****************************************************************************
99
100/**
101 * Macro to read the port task scheduler control register
102 */
103#define SCU_PTSxCR_READ(port) \
104   scu_port_task_scheduler_read(port, control)
105
106/**
107 * Macro to write the port task scheduler control regsister
108 */
109#define SCU_PTSxCR_WRITE(port, value) \
110   scu_port_task_scheduler_write(port, control, value)
111
112//****************************************************************************
113//* Port PE Configuration registers
114//****************************************************************************
115
116/**
117 * Macro to write the PE Port Configuration Register
118 */
119#define SCU_PCSPExCR_WRITE(port, phy_id, value) \
120   scu_register_write( \
121      scic_sds_port_get_controller(port), \
122      (port)->port_pe_configuration_register[phy_id], \
123      (value) \
124   )
125
126/**
127 * Macro to read the PE Port Configuration Regsiter
128 */
129#define SCU_PCSPExCR_READ(port, phy_id) \
130   scu_register_read( \
131      scic_sds_port_get_controller(port), \
132      (port)->port_pe_configuration_register[phy_id] \
133   )
134
135#ifdef __cplusplus
136}
137#endif // __cplusplus
138
139#endif // _SCIC_SDS_PORT_REGISTERS_H_
140