1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/10.3/sys/dev/ieee488/upd7210.h 230134 2012-01-15 13:23:43Z uqs $ 28 * 29 * Locating an actual ��PD7210 data book has proven quite impossible for me. 30 * There are a fair number of newer chips which are supersets of the ��PD7210 31 * but they are particular eager to comprehensively mark what the extensions 32 * are and what is in the base set. Some even give the registers and their 33 * bits new names. 34 * 35 * The following information is based on a description of the ��PD7210 found 36 * in an old manual for a VME board which used the chip. 37 */ 38 39#ifndef _DEV_IEEE488_UPD7210_H_ 40#define _DEV_IEEE488_UPD7210_H_ 41#ifdef _KERNEL 42 43struct upd7210; 44struct ibfoo; 45 46/* upd7210 interface definitions for HW drivers */ 47 48typedef int upd7210_irq_t(struct upd7210 *, int); 49 50struct upd7210 { 51 struct resource *reg_res[8]; 52 struct resource *irq_clear_res; 53 u_int reg_offset[8]; 54 int dmachan; 55 int unit; 56 int use_fifo; 57 58 /* private stuff */ 59 struct mtx mutex; 60 uint8_t rreg[8]; 61 uint8_t wreg[8 + 8]; 62 63 upd7210_irq_t *irq; 64 65 int busy; 66 u_char *buf; 67 size_t bufsize; 68 u_int buf_wp; 69 u_int buf_rp; 70 struct cdev *cdev; 71 72 struct ibfoo *ibfoo; 73}; 74 75#ifdef UPD7210_HW_DRIVER 76void upd7210intr(void *); 77void upd7210attach(struct upd7210 *); 78void upd7210detach(struct upd7210 *); 79#endif 80 81#ifdef UPD7210_SW_DRIVER 82 83/* upd7210 hardware definitions. */ 84 85/* Write registers */ 86enum upd7210_wreg { 87 CDOR = 0, /* Command/Data Out Register */ 88 IMR1 = 1, /* Interrupt Mask Register 1 */ 89 IMR2 = 2, /* Interrupt Mask Register 2 */ 90 SPMR = 3, /* Serial Poll Mode Register */ 91 ADMR = 4, /* ADdress Mode Register */ 92 AUXMR = 5, /* AUXilliary Mode Register */ 93 ICR = 5, /* Internal Counter Register */ 94 PPR = 5, /* Parallel Poll Register */ 95 AUXRA = 5, /* AUXilliary Register A */ 96 AUXRB = 5, /* AUXilliary Register B */ 97 AUXRE = 5, /* AUXilliary Register E */ 98 ADR = 6, /* ADdress Register */ 99 EOSR = 7, /* End-Of-String Register */ 100}; 101 102/* Read registers */ 103enum upd7210_rreg { 104 DIR = 0, /* Data In Register */ 105 ISR1 = 1, /* Interrupt Status Register 1 */ 106 ISR2 = 2, /* Interrupt Status Register 2 */ 107 SPSR = 3, /* Serial Poll Status Register */ 108 ADSR = 4, /* ADdress Status Register */ 109 CPTR = 5, /* Command Pass Though Register */ 110 ADR0 = 6, /* ADdress Register 0 */ 111 ADR1 = 7, /* ADdress Register 1 */ 112}; 113 114/* Bits for ISR1 and IMR1 */ 115#define IXR1_DI (1 << 0) /* Data In */ 116#define IXR1_DO (1 << 1) /* Data Out */ 117#define IXR1_ERR (1 << 2) /* Error */ 118#define IXR1_DEC (1 << 3) /* Device Clear */ 119#define IXR1_ENDRX (1 << 4) /* End Received */ 120#define IXR1_DET (1 << 5) /* Device Execute Trigger */ 121#define IXR1_APT (1 << 6) /* Address Pass-Through */ 122#define IXR1_CPT (1 << 7) /* Command Pass-Through */ 123 124/* Bits for ISR2 and IMR2 */ 125#define IXR2_ADSC (1 << 0) /* Addressed Status Change */ 126#define IXR2_REMC (1 << 1) /* Remote Change */ 127#define IXR2_LOKC (1 << 2) /* Lockout Change */ 128#define IXR2_CO (1 << 3) /* Command Out */ 129#define ISR2_REM (1 << 4) /* Remove */ 130#define IMR2_DMAI (1 << 4) /* DMA In Enable */ 131#define ISR2_LOK (1 << 5) /* Lockout */ 132#define IMR2_DMAO (1 << 5) /* DMA Out Enable */ 133#define IXR2_SRQI (1 << 6) /* Service Request Input */ 134#define ISR2_INT (1 << 7) /* Interrupt */ 135 136#define SPSR_PEND (1 << 6) /* Pending */ 137#define SPMR_RSV (1 << 6) /* Request SerVice */ 138 139#define ADSR_MJMN (1 << 0) /* MaJor MiNor */ 140#define ADSR_TA (1 << 1) /* Talker Active */ 141#define ADSR_LA (1 << 2) /* Listener Active */ 142#define ADSR_TPAS (1 << 3) /* Talker Primary Addr. State */ 143#define ADSR_LPAS (1 << 4) /* Listener Primary Addr. State */ 144#define ADSR_SPMS (1 << 5) /* Serial Poll Mode State */ 145#define ADSR_ATN (1 << 6) /* Attention */ 146#define ADSR_CIC (1 << 7) /* Controller In Charge */ 147 148#define ADMR_ADM0 (1 << 0) /* Address Mode 0 */ 149#define ADMR_ADM1 (1 << 1) /* Address Mode 1 */ 150#define ADMR_TRM0 (1 << 4) /* Transmit/Receive Mode 0 */ 151#define ADMR_TRM1 (1 << 5) /* Transmit/Receive Mode 1 */ 152#define ADMR_LON (1 << 6) /* Listen Only */ 153#define ADMR_TON (1 << 7) /* Talk Only */ 154 155/* Constant part of overloaded write registers */ 156#define C_ICR 0x20 157#define C_PPR 0x60 158#define C_AUXA 0x80 159#define C_AUXB 0xa0 160#define C_AUXE 0xc0 161 162#define AUXMR_PON 0x00 /* Immediate Execute pon */ 163#define AUXMR_CPP 0x01 /* Clear Parallel Poll */ 164#define AUXMR_CRST 0x02 /* Chip Reset */ 165#define AUXMR_RFD 0x03 /* Finish Handshake */ 166#define AUXMR_TRIG 0x04 /* Trigger */ 167#define AUXMR_RTL 0x05 /* Return to local */ 168#define AUXMR_SEOI 0x06 /* Send EOI */ 169#define AUXMR_NVSA 0x07 /* Non-Valid Secondary cmd/addr */ 170 /* 0x08 undefined/unknown */ 171#define AUXMR_SPP 0x09 /* Set Parallel Poll */ 172 /* 0x0a undefined/unknown */ 173 /* 0x0b undefined/unknown */ 174 /* 0x0c undefined/unknown */ 175 /* 0x0d undefined/unknown */ 176 /* 0x0e undefined/unknown */ 177#define AUXMR_VSA 0x0f /* Valid Secondary cmd/addr */ 178#define AUXMR_GTS 0x10 /* Go to Standby */ 179#define AUXMR_TCA 0x11 /* Take Control Async (pulsed) */ 180#define AUXMR_TCS 0x12 /* Take Control Synchronously */ 181#define AUXMR_LISTEN 0x13 /* Listen */ 182#define AUXMR_DSC 0x14 /* Disable System Control */ 183 /* 0x15 undefined/unknown */ 184#define AUXMR_SIFC 0x16 /* Set IFC */ 185#define AUXMR_CREN 0x17 /* Clear REN */ 186 /* 0x18 undefined/unknown */ 187 /* 0x19 undefined/unknown */ 188#define AUXMR_TCSE 0x1a /* Take Control Sync on End */ 189#define AUXMR_LCM 0x1b /* Listen Continuously Mode */ 190#define AUXMR_LUNL 0x1c /* Local Unlisten */ 191#define AUXMR_EPP 0x1d /* Execute Parallel Poll */ 192#define AUXMR_CIFC 0x1e /* Clear IFC */ 193#define AUXMR_SREN 0x1f /* Set REN */ 194 195#define PPR_U (1 << 4) /* Unconfigure */ 196#define PPR_S (1 << 3) /* Status Polarity */ 197 198#define AUXA_HLDA (1 << 0) /* Holdoff on All */ 199#define AUXA_HLDE (1 << 1) /* Holdoff on END */ 200#define AUXA_REOS (1 << 2) /* End on EOS received */ 201#define AUXA_XEOS (1 << 3) /* Transmit END with EOS */ 202#define AUXA_BIN (1 << 4) /* Binary */ 203 204#define AUXB_CPTE (1 << 0) /* Cmd Pass Through Enable */ 205#define AUXB_SPEOI (1 << 1) /* Send Serial Poll EOI */ 206#define AUXB_TRI (1 << 2) /* Three-State Timing */ 207#define AUXB_INV (1 << 3) /* Invert */ 208#define AUXB_ISS (1 << 4) /* Individual Status Select */ 209 210#define AUXE_DHDT (1 << 0) /* DAC Holdoff on DTAS */ 211#define AUXE_DHDC (1 << 1) /* DAC Holdoff on DCAS */ 212 213#define ADR0_DL0 (1 << 5) /* Disable Listener 0 */ 214#define ADR0_DT0 (1 << 6) /* Disable Talker 0 */ 215 216#define ADR_DL (1 << 5) /* Disable Listener */ 217#define ADR_DT (1 << 6) /* Disable Talker */ 218#define ADR_ARS (1 << 7) /* Address Register Select */ 219 220#define ADR1_DL1 (1 << 5) /* Disable Listener 1 */ 221#define ADR1_DT1 (1 << 6) /* Disable Talker 1 */ 222#define ADR1_EOI (1 << 7) /* End or Identify */ 223 224/* Stuff from software drivers */ 225extern struct cdevsw gpib_ib_cdevsw; 226 227/* Stuff from upd7210.c */ 228void upd7210_print_isr(u_int isr1, u_int isr2); 229u_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg); 230void upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val); 231int upd7210_take_ctrl_async(struct upd7210 *u); 232int upd7210_goto_standby(struct upd7210 *u); 233 234#endif /* UPD7210_SW_DRIVER */ 235 236#endif /* _KERNEL */ 237#endif /* _DEV_IEEE488_UPD7210_H_ */ 238