1252867Sdelphij/* $Id: him.h,v 1.57 2011/02/21 06:03:21 zsf Exp $ */ 2252867Sdelphij/*- 3252867Sdelphij * Copyright (C) 2004-2005 HighPoint Technologies, Inc. 4252867Sdelphij * All rights reserved. 5252867Sdelphij * 6252867Sdelphij * Redistribution and use in source and binary forms, with or without 7252867Sdelphij * modification, are permitted provided that the following conditions 8252867Sdelphij * are met: 9252867Sdelphij * 1. Redistributions of source code must retain the above copyright 10252867Sdelphij * notice, this list of conditions and the following disclaimer. 11252867Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 12252867Sdelphij * notice, this list of conditions and the following disclaimer in the 13252867Sdelphij * documentation and/or other materials provided with the distribution. 14252867Sdelphij * 15252867Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16252867Sdelphij * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17252867Sdelphij * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18252867Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19252867Sdelphij * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20252867Sdelphij * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21252867Sdelphij * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22252867Sdelphij * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23252867Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24252867Sdelphij * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25252867Sdelphij * SUCH DAMAGE. 26252867Sdelphij * 27252867Sdelphij * $FreeBSD: releng/10.3/sys/dev/hptnr/him.h 284935 2015-06-29 18:34:30Z delphij $ 28252867Sdelphij */ 29252867Sdelphij#include <dev/hptnr/hptnr_config.h> 30252867Sdelphij#ifndef _HPT_HIM_H_ 31252867Sdelphij#define _HPT_HIM_H_ 32252867Sdelphij 33252867Sdelphij#define VERMAGIC_HIM 55 34252867Sdelphij 35252867Sdelphij#if defined(__cplusplus) 36252867Sdelphijextern "C" { 37252867Sdelphij#endif 38252867Sdelphij 39252867Sdelphij#include <dev/hptnr/list.h> 40252867Sdelphij 41252867Sdelphij#define SECTOR_TO_BYTE_SHIFT 9 42252867Sdelphij#define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT) 43252867Sdelphij#define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT) 44252867Sdelphij 45252867Sdelphijtypedef struct _PCI_ID 46252867Sdelphij{ 47252867Sdelphij HPT_U16 vid; 48252867Sdelphij HPT_U16 did; 49252867Sdelphij HPT_U32 subsys; 50252867Sdelphij HPT_U8 rev; 51252867Sdelphij HPT_U8 nbase; 52252867Sdelphij HPT_U16 reserve; 53252867Sdelphij} 54252867SdelphijPCI_ID; 55252867Sdelphij 56252867Sdelphijtypedef struct _PCI_ADDRESS 57252867Sdelphij{ 58252867Sdelphij HPT_U8 tree; 59252867Sdelphij HPT_U8 bus; 60252867Sdelphij HPT_U8 device; 61252867Sdelphij HPT_U8 function; 62252867Sdelphij} 63252867SdelphijPCI_ADDRESS; 64252867Sdelphij 65252867Sdelphijtypedef struct _HIM_ADAPTER_CONFIG 66252867Sdelphij{ 67252867Sdelphij PCI_ADDRESS pci_addr; 68252867Sdelphij PCI_ID pci_id; 69252867Sdelphij 70252867Sdelphij HPT_U8 max_devices; 71252867Sdelphij 72252867Sdelphij HPT_U8 bProbeInInitializing:1; 73252867Sdelphij 74252867Sdelphij HPT_U8 bSpinupOneDevEachTime:1; 75252867Sdelphij 76252867Sdelphij HPT_U8 bGlobalNcq:1; 77252867Sdelphij HPT_U8 bSGPIOPartSupport:1; 78252867Sdelphij 79252867Sdelphij HPT_U8 bNeedSASIdleTimer:1; 80252867Sdelphij HPT_U8 reserved:3; 81252867Sdelphij 82252867Sdelphij HPT_U8 bDevsPerBus; 83252867Sdelphij HPT_U8 first_on_slot; 84252867Sdelphij 85252867Sdelphij HPT_U8 bChipType; 86252867Sdelphij HPT_U8 bChipIntrNum; 87252867Sdelphij HPT_U8 bChipFlags; 88252867Sdelphij HPT_U8 bNumBuses; 89252867Sdelphij 90252867Sdelphij HPT_U8 szVendorID[36]; 91252867Sdelphij HPT_U8 szProductID[36]; 92252867Sdelphij HPT_U32 nvramSize; 93252867Sdelphij HPT_U64 nvramAddress; 94252867Sdelphij HPT_U8 slot_index; 95252867Sdelphij HPT_U8 maxWidth; 96252867Sdelphij HPT_U8 currentWidth; 97252867Sdelphij HPT_U8 maxSpeed; 98252867Sdelphij HPT_U8 currentSpeed; 99252867Sdelphij HPT_U8 reserved2[7]; 100252867Sdelphij} 101252867SdelphijHIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG; 102252867Sdelphij 103252867Sdelphijtypedef struct _HIM_CHANNEL_CONFIG 104252867Sdelphij{ 105252867Sdelphij HPT_U32 io_port; 106252867Sdelphij HPT_U32 ctl_port; 107252867Sdelphij} HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG; 108252867Sdelphij 109252867Sdelphijtypedef struct _HIM_DEVICE_FLAGS 110252867Sdelphij{ 111252867Sdelphij HPT_UINT df_atapi :1; 112252867Sdelphij HPT_UINT df_removable_drive :1; 113252867Sdelphij HPT_UINT df_on_line :1; 114252867Sdelphij HPT_UINT df_reduce_mode :1; 115252867Sdelphij HPT_UINT df_sata :1; 116252867Sdelphij HPT_UINT df_on_pm_port :1; 117252867Sdelphij HPT_UINT df_support_read_ahead :1; 118252867Sdelphij HPT_UINT df_read_ahead_enabled :1; 119252867Sdelphij HPT_UINT df_support_write_cache :1; 120252867Sdelphij HPT_UINT df_write_cache_enabled :1; 121252867Sdelphij HPT_UINT df_cdrom_device :1; 122252867Sdelphij HPT_UINT df_tape_device :1; 123252867Sdelphij HPT_UINT df_support_tcq :1; 124252867Sdelphij HPT_UINT df_tcq_enabled :1; 125252867Sdelphij HPT_UINT df_support_ncq :1; 126252867Sdelphij HPT_UINT df_ncq_enabled :1; 127252867Sdelphij HPT_UINT df_sas :1; 128252867Sdelphij HPT_UINT df_in_enclosure :1; 129252867Sdelphij HPT_UINT df_ssd :1; 130252867Sdelphij} DEVICE_FLAGS, *PDEVICE_FLAGS; 131252867Sdelphij 132252867Sdelphij#pragma pack(1) 133252867Sdelphijtypedef struct _IDENTIFY_DATA { 134252867Sdelphij HPT_U16 GeneralConfiguration; 135252867Sdelphij HPT_U16 NumberOfCylinders; 136252867Sdelphij HPT_U16 Reserved1; 137252867Sdelphij HPT_U16 NumberOfHeads; 138252867Sdelphij HPT_U16 UnformattedBytesPerTrack; 139252867Sdelphij HPT_U16 UnformattedBytesPerSector; 140252867Sdelphij HPT_U8 SasAddress[8]; 141252867Sdelphij HPT_U16 SerialNumber[10]; 142252867Sdelphij HPT_U16 BufferType; 143252867Sdelphij HPT_U16 BufferSectorSize; 144252867Sdelphij HPT_U16 NumberOfEccBytes; 145252867Sdelphij HPT_U16 FirmwareRevision[4]; 146252867Sdelphij HPT_U16 ModelNumber[20]; 147252867Sdelphij HPT_U8 MaximumBlockTransfer; 148252867Sdelphij HPT_U8 VendorUnique2; 149252867Sdelphij HPT_U16 DoubleWordIo; 150252867Sdelphij HPT_U16 Capabilities; 151252867Sdelphij HPT_U16 Reserved2; 152252867Sdelphij HPT_U8 VendorUnique3; 153252867Sdelphij HPT_U8 PioCycleTimingMode; 154252867Sdelphij HPT_U8 VendorUnique4; 155252867Sdelphij HPT_U8 DmaCycleTimingMode; 156252867Sdelphij HPT_U16 TranslationFieldsValid; 157252867Sdelphij HPT_U16 NumberOfCurrentCylinders; 158252867Sdelphij HPT_U16 NumberOfCurrentHeads; 159252867Sdelphij HPT_U16 CurrentSectorsPerTrack; 160252867Sdelphij HPT_U32 CurrentSectorCapacity; 161252867Sdelphij HPT_U16 CurrentMultiSectorSetting; 162252867Sdelphij HPT_U32 UserAddressableSectors; 163252867Sdelphij HPT_U8 SingleWordDMASupport; 164252867Sdelphij HPT_U8 SingleWordDMAActive; 165252867Sdelphij HPT_U8 MultiWordDMASupport; 166252867Sdelphij HPT_U8 MultiWordDMAActive; 167252867Sdelphij HPT_U8 AdvancedPIOModes; 168252867Sdelphij HPT_U8 Reserved4; 169252867Sdelphij HPT_U16 MinimumMWXferCycleTime; 170252867Sdelphij HPT_U16 RecommendedMWXferCycleTime; 171252867Sdelphij HPT_U16 MinimumPIOCycleTime; 172252867Sdelphij HPT_U16 MinimumPIOCycleTimeIORDY; 173252867Sdelphij HPT_U16 Reserved5[2]; 174252867Sdelphij HPT_U16 ReleaseTimeOverlapped; 175252867Sdelphij HPT_U16 ReleaseTimeServiceCommand; 176252867Sdelphij HPT_U16 MajorRevision; 177252867Sdelphij HPT_U16 MinorRevision; 178252867Sdelphij HPT_U16 MaxQueueDepth; 179252867Sdelphij HPT_U16 SataCapability; 180252867Sdelphij HPT_U16 Reserved6[9]; 181252867Sdelphij HPT_U16 CommandSupport; 182252867Sdelphij HPT_U16 CommandEnable; 183252867Sdelphij HPT_U16 UtralDmaMode; 184252867Sdelphij HPT_U16 Reserved7[11]; 185252867Sdelphij HPT_U32 Lba48BitLow; 186252867Sdelphij HPT_U32 Lba48BitHigh; 187252867Sdelphij HPT_U16 Reserved8[23]; 188252867Sdelphij HPT_U16 SpecialFunctionsEnabled; 189252867Sdelphij HPT_U16 Reserved9[128]; 190252867Sdelphij} 191252867Sdelphij#ifdef __GNUC__ 192252867Sdelphij__attribute__((packed)) 193252867Sdelphij#endif 194252867SdelphijIDENTIFY_DATA, *PIDENTIFY_DATA; 195252867Sdelphij#pragma pack() 196252867Sdelphij 197252867Sdelphijtypedef struct _HIM_DEVICE_CONFIG 198252867Sdelphij{ 199252867Sdelphij HPT_U64 capacity; 200281957Sdelphij HPT_U32 logical_sector_size; 201284935Sdelphij HPT_U8 logicalsectors_per_physicalsector; 202284935Sdelphij HPT_U16 lowest_aligned; 203284935Sdelphij 204252867Sdelphij DEVICE_FLAGS flags; 205252867Sdelphij 206252867Sdelphij HPT_U8 path_id; 207252867Sdelphij HPT_U8 target_id; 208252867Sdelphij HPT_U8 max_queue_depth; 209252867Sdelphij HPT_U8 spin_up_mode; 210252867Sdelphij 211252867Sdelphij HPT_U8 reserved; 212252867Sdelphij HPT_U8 transfer_mode; 213252867Sdelphij HPT_U8 bMaxShowMode; 214252867Sdelphij HPT_U8 bDeUsable_Mode; 215252867Sdelphij 216252867Sdelphij HPT_U16 max_sectors_per_cmd; 217252867Sdelphij 218252867Sdelphij PIDENTIFY_DATA pIdentifyData; 219252867Sdelphij 220252867Sdelphij 221252867Sdelphij HPT_U8 fixed_path_id; /*equals to phy id */ 222252867Sdelphij} 223252867SdelphijHIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG; 224252867Sdelphij 225252867Sdelphij 226252867Sdelphij#define _DIT_MODE 0 227252867Sdelphij#define _DIT_601 1 228252867Sdelphij#define _DIT_READ_AHEAD 2 229252867Sdelphij#define _DIT_WRITE_CACHE 3 230252867Sdelphij#define _DIT_TCQ 4 231252867Sdelphij#define _DIT_NCQ 5 232252867Sdelphij#define _DIT_BEEP_OFF 6 233252867Sdelphij#define _DIT_SPIN_UP_MODE 7 234252867Sdelphij#define _DIT_IDLE_STANDBY 8 235252867Sdelphij#define _DIT_IDENTIFY 9 236252867Sdelphij 237252867Sdelphij#define SPIN_UP_MODE_NOSUPPORT 0 238252867Sdelphij#define SPIN_UP_MODE_FULL 1 239252867Sdelphij#define SPIN_UP_MODE_STANDBY 2 240252867Sdelphij 241252867Sdelphijstruct tcq_control { 242252867Sdelphij HPT_U8 enable; 243252867Sdelphij HPT_U8 depth; 244252867Sdelphij}; 245252867Sdelphij 246252867Sdelphijstruct ncq_control { 247252867Sdelphij HPT_U8 enable; 248252867Sdelphij HPT_U8 depth; 249252867Sdelphij}; 250252867Sdelphij 251252867Sdelphijtypedef struct _HIM_ALTERABLE_DEV_INFO{ 252252867Sdelphij HPT_U8 type; 253252867Sdelphij union { 254252867Sdelphij HPT_U8 mode; 255252867Sdelphij HPT_U8 enable_read_ahead; 256252867Sdelphij HPT_U8 enable_read_cache; 257252867Sdelphij HPT_U8 enable_write_cache; 258252867Sdelphij struct tcq_control tcq; 259252867Sdelphij struct ncq_control ncq; 260252867Sdelphij void * adapter; 261252867Sdelphij HPT_U8 spin_up_mode; 262252867Sdelphij HPT_U8 idle_standby_timeout; 263252867Sdelphij HPT_U8 identify_indicator; 264252867Sdelphij }u; 265252867Sdelphij} HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO; 266252867Sdelphij 267252867Sdelphijstruct _COMMAND; 268252867Sdelphijstruct _IOCTL_ARG; 269252867Sdelphij 270252867Sdelphijtypedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index); 271252867Sdelphij 272252867Sdelphijtypedef struct _HIM { 273252867Sdelphij char *name; 274252867Sdelphij struct _HIM *next; 275252867Sdelphij HPT_UINT max_sg_descriptors; 276252867Sdelphij #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args; 277252867Sdelphij #include <dev/hptnr/himfuncs.h> 278252867Sdelphij} 279252867SdelphijHIM, *PHIM; 280252867Sdelphij 281252867Sdelphij 282252867Sdelphij#pragma pack(1) 283252867Sdelphij#ifdef SG_FLAG_EOT 284252867Sdelphij#error "don't use SG_FLAG_EOT with _SG.eot. clean the code!" 285252867Sdelphij#endif 286252867Sdelphij 287252867Sdelphijtypedef struct _SG { 288252867Sdelphij HPT_U32 size; 289252867Sdelphij HPT_UINT eot; 290252867Sdelphij union { 291252867Sdelphij HPT_U8 FAR * _logical; 292252867Sdelphij BUS_ADDRESS bus; 293252867Sdelphij } 294252867Sdelphij addr; 295252867Sdelphij} 296252867SdelphijSG, *PSG; 297252867Sdelphij#pragma pack() 298252867Sdelphij 299252867Sdelphijtypedef struct _AtaCommand 300252867Sdelphij{ 301252867Sdelphij HPT_U64 Lba; 302252867Sdelphij HPT_U16 nSectors; 303252867Sdelphij HPT_U16 pad; 304252867Sdelphij} AtaComm, *PAtaComm; 305252867Sdelphij 306252867Sdelphij#define ATA_CMD_NOP 0x0 307252867Sdelphij 308252867Sdelphij#define ATA_CMD_SET_FEATURES 0xef 309252867Sdelphij#define ATA_CMD_FLUSH 0xE7 310252867Sdelphij#define ATA_CMD_VERIFY 0x40 311252867Sdelphij#define ATA_CMD_STANDBY 0xe2 312252867Sdelphij#define ATA_CMD_READ_MULTI 0xC4 313252867Sdelphij#define ATA_CMD_READ_MULTI_EXT 0x29 314252867Sdelphij#define ATA_CMD_WRITE_MULTI 0xC5 315252867Sdelphij#define ATA_CMD_WRITE_MULTI_EXT 0x39 316252867Sdelphij#define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE 317252867Sdelphij 318252867Sdelphij#define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */ 319252867Sdelphij#define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */ 320252867Sdelphij#define ATA_CMD_READ_DMA_EXT 0x25 321252867Sdelphij#define ATA_CMD_READ_QUEUE_EXT 0x26 322252867Sdelphij#define ATA_CMD_READ_MAX_ADDR 0x27 323252867Sdelphij#define ATA_CMD_READ_EXT 0x24 324252867Sdelphij#define ATA_CMD_VERIFY_EXT 0x42 325252867Sdelphij#define ATA_CMD_WRITE_DMA_EXT 0x35 326252867Sdelphij#define ATA_CMD_WRITE_QUEUE_EXT 0x36 327252867Sdelphij#define ATA_CMD_WRITE_EXT 0x34 328252867Sdelphij 329252867Sdelphij#define ATA_SET_FEATURES_XFER 0x3 330252867Sdelphij#define ATA_SECTOR_SIZE 512 331252867Sdelphij 332252867Sdelphijtypedef struct _PassthroughCmd { 333252867Sdelphij HPT_U16 bFeaturesReg; 334252867Sdelphij HPT_U16 bSectorCountReg; 335252867Sdelphij HPT_U16 bLbaLowReg; 336252867Sdelphij HPT_U16 bLbaMidReg; 337252867Sdelphij HPT_U16 bLbaHighReg; 338252867Sdelphij HPT_U8 bDriveHeadReg; 339252867Sdelphij HPT_U8 bCommandReg; 340252867Sdelphij HPT_U16 nSectors; 341252867Sdelphij HPT_U8 *pDataBuffer; 342252867Sdelphij} 343252867SdelphijPassthroughCmd; 344252867Sdelphij 345252867Sdelphijtypedef struct _ScsiComm { 346252867Sdelphij HPT_U8 cdbLength; 347252867Sdelphij HPT_U8 senseLength; 348252867Sdelphij HPT_U8 scsiStatus; 349252867Sdelphij HPT_U8 reserve1; 350252867Sdelphij HPT_U32 dataLength; 351252867Sdelphij HPT_U8 cdb[16]; 352252867Sdelphij HPT_U8 *senseBuffer; 353252867Sdelphij} 354252867SdelphijScsiComm; 355252867Sdelphij 356252867Sdelphij 357252867Sdelphij#define CTRL_CMD_REBUILD 1 358252867Sdelphij#define CTRL_CMD_VERIFY 2 359252867Sdelphij#define CTRL_CMD_INIT 3 360252867Sdelphij 361252867Sdelphij 362252867Sdelphijtypedef struct _R5ControlCmd { 363252867Sdelphij HPT_U64 StripeLine; 364252867Sdelphij HPT_U16 Offset; 365252867Sdelphij HPT_U8 Command; 366252867Sdelphij HPT_U8 CmdTarget; 367252867Sdelphij} 368252867SdelphijR5ControlCmd, *PR5ControlCmd; 369252867Sdelphij 370252867Sdelphijtypedef struct _HPT_ADDRESS 371252867Sdelphij{ 372252867Sdelphij HPT_U8 * logical; 373252867Sdelphij BUS_ADDRESS bus; 374252867Sdelphij} 375252867SdelphijHPT_ADDRESS; 376252867Sdelphij 377252867Sdelphij 378252867Sdelphijtypedef struct ctl_pages { 379252867Sdelphij HPT_ADDRESS *pages; 380252867Sdelphij HPT_UINT page_size; 381252867Sdelphij HPT_UINT npages; 382252867Sdelphij HPT_UINT min_sg_descriptors; 383252867Sdelphij} CONTROL_PAGES, *PCONTROL_PAGES; 384252867Sdelphij 385252867Sdelphijtypedef struct _R1ControlCmd { 386252867Sdelphij HPT_U64 Lba; 387252867Sdelphij HPT_U16 nSectors; 388252867Sdelphij HPT_U8 Command; 389252867Sdelphij HPT_U8 CmdTarget; 390252867Sdelphij PCONTROL_PAGES ctl_pages; 391252867Sdelphij} 392252867SdelphijR1ControlCmd, *PR1ControlCmd; 393252867Sdelphij 394252867Sdelphijtypedef void (*TQ_PROC)(void *arg); 395252867Sdelphij 396252867Sdelphijstruct tq_item { 397252867Sdelphij TQ_PROC proc; 398252867Sdelphij void *arg; 399252867Sdelphij struct tq_item *next; 400252867Sdelphij}; 401252867Sdelphij 402252867Sdelphij#define INIT_TQ_ITEM(t, p, a) \ 403252867Sdelphij do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0) 404252867Sdelphij 405252867Sdelphijtypedef struct _COMMAND 406252867Sdelphij{ 407252867Sdelphij 408252867Sdelphij struct _VBUS * vbus; 409252867Sdelphij 410252867Sdelphij struct freelist *grplist; 411252867Sdelphij HPT_UINT grpcnt; 412252867Sdelphij 413252867Sdelphij 414252867Sdelphij struct list_head q_link; 415252867Sdelphij struct tq_item done_dpc; 416252867Sdelphij 417252867Sdelphij HPT_UINT extsize; 418252867Sdelphij void *ext; 419252867Sdelphij 420252867Sdelphij 421252867Sdelphij 422252867Sdelphij void *target; 423252867Sdelphij void *priv; 424252867Sdelphij HPT_UPTR priv2; 425252867Sdelphij 426252867Sdelphij int priority; 427252867Sdelphij struct lock_request *owned_lock; 428252867Sdelphij struct lock_request *lock_req; 429252867Sdelphij void (*dtor)(struct _COMMAND *, void *); 430252867Sdelphij void *dtor_arg; 431252867Sdelphij 432252867Sdelphij union{ 433252867Sdelphij AtaComm Ide; 434252867Sdelphij PassthroughCmd Passthrough; 435252867Sdelphij ScsiComm Scsi; 436252867Sdelphij R5ControlCmd R5Control; 437252867Sdelphij R1ControlCmd R1Control; 438252867Sdelphij } uCmd; 439252867Sdelphij 440252867Sdelphij HPT_U8 type; /* CMD_TYPE_* */ 441252867Sdelphij 442252867Sdelphij struct { 443252867Sdelphij HPT_U8 physical_sg: 1; 444252867Sdelphij HPT_U8 data_in: 1; 445252867Sdelphij HPT_U8 data_out: 1; 446252867Sdelphij HPT_U8 transform : 1; 447252867Sdelphij HPT_U8 hard_flush: 2; 448252867Sdelphij HPT_U8 from_cc: 1; 449252867Sdelphij HPT_U8 force_cc: 1; 450252867Sdelphij } flags; 451252867Sdelphij 452252867Sdelphij /* return status */ 453252867Sdelphij HPT_U8 Result; 454252867Sdelphij /* retry count */ 455252867Sdelphij HPT_U8 RetryCount; 456252867Sdelphij 457252867Sdelphij 458252867Sdelphij PSG psg; 459252867Sdelphij 460252867Sdelphij 461252867Sdelphij int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical); 462252867Sdelphij void (*done)(struct _COMMAND *cmd); 463252867Sdelphij} 464252867SdelphijCOMMAND, *PCOMMAND; 465252867Sdelphij 466252867Sdelphij/* command types */ 467252867Sdelphij#define CMD_TYPE_IO 0 468252867Sdelphij#define CMD_TYPE_CONTROL 1 469252867Sdelphij#define CMD_TYPE_ATAPI 2 470252867Sdelphij#define CMD_TYPE_SCSI CMD_TYPE_ATAPI 471252867Sdelphij#define CMD_TYPE_PASSTHROUGH 3 472252867Sdelphij#define CMD_TYPE_FLUSH 4 473252867Sdelphij#define CMD_TYPE_IO_INDIRECT 0x80 474252867Sdelphij 475252867Sdelphij/* flush command flags */ 476252867Sdelphij#define CF_HARD_FLUSH_CACHE 1 477252867Sdelphij#define CF_HARD_FLUSH_STANDBY 2 478252867Sdelphij 479252867Sdelphij/* command return values */ 480252867Sdelphij#define RETURN_PENDING 0 481252867Sdelphij#define RETURN_SUCCESS 1 482252867Sdelphij#define RETURN_BAD_DEVICE 2 483252867Sdelphij#define RETURN_BAD_PARAMETER 3 484252867Sdelphij#define RETURN_WRITE_NO_DRQ 4 485252867Sdelphij#define RETURN_DEVICE_BUSY 5 486252867Sdelphij#define RETURN_INVALID_REQUEST 6 487252867Sdelphij#define RETURN_SELECTION_TIMEOUT 7 488252867Sdelphij#define RETURN_IDE_ERROR 8 489252867Sdelphij#define RETURN_NEED_LOGICAL_SG 9 490252867Sdelphij#define RETURN_NEED_PHYSICAL_SG 10 491252867Sdelphij#define RETURN_RETRY 11 492252867Sdelphij#define RETURN_DATA_ERROR 12 493252867Sdelphij#define RETURN_BUS_RESET 13 494252867Sdelphij#define RETURN_BAD_TRANSFER_LENGTH 14 495252867Sdelphij#define RETURN_INSUFFICIENT_MEMORY 15 496252867Sdelphij#define RETURN_SECTOR_ERROR 16 497252867Sdelphij#define RETURN_NEED_SPINUP 17 498252867Sdelphij 499252867Sdelphij#if defined(__cplusplus) 500252867Sdelphij} 501252867Sdelphij#endif 502252867Sdelphij#endif 503