if_hmevar.h revision 91396
191396Stmm/*-
291396Stmm * Copyright (c) 1999 The NetBSD Foundation, Inc.
391396Stmm * All rights reserved.
491396Stmm *
591396Stmm * This code is derived from software contributed to The NetBSD Foundation
691396Stmm * by Paul Kranenburg.
791396Stmm *
891396Stmm * Redistribution and use in source and binary forms, with or without
991396Stmm * modification, are permitted provided that the following conditions
1091396Stmm * are met:
1191396Stmm * 1. Redistributions of source code must retain the above copyright
1291396Stmm *    notice, this list of conditions and the following disclaimer.
1391396Stmm * 2. Redistributions in binary form must reproduce the above copyright
1491396Stmm *    notice, this list of conditions and the following disclaimer in the
1591396Stmm *    documentation and/or other materials provided with the distribution.
1691396Stmm * 3. All advertising materials mentioning features or use of this software
1791396Stmm *    must display the following acknowledgement:
1891396Stmm *        This product includes software developed by the NetBSD
1991396Stmm *        Foundation, Inc. and its contributors.
2091396Stmm * 4. Neither the name of The NetBSD Foundation nor the names of its
2191396Stmm *    contributors may be used to endorse or promote products derived
2291396Stmm *    from this software without specific prior written permission.
2391396Stmm *
2491396Stmm * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
2591396Stmm * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
2691396Stmm * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
2791396Stmm * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
2891396Stmm * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2991396Stmm * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
3091396Stmm * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
3191396Stmm * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
3291396Stmm * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3391396Stmm * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
3491396Stmm * POSSIBILITY OF SUCH DAMAGE.
3591396Stmm *
3691396Stmm *	from: NetBSD: hmevar.h,v 1.5 2000/06/25 01:10:04 eeh Exp
3791396Stmm *
3891396Stmm * $FreeBSD: head/sys/dev/hme/if_hmevar.h 91396 2002-02-27 17:35:48Z tmm $
3991396Stmm */
4091396Stmm
4191396Stmm#include <sys/callout.h>
4291396Stmm
4391396Stmm/*
4491396Stmm * Number of receive and transmit descriptors. For each receive descriptor,
4591396Stmm * an mbuf cluster is allocated and set up to receive a packet, and a dma map
4691396Stmm * is created. Therefore, this number should not be too high to not waste
4791396Stmm * memory.
4891396Stmm * TX descriptors have less static cost (a dma map is allocated which could
4991396Stmm * cause bounce buffers to be reserved; other that that, the only required
5091396Stmm * memory is sizeof(struct hme_txdesc)).
5191396Stmm * Both must be a multiple of 16, and <= 128.
5291396Stmm */
5391396Stmm#define HME_NRXDESC	32
5491396Stmm#define HME_NTXDESC	64
5591396Stmm
5691396Stmm/* Maximum size of a mapped RX buffer. */
5791396Stmm#define	HME_BUFSZ	1600
5891396Stmm
5991396Stmm/*
6091396Stmm * RX DMA descriptor. The descriptors are preallocated; the dma map is
6191396Stmm * reused.
6291396Stmm */
6391396Stmmstruct hme_rxdesc {
6491396Stmm	struct mbuf	*hrx_m;
6591396Stmm	bus_dmamap_t	hrx_dmamap;
6691396Stmm	int		hrx_offs;
6791396Stmm	bus_size_t	hrx_len;
6891396Stmm};
6991396Stmm
7091396Stmmstruct hme_txdesc {
7191396Stmm	struct mbuf	*htx_m;
7291396Stmm	bus_dmamap_t	htx_dmamap;
7391396Stmm	int		htx_flags;
7491396Stmm};
7591396Stmm
7691396Stmm/* Value for htx_flags */
7791396Stmm#define	HTXF_MAPPED	1
7891396Stmm
7991396Stmmstruct hme_ring {
8091396Stmm	/* Ring Descriptors */
8191396Stmm	caddr_t		rb_membase;	/* Packet buffer: CPU address */
8291396Stmm	bus_addr_t	rb_dmabase;	/* Packet buffer: DMA address */
8391396Stmm	caddr_t		rb_txd;		/* Transmit descriptors */
8491396Stmm	bus_addr_t	rb_txddma;	/* DMA address of same */
8591396Stmm	caddr_t		rb_rxd;		/* Receive descriptors */
8691396Stmm	bus_addr_t	rb_rxddma;	/* DMA address of same */
8791396Stmm
8891396Stmm	/* Ring Descriptor state */
8991396Stmm	int	rb_tdhead, rb_tdtail;
9091396Stmm	int	rb_rdtail;
9191396Stmm	int	rb_td_nbusy;
9291396Stmm
9391396Stmm	/* Descriptors */
9491396Stmm	struct hme_rxdesc rb_rxdesc[HME_NRXDESC];
9591396Stmm	struct hme_txdesc rb_txdesc[HME_NTXDESC];
9691396Stmm
9791396Stmm	bus_dmamap_t	rb_spare_dmamap;
9891396Stmm};
9991396Stmm
10091396Stmmstruct hme_softc {
10191396Stmm	struct arpcom	sc_arpcom;
10291396Stmm	struct ifmedia	sc_ifmedia;
10391396Stmm	device_t	sc_dev;
10491396Stmm	device_t	sc_miibus;
10591396Stmm	struct mii_data	*sc_mii;	/* MII media control */
10691396Stmm	struct callout	sc_tick_ch;	/* tick callout */
10791396Stmm
10891396Stmm	/* The following bus handles are to be provided by the bus front-end */
10991396Stmm	bus_dma_tag_t	sc_pdmatag;	/* bus dma parent tag */
11091396Stmm	bus_dma_tag_t	sc_cdmatag;	/* control bus dma tag */
11191396Stmm	bus_dmamap_t	sc_cdmamap;	/* control bus dma handle */
11291396Stmm	bus_dma_tag_t	sc_rdmatag;	/* RX bus dma tag */
11391396Stmm	bus_dma_tag_t	sc_tdmatag;	/* RX bus dma tag */
11491396Stmm	bus_space_handle_t sc_sebh;	/* HME Global registers */
11591396Stmm	bus_space_handle_t sc_erxh;	/* HME ERX registers */
11691396Stmm	bus_space_handle_t sc_etxh;	/* HME ETX registers */
11791396Stmm	bus_space_handle_t sc_mach;	/* HME MAC registers */
11891396Stmm	bus_space_handle_t sc_mifh;	/* HME MIF registers */
11991396Stmm	bus_space_tag_t	sc_sebt;	/* HME Global registers */
12091396Stmm	bus_space_tag_t	sc_erxt;	/* HME ERX registers */
12191396Stmm	bus_space_tag_t	sc_etxt;	/* HME ETX registers */
12291396Stmm	bus_space_tag_t	sc_mact;	/* HME MAC registers */
12391396Stmm	bus_space_tag_t	sc_mift;	/* HME MIF registers */
12491396Stmm	bus_addr_t	sc_sebo;	/* HME Global registers */
12591396Stmm	bus_addr_t	sc_erxo;	/* HME ERX registers */
12691396Stmm	bus_addr_t	sc_etxo;	/* HME ETX registers */
12791396Stmm	bus_addr_t	sc_maco;	/* HME MAC registers */
12891396Stmm	bus_addr_t	sc_mifo;	/* HME MIF registers */
12991396Stmm	int		sc_burst;	/* DVMA burst size in effect */
13091396Stmm	int		sc_phys[2];	/* MII instance -> PHY map */
13191396Stmm
13291396Stmm	int		sc_pci;		/* XXXXX -- PCI buses are LE. */
13391396Stmm
13491396Stmm	/* Ring descriptor */
13591396Stmm	struct hme_ring		sc_rb;
13691396Stmm
13791396Stmm	int			sc_debug;
13891396Stmm
13991396Stmm	/* Special hardware hooks */
14091396Stmm	void	(*sc_hwreset)(struct hme_softc *);
14191396Stmm	void	(*sc_hwinit)(struct hme_softc *);
14291396Stmm};
14391396Stmm
14491396Stmmextern devclass_t hme_devclass;
14591396Stmm
14691396Stmmint	hme_config(struct hme_softc *);
14791396Stmmvoid	hme_intr(void *);
14891396Stmm
14991396Stmm/* MII methods & callbacks */
15091396Stmmint	hme_mii_readreg(device_t, int, int);
15191396Stmmint	hme_mii_writereg(device_t, int, int, int);
15291396Stmmvoid	hme_mii_statchg(device_t);
153