191396Stmm/*- 291396Stmm * Copyright (c) 1999 The NetBSD Foundation, Inc. 391396Stmm * All rights reserved. 491396Stmm * 591396Stmm * This code is derived from software contributed to The NetBSD Foundation 691396Stmm * by Paul Kranenburg. 791396Stmm * 891396Stmm * Redistribution and use in source and binary forms, with or without 991396Stmm * modification, are permitted provided that the following conditions 1091396Stmm * are met: 1191396Stmm * 1. Redistributions of source code must retain the above copyright 1291396Stmm * notice, this list of conditions and the following disclaimer. 1391396Stmm * 2. Redistributions in binary form must reproduce the above copyright 1491396Stmm * notice, this list of conditions and the following disclaimer in the 1591396Stmm * documentation and/or other materials provided with the distribution. 1691396Stmm * 1791396Stmm * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 1891396Stmm * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 1991396Stmm * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2091396Stmm * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2191396Stmm * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2291396Stmm * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2391396Stmm * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2491396Stmm * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2591396Stmm * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2691396Stmm * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2791396Stmm * POSSIBILITY OF SUCH DAMAGE. 2891396Stmm * 29129570Smarius * from: NetBSD: hmereg.h,v 1.16 2003/11/02 11:07:45 wiz Exp 3091396Stmm * 3191396Stmm * $FreeBSD: releng/10.3/sys/dev/hme/if_hmereg.h 220940 2011-04-22 09:39:05Z marius $ 3291396Stmm */ 3391396Stmm 3491396Stmm/* 3591396Stmm * HME Shared Ethernet Block register offsets 3691396Stmm */ 3791396Stmm#define HME_SEBI_RESET (0*4) 3891396Stmm#define HME_SEBI_CFG (1*4) 3991396Stmm#define HME_SEBI_STAT (64*4) 4091396Stmm#define HME_SEBI_IMASK (65*4) 4191396Stmm 4291396Stmm/* HME SEB bits. */ 4391396Stmm#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */ 4491396Stmm#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */ 4591396Stmm 4691396Stmm#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */ 4791396Stmm#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */ 4891396Stmm#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */ 4991396Stmm#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */ 50133149Syongari#define HME_SEB_CFG_64BIT 0x00000004 /* extended transfer mode */ 51133149Syongari#define HME_SEB_CFG_PARITY 0x00000008 /* parity check for DVMA/PIO */ 5291396Stmm 5391396Stmm#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */ 5491396Stmm#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */ 5591396Stmm#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */ 5691396Stmm#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */ 5791396Stmm#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */ 5891396Stmm#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ 5991396Stmm#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */ 6091396Stmm#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */ 6191396Stmm#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */ 6291396Stmm#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ 6391396Stmm#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ 6491396Stmm#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */ 6591396Stmm#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */ 6691396Stmm#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */ 6791396Stmm#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */ 6891396Stmm#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */ 6991396Stmm#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */ 7091396Stmm#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */ 71129570Smarius#define HME_SEB_STAT_RXERR 0x00040000 /* rx DMA error */ 72129570Smarius#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx DMA */ 73129570Smarius#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx DMA */ 74129570Smarius#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx DMA */ 7591396Stmm#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */ 7691396Stmm#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */ 7791396Stmm#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */ 7891396Stmm#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */ 79129570Smarius#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx DMA */ 80129570Smarius#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx DMA */ 81129570Smarius#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx DMA */ 82220940Smarius#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error during tx DMA */ 8391396Stmm#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */ 8491396Stmm#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */ 8591396Stmm#define HME_SEB_STAT_BITS "\177\020" \ 8691396Stmm "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \ 8791396Stmm "b\3CCNTEXP\0b\4LCNTEXP\0b\5RFIFOVF\0" \ 8891396Stmm "b\6CVCNTEXP\0b\7STSTERR\0b\10SENTFRAME\0" \ 8991396Stmm "b\11TFIFO_UND\0b\12MAXPKTERR\0b\13NCNTEXP\0" \ 9091396Stmm "b\14ECNTEXP\0b\15LCCNTEXP\0b\16FCNTEXP\0" \ 9191396Stmm "b\17DTIMEXP\0b\20RXTOHOST\0b\21NORXD\0" \ 9291396Stmm "b\22RXERR\0b\23RXLATERR\0b\24RXPERR\0" \ 9391396Stmm "b\25RXTERR\0b\26EOPERR\0b\27MIFIRQ\0" \ 9491396Stmm "b\30HOSTTOTX\0b\31TXALL\0b\32XTEACK\0" \ 9591396Stmm "b\33TXLERR\0b\34TXPERR\0b\35TXTERR\0" \ 9691396Stmm "b\36SLVERR\0b\37SLVPERR\0\0" 9791396Stmm 9891396Stmm#define HME_SEB_STAT_ALL_ERRORS \ 9991396Stmm (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 10091396Stmm HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 10191396Stmm HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ 10291396Stmm HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ 10397869Stmm HME_SEB_STAT_MAXPKTERR| HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR |\ 10497869Stmm HME_SEB_STAT_RFIFOVF) 10591396Stmm 10691396Stmm#define HME_SEB_STAT_VLAN_ERRORS \ 10791396Stmm (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 10891396Stmm HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 10991396Stmm HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ 11091396Stmm HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ 11197869Stmm HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_RFIFOVF) 11291396Stmm 113151639Syongari#define HME_SEB_STAT_FATAL_ERRORS \ 114151639Syongari (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 115151639Syongari HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 116151639Syongari HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR | HME_SEB_STAT_RXLATERR |\ 117151639Syongari HME_SEB_STAT_RXERR) 118151639Syongari 11991396Stmm/* 12091396Stmm * HME Transmitter register offsets 12191396Stmm */ 12291396Stmm#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */ 12391396Stmm#define HME_ETXI_CFG (1*4) 12491396Stmm#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */ 12591396Stmm#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */ 12691396Stmm#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */ 12791396Stmm#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */ 12891396Stmm#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */ 12991396Stmm#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */ 13091396Stmm#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */ 13191396Stmm#define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */ 13291396Stmm#define HME_ETXI_STATEMACHINE (10*4) /* State machine */ 13391396Stmm#define HME_ETXI_RSIZE (11*4) /* Ring size */ 13491396Stmm#define HME_ETXI_BPTR (12*4) /* Buffer pointer */ 13591396Stmm 13691396Stmm 13791396Stmm/* TXI_PENDING bits */ 13891396Stmm#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */ 13991396Stmm 14091396Stmm/* TXI_CFG bits */ 141129570Smarius#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX DMA */ 14291396Stmm#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */ 14391396Stmm#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */ 14491396Stmm#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */ 14591396Stmm 14691396Stmm 14791396Stmm/* 14891396Stmm * HME Receiver register offsets 14991396Stmm */ 15091396Stmm#define HME_ERXI_CFG (0*4) 15191396Stmm#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */ 15291396Stmm#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */ 15391396Stmm#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */ 15491396Stmm#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */ 15591396Stmm#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */ 156133149Syongari#define HME_ERXI_FIFO_PKTCNT (6*4) /* FIFO packet counter */ 15791396Stmm#define HME_ERXI_STATEMACHINE (7*4) /* State machine */ 15891396Stmm 15991396Stmm/* RXI_CFG bits */ 160129570Smarius#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX DMA */ 16191396Stmm#define HME_ERX_CFG_FBO_MASK 0x00000038 /* RX first byte offset */ 16291396Stmm#define HME_ERX_CFG_FBO_SHIFT 0x00000003 16391396Stmm#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */ 16491396Stmm#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */ 16591396Stmm#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */ 16691396Stmm#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */ 16791396Stmm#define HME_ERX_CFG_RINGSIZEMSK 0x00000600 /* Descriptor ring size: 256 */ 168133149Syongari#define HME_ERX_CFG_CSUMSTART_MASK 0x007f0000 /* cksum offset mask */ 169133149Syongari#define HME_ERX_CFG_CSUMSTART_SHIFT 16 17091396Stmm 17191396Stmm/* 17291396Stmm * HME MAC-core register offsets 17391396Stmm */ 17491396Stmm#define HME_MACI_XIF (0*4) 17591396Stmm#define HME_MACI_TXSWRST (130*4) /* TX reset */ 17691396Stmm#define HME_MACI_TXCFG (131*4) /* TX config */ 17791396Stmm#define HME_MACI_JSIZE (139*4) /* TX jam size */ 17891396Stmm#define HME_MACI_TXSIZE (140*4) /* TX max size */ 17991396Stmm#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */ 18091396Stmm#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */ 18191396Stmm#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */ 18291396Stmm#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */ 18391396Stmm#define HME_MACI_RANDSEED (148*4) /* */ 18491396Stmm#define HME_MACI_RXSWRST (194*4) /* RX reset */ 18591396Stmm#define HME_MACI_RXCFG (195*4) /* RX config */ 18691396Stmm#define HME_MACI_RXSIZE (196*4) /* RX max size */ 18791396Stmm#define HME_MACI_MACADDR2 (198*4) /* MAC address */ 18891396Stmm#define HME_MACI_MACADDR1 (199*4) 18991396Stmm#define HME_MACI_MACADDR0 (200*4) 19091396Stmm#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */ 19191396Stmm#define HME_MACI_HASHTAB2 (209*4) 19291396Stmm#define HME_MACI_HASHTAB1 (210*4) 19391396Stmm#define HME_MACI_HASHTAB0 (211*4) 19491396Stmm#define HME_MACI_AFILTER2 (212*4) /* Address filter */ 19591396Stmm#define HME_MACI_AFILTER1 (213*4) 19691396Stmm#define HME_MACI_AFILTER0 (214*4) 19791396Stmm#define HME_MACI_AFILTER_MASK (215*4) 19891396Stmm 19991396Stmm/* XIF config register. */ 20091396Stmm#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */ 20191396Stmm#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */ 20291396Stmm#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */ 20391396Stmm#define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */ 20491396Stmm#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */ 20591396Stmm#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */ 20691396Stmm#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */ 20791396Stmm#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */ 20891396Stmm 20991396Stmm/* Transmit config register. */ 21091396Stmm#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */ 21191396Stmm#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */ 21291396Stmm#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */ 21391396Stmm#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */ 21491396Stmm#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */ 21591396Stmm#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */ 21691396Stmm#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */ 21791396Stmm 21891396Stmm/* Receive config register. */ 21991396Stmm#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */ 22091396Stmm#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */ 221129570Smarius#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */ 22291396Stmm#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */ 22391396Stmm#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */ 22491396Stmm#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */ 22591396Stmm#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */ 22691396Stmm#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */ 22791396Stmm#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */ 22891396Stmm 22991396Stmm/* 23091396Stmm * HME MIF register offsets 23191396Stmm */ 23291396Stmm#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */ 23391396Stmm#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */ 23491396Stmm#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */ 23591396Stmm#define HME_MIFI_FO (3*4) /* frame output */ 23691396Stmm#define HME_MIFI_CFG (4*4) /* */ 23791396Stmm#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */ 23891396Stmm#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */ 23991396Stmm#define HME_MIFI_SM (7*4) /* State machine (ro) */ 24091396Stmm 24191396Stmm/* MIF Configuration register */ 24291396Stmm#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */ 24391396Stmm#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */ 24491396Stmm#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */ 245129570Smarius#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register address */ 24691396Stmm#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */ 24791396Stmm#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */ 248129570Smarius#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy address */ 24991396Stmm 25091396Stmm/* MIF Frame/Output register */ 25191396Stmm#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */ 25291396Stmm#define HME_MIF_FO_ST_SHIFT 30 /* */ 25391396Stmm#define HME_MIF_FO_OPC 0x30000000 /* Opcode */ 25491396Stmm#define HME_MIF_FO_OPC_SHIFT 28 /* */ 25591396Stmm#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */ 25691396Stmm#define HME_MIF_FO_PHYAD_SHIFT 23 /* */ 25791396Stmm#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */ 25891396Stmm#define HME_MIF_FO_REGAD_SHIFT 18 /* */ 25991396Stmm#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */ 26091396Stmm#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */ 26191396Stmm#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */ 26291396Stmm 26391396Stmm/* Wired HME PHY addresses */ 26491396Stmm#define HME_PHYAD_INTERNAL 1 26591396Stmm#define HME_PHYAD_EXTERNAL 0 26691396Stmm 26791396Stmm/* 26891396Stmm * Buffer Descriptors. 26991396Stmm */ 27091396Stmm#define HME_XD_SIZE 8 27191396Stmm#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0) 27291396Stmm#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4) 27391396Stmm#define HME_XD_GETFLAGS(p, b, i) \ 27491396Stmm ((p) ? le32toh(*((u_int32_t *)HME_XD_FLAGS(b,i))) : \ 27591396Stmm (*((u_int32_t *)HME_XD_FLAGS(b,i)))) 27691396Stmm#define HME_XD_SETFLAGS(p, b, i, f) do { \ 277129570Smarius *((u_int32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32((f)) : (f)); \ 278129570Smarius} while(/* CONSTCOND */ 0) 27991396Stmm#define HME_XD_SETADDR(p, b, i, a) do { \ 280129570Smarius *((u_int32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32((a)) : (a)); \ 281129570Smarius} while(/* CONSTCOND */ 0) 28291396Stmm 28391396Stmm/* Descriptor flag values */ 28491396Stmm#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */ 28591396Stmm#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */ 28691396Stmm#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */ 28791396Stmm#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */ 28891396Stmm#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */ 28991396Stmm#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */ 29091396Stmm#define HME_XD_RXLENSHIFT 16 29191396Stmm#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */ 292133149Syongari#define HME_XD_TXCKSUM_SSHIFT 14 293133149Syongari#define HME_XD_TXCKSUM_OSHIFT 20 29491396Stmm#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */ 29591396Stmm 29691396Stmm/* Macros to encode/decode the receive buffer size from the flags field */ 29791396Stmm#define HME_XD_ENCODE_RSIZE(sz) \ 29891396Stmm (((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK) 29991396Stmm#define HME_XD_DECODE_RSIZE(flags) \ 30091396Stmm (((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT) 30191396Stmm 30291396Stmm/* Provide encode/decode macros for the transmit buffers for symmetry */ 30391396Stmm#define HME_XD_ENCODE_TSIZE(sz) \ 30491396Stmm (((sz) << 0) & HME_XD_TXLENMSK) 30591396Stmm#define HME_XD_DECODE_TSIZE(flags) \ 30691396Stmm (((flags) & HME_XD_TXLENMSK) >> 0) 30791396Stmm 308108834Stmm#define HME_MINRXALIGN 0x10 309108834Stmm#define HME_RXOFFS 2 310