if_gemvar.h revision 91398
1/* 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * from: NetBSD: gemvar.h,v 1.5 2001/10/18 15:19:22 thorpej Exp 27 * 28 * $FreeBSD: head/sys/dev/gem/if_gemvar.h 91398 2002-02-27 17:41:06Z tmm $ 29 */ 30 31#ifndef _IF_GEMVAR_H 32#define _IF_GEMVAR_H 33 34 35#include <sys/queue.h> 36#include <sys/callout.h> 37 38/* 39 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 40 */ 41 42/* 43 * Transmit descriptor list size. This is arbitrary, but allocate 44 * enough descriptors for 64 pending transmissions and 16 segments 45 * per packet. 46 */ 47#define GEM_NTXSEGS 16 48 49#define GEM_TXQUEUELEN 64 50#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 51#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 52#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 53 54/* 55 * Receive descriptor list size. We have one Rx buffer per incoming 56 * packet, so this logic is a little simpler. 57 */ 58#define GEM_NRXDESC 128 59#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 60#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 61 62/* 63 * Control structures are DMA'd to the GEM chip. We allocate them in 64 * a single clump that maps to a single DMA segment to make several things 65 * easier. 66 */ 67struct gem_control_data { 68 /* 69 * The transmit descriptors. 70 */ 71 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 72 73 /* 74 * The receive descriptors. 75 */ 76 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 77}; 78 79#define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 80#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 81#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 82 83/* 84 * Software state for transmit job mbufs (may be elements of mbuf chains). 85 */ 86struct gem_txsoft { 87 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 88 bus_dmamap_t txs_dmamap; /* our DMA map */ 89 int txs_firstdesc; /* first descriptor in packet */ 90 int txs_lastdesc; /* last descriptor in packet */ 91 int txs_ndescs; /* number of descriptors */ 92 STAILQ_ENTRY(gem_txsoft) txs_q; 93}; 94 95STAILQ_HEAD(gem_txsq, gem_txsoft); 96 97/* Argument structure for busdma callback */ 98struct gem_txdma { 99 struct gem_softc *txd_sc; 100 int txd_nexttx; 101 int txd_lasttx; 102 int txd_nsegs; 103 int txd_flags; 104#define GTXD_FIRST 1 105#define GTXD_LAST 2 106 int txd_error; 107}; 108 109/* Transmit job descriptor */ 110struct gem_txjob { 111 int txj_nexttx; 112 int txj_lasttx; 113 int txj_nsegs; 114 STAILQ_HEAD(, gem_txsoft) txj_txsq; 115}; 116 117/* 118 * Software state for receive jobs. 119 */ 120struct gem_rxsoft { 121 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 122 bus_dmamap_t rxs_dmamap; /* our DMA map */ 123 bus_addr_t rxs_paddr; /* physical address of the segment */ 124}; 125 126/* 127 * Software state per device. 128 */ 129struct gem_softc { 130 struct arpcom sc_arpcom; /* arp common data */ 131 device_t sc_miibus; 132 struct mii_data *sc_mii; /* MII media control */ 133 device_t sc_dev; /* generic device information */ 134 struct callout sc_tick_ch; /* tick callout */ 135 136 /* The following bus handles are to be provided by the bus front-end */ 137 bus_space_tag_t sc_bustag; /* bus tag */ 138 bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */ 139 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 140 bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */ 141 bus_dmamap_t sc_dmamap; /* bus dma handle */ 142 bus_space_handle_t sc_h; /* bus space handle for all regs */ 143 144 int sc_phys[2]; /* MII instance -> PHY map */ 145 146 int sc_mif_config; /* Selected MII reg setting */ 147 148 int sc_pci; /* XXXXX -- PCI buses are LE. */ 149 150 /* 151 * Ring buffer DMA stuff. 152 */ 153 bus_dma_segment_t sc_cdseg; /* control data memory */ 154 int sc_cdnseg; /* number of segments */ 155 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 156 bus_addr_t sc_cddma; 157 158 /* 159 * Software state for transmit and receive descriptors. 160 */ 161 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 162 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 163 164 /* 165 * Control data structures. 166 */ 167 struct gem_control_data *sc_control_data; 168#define sc_txdescs sc_control_data->gcd_txdescs 169#define sc_rxdescs sc_control_data->gcd_rxdescs 170 171 int sc_txfree; /* number of free Tx descriptors */ 172 int sc_txnext; /* next ready Tx descriptor */ 173 174 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 175 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 176 177 int sc_rxptr; /* next ready RX descriptor/descsoft */ 178 179 /* ========== */ 180 int sc_inited; 181 int sc_debug; 182 int sc_flags; 183 184 /* Special hardware hooks */ 185 void (*sc_hwreset) __P((struct gem_softc *)); 186 void (*sc_hwinit) __P((struct gem_softc *)); 187}; 188 189#define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v)) 190#define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v)) 191 192#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 193#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 194 195#define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF) 196 197#define GEM_CDTXSYNC(sc, x, n, ops) \ 198 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops)); \ 199 200#define GEM_CDRXSYNC(sc, x, ops) \ 201 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops)) 202 203#define GEM_CDSPSYNC(sc, ops) \ 204 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, (ops)) 205 206#define GEM_INIT_RXDESC(sc, x) \ 207do { \ 208 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 209 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 210 struct mbuf *__m = __rxs->rxs_mbuf; \ 211 \ 212 __m->m_data = __m->m_ext.ext_buf; \ 213 __rxd->gd_addr = \ 214 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \ 215 __rxd->gd_flags = \ 216 GEM_DMA_WRITE((sc), \ 217 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 218 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 219 GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 220} while (0) 221 222#ifdef _KERNEL 223extern devclass_t gem_devclass; 224 225int gem_attach __P((struct gem_softc *)); 226int gem_detach __P((struct gem_softc *)); 227void gem_intr __P((void *)); 228 229int gem_mediachange __P((struct ifnet *)); 230void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 231 232void gem_reset __P((struct gem_softc *)); 233 234/* MII methods & callbacks */ 235int gem_mii_readreg __P((device_t, int, int)); 236int gem_mii_writereg __P((device_t, int, int, int)); 237void gem_mii_statchg __P((device_t)); 238 239#endif /* _KERNEL */ 240 241 242#endif 243