1139749Simp/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 391398Stmm * All rights reserved. 491398Stmm * 591398Stmm * Redistribution and use in source and binary forms, with or without 691398Stmm * modification, are permitted provided that the following conditions 791398Stmm * are met: 891398Stmm * 1. Redistributions of source code must retain the above copyright 991398Stmm * notice, this list of conditions and the following disclaimer. 1091398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1191398Stmm * notice, this list of conditions and the following disclaimer in the 1291398Stmm * documentation and/or other materials provided with the distribution. 1391398Stmm * 1491398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1591398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1691398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1791398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1891398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1991398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2091398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2191398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2291398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2391398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2491398Stmm * SUCH DAMAGE. 2591398Stmm * 2699726Sbenno * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp 2791398Stmm * 2891398Stmm * $FreeBSD: releng/10.3/sys/dev/gem/if_gemvar.h 223648 2011-06-28 16:16:43Z marius $ 2991398Stmm */ 3091398Stmm 3191398Stmm#ifndef _IF_GEMVAR_H 3291398Stmm#define _IF_GEMVAR_H 3391398Stmm 3491398Stmm#include <sys/queue.h> 3591398Stmm#include <sys/callout.h> 3691398Stmm 3791398Stmm/* 38194763Smarius * Transmit descriptor ring size - this is arbitrary, but allocate 3991398Stmm * enough descriptors for 64 pending transmissions and 16 segments 40174987Smarius * per packet. This limit is not actually enforced (packets with 41174987Smarius * more segments can be sent, depending on the busdma backend); it 42174987Smarius * is however used as an estimate for the TX window size. 4391398Stmm */ 4491398Stmm#define GEM_NTXSEGS 16 4591398Stmm 4691398Stmm#define GEM_TXQUEUELEN 64 4791398Stmm#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 48108832Stmm#define GEM_MAXTXFREE (GEM_NTXDESC - 1) 4991398Stmm#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 5091398Stmm#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 5191398Stmm 5291398Stmm/* 53194763Smarius * Receive descriptor ring size - we have one RX buffer per incoming 5491398Stmm * packet, so this logic is a little simpler. 5591398Stmm */ 56172334Smarius#define GEM_NRXDESC 256 5791398Stmm#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 5891398Stmm#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 5991398Stmm 6091398Stmm/* 61174987Smarius * How many ticks to wait until to retry on a RX descriptor that is 62174987Smarius * still owned by the hardware. 6393045Stmm */ 6493045Stmm#define GEM_RXOWN_TICKS (hz / 50) 6593045Stmm 6693045Stmm/* 67194763Smarius * Control structures are DMA'd to the chip. We allocate them 68174987Smarius * in a single clump that maps to a single DMA segment to make 69174987Smarius * several things easier. 7091398Stmm */ 7191398Stmmstruct gem_control_data { 72174987Smarius struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */ 73174987Smarius struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */ 7491398Stmm}; 7591398Stmm 7691398Stmm#define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 7791398Stmm#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 7891398Stmm#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 7991398Stmm 8091398Stmm/* 81174987Smarius * software state for transmit job mbufs (may be elements of mbuf chains) 8291398Stmm */ 8391398Stmmstruct gem_txsoft { 8491398Stmm struct mbuf *txs_mbuf; /* head of our mbuf chain */ 8591398Stmm bus_dmamap_t txs_dmamap; /* our DMA map */ 86194763Smarius u_int txs_firstdesc; /* first descriptor in packet */ 87194763Smarius u_int txs_lastdesc; /* last descriptor in packet */ 88194763Smarius u_int txs_ndescs; /* number of descriptors */ 8991398Stmm STAILQ_ENTRY(gem_txsoft) txs_q; 9091398Stmm}; 9191398Stmm 9291398StmmSTAILQ_HEAD(gem_txsq, gem_txsoft); 9391398Stmm 9491398Stmm/* 95174987Smarius * software state for receive jobs 9691398Stmm */ 9791398Stmmstruct gem_rxsoft { 9891398Stmm struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 9991398Stmm bus_dmamap_t rxs_dmamap; /* our DMA map */ 10091398Stmm bus_addr_t rxs_paddr; /* physical address of the segment */ 10191398Stmm}; 10291398Stmm 10391398Stmm/* 104174987Smarius * software state per device 10591398Stmm */ 10691398Stmmstruct gem_softc { 107147256Sbrooks struct ifnet *sc_ifp; 108172334Smarius struct mtx sc_mtx; 10991398Stmm device_t sc_miibus; 11091398Stmm struct mii_data *sc_mii; /* MII media control */ 11191398Stmm device_t sc_dev; /* generic device information */ 112172334Smarius u_char sc_enaddr[ETHER_ADDR_LEN]; 11391398Stmm struct callout sc_tick_ch; /* tick callout */ 114174987Smarius struct callout sc_rx_ch; /* delayed RX callout */ 115194763Smarius u_int sc_wdog_timer; /* watchdog timer */ 11691398Stmm 117169269Sphk void *sc_ih; 118177560Smarius struct resource *sc_res[3]; 119177560Smarius#define GEM_RES_INTR 0 120177560Smarius#define GEM_RES_BANK1 1 121177560Smarius#define GEM_RES_BANK2 2 122177560Smarius 123174987Smarius bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */ 124174987Smarius bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */ 125174987Smarius bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */ 126174987Smarius bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */ 127174987Smarius bus_dmamap_t sc_dmamap; /* bus DMA handle */ 12891398Stmm 129174987Smarius u_int sc_variant; 13099726Sbenno#define GEM_UNKNOWN 0 /* don't know */ 131172334Smarius#define GEM_SUN_GEM 1 /* Sun GEM */ 132172334Smarius#define GEM_SUN_ERI 2 /* Sun ERI */ 133172334Smarius#define GEM_APPLE_GMAC 3 /* Apple GMAC */ 134172334Smarius#define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */ 13591398Stmm 136172334Smarius#define GEM_IS_APPLE(sc) \ 137172334Smarius ((sc)->sc_variant == GEM_APPLE_GMAC || \ 138172334Smarius (sc)->sc_variant == GEM_APPLE_K2_GMAC) 139172334Smarius 140174987Smarius u_int sc_flags; 141174987Smarius#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */ 142194886Smarius#define GEM_LINK (1 << 1) /* link is up */ 143194886Smarius#define GEM_PCI (1 << 2) /* PCI busses are little-endian */ 144194886Smarius#define GEM_PCI66 (1 << 3) /* PCI bus runs at 66MHz */ 145194886Smarius#define GEM_SERDES (1 << 4) /* use the SERDES */ 14699726Sbenno 14791398Stmm /* 148174987Smarius * ring buffer DMA stuff 14991398Stmm */ 15091398Stmm bus_dmamap_t sc_cddmamap; /* control data DMA map */ 15191398Stmm bus_addr_t sc_cddma; 15291398Stmm 15391398Stmm /* 154174987Smarius * software state for transmit and receive descriptors 15591398Stmm */ 15691398Stmm struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 15791398Stmm struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 15891398Stmm 15991398Stmm /* 160174987Smarius * control data structures 16191398Stmm */ 16291398Stmm struct gem_control_data *sc_control_data; 16391398Stmm#define sc_txdescs sc_control_data->gcd_txdescs 16491398Stmm#define sc_rxdescs sc_control_data->gcd_rxdescs 16591398Stmm 166194763Smarius u_int sc_txfree; /* number of free TX descriptors */ 167194763Smarius u_int sc_txnext; /* next ready TX descriptor */ 168194763Smarius u_int sc_txwin; /* TX desc. since last TX intr. */ 16991398Stmm 170174987Smarius struct gem_txsq sc_txfreeq; /* free TX descsofts */ 171174987Smarius struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */ 17291398Stmm 173194763Smarius u_int sc_rxptr; /* next ready RX descriptor/state */ 174194763Smarius u_int sc_rxfifosize; /* RX FIFO size (bytes) */ 17591398Stmm 176223648Smarius uint32_t sc_mac_rxcfg; /* RX MAC conf. % GEM_MAC_RX_ENABLE */ 177223648Smarius 17899726Sbenno int sc_ifflags; 179194763Smarius u_long sc_csum_features; 18091398Stmm}; 18191398Stmm 182177560Smarius#define GEM_BANKN_BARRIER(n, sc, offs, len, flags) \ 183177560Smarius bus_barrier((sc)->sc_res[(n)], (offs), (len), (flags)) 184177560Smarius#define GEM_BANK1_BARRIER(sc, offs, len, flags) \ 185177560Smarius GEM_BANKN_BARRIER(GEM_RES_BANK1, (sc), (offs), (len), (flags)) 186177560Smarius#define GEM_BANK2_BARRIER(sc, offs, len, flags) \ 187177560Smarius GEM_BANKN_BARRIER(GEM_RES_BANK2, (sc), (offs), (len), (flags)) 188177560Smarius 189177560Smarius#define GEM_BANKN_READ_M(n, m, sc, offs) \ 190177560Smarius bus_read_ ## m((sc)->sc_res[(n)], (offs)) 191177560Smarius#define GEM_BANK1_READ_1(sc, offs) \ 192177560Smarius GEM_BANKN_READ_M(GEM_RES_BANK1, 1, (sc), (offs)) 193177560Smarius#define GEM_BANK1_READ_2(sc, offs) \ 194177560Smarius GEM_BANKN_READ_M(GEM_RES_BANK1, 2, (sc), (offs)) 195177560Smarius#define GEM_BANK1_READ_4(sc, offs) \ 196177560Smarius GEM_BANKN_READ_M(GEM_RES_BANK1, 4, (sc), (offs)) 197177560Smarius#define GEM_BANK2_READ_1(sc, offs) \ 198177560Smarius GEM_BANKN_READ_M(GEM_RES_BANK2, 1, (sc), (offs)) 199177560Smarius#define GEM_BANK2_READ_2(sc, offs) \ 200177560Smarius GEM_BANKN_READ_M(GEM_RES_BANK2, 2, (sc), (offs)) 201177560Smarius#define GEM_BANK2_READ_4(sc, offs) \ 202177560Smarius GEM_BANKN_READ_M(GEM_RES_BANK2, 4, (sc), (offs)) 203177560Smarius 204177560Smarius#define GEM_BANKN_WRITE_M(n, m, sc, offs, v) \ 205177560Smarius bus_write_ ## m((sc)->sc_res[n], (offs), (v)) 206177560Smarius#define GEM_BANK1_WRITE_1(sc, offs, v) \ 207177560Smarius GEM_BANKN_WRITE_M(GEM_RES_BANK1, 1, (sc), (offs), (v)) 208177560Smarius#define GEM_BANK1_WRITE_2(sc, offs, v) \ 209177560Smarius GEM_BANKN_WRITE_M(GEM_RES_BANK1, 2, (sc), (offs), (v)) 210177560Smarius#define GEM_BANK1_WRITE_4(sc, offs, v) \ 211177560Smarius GEM_BANKN_WRITE_M(GEM_RES_BANK1, 4, (sc), (offs), (v)) 212177560Smarius#define GEM_BANK2_WRITE_1(sc, offs, v) \ 213177560Smarius GEM_BANKN_WRITE_M(GEM_RES_BANK2, 1, (sc), (offs), (v)) 214177560Smarius#define GEM_BANK2_WRITE_2(sc, offs, v) \ 215177560Smarius GEM_BANKN_WRITE_M(GEM_RES_BANK2, 2, (sc), (offs), (v)) 216177560Smarius#define GEM_BANK2_WRITE_4(sc, offs, v) \ 217177560Smarius GEM_BANKN_WRITE_M(GEM_RES_BANK2, 4, (sc), (offs), (v)) 218177560Smarius 219174987Smarius/* XXX this should be handled by bus_dma(9). */ 220172334Smarius#define GEM_DMA_READ(sc, v) \ 221172334Smarius ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v)) 222172334Smarius#define GEM_DMA_WRITE(sc, v) \ 223172334Smarius ((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v)) 22491398Stmm 22591398Stmm#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 22691398Stmm#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 22791398Stmm 228109648Stmm#define GEM_CDSYNC(sc, ops) \ 229172334Smarius bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); 23091398Stmm 23191398Stmm#define GEM_INIT_RXDESC(sc, x) \ 23291398Stmmdo { \ 23391398Stmm struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 23491398Stmm struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 23591398Stmm struct mbuf *__m = __rxs->rxs_mbuf; \ 23691398Stmm \ 23791398Stmm __m->m_data = __m->m_ext.ext_buf; \ 23891398Stmm __rxd->gd_addr = \ 23991398Stmm GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \ 240194763Smarius __rxd->gd_flags = GEM_DMA_WRITE((sc), \ 241194763Smarius (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) & \ 242194763Smarius GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 24391398Stmm} while (0) 24491398Stmm 245172334Smarius#define GEM_UPDATE_RXDESC(sc, x) \ 246172334Smariusdo { \ 247172334Smarius struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 248172334Smarius struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 249172334Smarius struct mbuf *__m = __rxs->rxs_mbuf; \ 250172334Smarius \ 251194763Smarius __rxd->gd_flags = GEM_DMA_WRITE((sc), \ 252194763Smarius (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) & \ 253194763Smarius GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 254172334Smarius} while (0) 255172334Smarius 256148369Smarius#define GEM_LOCK_INIT(_sc, _name) \ 257148369Smarius mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 258148369Smarius#define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 259148369Smarius#define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 260148369Smarius#define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 261148369Smarius#define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 262148369Smarius 26391398Stmm#ifdef _KERNEL 26491398Stmmextern devclass_t gem_devclass; 26591398Stmm 266174987Smariusint gem_attach(struct gem_softc *sc); 267174987Smariusvoid gem_detach(struct gem_softc *sc); 268174987Smariusvoid gem_intr(void *v); 269174987Smariusvoid gem_resume(struct gem_softc *sc); 270174987Smariusvoid gem_suspend(struct gem_softc *sc); 27191398Stmm 272174987Smariusint gem_mediachange(struct ifnet *ifp); 273174987Smariusvoid gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 27491398Stmm 27591398Stmm/* MII methods & callbacks */ 276174987Smariusint gem_mii_readreg(device_t dev, int phy, int reg); 277174987Smariusvoid gem_mii_statchg(device_t dev); 278174987Smariusint gem_mii_writereg(device_t dev, int phy, int reg, int val); 27991398Stmm 28091398Stmm#endif /* _KERNEL */ 28191398Stmm 28291398Stmm#endif 283