if_gem.c revision 223944
18146Sdufault/*- 28146Sdufault * Copyright (C) 2001 Eduardo Horvath. 38146Sdufault * Copyright (c) 2001-2003 Thomas Moestl 48146Sdufault * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org> 58146Sdufault * All rights reserved. 68146Sdufault * 78146Sdufault * Redistribution and use in source and binary forms, with or without 88146Sdufault * modification, are permitted provided that the following conditions 98146Sdufault * are met: 108146Sdufault * 1. Redistributions of source code must retain the above copyright 118146Sdufault * notice, this list of conditions and the following disclaimer. 128146Sdufault * 2. Redistributions in binary form must reproduce the above copyright 138146Sdufault * notice, this list of conditions and the following disclaimer in the 148146Sdufault * documentation and/or other materials provided with the distribution. 158146Sdufault * 168146Sdufault * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 178146Sdufault * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 188146Sdufault * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 198146Sdufault * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 208146Sdufault * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 218146Sdufault * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 228146Sdufault * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 238146Sdufault * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 248146Sdufault * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 258146Sdufault * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 268146Sdufault * SUCH DAMAGE. 278146Sdufault * 288146Sdufault * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 298146Sdufault */ 3064382Skbyanc 3164382Skbyanc#include <sys/cdefs.h> 3264382Skbyanc__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 223944 2011-07-12 08:20:15Z marius $"); 338146Sdufault 348146Sdufault/* 358146Sdufault * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 368146Sdufault */ 3764382Skbyanc 388299Sdufault#if 0 398299Sdufault#define GEM_DEBUG 408299Sdufault#endif 418299Sdufault 428299Sdufault#if 0 /* XXX: In case of emergency, re-enable this. */ 438299Sdufault#define GEM_RINT_TIMEOUT 448299Sdufault#endif 458299Sdufault 468299Sdufault#include <sys/param.h> 478299Sdufault#include <sys/systm.h> 488299Sdufault#include <sys/bus.h> 498146Sdufault#include <sys/callout.h> 508146Sdufault#include <sys/endian.h> 518146Sdufault#include <sys/mbuf.h> 528146Sdufault#include <sys/malloc.h> 5364382Skbyanc#include <sys/kernel.h> 548146Sdufault#include <sys/lock.h> 558146Sdufault#include <sys/module.h> 568146Sdufault#include <sys/mutex.h> 578146Sdufault#include <sys/socket.h> 588146Sdufault#include <sys/sockio.h> 598146Sdufault#include <sys/rman.h> 608299Sdufault 618299Sdufault#include <net/bpf.h> 628146Sdufault#include <net/ethernet.h> 638146Sdufault#include <net/if.h> 648146Sdufault#include <net/if_arp.h> 658146Sdufault#include <net/if_dl.h> 668146Sdufault#include <net/if_media.h> 6764382Skbyanc#include <net/if_types.h> 688146Sdufault#include <net/if_vlan_var.h> 698146Sdufault 708146Sdufault#include <netinet/in.h> 718146Sdufault#include <netinet/in_systm.h> 728146Sdufault#include <netinet/ip.h> 738146Sdufault#include <netinet/tcp.h> 748146Sdufault#include <netinet/udp.h> 758146Sdufault 768146Sdufault#include <machine/bus.h> 7764382Skbyanc 7831562Stegge#include <dev/mii/mii.h> 7931562Stegge#include <dev/mii/miivar.h> 8031562Stegge 8131562Stegge#include <dev/gem/if_gemreg.h> 8231562Stegge#include <dev/gem/if_gemvar.h> 838299Sdufault 848299SdufaultCTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); 858299SdufaultCTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); 868299Sdufault 878299Sdufault#define GEM_TRIES 10000 888146Sdufault 8917766Smpp/* 908146Sdufault * The hardware supports basic TCP/UDP checksum offloading. However, 918146Sdufault * the hardware doesn't compensate the checksum for UDP datagram which 928146Sdufault * can yield to 0x0. As a safe guard, UDP checksum offload is disabled 938146Sdufault * by default. It can be reactivated by setting special link option 9464382Skbyanc * link0 with ifconfig(8). 958146Sdufault */ 968146Sdufault#define GEM_CSUM_FEATURES (CSUM_TCP) 978146Sdufault 988146Sdufaultstatic int gem_add_rxbuf(struct gem_softc *sc, int idx); 998146Sdufaultstatic int gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, 1008146Sdufault uint32_t clr, uint32_t set); 1018146Sdufaultstatic void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, 1028146Sdufault int nsegs, int error); 1038146Sdufaultstatic int gem_disable_rx(struct gem_softc *sc); 1048146Sdufaultstatic int gem_disable_tx(struct gem_softc *sc); 1058146Sdufaultstatic void gem_eint(struct gem_softc *sc, u_int status); 1068146Sdufaultstatic void gem_init(void *xsc); 1078299Sdufaultstatic void gem_init_locked(struct gem_softc *sc); 1088299Sdufaultstatic void gem_init_regs(struct gem_softc *sc); 1098299Sdufaultstatic int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 1108299Sdufaultstatic int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); 1118299Sdufaultstatic int gem_meminit(struct gem_softc *sc); 1128299Sdufaultstatic void gem_mifinit(struct gem_softc *sc); 1138146Sdufaultstatic void gem_reset(struct gem_softc *sc); 1148146Sdufaultstatic int gem_reset_rx(struct gem_softc *sc); 1158146Sdufaultstatic void gem_reset_rxdma(struct gem_softc *sc); 1168299Sdufaultstatic int gem_reset_tx(struct gem_softc *sc); 1178299Sdufaultstatic u_int gem_ringsize(u_int sz); 1188299Sdufaultstatic void gem_rint(struct gem_softc *sc); 1198299Sdufault#ifdef GEM_RINT_TIMEOUT 1208146Sdufaultstatic void gem_rint_timeout(void *arg); 1218146Sdufault#endif 1228146Sdufaultstatic inline void gem_rxcksum(struct mbuf *m, uint64_t flags); 1238146Sdufaultstatic void gem_rxdrain(struct gem_softc *sc); 1248146Sdufaultstatic void gem_setladrf(struct gem_softc *sc, u_int enable); 12564382Skbyancstatic void gem_start(struct ifnet *ifp); 1268146Sdufaultstatic void gem_start_locked(struct ifnet *ifp); 1278146Sdufaultstatic void gem_stop(struct ifnet *ifp, int disable); 1288146Sdufaultstatic void gem_tick(void *arg); 1298146Sdufaultstatic void gem_tint(struct gem_softc *sc); 1308146Sdufaultstatic inline void gem_txkick(struct gem_softc *sc); 1318146Sdufaultstatic int gem_watchdog(struct gem_softc *sc); 1328146Sdufault 1338146Sdufaultdevclass_t gem_devclass; 1348146SdufaultDRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); 1358299SdufaultMODULE_DEPEND(gem, miibus, 1, 1, 1); 1368299Sdufault 1378299Sdufault#ifdef GEM_DEBUG 1388299Sdufault#include <sys/ktr.h> 1398299Sdufault#define KTR_GEM KTR_SPARE2 1408146Sdufault#endif 1418146Sdufault 14264382Skbyanc#define GEM_BANK1_BITWAIT(sc, r, clr, set) \ 1438146Sdufault gem_bitwait((sc), GEM_RES_BANK1, (r), (clr), (set)) 1448146Sdufault#define GEM_BANK2_BITWAIT(sc, r, clr, set) \ 1458146Sdufault gem_bitwait((sc), GEM_RES_BANK2, (r), (clr), (set)) 1468146Sdufault 1478146Sdufaultint 1488146Sdufaultgem_attach(struct gem_softc *sc) 1498146Sdufault{ 1508146Sdufault struct gem_txsoft *txs; 1518146Sdufault struct ifnet *ifp; 15264382Skbyanc int error, i, phy; 1538146Sdufault uint32_t v; 15464382Skbyanc 1558299Sdufault if (bootverbose) 1568299Sdufault device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); 1578299Sdufault 1588299Sdufault /* Set up ifnet structure. */ 1598299Sdufault ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 1608299Sdufault if (ifp == NULL) 1618299Sdufault return (ENOSPC); 1628299Sdufault sc->sc_csum_features = GEM_CSUM_FEATURES; 1638146Sdufault ifp->if_softc = sc; 1648146Sdufault if_initname(ifp, device_get_name(sc->sc_dev), 1658146Sdufault device_get_unit(sc->sc_dev)); 1668146Sdufault ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1678146Sdufault ifp->if_start = gem_start; 1688146Sdufault ifp->if_ioctl = gem_ioctl; 1698146Sdufault ifp->if_init = gem_init; 1708146Sdufault IFQ_SET_MAXLEN(&ifp->if_snd, GEM_TXQUEUELEN); 1718146Sdufault ifp->if_snd.ifq_drv_maxlen = GEM_TXQUEUELEN; 1728146Sdufault IFQ_SET_READY(&ifp->if_snd); 17364382Skbyanc 1748146Sdufault callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 1758146Sdufault#ifdef GEM_RINT_TIMEOUT 1768146Sdufault callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 1778146Sdufault#endif 1788146Sdufault 1798146Sdufault /* Make sure the chip is stopped. */ 1808299Sdufault gem_reset(sc); 1818299Sdufault 1828146Sdufault error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1838146Sdufault BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1848146Sdufault BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 1858146Sdufault NULL, &sc->sc_pdmatag); 1868146Sdufault if (error != 0) 1878146Sdufault goto fail_ifnet; 1888146Sdufault 18964382Skbyanc error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 1908299Sdufault BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1918299Sdufault 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdmatag); 1928299Sdufault if (error != 0) 1938299Sdufault goto fail_ptag; 1948299Sdufault 1958146Sdufault error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 1968146Sdufault BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1978146Sdufault MCLBYTES * GEM_NTXSEGS, GEM_NTXSEGS, MCLBYTES, 1988146Sdufault BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 1998146Sdufault if (error != 0) 2008146Sdufault goto fail_rtag; 2018146Sdufault 2028146Sdufault error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0, 2038146Sdufault BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 20413077Sjoerg sizeof(struct gem_control_data), 1, 20564382Skbyanc sizeof(struct gem_control_data), 0, 20613077Sjoerg NULL, NULL, &sc->sc_cdmatag); 20713077Sjoerg if (error != 0) 20813077Sjoerg goto fail_ttag; 20913077Sjoerg 21013077Sjoerg /* 21113077Sjoerg * Allocate the control data structures, create and load the 21213077Sjoerg * DMA map for it. 21313077Sjoerg */ 21413077Sjoerg if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 21513077Sjoerg (void **)&sc->sc_control_data, 21613077Sjoerg BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 21713077Sjoerg &sc->sc_cddmamap)) != 0) { 21813077Sjoerg device_printf(sc->sc_dev, 21913077Sjoerg "unable to allocate control data, error = %d\n", error); 22013077Sjoerg goto fail_ctag; 22113077Sjoerg } 22213077Sjoerg 22313077Sjoerg sc->sc_cddma = 0; 22413077Sjoerg if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 22513077Sjoerg sc->sc_control_data, sizeof(struct gem_control_data), 22613077Sjoerg gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 22713077Sjoerg device_printf(sc->sc_dev, 22821812Sjoerg "unable to load control data DMA map, error = %d\n", 22921812Sjoerg error); 23021812Sjoerg goto fail_cmem; 23121812Sjoerg } 23221812Sjoerg 23321812Sjoerg /* 23421812Sjoerg * Initialize the transmit job descriptors. 23521812Sjoerg */ 23621812Sjoerg STAILQ_INIT(&sc->sc_txfreeq); 23721812Sjoerg STAILQ_INIT(&sc->sc_txdirtyq); 23821812Sjoerg 23921812Sjoerg /* 24021812Sjoerg * Create the transmit buffer DMA maps. 24164382Skbyanc */ 24221812Sjoerg error = ENOMEM; 24321812Sjoerg for (i = 0; i < GEM_TXQUEUELEN; i++) { 24421812Sjoerg txs = &sc->sc_txsoft[i]; 24521812Sjoerg txs->txs_mbuf = NULL; 24621812Sjoerg txs->txs_ndescs = 0; 24721812Sjoerg if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 24821812Sjoerg &txs->txs_dmamap)) != 0) { 24921812Sjoerg device_printf(sc->sc_dev, 25021812Sjoerg "unable to create TX DMA map %d, error = %d\n", 25121812Sjoerg i, error); 25221812Sjoerg goto fail_txd; 25321812Sjoerg } 25464382Skbyanc STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 25564382Skbyanc } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, 262 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 device_printf(sc->sc_dev, 264 "unable to create RX DMA map %d, error = %d\n", 265 i, error); 266 goto fail_rxd; 267 } 268 sc->sc_rxsoft[i].rxs_mbuf = NULL; 269 } 270 271 /* Bypass probing PHYs if we already know for sure to use a SERDES. */ 272 if ((sc->sc_flags & GEM_SERDES) != 0) 273 goto serdes; 274 275 /* Bad things will happen when touching this register on ERI. */ 276 if (sc->sc_variant != GEM_SUN_ERI) { 277 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 278 GEM_MII_DATAPATH_MII); 279 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 280 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281 } 282 283 gem_mifinit(sc); 284 285 /* 286 * Look for an external PHY. 287 */ 288 error = ENXIO; 289 v = GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG); 290 if ((v & GEM_MIF_CONFIG_MDI1) != 0) { 291 v |= GEM_MIF_CONFIG_PHY_SEL; 292 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 293 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 294 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 295 switch (sc->sc_variant) { 296 case GEM_SUN_ERI: 297 phy = GEM_PHYAD_EXTERNAL; 298 break; 299 default: 300 phy = MII_PHY_ANY; 301 break; 302 } 303 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 304 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 305 MII_OFFSET_ANY, MIIF_DOPAUSE); 306 } 307 308 /* 309 * Fall back on an internal PHY if no external PHY was found. 310 * Note that with Apple (K2) GMACs GEM_MIF_CONFIG_MDI0 can't be 311 * trusted when the firmware has powered down the chip. 312 */ 313 if (error != 0 && 314 ((v & GEM_MIF_CONFIG_MDI0) != 0 || GEM_IS_APPLE(sc))) { 315 v &= ~GEM_MIF_CONFIG_PHY_SEL; 316 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, v); 317 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 318 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 319 switch (sc->sc_variant) { 320 case GEM_SUN_ERI: 321 case GEM_APPLE_K2_GMAC: 322 phy = GEM_PHYAD_INTERNAL; 323 break; 324 case GEM_APPLE_GMAC: 325 phy = GEM_PHYAD_EXTERNAL; 326 break; 327 default: 328 phy = MII_PHY_ANY; 329 break; 330 } 331 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 332 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, phy, 333 MII_OFFSET_ANY, MIIF_DOPAUSE); 334 } 335 336 /* 337 * Try the external PCS SERDES if we didn't find any PHYs. 338 */ 339 if (error != 0 && sc->sc_variant == GEM_SUN_GEM) { 340 serdes: 341 GEM_BANK1_WRITE_4(sc, GEM_MII_DATAPATH_MODE, 342 GEM_MII_DATAPATH_SERDES); 343 GEM_BANK1_BARRIER(sc, GEM_MII_DATAPATH_MODE, 4, 344 BUS_SPACE_BARRIER_WRITE); 345 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 346 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 347 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 348 BUS_SPACE_BARRIER_WRITE); 349 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 350 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 351 BUS_SPACE_BARRIER_WRITE); 352 sc->sc_flags |= GEM_SERDES; 353 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 354 gem_mediachange, gem_mediastatus, BMSR_DEFCAPMASK, 355 GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 356 } 357 if (error != 0) { 358 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 359 goto fail_rxd; 360 } 361 sc->sc_mii = device_get_softc(sc->sc_miibus); 362 363 /* 364 * From this point forward, the attachment cannot fail. A failure 365 * before this point releases all resources that may have been 366 * allocated. 367 */ 368 369 /* Get RX FIFO size. */ 370 sc->sc_rxfifosize = 64 * 371 GEM_BANK1_READ_4(sc, GEM_RX_FIFO_SIZE); 372 373 /* Get TX FIFO size. */ 374 v = GEM_BANK1_READ_4(sc, GEM_TX_FIFO_SIZE); 375 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 376 sc->sc_rxfifosize / 1024, v / 16); 377 378 /* Attach the interface. */ 379 ether_ifattach(ifp, sc->sc_enaddr); 380 381 /* 382 * Tell the upper layer(s) we support long frames/checksum offloads. 383 */ 384 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 385 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 386 ifp->if_hwassist |= sc->sc_csum_features; 387 ifp->if_capenable |= IFCAP_VLAN_MTU | IFCAP_HWCSUM; 388 389 return (0); 390 391 /* 392 * Free any resources we've allocated during the failed attach 393 * attempt. Do this in reverse order and fall through. 394 */ 395 fail_rxd: 396 for (i = 0; i < GEM_NRXDESC; i++) 397 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 398 bus_dmamap_destroy(sc->sc_rdmatag, 399 sc->sc_rxsoft[i].rxs_dmamap); 400 fail_txd: 401 for (i = 0; i < GEM_TXQUEUELEN; i++) 402 if (sc->sc_txsoft[i].txs_dmamap != NULL) 403 bus_dmamap_destroy(sc->sc_tdmatag, 404 sc->sc_txsoft[i].txs_dmamap); 405 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 406 fail_cmem: 407 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 408 sc->sc_cddmamap); 409 fail_ctag: 410 bus_dma_tag_destroy(sc->sc_cdmatag); 411 fail_ttag: 412 bus_dma_tag_destroy(sc->sc_tdmatag); 413 fail_rtag: 414 bus_dma_tag_destroy(sc->sc_rdmatag); 415 fail_ptag: 416 bus_dma_tag_destroy(sc->sc_pdmatag); 417 fail_ifnet: 418 if_free(ifp); 419 return (error); 420} 421 422void 423gem_detach(struct gem_softc *sc) 424{ 425 struct ifnet *ifp = sc->sc_ifp; 426 int i; 427 428 ether_ifdetach(ifp); 429 GEM_LOCK(sc); 430 gem_stop(ifp, 1); 431 GEM_UNLOCK(sc); 432 callout_drain(&sc->sc_tick_ch); 433#ifdef GEM_RINT_TIMEOUT 434 callout_drain(&sc->sc_rx_ch); 435#endif 436 if_free(ifp); 437 device_delete_child(sc->sc_dev, sc->sc_miibus); 438 439 for (i = 0; i < GEM_NRXDESC; i++) 440 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 441 bus_dmamap_destroy(sc->sc_rdmatag, 442 sc->sc_rxsoft[i].rxs_dmamap); 443 for (i = 0; i < GEM_TXQUEUELEN; i++) 444 if (sc->sc_txsoft[i].txs_dmamap != NULL) 445 bus_dmamap_destroy(sc->sc_tdmatag, 446 sc->sc_txsoft[i].txs_dmamap); 447 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 448 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 449 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 450 sc->sc_cddmamap); 451 bus_dma_tag_destroy(sc->sc_cdmatag); 452 bus_dma_tag_destroy(sc->sc_tdmatag); 453 bus_dma_tag_destroy(sc->sc_rdmatag); 454 bus_dma_tag_destroy(sc->sc_pdmatag); 455} 456 457void 458gem_suspend(struct gem_softc *sc) 459{ 460 struct ifnet *ifp = sc->sc_ifp; 461 462 GEM_LOCK(sc); 463 gem_stop(ifp, 0); 464 GEM_UNLOCK(sc); 465} 466 467void 468gem_resume(struct gem_softc *sc) 469{ 470 struct ifnet *ifp = sc->sc_ifp; 471 472 GEM_LOCK(sc); 473 /* 474 * On resume all registers have to be initialized again like 475 * after power-on. 476 */ 477 sc->sc_flags &= ~GEM_INITED; 478 if (ifp->if_flags & IFF_UP) 479 gem_init_locked(sc); 480 GEM_UNLOCK(sc); 481} 482 483static inline void 484gem_rxcksum(struct mbuf *m, uint64_t flags) 485{ 486 struct ether_header *eh; 487 struct ip *ip; 488 struct udphdr *uh; 489 uint16_t *opts; 490 int32_t hlen, len, pktlen; 491 uint32_t temp32; 492 uint16_t cksum; 493 494 pktlen = m->m_pkthdr.len; 495 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 496 return; 497 eh = mtod(m, struct ether_header *); 498 if (eh->ether_type != htons(ETHERTYPE_IP)) 499 return; 500 ip = (struct ip *)(eh + 1); 501 if (ip->ip_v != IPVERSION) 502 return; 503 504 hlen = ip->ip_hl << 2; 505 pktlen -= sizeof(struct ether_header); 506 if (hlen < sizeof(struct ip)) 507 return; 508 if (ntohs(ip->ip_len) < hlen) 509 return; 510 if (ntohs(ip->ip_len) != pktlen) 511 return; 512 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 513 return; /* Cannot handle fragmented packet. */ 514 515 switch (ip->ip_p) { 516 case IPPROTO_TCP: 517 if (pktlen < (hlen + sizeof(struct tcphdr))) 518 return; 519 break; 520 case IPPROTO_UDP: 521 if (pktlen < (hlen + sizeof(struct udphdr))) 522 return; 523 uh = (struct udphdr *)((uint8_t *)ip + hlen); 524 if (uh->uh_sum == 0) 525 return; /* no checksum */ 526 break; 527 default: 528 return; 529 } 530 531 cksum = ~(flags & GEM_RD_CHECKSUM); 532 /* checksum fixup for IP options */ 533 len = hlen - sizeof(struct ip); 534 if (len > 0) { 535 opts = (uint16_t *)(ip + 1); 536 for (; len > 0; len -= sizeof(uint16_t), opts++) { 537 temp32 = cksum - *opts; 538 temp32 = (temp32 >> 16) + (temp32 & 65535); 539 cksum = temp32 & 65535; 540 } 541 } 542 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 543 m->m_pkthdr.csum_data = cksum; 544} 545 546static void 547gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 548{ 549 struct gem_softc *sc = xsc; 550 551 if (error != 0) 552 return; 553 if (nsegs != 1) 554 panic("%s: bad control buffer segment count", __func__); 555 sc->sc_cddma = segs[0].ds_addr; 556} 557 558static void 559gem_tick(void *arg) 560{ 561 struct gem_softc *sc = arg; 562 struct ifnet *ifp = sc->sc_ifp; 563 uint32_t v; 564 565 GEM_LOCK_ASSERT(sc, MA_OWNED); 566 567 /* 568 * Unload collision and error counters. 569 */ 570 ifp->if_collisions += 571 GEM_BANK1_READ_4(sc, GEM_MAC_NORM_COLL_CNT) + 572 GEM_BANK1_READ_4(sc, GEM_MAC_FIRST_COLL_CNT); 573 v = GEM_BANK1_READ_4(sc, GEM_MAC_EXCESS_COLL_CNT) + 574 GEM_BANK1_READ_4(sc, GEM_MAC_LATE_COLL_CNT); 575 ifp->if_collisions += v; 576 ifp->if_oerrors += v; 577 ifp->if_ierrors += 578 GEM_BANK1_READ_4(sc, GEM_MAC_RX_LEN_ERR_CNT) + 579 GEM_BANK1_READ_4(sc, GEM_MAC_RX_ALIGN_ERR) + 580 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CRC_ERR_CNT) + 581 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CODE_VIOL); 582 583 /* 584 * Then clear the hardware counters. 585 */ 586 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 587 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 588 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 589 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 590 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 591 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 592 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 593 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 594 595 mii_tick(sc->sc_mii); 596 597 if (gem_watchdog(sc) == EJUSTRETURN) 598 return; 599 600 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 601} 602 603static int 604gem_bitwait(struct gem_softc *sc, u_int bank, bus_addr_t r, uint32_t clr, 605 uint32_t set) 606{ 607 int i; 608 uint32_t reg; 609 610 for (i = GEM_TRIES; i--; DELAY(100)) { 611 reg = GEM_BANKN_READ_M(bank, 4, sc, r); 612 if ((reg & clr) == 0 && (reg & set) == set) 613 return (1); 614 } 615 return (0); 616} 617 618static void 619gem_reset(struct gem_softc *sc) 620{ 621 622#ifdef GEM_DEBUG 623 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 624#endif 625 gem_reset_rx(sc); 626 gem_reset_tx(sc); 627 628 /* Do a full reset. */ 629 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX | 630 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE << 631 GEM_RESET_CLSZ_SHFT : 0)); 632 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 633 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 634 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 635 device_printf(sc->sc_dev, "cannot reset device\n"); 636} 637 638static void 639gem_rxdrain(struct gem_softc *sc) 640{ 641 struct gem_rxsoft *rxs; 642 int i; 643 644 for (i = 0; i < GEM_NRXDESC; i++) { 645 rxs = &sc->sc_rxsoft[i]; 646 if (rxs->rxs_mbuf != NULL) { 647 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 648 BUS_DMASYNC_POSTREAD); 649 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 650 m_freem(rxs->rxs_mbuf); 651 rxs->rxs_mbuf = NULL; 652 } 653 } 654} 655 656static void 657gem_stop(struct ifnet *ifp, int disable) 658{ 659 struct gem_softc *sc = ifp->if_softc; 660 struct gem_txsoft *txs; 661 662#ifdef GEM_DEBUG 663 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 664#endif 665 666 callout_stop(&sc->sc_tick_ch); 667#ifdef GEM_RINT_TIMEOUT 668 callout_stop(&sc->sc_rx_ch); 669#endif 670 671 gem_reset_tx(sc); 672 gem_reset_rx(sc); 673 674 /* 675 * Release any queued transmit buffers. 676 */ 677 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 678 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 679 if (txs->txs_ndescs != 0) { 680 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 681 BUS_DMASYNC_POSTWRITE); 682 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 683 if (txs->txs_mbuf != NULL) { 684 m_freem(txs->txs_mbuf); 685 txs->txs_mbuf = NULL; 686 } 687 } 688 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 689 } 690 691 if (disable) 692 gem_rxdrain(sc); 693 694 /* 695 * Mark the interface down and cancel the watchdog timer. 696 */ 697 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 698 sc->sc_flags &= ~GEM_LINK; 699 sc->sc_wdog_timer = 0; 700} 701 702static int 703gem_reset_rx(struct gem_softc *sc) 704{ 705 706 /* 707 * Resetting while DMA is in progress can cause a bus hang, so we 708 * disable DMA first. 709 */ 710 (void)gem_disable_rx(sc); 711 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 0); 712 GEM_BANK1_BARRIER(sc, GEM_RX_CONFIG, 4, 713 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 714 if (!GEM_BANK1_BITWAIT(sc, GEM_RX_CONFIG, GEM_RX_CONFIG_RXDMA_EN, 0)) 715 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 716 717 /* Wait 5ms extra. */ 718 DELAY(5000); 719 720 /* Reset the ERX. */ 721 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_RX | 722 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE << 723 GEM_RESET_CLSZ_SHFT : 0)); 724 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 725 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 726 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_RX, 0)) { 727 device_printf(sc->sc_dev, "cannot reset receiver\n"); 728 return (1); 729 } 730 731 /* Finally, reset RX MAC. */ 732 GEM_BANK1_WRITE_4(sc, GEM_MAC_RXRESET, 1); 733 GEM_BANK1_BARRIER(sc, GEM_MAC_RXRESET, 4, 734 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 735 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RXRESET, 1, 0)) { 736 device_printf(sc->sc_dev, "cannot reset RX MAC\n"); 737 return (1); 738 } 739 740 return (0); 741} 742 743/* 744 * Reset the receiver DMA engine. 745 * 746 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 747 * etc in order to reset the receiver DMA engine only and not do a full 748 * reset which amongst others also downs the link and clears the FIFOs. 749 */ 750static void 751gem_reset_rxdma(struct gem_softc *sc) 752{ 753 int i; 754 755 if (gem_reset_rx(sc) != 0) { 756 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 757 return (gem_init_locked(sc)); 758 } 759 for (i = 0; i < GEM_NRXDESC; i++) 760 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 761 GEM_UPDATE_RXDESC(sc, i); 762 sc->sc_rxptr = 0; 763 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 764 765 /* NOTE: we use only 32-bit DMA addresses here. */ 766 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 767 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 768 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 769 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 770 gem_ringsize(GEM_NRXDESC /* XXX */) | 771 ((ETHER_HDR_LEN + sizeof(struct ip)) << 772 GEM_RX_CONFIG_CXM_START_SHFT) | 773 (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 774 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT)); 775 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 776 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 777 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 778 GEM_RX_BLANKING_TIME_SHIFT) | 6); 779 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 780 (3 * sc->sc_rxfifosize / 256) | 781 ((sc->sc_rxfifosize / 256) << 12)); 782 /* 783 * Clear the RX filter and reprogram it. This will also set the 784 * current RX MAC configuration. 785 */ 786 gem_setladrf(sc, 0); 787 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 788 GEM_BANK1_READ_4(sc, GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); 789 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 790 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 791 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 792 sc->sc_mac_rxcfg | GEM_MAC_RX_ENABLE); 793} 794 795static int 796gem_reset_tx(struct gem_softc *sc) 797{ 798 799 /* 800 * Resetting while DMA is in progress can cause a bus hang, so we 801 * disable DMA first. 802 */ 803 (void)gem_disable_tx(sc); 804 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, 0); 805 GEM_BANK1_BARRIER(sc, GEM_TX_CONFIG, 4, 806 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 807 if (!GEM_BANK1_BITWAIT(sc, GEM_TX_CONFIG, GEM_TX_CONFIG_TXDMA_EN, 0)) 808 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 809 810 /* Wait 5ms extra. */ 811 DELAY(5000); 812 813 /* Finally, reset the ETX. */ 814 GEM_BANK2_WRITE_4(sc, GEM_RESET, GEM_RESET_TX | 815 (sc->sc_variant == GEM_SUN_ERI ? GEM_ERI_CACHE_LINE_SIZE << 816 GEM_RESET_CLSZ_SHFT : 0)); 817 GEM_BANK2_BARRIER(sc, GEM_RESET, 4, 818 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 819 if (!GEM_BANK2_BITWAIT(sc, GEM_RESET, GEM_RESET_TX, 0)) { 820 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 821 return (1); 822 } 823 return (0); 824} 825 826static int 827gem_disable_rx(struct gem_softc *sc) 828{ 829 830 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 831 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG) & ~GEM_MAC_RX_ENABLE); 832 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 833 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 834 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 835 return (1); 836 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 837 return (0); 838} 839 840static int 841gem_disable_tx(struct gem_softc *sc) 842{ 843 844 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 845 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG) & ~GEM_MAC_TX_ENABLE); 846 GEM_BANK1_BARRIER(sc, GEM_MAC_TX_CONFIG, 4, 847 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 848 if (GEM_BANK1_BITWAIT(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 849 return (1); 850 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 851 return (0); 852} 853 854static int 855gem_meminit(struct gem_softc *sc) 856{ 857 struct gem_rxsoft *rxs; 858 int error, i; 859 860 GEM_LOCK_ASSERT(sc, MA_OWNED); 861 862 /* 863 * Initialize the transmit descriptor ring. 864 */ 865 for (i = 0; i < GEM_NTXDESC; i++) { 866 sc->sc_txdescs[i].gd_flags = 0; 867 sc->sc_txdescs[i].gd_addr = 0; 868 } 869 sc->sc_txfree = GEM_MAXTXFREE; 870 sc->sc_txnext = 0; 871 sc->sc_txwin = 0; 872 873 /* 874 * Initialize the receive descriptor and receive job 875 * descriptor rings. 876 */ 877 for (i = 0; i < GEM_NRXDESC; i++) { 878 rxs = &sc->sc_rxsoft[i]; 879 if (rxs->rxs_mbuf == NULL) { 880 if ((error = gem_add_rxbuf(sc, i)) != 0) { 881 device_printf(sc->sc_dev, 882 "unable to allocate or map RX buffer %d, " 883 "error = %d\n", i, error); 884 /* 885 * XXX we should attempt to run with fewer 886 * receive buffers instead of just failing. 887 */ 888 gem_rxdrain(sc); 889 return (1); 890 } 891 } else 892 GEM_INIT_RXDESC(sc, i); 893 } 894 sc->sc_rxptr = 0; 895 896 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 897 898 return (0); 899} 900 901static u_int 902gem_ringsize(u_int sz) 903{ 904 905 switch (sz) { 906 case 32: 907 return (GEM_RING_SZ_32); 908 case 64: 909 return (GEM_RING_SZ_64); 910 case 128: 911 return (GEM_RING_SZ_128); 912 case 256: 913 return (GEM_RING_SZ_256); 914 case 512: 915 return (GEM_RING_SZ_512); 916 case 1024: 917 return (GEM_RING_SZ_1024); 918 case 2048: 919 return (GEM_RING_SZ_2048); 920 case 4096: 921 return (GEM_RING_SZ_4096); 922 case 8192: 923 return (GEM_RING_SZ_8192); 924 default: 925 printf("%s: invalid ring size %d\n", __func__, sz); 926 return (GEM_RING_SZ_32); 927 } 928} 929 930static void 931gem_init(void *xsc) 932{ 933 struct gem_softc *sc = xsc; 934 935 GEM_LOCK(sc); 936 gem_init_locked(sc); 937 GEM_UNLOCK(sc); 938} 939 940/* 941 * Initialization of interface; set up initialization block 942 * and transmit/receive descriptor rings. 943 */ 944static void 945gem_init_locked(struct gem_softc *sc) 946{ 947 struct ifnet *ifp = sc->sc_ifp; 948 uint32_t v; 949 950 GEM_LOCK_ASSERT(sc, MA_OWNED); 951 952 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 953 return; 954 955#ifdef GEM_DEBUG 956 CTR2(KTR_GEM, "%s: %s: calling stop", device_get_name(sc->sc_dev), 957 __func__); 958#endif 959 /* 960 * Initialization sequence. The numbered steps below correspond 961 * to the sequence outlined in section 6.3.5.1 in the Ethernet 962 * Channel Engine manual (part of the PCIO manual). 963 * See also the STP2002-STQ document from Sun Microsystems. 964 */ 965 966 /* step 1 & 2. Reset the Ethernet Channel. */ 967 gem_stop(ifp, 0); 968 gem_reset(sc); 969#ifdef GEM_DEBUG 970 CTR2(KTR_GEM, "%s: %s: restarting", device_get_name(sc->sc_dev), 971 __func__); 972#endif 973 974 if ((sc->sc_flags & GEM_SERDES) == 0) 975 /* Re-initialize the MIF. */ 976 gem_mifinit(sc); 977 978 /* step 3. Setup data structures in host memory. */ 979 if (gem_meminit(sc) != 0) 980 return; 981 982 /* step 4. TX MAC registers & counters */ 983 gem_init_regs(sc); 984 985 /* step 5. RX MAC registers & counters */ 986 gem_setladrf(sc, 0); 987 988 /* step 6 & 7. Program Descriptor Ring Base Addresses. */ 989 /* NOTE: we use only 32-bit DMA addresses here. */ 990 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_HI, 0); 991 GEM_BANK1_WRITE_4(sc, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 992 993 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_HI, 0); 994 GEM_BANK1_WRITE_4(sc, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 995#ifdef GEM_DEBUG 996 CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", 997 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 998#endif 999 1000 /* step 8. Global Configuration & Interrupt Mask */ 1001 1002 /* 1003 * Set the internal arbitration to "infinite" bursts of the 1004 * maximum length of 31 * 64 bytes so DMA transfers aren't 1005 * split up in cache line size chunks. This greatly improves 1006 * RX performance. 1007 * Enable silicon bug workarounds for the Apple variants. 1008 */ 1009 GEM_BANK1_WRITE_4(sc, GEM_CONFIG, 1010 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1011 ((sc->sc_flags & GEM_PCI) != 0 ? GEM_CONFIG_BURST_INF : 1012 GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1013 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1014 1015 GEM_BANK1_WRITE_4(sc, GEM_INTMASK, 1016 ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | 1017 GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | 1018 GEM_INTR_BERR 1019#ifdef GEM_DEBUG 1020 | GEM_INTR_PCS | GEM_INTR_MIF 1021#endif 1022 )); 1023 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_MASK, 1024 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1025 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_MASK, 1026 GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1027 GEM_MAC_TX_PEAK_EXP); 1028#ifdef GEM_DEBUG 1029 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 1030 ~(GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME)); 1031#else 1032 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_MASK, 1033 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1034#endif 1035 1036 /* step 9. ETX Configuration: use mostly default values. */ 1037 1038 /* Enable DMA. */ 1039 v = gem_ringsize(GEM_NTXDESC); 1040 /* Set TX FIFO threshold and enable DMA. */ 1041 v |= ((sc->sc_variant == GEM_SUN_ERI ? 0x100 : 0x4ff) << 10) & 1042 GEM_TX_CONFIG_TXFIFO_TH; 1043 GEM_BANK1_WRITE_4(sc, GEM_TX_CONFIG, v | GEM_TX_CONFIG_TXDMA_EN); 1044 1045 /* step 10. ERX Configuration */ 1046 1047 /* Encode Receive Descriptor ring size. */ 1048 v = gem_ringsize(GEM_NRXDESC /* XXX */); 1049 /* RX TCP/UDP checksum offset */ 1050 v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << 1051 GEM_RX_CONFIG_CXM_START_SHFT); 1052 /* Set RX FIFO threshold, set first byte offset and enable DMA. */ 1053 GEM_BANK1_WRITE_4(sc, GEM_RX_CONFIG, 1054 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 1055 (ETHER_ALIGN << GEM_RX_CONFIG_FBOFF_SHFT) | 1056 GEM_RX_CONFIG_RXDMA_EN); 1057 1058 /* Adjust for the SBus clock probably isn't worth the fuzz. */ 1059 GEM_BANK1_WRITE_4(sc, GEM_RX_BLANKING, 1060 ((6 * (sc->sc_flags & GEM_PCI66) != 0 ? 2 : 1) << 1061 GEM_RX_BLANKING_TIME_SHIFT) | 6); 1062 1063 /* 1064 * The following value is for an OFF Threshold of about 3/4 full 1065 * and an ON Threshold of 1/4 full. 1066 */ 1067 GEM_BANK1_WRITE_4(sc, GEM_RX_PAUSE_THRESH, 1068 (3 * sc->sc_rxfifosize / 256) | 1069 ((sc->sc_rxfifosize / 256) << 12)); 1070 1071 /* step 11. Configure Media. */ 1072 1073 /* step 12. RX_MAC Configuration Register */ 1074 v = GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG); 1075 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1076 (void)gem_disable_rx(sc); 1077 sc->sc_mac_rxcfg = v & ~GEM_MAC_RX_ENABLE; 1078 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 1079 1080 /* step 13. TX_MAC Configuration Register */ 1081 v = GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG); 1082 v |= GEM_MAC_TX_ENABLE; 1083 (void)gem_disable_tx(sc); 1084 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, v); 1085 1086 /* step 14. Issue Transmit Pending command. */ 1087 1088 /* step 15. Give the receiver a swift kick. */ 1089 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, GEM_NRXDESC - 4); 1090 1091 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1092 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1093 1094 mii_mediachg(sc->sc_mii); 1095 1096 /* Start the one second timer. */ 1097 sc->sc_wdog_timer = 0; 1098 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1099} 1100 1101static int 1102gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) 1103{ 1104 bus_dma_segment_t txsegs[GEM_NTXSEGS]; 1105 struct gem_txsoft *txs; 1106 struct ip *ip; 1107 struct mbuf *m; 1108 uint64_t cflags, flags; 1109 int error, nexttx, nsegs, offset, seg; 1110 1111 GEM_LOCK_ASSERT(sc, MA_OWNED); 1112 1113 /* Get a work queue entry. */ 1114 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1115 /* Ran out of descriptors. */ 1116 return (ENOBUFS); 1117 } 1118 1119 cflags = 0; 1120 if (((*m_head)->m_pkthdr.csum_flags & sc->sc_csum_features) != 0) { 1121 if (M_WRITABLE(*m_head) == 0) { 1122 m = m_dup(*m_head, M_DONTWAIT); 1123 m_freem(*m_head); 1124 *m_head = m; 1125 if (m == NULL) 1126 return (ENOBUFS); 1127 } 1128 offset = sizeof(struct ether_header); 1129 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1130 if (m == NULL) { 1131 *m_head = NULL; 1132 return (ENOBUFS); 1133 } 1134 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1135 offset += (ip->ip_hl << 2); 1136 cflags = offset << GEM_TD_CXSUM_STARTSHFT | 1137 ((offset + m->m_pkthdr.csum_data) << 1138 GEM_TD_CXSUM_STUFFSHFT) | GEM_TD_CXSUM_ENABLE; 1139 *m_head = m; 1140 } 1141 1142 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1143 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1144 if (error == EFBIG) { 1145 m = m_collapse(*m_head, M_DONTWAIT, GEM_NTXSEGS); 1146 if (m == NULL) { 1147 m_freem(*m_head); 1148 *m_head = NULL; 1149 return (ENOBUFS); 1150 } 1151 *m_head = m; 1152 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1153 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1154 BUS_DMA_NOWAIT); 1155 if (error != 0) { 1156 m_freem(*m_head); 1157 *m_head = NULL; 1158 return (error); 1159 } 1160 } else if (error != 0) 1161 return (error); 1162 /* If nsegs is wrong then the stack is corrupt. */ 1163 KASSERT(nsegs <= GEM_NTXSEGS, 1164 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1165 if (nsegs == 0) { 1166 m_freem(*m_head); 1167 *m_head = NULL; 1168 return (EIO); 1169 } 1170 1171 /* 1172 * Ensure we have enough descriptors free to describe 1173 * the packet. Note, we always reserve one descriptor 1174 * at the end of the ring as a termination point, in 1175 * order to prevent wrap-around. 1176 */ 1177 if (nsegs > sc->sc_txfree - 1) { 1178 txs->txs_ndescs = 0; 1179 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1180 return (ENOBUFS); 1181 } 1182 1183 txs->txs_ndescs = nsegs; 1184 txs->txs_firstdesc = sc->sc_txnext; 1185 nexttx = txs->txs_firstdesc; 1186 for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { 1187#ifdef GEM_DEBUG 1188 CTR6(KTR_GEM, 1189 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1190 __func__, seg, nexttx, txsegs[seg].ds_len, 1191 txsegs[seg].ds_addr, 1192 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); 1193#endif 1194 sc->sc_txdescs[nexttx].gd_addr = 1195 GEM_DMA_WRITE(sc, txsegs[seg].ds_addr); 1196 KASSERT(txsegs[seg].ds_len < GEM_TD_BUFSIZE, 1197 ("%s: segment size too large!", __func__)); 1198 flags = txsegs[seg].ds_len & GEM_TD_BUFSIZE; 1199 sc->sc_txdescs[nexttx].gd_flags = 1200 GEM_DMA_WRITE(sc, flags | cflags); 1201 txs->txs_lastdesc = nexttx; 1202 } 1203 1204 /* Set EOP on the last descriptor. */ 1205#ifdef GEM_DEBUG 1206 CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", 1207 __func__, seg, nexttx); 1208#endif 1209 sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= 1210 GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); 1211 1212 /* Lastly set SOP on the first descriptor. */ 1213#ifdef GEM_DEBUG 1214 CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", 1215 __func__, seg, nexttx); 1216#endif 1217 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1218 sc->sc_txwin = 0; 1219 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1220 GEM_DMA_WRITE(sc, GEM_TD_INTERRUPT_ME | 1221 GEM_TD_START_OF_PACKET); 1222 } else 1223 sc->sc_txdescs[txs->txs_firstdesc].gd_flags |= 1224 GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); 1225 1226 /* Sync the DMA map. */ 1227 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1228 BUS_DMASYNC_PREWRITE); 1229 1230#ifdef GEM_DEBUG 1231 CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1232 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1233 txs->txs_ndescs); 1234#endif 1235 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1236 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1237 txs->txs_mbuf = *m_head; 1238 1239 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc); 1240 sc->sc_txfree -= txs->txs_ndescs; 1241 1242 return (0); 1243} 1244 1245static void 1246gem_init_regs(struct gem_softc *sc) 1247{ 1248 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1249 1250 GEM_LOCK_ASSERT(sc, MA_OWNED); 1251 1252 /* These registers are not cleared on reset. */ 1253 if ((sc->sc_flags & GEM_INITED) == 0) { 1254 /* magic values */ 1255 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG0, 0); 1256 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG1, 8); 1257 GEM_BANK1_WRITE_4(sc, GEM_MAC_IPG2, 4); 1258 1259 /* min frame length */ 1260 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1261 /* max frame length and max burst size */ 1262 GEM_BANK1_WRITE_4(sc, GEM_MAC_MAC_MAX_FRAME, 1263 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); 1264 1265 /* more magic values */ 1266 GEM_BANK1_WRITE_4(sc, GEM_MAC_PREAMBLE_LEN, 0x7); 1267 GEM_BANK1_WRITE_4(sc, GEM_MAC_JAM_SIZE, 0x4); 1268 GEM_BANK1_WRITE_4(sc, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1269 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_TYPE, 0x8808); 1270 1271 /* random number seed */ 1272 GEM_BANK1_WRITE_4(sc, GEM_MAC_RANDOM_SEED, 1273 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1274 1275 /* secondary MAC address: 0:0:0:0:0:0 */ 1276 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR3, 0); 1277 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR4, 0); 1278 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR5, 0); 1279 1280 /* MAC control address: 01:80:c2:00:00:01 */ 1281 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR6, 0x0001); 1282 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR7, 0xc200); 1283 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR8, 0x0180); 1284 1285 /* MAC filter address: 0:0:0:0:0:0 */ 1286 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER0, 0); 1287 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER1, 0); 1288 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR_FILTER2, 0); 1289 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK1_2, 0); 1290 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADR_FLT_MASK0, 0); 1291 1292 sc->sc_flags |= GEM_INITED; 1293 } 1294 1295 /* Counters need to be zeroed. */ 1296 GEM_BANK1_WRITE_4(sc, GEM_MAC_NORM_COLL_CNT, 0); 1297 GEM_BANK1_WRITE_4(sc, GEM_MAC_FIRST_COLL_CNT, 0); 1298 GEM_BANK1_WRITE_4(sc, GEM_MAC_EXCESS_COLL_CNT, 0); 1299 GEM_BANK1_WRITE_4(sc, GEM_MAC_LATE_COLL_CNT, 0); 1300 GEM_BANK1_WRITE_4(sc, GEM_MAC_DEFER_TMR_CNT, 0); 1301 GEM_BANK1_WRITE_4(sc, GEM_MAC_PEAK_ATTEMPTS, 0); 1302 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_FRAME_COUNT, 0); 1303 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_LEN_ERR_CNT, 0); 1304 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_ALIGN_ERR, 0); 1305 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CRC_ERR_CNT, 0); 1306 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CODE_VIOL, 0); 1307 1308 /* Set XOFF PAUSE time. */ 1309 GEM_BANK1_WRITE_4(sc, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1310 1311 /* Set the station address. */ 1312 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1313 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1314 GEM_BANK1_WRITE_4(sc, GEM_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1315 1316 /* Enable MII outputs. */ 1317 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); 1318} 1319 1320static void 1321gem_start(struct ifnet *ifp) 1322{ 1323 struct gem_softc *sc = ifp->if_softc; 1324 1325 GEM_LOCK(sc); 1326 gem_start_locked(ifp); 1327 GEM_UNLOCK(sc); 1328} 1329 1330static inline void 1331gem_txkick(struct gem_softc *sc) 1332{ 1333 1334 /* 1335 * Update the TX kick register. This register has to point to the 1336 * descriptor after the last valid one and for optimum performance 1337 * should be incremented in multiples of 4 (the DMA engine fetches/ 1338 * updates descriptors in batches of 4). 1339 */ 1340#ifdef GEM_DEBUG 1341 CTR3(KTR_GEM, "%s: %s: kicking TX %d", 1342 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1343#endif 1344 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1345 GEM_BANK1_WRITE_4(sc, GEM_TX_KICK, sc->sc_txnext); 1346} 1347 1348static void 1349gem_start_locked(struct ifnet *ifp) 1350{ 1351 struct gem_softc *sc = ifp->if_softc; 1352 struct mbuf *m; 1353 int kicked, ntx; 1354 1355 GEM_LOCK_ASSERT(sc, MA_OWNED); 1356 1357 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1358 IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) 1359 return; 1360 1361#ifdef GEM_DEBUG 1362 CTR4(KTR_GEM, "%s: %s: txfree %d, txnext %d", 1363 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1364 sc->sc_txnext); 1365#endif 1366 ntx = 0; 1367 kicked = 0; 1368 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1369 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1370 if (m == NULL) 1371 break; 1372 if (gem_load_txmbuf(sc, &m) != 0) { 1373 if (m == NULL) 1374 break; 1375 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1376 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1377 break; 1378 } 1379 if ((sc->sc_txnext % 4) == 0) { 1380 gem_txkick(sc); 1381 kicked = 1; 1382 } else 1383 kicked = 0; 1384 ntx++; 1385 BPF_MTAP(ifp, m); 1386 } 1387 1388 if (ntx > 0) { 1389 if (kicked == 0) 1390 gem_txkick(sc); 1391#ifdef GEM_DEBUG 1392 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d", 1393 device_get_name(sc->sc_dev), sc->sc_txnext); 1394#endif 1395 1396 /* Set a watchdog timer in case the chip flakes out. */ 1397 sc->sc_wdog_timer = 5; 1398#ifdef GEM_DEBUG 1399 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1400 device_get_name(sc->sc_dev), __func__, 1401 sc->sc_wdog_timer); 1402#endif 1403 } 1404} 1405 1406static void 1407gem_tint(struct gem_softc *sc) 1408{ 1409 struct ifnet *ifp = sc->sc_ifp; 1410 struct gem_txsoft *txs; 1411 int progress; 1412 uint32_t txlast; 1413#ifdef GEM_DEBUG 1414 int i; 1415 1416 GEM_LOCK_ASSERT(sc, MA_OWNED); 1417 1418 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1419#endif 1420 1421 /* 1422 * Go through our TX list and free mbufs for those 1423 * frames that have been transmitted. 1424 */ 1425 progress = 0; 1426 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1427 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1428#ifdef GEM_DEBUG 1429 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1430 printf(" txsoft %p transmit chain:\n", txs); 1431 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1432 printf("descriptor %d: ", i); 1433 printf("gd_flags: 0x%016llx\t", 1434 (long long)GEM_DMA_READ(sc, 1435 sc->sc_txdescs[i].gd_flags)); 1436 printf("gd_addr: 0x%016llx\n", 1437 (long long)GEM_DMA_READ(sc, 1438 sc->sc_txdescs[i].gd_addr)); 1439 if (i == txs->txs_lastdesc) 1440 break; 1441 } 1442 } 1443#endif 1444 1445 /* 1446 * In theory, we could harvest some descriptors before 1447 * the ring is empty, but that's a bit complicated. 1448 * 1449 * GEM_TX_COMPLETION points to the last descriptor 1450 * processed + 1. 1451 */ 1452 txlast = GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION); 1453#ifdef GEM_DEBUG 1454 CTR4(KTR_GEM, "%s: txs->txs_firstdesc = %d, " 1455 "txs->txs_lastdesc = %d, txlast = %d", 1456 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1457#endif 1458 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1459 if ((txlast >= txs->txs_firstdesc) && 1460 (txlast <= txs->txs_lastdesc)) 1461 break; 1462 } else { 1463 /* Ick -- this command wraps. */ 1464 if ((txlast >= txs->txs_firstdesc) || 1465 (txlast <= txs->txs_lastdesc)) 1466 break; 1467 } 1468 1469#ifdef GEM_DEBUG 1470 CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); 1471#endif 1472 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1473 1474 sc->sc_txfree += txs->txs_ndescs; 1475 1476 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1477 BUS_DMASYNC_POSTWRITE); 1478 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1479 if (txs->txs_mbuf != NULL) { 1480 m_freem(txs->txs_mbuf); 1481 txs->txs_mbuf = NULL; 1482 } 1483 1484 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1485 1486 ifp->if_opackets++; 1487 progress = 1; 1488 } 1489 1490#ifdef GEM_DEBUG 1491 CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " 1492 "GEM_TX_COMPLETION %x", 1493 __func__, GEM_BANK1_READ_4(sc, GEM_TX_STATE_MACHINE), 1494 ((long long)GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_HI) << 32) | 1495 GEM_BANK1_READ_4(sc, GEM_TX_DATA_PTR_LO), 1496 GEM_BANK1_READ_4(sc, GEM_TX_COMPLETION)); 1497#endif 1498 1499 if (progress) { 1500 if (sc->sc_txfree == GEM_NTXDESC - 1) 1501 sc->sc_txwin = 0; 1502 1503 /* 1504 * We freed some descriptors, so reset IFF_DRV_OACTIVE 1505 * and restart. 1506 */ 1507 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1508 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1509 sc->sc_wdog_timer = 0; 1510 gem_start_locked(ifp); 1511 } 1512 1513#ifdef GEM_DEBUG 1514 CTR3(KTR_GEM, "%s: %s: watchdog %d", 1515 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1516#endif 1517} 1518 1519#ifdef GEM_RINT_TIMEOUT 1520static void 1521gem_rint_timeout(void *arg) 1522{ 1523 struct gem_softc *sc = arg; 1524 1525 GEM_LOCK_ASSERT(sc, MA_OWNED); 1526 1527 gem_rint(sc); 1528} 1529#endif 1530 1531static void 1532gem_rint(struct gem_softc *sc) 1533{ 1534 struct ifnet *ifp = sc->sc_ifp; 1535 struct mbuf *m; 1536 uint64_t rxstat; 1537 uint32_t rxcomp; 1538 1539 GEM_LOCK_ASSERT(sc, MA_OWNED); 1540 1541#ifdef GEM_RINT_TIMEOUT 1542 callout_stop(&sc->sc_rx_ch); 1543#endif 1544#ifdef GEM_DEBUG 1545 CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); 1546#endif 1547 1548 /* 1549 * Read the completion register once. This limits 1550 * how long the following loop can execute. 1551 */ 1552 rxcomp = GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION); 1553#ifdef GEM_DEBUG 1554 CTR3(KTR_GEM, "%s: sc->sc_rxptr %d, complete %d", 1555 __func__, sc->sc_rxptr, rxcomp); 1556#endif 1557 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1558 for (; sc->sc_rxptr != rxcomp;) { 1559 m = sc->sc_rxsoft[sc->sc_rxptr].rxs_mbuf; 1560 rxstat = GEM_DMA_READ(sc, 1561 sc->sc_rxdescs[sc->sc_rxptr].gd_flags); 1562 1563 if (rxstat & GEM_RD_OWN) { 1564#ifdef GEM_RINT_TIMEOUT 1565 /* 1566 * The descriptor is still marked as owned, although 1567 * it is supposed to have completed. This has been 1568 * observed on some machines. Just exiting here 1569 * might leave the packet sitting around until another 1570 * one arrives to trigger a new interrupt, which is 1571 * generally undesirable, so set up a timeout. 1572 */ 1573 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS, 1574 gem_rint_timeout, sc); 1575#endif 1576 m = NULL; 1577 goto kickit; 1578 } 1579 1580 if (rxstat & GEM_RD_BAD_CRC) { 1581 ifp->if_ierrors++; 1582 device_printf(sc->sc_dev, "receive error: CRC error\n"); 1583 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1584 m = NULL; 1585 goto kickit; 1586 } 1587 1588#ifdef GEM_DEBUG 1589 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1590 printf(" rxsoft %p descriptor %d: ", 1591 &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); 1592 printf("gd_flags: 0x%016llx\t", 1593 (long long)GEM_DMA_READ(sc, 1594 sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); 1595 printf("gd_addr: 0x%016llx\n", 1596 (long long)GEM_DMA_READ(sc, 1597 sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); 1598 } 1599#endif 1600 1601 /* 1602 * Allocate a new mbuf cluster. If that fails, we are 1603 * out of memory, and must drop the packet and recycle 1604 * the buffer that's already attached to this descriptor. 1605 */ 1606 if (gem_add_rxbuf(sc, sc->sc_rxptr) != 0) { 1607 ifp->if_iqdrops++; 1608 GEM_INIT_RXDESC(sc, sc->sc_rxptr); 1609 m = NULL; 1610 } 1611 1612 kickit: 1613 /* 1614 * Update the RX kick register. This register has to point 1615 * to the descriptor after the last valid one (before the 1616 * current batch) and for optimum performance should be 1617 * incremented in multiples of 4 (the DMA engine fetches/ 1618 * updates descriptors in batches of 4). 1619 */ 1620 sc->sc_rxptr = GEM_NEXTRX(sc->sc_rxptr); 1621 if ((sc->sc_rxptr % 4) == 0) { 1622 GEM_CDSYNC(sc, 1623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1624 GEM_BANK1_WRITE_4(sc, GEM_RX_KICK, 1625 (sc->sc_rxptr + GEM_NRXDESC - 4) & 1626 GEM_NRXDESC_MASK); 1627 } 1628 1629 if (m == NULL) { 1630 if (rxstat & GEM_RD_OWN) 1631 break; 1632 continue; 1633 } 1634 1635 ifp->if_ipackets++; 1636 m->m_data += ETHER_ALIGN; /* first byte offset */ 1637 m->m_pkthdr.rcvif = ifp; 1638 m->m_pkthdr.len = m->m_len = GEM_RD_BUFLEN(rxstat); 1639 1640 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1641 gem_rxcksum(m, rxstat); 1642 1643 /* Pass it on. */ 1644 GEM_UNLOCK(sc); 1645 (*ifp->if_input)(ifp, m); 1646 GEM_LOCK(sc); 1647 } 1648 1649#ifdef GEM_DEBUG 1650 CTR3(KTR_GEM, "%s: done sc->sc_rxptr %d, complete %d", __func__, 1651 sc->sc_rxptr, GEM_BANK1_READ_4(sc, GEM_RX_COMPLETION)); 1652#endif 1653} 1654 1655static int 1656gem_add_rxbuf(struct gem_softc *sc, int idx) 1657{ 1658 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1659 struct mbuf *m; 1660 bus_dma_segment_t segs[1]; 1661 int error, nsegs; 1662 1663 GEM_LOCK_ASSERT(sc, MA_OWNED); 1664 1665 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1666 if (m == NULL) 1667 return (ENOBUFS); 1668 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1669 1670#ifdef GEM_DEBUG 1671 /* Bzero the packet to check DMA. */ 1672 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1673#endif 1674 1675 if (rxs->rxs_mbuf != NULL) { 1676 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1677 BUS_DMASYNC_POSTREAD); 1678 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap); 1679 } 1680 1681 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, 1682 m, segs, &nsegs, BUS_DMA_NOWAIT); 1683 if (error != 0) { 1684 device_printf(sc->sc_dev, 1685 "cannot load RS DMA map %d, error = %d\n", idx, error); 1686 m_freem(m); 1687 return (error); 1688 } 1689 /* If nsegs is wrong then the stack is corrupt. */ 1690 KASSERT(nsegs == 1, 1691 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1692 rxs->rxs_mbuf = m; 1693 rxs->rxs_paddr = segs[0].ds_addr; 1694 1695 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, 1696 BUS_DMASYNC_PREREAD); 1697 1698 GEM_INIT_RXDESC(sc, idx); 1699 1700 return (0); 1701} 1702 1703static void 1704gem_eint(struct gem_softc *sc, u_int status) 1705{ 1706 1707 sc->sc_ifp->if_ierrors++; 1708 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1709 gem_reset_rxdma(sc); 1710 return; 1711 } 1712 1713 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1714 if ((status & GEM_INTR_BERR) != 0) { 1715 if ((sc->sc_flags & GEM_PCI) != 0) 1716 printf(", PCI bus error 0x%x\n", 1717 GEM_BANK1_READ_4(sc, GEM_PCI_ERROR_STATUS)); 1718 else 1719 printf(", SBus error 0x%x\n", 1720 GEM_BANK1_READ_4(sc, GEM_SBUS_STATUS)); 1721 } 1722} 1723 1724void 1725gem_intr(void *v) 1726{ 1727 struct gem_softc *sc = v; 1728 uint32_t status, status2; 1729 1730 GEM_LOCK(sc); 1731 status = GEM_BANK1_READ_4(sc, GEM_STATUS); 1732 1733#ifdef GEM_DEBUG 1734 CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", 1735 device_get_name(sc->sc_dev), __func__, 1736 (status >> GEM_STATUS_TX_COMPLETION_SHFT), (u_int)status); 1737 1738 /* 1739 * PCS interrupts must be cleared, otherwise no traffic is passed! 1740 */ 1741 if ((status & GEM_INTR_PCS) != 0) { 1742 status2 = 1743 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS) | 1744 GEM_BANK1_READ_4(sc, GEM_MII_INTERRUP_STATUS); 1745 if ((status2 & GEM_MII_INTERRUP_LINK) != 0) 1746 device_printf(sc->sc_dev, 1747 "%s: PCS link status changed\n", __func__); 1748 } 1749 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 1750 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_STATUS); 1751 if ((status2 & GEM_MAC_PAUSED) != 0) 1752 device_printf(sc->sc_dev, 1753 "%s: PAUSE received (PAUSE time %d slots)\n", 1754 __func__, GEM_MAC_PAUSE_TIME(status2)); 1755 if ((status2 & GEM_MAC_PAUSE) != 0) 1756 device_printf(sc->sc_dev, 1757 "%s: transited to PAUSE state\n", __func__); 1758 if ((status2 & GEM_MAC_RESUME) != 0) 1759 device_printf(sc->sc_dev, 1760 "%s: transited to non-PAUSE state\n", __func__); 1761 } 1762 if ((status & GEM_INTR_MIF) != 0) 1763 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 1764#endif 1765 1766 if (__predict_false(status & 1767 (GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | GEM_INTR_BERR)) != 0) 1768 gem_eint(sc, status); 1769 1770 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1771 gem_rint(sc); 1772 1773 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1774 gem_tint(sc); 1775 1776 if (__predict_false((status & GEM_INTR_TX_MAC) != 0)) { 1777 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS); 1778 if ((status2 & 1779 ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP | 1780 GEM_MAC_TX_PEAK_EXP)) != 0) 1781 device_printf(sc->sc_dev, 1782 "MAC TX fault, status %x\n", status2); 1783 if ((status2 & 1784 (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) { 1785 sc->sc_ifp->if_oerrors++; 1786 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1787 gem_init_locked(sc); 1788 } 1789 } 1790 if (__predict_false((status & GEM_INTR_RX_MAC) != 0)) { 1791 status2 = GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS); 1792 /* 1793 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 1794 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 1795 * silicon bug so handle them silently. Moreover, it's 1796 * likely that the receiver has hung so we reset it. 1797 */ 1798 if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { 1799 sc->sc_ifp->if_ierrors++; 1800 gem_reset_rxdma(sc); 1801 } else if ((status2 & 1802 ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) 1803 device_printf(sc->sc_dev, 1804 "MAC RX fault, status %x\n", status2); 1805 } 1806 GEM_UNLOCK(sc); 1807} 1808 1809static int 1810gem_watchdog(struct gem_softc *sc) 1811{ 1812 struct ifnet *ifp = sc->sc_ifp; 1813 1814 GEM_LOCK_ASSERT(sc, MA_OWNED); 1815 1816#ifdef GEM_DEBUG 1817 CTR4(KTR_GEM, 1818 "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", 1819 __func__, GEM_BANK1_READ_4(sc, GEM_RX_CONFIG), 1820 GEM_BANK1_READ_4(sc, GEM_MAC_RX_STATUS), 1821 GEM_BANK1_READ_4(sc, GEM_MAC_RX_CONFIG)); 1822 CTR4(KTR_GEM, 1823 "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", 1824 __func__, GEM_BANK1_READ_4(sc, GEM_TX_CONFIG), 1825 GEM_BANK1_READ_4(sc, GEM_MAC_TX_STATUS), 1826 GEM_BANK1_READ_4(sc, GEM_MAC_TX_CONFIG)); 1827#endif 1828 1829 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1830 return (0); 1831 1832 if ((sc->sc_flags & GEM_LINK) != 0) 1833 device_printf(sc->sc_dev, "device timeout\n"); 1834 else if (bootverbose) 1835 device_printf(sc->sc_dev, "device timeout (no link)\n"); 1836 ++ifp->if_oerrors; 1837 1838 /* Try to get more packets going. */ 1839 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1840 gem_init_locked(sc); 1841 gem_start_locked(ifp); 1842 return (EJUSTRETURN); 1843} 1844 1845static void 1846gem_mifinit(struct gem_softc *sc) 1847{ 1848 1849 /* Configure the MIF in frame mode. */ 1850 GEM_BANK1_WRITE_4(sc, GEM_MIF_CONFIG, 1851 GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & ~GEM_MIF_CONFIG_BB_ENA); 1852 GEM_BANK1_BARRIER(sc, GEM_MIF_CONFIG, 4, 1853 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1854} 1855 1856/* 1857 * MII interface 1858 * 1859 * The MII interface supports at least three different operating modes: 1860 * 1861 * Bitbang mode is implemented using data, clock and output enable registers. 1862 * 1863 * Frame mode is implemented by loading a complete frame into the frame 1864 * register and polling the valid bit for completion. 1865 * 1866 * Polling mode uses the frame register but completion is indicated by 1867 * an interrupt. 1868 * 1869 */ 1870int 1871gem_mii_readreg(device_t dev, int phy, int reg) 1872{ 1873 struct gem_softc *sc; 1874 int n; 1875 uint32_t v; 1876 1877#ifdef GEM_DEBUG_PHY 1878 printf("%s: phy %d reg %d\n", __func__, phy, reg); 1879#endif 1880 1881 sc = device_get_softc(dev); 1882 if ((sc->sc_flags & GEM_SERDES) != 0) { 1883 switch (reg) { 1884 case MII_BMCR: 1885 reg = GEM_MII_CONTROL; 1886 break; 1887 case MII_BMSR: 1888 reg = GEM_MII_STATUS; 1889 break; 1890 case MII_PHYIDR1: 1891 case MII_PHYIDR2: 1892 return (0); 1893 case MII_ANAR: 1894 reg = GEM_MII_ANAR; 1895 break; 1896 case MII_ANLPAR: 1897 reg = GEM_MII_ANLPAR; 1898 break; 1899 case MII_EXTSR: 1900 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 1901 default: 1902 device_printf(sc->sc_dev, 1903 "%s: unhandled register %d\n", __func__, reg); 1904 return (0); 1905 } 1906 return (GEM_BANK1_READ_4(sc, reg)); 1907 } 1908 1909 /* Construct the frame command. */ 1910 v = GEM_MIF_FRAME_READ | 1911 (phy << GEM_MIF_PHY_SHIFT) | 1912 (reg << GEM_MIF_REG_SHIFT); 1913 1914 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1915 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1916 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1917 for (n = 0; n < 100; n++) { 1918 DELAY(1); 1919 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1920 if (v & GEM_MIF_FRAME_TA0) 1921 return (v & GEM_MIF_FRAME_DATA); 1922 } 1923 1924 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 1925 return (0); 1926} 1927 1928int 1929gem_mii_writereg(device_t dev, int phy, int reg, int val) 1930{ 1931 struct gem_softc *sc; 1932 int n; 1933 uint32_t v; 1934 1935#ifdef GEM_DEBUG_PHY 1936 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 1937#endif 1938 1939 sc = device_get_softc(dev); 1940 if ((sc->sc_flags & GEM_SERDES) != 0) { 1941 switch (reg) { 1942 case MII_BMSR: 1943 reg = GEM_MII_STATUS; 1944 break; 1945 case MII_BMCR: 1946 reg = GEM_MII_CONTROL; 1947 if ((val & GEM_MII_CONTROL_RESET) == 0) 1948 break; 1949 GEM_BANK1_WRITE_4(sc, GEM_MII_CONTROL, val); 1950 GEM_BANK1_BARRIER(sc, GEM_MII_CONTROL, 4, 1951 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1952 if (!GEM_BANK1_BITWAIT(sc, GEM_MII_CONTROL, 1953 GEM_MII_CONTROL_RESET, 0)) 1954 device_printf(sc->sc_dev, 1955 "cannot reset PCS\n"); 1956 /* FALLTHROUGH */ 1957 case MII_ANAR: 1958 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 0); 1959 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1960 BUS_SPACE_BARRIER_WRITE); 1961 GEM_BANK1_WRITE_4(sc, GEM_MII_ANAR, val); 1962 GEM_BANK1_BARRIER(sc, GEM_MII_ANAR, 4, 1963 BUS_SPACE_BARRIER_WRITE); 1964 GEM_BANK1_WRITE_4(sc, GEM_MII_SLINK_CONTROL, 1965 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_EN_SYNC_D); 1966 GEM_BANK1_BARRIER(sc, GEM_MII_SLINK_CONTROL, 4, 1967 BUS_SPACE_BARRIER_WRITE); 1968 GEM_BANK1_WRITE_4(sc, GEM_MII_CONFIG, 1969 GEM_MII_CONFIG_ENABLE); 1970 GEM_BANK1_BARRIER(sc, GEM_MII_CONFIG, 4, 1971 BUS_SPACE_BARRIER_WRITE); 1972 return (0); 1973 case MII_ANLPAR: 1974 reg = GEM_MII_ANLPAR; 1975 break; 1976 default: 1977 device_printf(sc->sc_dev, 1978 "%s: unhandled register %d\n", __func__, reg); 1979 return (0); 1980 } 1981 GEM_BANK1_WRITE_4(sc, reg, val); 1982 GEM_BANK1_BARRIER(sc, reg, 4, 1983 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1984 return (0); 1985 } 1986 1987 /* Construct the frame command. */ 1988 v = GEM_MIF_FRAME_WRITE | 1989 (phy << GEM_MIF_PHY_SHIFT) | 1990 (reg << GEM_MIF_REG_SHIFT) | 1991 (val & GEM_MIF_FRAME_DATA); 1992 1993 GEM_BANK1_WRITE_4(sc, GEM_MIF_FRAME, v); 1994 GEM_BANK1_BARRIER(sc, GEM_MIF_FRAME, 4, 1995 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1996 for (n = 0; n < 100; n++) { 1997 DELAY(1); 1998 v = GEM_BANK1_READ_4(sc, GEM_MIF_FRAME); 1999 if (v & GEM_MIF_FRAME_TA0) 2000 return (1); 2001 } 2002 2003 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2004 return (0); 2005} 2006 2007void 2008gem_mii_statchg(device_t dev) 2009{ 2010 struct gem_softc *sc; 2011 int gigabit; 2012 uint32_t rxcfg, txcfg, v; 2013 2014 sc = device_get_softc(dev); 2015 2016 GEM_LOCK_ASSERT(sc, MA_OWNED); 2017 2018#ifdef GEM_DEBUG 2019 if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) 2020 device_printf(sc->sc_dev, "%s: status change\n", __func__); 2021#endif 2022 2023 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2024 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2025 sc->sc_flags |= GEM_LINK; 2026 else 2027 sc->sc_flags &= ~GEM_LINK; 2028 2029 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2030 case IFM_1000_SX: 2031 case IFM_1000_LX: 2032 case IFM_1000_CX: 2033 case IFM_1000_T: 2034 gigabit = 1; 2035 break; 2036 default: 2037 gigabit = 0; 2038 } 2039 2040 /* 2041 * The configuration done here corresponds to the steps F) and 2042 * G) and as far as enabling of RX and TX MAC goes also step H) 2043 * of the initialization sequence outlined in section 3.2.1 of 2044 * the GEM Gigabit Ethernet ASIC Specification. 2045 */ 2046 2047 rxcfg = sc->sc_mac_rxcfg; 2048 rxcfg &= ~GEM_MAC_RX_CARR_EXTEND; 2049 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2050 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2051 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2052 else if (gigabit != 0) { 2053 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2054 txcfg |= GEM_MAC_TX_CARR_EXTEND; 2055 } 2056 (void)gem_disable_tx(sc); 2057 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, txcfg); 2058 (void)gem_disable_rx(sc); 2059 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, rxcfg); 2060 2061 v = GEM_BANK1_READ_4(sc, GEM_MAC_CONTROL_CONFIG) & 2062 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2063 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2064 IFM_ETH_RXPAUSE) != 0) 2065 v |= GEM_MAC_CC_RX_PAUSE; 2066 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2067 IFM_ETH_TXPAUSE) != 0) 2068 v |= GEM_MAC_CC_TX_PAUSE; 2069 GEM_BANK1_WRITE_4(sc, GEM_MAC_CONTROL_CONFIG, v); 2070 2071 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2072 gigabit != 0) 2073 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2074 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2075 else 2076 GEM_BANK1_WRITE_4(sc, GEM_MAC_SLOT_TIME, 2077 GEM_MAC_SLOT_TIME_NORMAL); 2078 2079 /* XIF Configuration */ 2080 v = GEM_MAC_XIF_LINK_LED; 2081 v |= GEM_MAC_XIF_TX_MII_ENA; 2082 if ((sc->sc_flags & GEM_SERDES) == 0) { 2083 if ((GEM_BANK1_READ_4(sc, GEM_MIF_CONFIG) & 2084 GEM_MIF_CONFIG_PHY_SEL) != 0) { 2085 /* External MII needs echo disable if half duplex. */ 2086 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2087 IFM_FDX) == 0) 2088 v |= GEM_MAC_XIF_ECHO_DISABL; 2089 } else 2090 /* 2091 * Internal MII needs buffer enable. 2092 * XXX buffer enable makes only sense for an 2093 * external PHY. 2094 */ 2095 v |= GEM_MAC_XIF_MII_BUF_ENA; 2096 } 2097 if (gigabit != 0) 2098 v |= GEM_MAC_XIF_GMII_MODE; 2099 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2100 v |= GEM_MAC_XIF_FDPLX_LED; 2101 GEM_BANK1_WRITE_4(sc, GEM_MAC_XIF_CONFIG, v); 2102 2103 sc->sc_mac_rxcfg = rxcfg; 2104 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2105 (sc->sc_flags & GEM_LINK) != 0) { 2106 GEM_BANK1_WRITE_4(sc, GEM_MAC_TX_CONFIG, 2107 txcfg | GEM_MAC_TX_ENABLE); 2108 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, 2109 rxcfg | GEM_MAC_RX_ENABLE); 2110 } 2111} 2112 2113int 2114gem_mediachange(struct ifnet *ifp) 2115{ 2116 struct gem_softc *sc = ifp->if_softc; 2117 int error; 2118 2119 /* XXX add support for serial media. */ 2120 2121 GEM_LOCK(sc); 2122 error = mii_mediachg(sc->sc_mii); 2123 GEM_UNLOCK(sc); 2124 return (error); 2125} 2126 2127void 2128gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2129{ 2130 struct gem_softc *sc = ifp->if_softc; 2131 2132 GEM_LOCK(sc); 2133 if ((ifp->if_flags & IFF_UP) == 0) { 2134 GEM_UNLOCK(sc); 2135 return; 2136 } 2137 2138 mii_pollstat(sc->sc_mii); 2139 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2140 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2141 GEM_UNLOCK(sc); 2142} 2143 2144static int 2145gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2146{ 2147 struct gem_softc *sc = ifp->if_softc; 2148 struct ifreq *ifr = (struct ifreq *)data; 2149 int error; 2150 2151 error = 0; 2152 switch (cmd) { 2153 case SIOCSIFFLAGS: 2154 GEM_LOCK(sc); 2155 if ((ifp->if_flags & IFF_UP) != 0) { 2156 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2157 ((ifp->if_flags ^ sc->sc_ifflags) & 2158 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2159 gem_setladrf(sc, 1); 2160 else 2161 gem_init_locked(sc); 2162 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2163 gem_stop(ifp, 0); 2164 if ((ifp->if_flags & IFF_LINK0) != 0) 2165 sc->sc_csum_features |= CSUM_UDP; 2166 else 2167 sc->sc_csum_features &= ~CSUM_UDP; 2168 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2169 ifp->if_hwassist = sc->sc_csum_features; 2170 sc->sc_ifflags = ifp->if_flags; 2171 GEM_UNLOCK(sc); 2172 break; 2173 case SIOCADDMULTI: 2174 case SIOCDELMULTI: 2175 GEM_LOCK(sc); 2176 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2177 gem_setladrf(sc, 1); 2178 GEM_UNLOCK(sc); 2179 break; 2180 case SIOCGIFMEDIA: 2181 case SIOCSIFMEDIA: 2182 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2183 break; 2184 case SIOCSIFCAP: 2185 GEM_LOCK(sc); 2186 ifp->if_capenable = ifr->ifr_reqcap; 2187 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2188 ifp->if_hwassist = sc->sc_csum_features; 2189 else 2190 ifp->if_hwassist = 0; 2191 GEM_UNLOCK(sc); 2192 break; 2193 default: 2194 error = ether_ioctl(ifp, cmd, data); 2195 break; 2196 } 2197 2198 return (error); 2199} 2200 2201static void 2202gem_setladrf(struct gem_softc *sc, u_int enable) 2203{ 2204 struct ifnet *ifp = sc->sc_ifp; 2205 struct ifmultiaddr *inm; 2206 int i; 2207 uint32_t hash[16]; 2208 uint32_t crc, v; 2209 2210 GEM_LOCK_ASSERT(sc, MA_OWNED); 2211 2212 /* 2213 * Turn off the RX MAC and the hash filter as required by the Sun GEM 2214 * programming restrictions. 2215 */ 2216 v = sc->sc_mac_rxcfg & ~GEM_MAC_RX_HASH_FILTER; 2217 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2218 GEM_BANK1_BARRIER(sc, GEM_MAC_RX_CONFIG, 4, 2219 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2220 if (!GEM_BANK1_BITWAIT(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_HASH_FILTER | 2221 GEM_MAC_RX_ENABLE, 0)) 2222 device_printf(sc->sc_dev, 2223 "cannot disable RX MAC or hash filter\n"); 2224 2225 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_PROMISC_GRP); 2226 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2227 v |= GEM_MAC_RX_PROMISCUOUS; 2228 goto chipit; 2229 } 2230 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2231 v |= GEM_MAC_RX_PROMISC_GRP; 2232 goto chipit; 2233 } 2234 2235 /* 2236 * Set up multicast address filter by passing all multicast 2237 * addresses through a crc generator, and then using the high 2238 * order 8 bits as an index into the 256 bit logical address 2239 * filter. The high order 4 bits selects the word, while the 2240 * other 4 bits select the bit within the word (where bit 0 2241 * is the MSB). 2242 */ 2243 2244 /* Clear the hash table. */ 2245 memset(hash, 0, sizeof(hash)); 2246 2247 if_maddr_rlock(ifp); 2248 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2249 if (inm->ifma_addr->sa_family != AF_LINK) 2250 continue; 2251 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2252 inm->ifma_addr), ETHER_ADDR_LEN); 2253 2254 /* We just want the 8 most significant bits. */ 2255 crc >>= 24; 2256 2257 /* Set the corresponding bit in the filter. */ 2258 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2259 } 2260 if_maddr_runlock(ifp); 2261 2262 v |= GEM_MAC_RX_HASH_FILTER; 2263 2264 /* Now load the hash table into the chip (if we are using it). */ 2265 for (i = 0; i < 16; i++) 2266 GEM_BANK1_WRITE_4(sc, 2267 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), 2268 hash[i]); 2269 2270 chipit: 2271 sc->sc_mac_rxcfg = v; 2272 if (enable) 2273 v |= GEM_MAC_RX_ENABLE; 2274 GEM_BANK1_WRITE_4(sc, GEM_MAC_RX_CONFIG, v); 2275} 2276