if_ffecreg.h revision 256806
115645Sjoerg/*- 215645Sjoerg * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 31592Srgrimes * All rights reserved. 41592Srgrimes * 51592Srgrimes * Redistribution and use in source and binary forms, with or without 61592Srgrimes * modification, are permitted provided that the following conditions 71592Srgrimes * are met: 81592Srgrimes * 1. Redistributions of source code must retain the above copyright 91592Srgrimes * notice, this list of conditions and the following disclaimer. 101592Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111592Srgrimes * notice, this list of conditions and the following disclaimer in the 121592Srgrimes * documentation and/or other materials provided with the distribution. 131592Srgrimes * 141592Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 151592Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 161592Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 171592Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 181592Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 191592Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 201592Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 211592Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 221592Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 231592Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 241592Srgrimes * SUCH DAMAGE. 251592Srgrimes * 261592Srgrimes */ 271592Srgrimes 281592Srgrimes#ifndef IF_FFECREG_H 291592Srgrimes#define IF_FFECREG_H 301592Srgrimes 311592Srgrimes#include <sys/cdefs.h> 3215645Sjoerg__FBSDID("$FreeBSD: head/sys/dev/ffec/if_ffecreg.h 256806 2013-10-20 21:07:38Z ian $"); 3350476Speter 3415645Sjoerg/* 3515645Sjoerg * Hardware defines for Freescale Fast Ethernet Controller. 361592Srgrimes */ 3779529Sru 381592Srgrimes/* 391592Srgrimes * MAC registers. 401592Srgrimes */ 411592Srgrimes#define FEC_IER_REG 0x0004 4268949Sru#define FEC_IEM_REG 0x0008 431592Srgrimes#define FEC_IER_HBERR (1 << 31) 441592Srgrimes#define FEC_IER_BABR (1 << 30) 4531331Scharnier#define FEC_IER_BABT (1 << 29) 461592Srgrimes#define FEC_IER_GRA (1 << 28) 471592Srgrimes#define FEC_IER_TXF (1 << 27) 481592Srgrimes#define FEC_IER_TXB (1 << 26) 491592Srgrimes#define FEC_IER_RXF (1 << 25) 501592Srgrimes#define FEC_IER_RXB (1 << 24) 511592Srgrimes#define FEC_IER_MII (1 << 23) 521592Srgrimes#define FEC_IER_EBERR (1 << 22) 531592Srgrimes#define FEC_IER_LC (1 << 21) 5431331Scharnier#define FEC_IER_RL (1 << 20) 551592Srgrimes#define FEC_IER_UN (1 << 19) 561592Srgrimes#define FEC_IER_PLR (1 << 18) 571592Srgrimes#define FEC_IER_WAKEUP (1 << 17) 581592Srgrimes#define FEC_IER_AVAIL (1 << 16) 591592Srgrimes#define FEC_IER_TIMER (1 << 15) 601592Srgrimes 61116152Syar#define FEC_RDAR_REG 0x0010 621592Srgrimes#define FEC_RDAR_RDAR (1 << 24) 631592Srgrimes 64116152Syar#define FEC_TDAR_REG 0x0014 651592Srgrimes#define FEC_TDAR_TDAR (1 << 24) 661592Srgrimes 671592Srgrimes#define FEC_ECR_REG 0x0024 681592Srgrimes#define FEC_ECR_DBSWP (1 << 8) 691592Srgrimes#define FEC_ECR_STOPEN (1 << 7) 701592Srgrimes#define FEC_ECR_DBGEN (1 << 6) 711592Srgrimes#define FEC_ECR_SPEED (1 << 5) 72116152Syar#define FEC_ECR_EN1588 (1 << 4) 731592Srgrimes#define FEC_ECR_SLEEP (1 << 3) 741592Srgrimes#define FEC_ECR_MAGICEN (1 << 2) 75116152Syar#define FEC_ECR_ETHEREN (1 << 1) 761592Srgrimes#define FEC_ECR_RESET (1 << 0) 7770227Sru 78233510Sjoel#define FEC_MMFR_REG 0x0040 7922208Sdavidn#define FEC_MMFR_ST_SHIFT 30 8045291Speter#define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT) 811592Srgrimes#define FEC_MMFR_OP_SHIFT 28 821592Srgrimes#define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT) 8315645Sjoerg#define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT) 8415645Sjoerg#define FEC_MMFR_PA_SHIFT 23 8515645Sjoerg#define FEC_MMFR_PA_MASK (0x1f << FEC_MMFR_PA_SHIFT) 861592Srgrimes#define FEC_MMFR_RA_SHIFT 18 871592Srgrimes#define FEC_MMFR_RA_MASK (0x1f << FEC_MMFR_RA_SHIFT) 8815645Sjoerg#define FEC_MMFR_TA_SHIFT 16 891592Srgrimes#define FEC_MMFR_TA_VALUE (0x02 << FEC_MMFR_TA_SHIFT) 901592Srgrimes#define FEC_MMFR_DATA_SHIFT 0 911592Srgrimes#define FEC_MMFR_DATA_MASK (0xffff << FEC_MMFR_DATA_SHIFT) 921592Srgrimes 93116152Syar#define FEC_MSCR_REG 0x0044 94116152Syar#define FEC_MSCR_HOLDTIME_SHIFT 8 95116152Syar#define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT) 96116152Syar#define FEC_MSCR_DIS_PRE (1 << 7) 97116152Syar#define FEC_MSCR_MII_SPEED_SHIFT 1 9822208Sdavidn#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT) 9922208Sdavidn 10077874Syar#define FEC_MIBC_REG 0x0064 1011592Srgrimes#define FEC_MIBC_DIS (1 << 31) 1021592Srgrimes#define FEC_MIBC_IDLE (1 << 30) 1031592Srgrimes#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */ 1041592Srgrimes 1051592Srgrimes#define FEC_RCR_REG 0x0084 106116152Syar#define FEC_RCR_GRS (1 << 31) 1071592Srgrimes#define FEC_RCR_NLC (1 << 30) 1081592Srgrimes#define FEC_RCR_MAX_FL_SHIFT 16 1091592Srgrimes#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT) 1101592Srgrimes#define FEC_RCR_CFEN (1 << 15) 1111592Srgrimes#define FEC_RCR_CRCFWD (1 << 14) 1121592Srgrimes#define FEC_RCR_PAUFWD (1 << 13) 1131592Srgrimes#define FEC_RCR_PADEN (1 << 12) 11415645Sjoerg#define FEC_RCR_RMII_10T (1 << 9) 1151592Srgrimes#define FEC_RCR_RMII_MODE (1 << 8) 1161592Srgrimes#define FEC_RCR_RGMII_EN (1 << 6) 1171592Srgrimes#define FEC_RCR_FCE (1 << 5) 1181592Srgrimes#define FEC_RCR_BC_REJ (1 << 4) 1191592Srgrimes#define FEC_RCR_PROM (1 << 3) 1201592Srgrimes#define FEC_RCR_MII_MODE (1 << 2) 1211592Srgrimes#define FEC_RCR_DRT (1 << 1) 122116152Syar#define FEC_RCR_LOOP (1 << 0) 1231592Srgrimes 12415645Sjoerg#define FEC_TCR_REG 0x00c4 1251592Srgrimes#define FEC_TCR_ADDINS (1 << 9) 1261592Srgrimes#define FEC_TCR_ADDSEL_SHIFT 5 1271592Srgrimes#define FEC_TCR_ADDSEL_MASK (0x07 << FEC_TCR_ADDSEL_SHIFT) 12822208Sdavidn#define FEC_TCR_RFC_PAUSE (1 << 4) 12915645Sjoerg#define FEC_TCR_TFC_PAUSE (1 << 3) 13015645Sjoerg#define FEC_TCR_FDEN (1 << 2) 13115645Sjoerg#define FEC_TCR_GTS (1 << 0) 13222208Sdavidn 13335665Ssteve#define FEC_PALR_REG 0x00e4 1341592Srgrimes#define FEC_PALR_PADDR1_SHIFT 0 1351592Srgrimes#define FEC_PALR_PADDR1_MASK (0xffffffff << FEC_PALR_PADDR1_SHIFT) 1361592Srgrimes 1371592Srgrimes#define FEC_PAUR_REG 0x00e8 1381592Srgrimes#define FEC_PAUR_PADDR2_SHIFT 16 1391592Srgrimes#define FEC_PAUR_PADDR2_MASK (0xffff << FEC_PAUR_PADDR2_SHIFT) 1401592Srgrimes#define FEC_PAUR_TYPE_VALUE (0x8808) 1411592Srgrimes 14215645Sjoerg#define FEC_OPD_REG 0x00ec 14315645Sjoerg#define FEC_OPD_PAUSE_DUR_SHIFT 0 14415645Sjoerg#define FEC_OPD_PAUSE_DUR_MASK (0xffff << FEC_OPD_PAUSE_DUR_SHIFT) 1451592Srgrimes 1461592Srgrimes#define FEC_IAUR_REG 0x0118 1471592Srgrimes#define FEC_IALR_REG 0x011c 1481592Srgrimes 1491592Srgrimes#define FEC_GAUR_REG 0x0120 15015645Sjoerg#define FEC_GALR_REG 0x0124 15164076Snsayer 1521592Srgrimes#define FEC_TFWR_REG 0x0144 15315645Sjoerg#define FEC_TFWR_STRFWD (1 << 8) 1541592Srgrimes#define FEC_TFWR_TWFR_SHIFT 0 15515645Sjoerg#define FEC_TFWR_TWFR_MASK (0x3f << FEC_TFWR_TWFR_SHIFT) 15615645Sjoerg#define FEC_TFWR_TWFR_128BYTE (0x02 << FEC_TFWR_TWFR_SHIFT) 15715645Sjoerg 1581592Srgrimes#define FEC_RDSR_REG 0x0180 1591592Srgrimes 1601592Srgrimes#define FEC_TDSR_REG 0x0184 1611592Srgrimes 1621592Srgrimes#define FEC_MRBR_REG 0x0188 1631592Srgrimes#define FEC_MRBR_R_BUF_SIZE_SHIFT 0 1641592Srgrimes#define FEC_MRBR_R_BUF_SIZE_MASK (0x3fff << FEC_MRBR_R_BUF_SIZE_SHIFT) 165116482Syar 166116152Syar#define FEC_RSFL_REG 0x0190 167116151Syar#define FEC_RSEM_REG 0x0194 168116151Syar#define FEC_RAEM_REG 0x0198 1691592Srgrimes#define FEC_RAFL_REG 0x019c 1701592Srgrimes#define FEC_TSEM_REG 0x01a0 1711592Srgrimes#define FEC_TAEM_REG 0x01a4 1721592Srgrimes#define FEC_TAFL_REG 0x01a8 1731592Srgrimes#define FEC_TIPG_REG 0x01ac 1741592Srgrimes#define FEC_FTRL_REG 0x01b0 1751592Srgrimes 176116152Syar#define FEC_TACC_REG 0x01c0 177116152Syar#define FEC_TACC_PROCHK (1 << 4) 1781592Srgrimes#define FEC_TACC_IPCHK (1 << 3) 179116152Syar#define FEC_TACC_SHIFT16 (1 << 0) 1801592Srgrimes 1811592Srgrimes#define FEC_RACC_REG 0x01c4 1821592Srgrimes#define FEC_RACC_SHIFT16 (1 << 7) 1831592Srgrimes#define FEC_RACC_LINEDIS (1 << 6) 1841592Srgrimes#define FEC_RACC_PRODIS (1 << 2) 1851592Srgrimes#define FEC_RACC_IPDIS (1 << 1) 1861592Srgrimes#define FEC_RACC_PADREM (1 << 0) 1871592Srgrimes 1881592Srgrimes/* 1891592Srgrimes * Statistics registers 1901592Srgrimes */ 191233510Sjoel#define FEC_RMON_T_DROP 0x200 192116152Syar#define FEC_RMON_T_PACKETS 0x204 1931592Srgrimes#define FEC_RMON_T_BC_PKT 0x208 1941592Srgrimes#define FEC_RMON_T_MC_PKT 0x20C 1951592Srgrimes#define FEC_RMON_T_CRC_ALIGN 0x210 1961592Srgrimes#define FEC_RMON_T_UNDERSIZE 0x214 1971592Srgrimes#define FEC_RMON_T_OVERSIZE 0x218 1981592Srgrimes#define FEC_RMON_T_FRAG 0x21C 19915645Sjoerg#define FEC_RMON_T_JAB 0x220 2001592Srgrimes#define FEC_RMON_T_COL 0x224 2011592Srgrimes#define FEC_RMON_T_P64 0x228 20231331Scharnier#define FEC_RMON_T_P65TO127 0x22C 203101828Sru#define FEC_RMON_T_P128TO255 0x230 20470227Sru#define FEC_RMON_T_P256TO511 0x234 20515645Sjoerg#define FEC_RMON_T_P512TO1023 0x238 20615645Sjoerg#define FEC_RMON_T_P1024TO2047 0x23C 20715645Sjoerg#define FEC_RMON_T_P_GTE2048 0x240 20815645Sjoerg#define FEC_RMON_T_OCTECTS 0x240 20915645Sjoerg#define FEC_IEEE_T_DROP 0x248 21015645Sjoerg#define FEC_IEEE_T_FRAME_OK 0x24C 21115645Sjoerg#define FEC_IEEE_T_1COL 0x250 21215645Sjoerg#define FEC_IEEE_T_MCOL 0x254 21315645Sjoerg#define FEC_IEEE_T_DEF 0x258 2141592Srgrimes#define FEC_IEEE_T_LCOL 0x25C 2151592Srgrimes#define FEC_IEEE_T_EXCOL 0x260 2161592Srgrimes#define FEC_IEEE_T_MACERR 0x264 2171592Srgrimes#define FEC_IEEE_T_CSERR 0x268 2181592Srgrimes#define FEC_IEEE_T_SQE 0x26C 2191592Srgrimes#define FEC_IEEE_T_FDXFC 0x270 2201592Srgrimes#define FEC_IEEE_T_OCTETS_OK 0x274 2211592Srgrimes#define FEC_RMON_R_PACKETS 0x284 2221592Srgrimes#define FEC_RMON_R_BC_PKT 0x288 2231592Srgrimes#define FEC_RMON_R_MC_PKT 0x28C 2241592Srgrimes#define FEC_RMON_R_CRC_ALIGN 0x290 2251592Srgrimes#define FEC_RMON_R_UNDERSIZE 0x294 226116152Syar#define FEC_RMON_R_OVERSIZE 0x298 227116152Syar#define FEC_RMON_R_FRAG 0x29C 228116152Syar#define FEC_RMON_R_JAB 0x2A0 229116152Syar#define FEC_RMON_R_RESVD_0 0x2A4 230116152Syar#define FEC_RMON_R_P64 0x2A8 231116152Syar#define FEC_RMON_R_P65TO127 0x2AC 232116152Syar#define FEC_RMON_R_P128TO255 0x2B0 233116152Syar#define FEC_RMON_R_P256TO511 0x2B4 234116152Syar#define FEC_RMON_R_P512TO1023 0x2B8 235116152Syar#define FEC_RMON_R_P1024TO2047 0x2BC 236116152Syar#define FEC_RMON_R_P_GTE2048 0x2C0 2371592Srgrimes#define FEC_RMON_R_OCTETS 0x2C4 238116152Syar#define FEC_IEEE_R_DROP 0x2C8 2391592Srgrimes#define FEC_IEEE_R_FRAME_OK 0x2CC 2401592Srgrimes#define FEC_IEEE_R_CRC 0x2D0 2411592Srgrimes#define FEC_IEEE_R_ALIGN 0x2D4 24215645Sjoerg#define FEC_IEEE_R_MACERR 0x2D8 243116152Syar#define FEC_IEEE_R_FDXFC 0x2DC 244116152Syar#define FEC_IEEE_R_OCTETS_OK 0x2E0 245116152Syar 24615645Sjoerg#define FEC_MIIGSK_CFGR 0x300 247116152Syar#define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */ 248116153Syar#define FEC_MIIGSK_CFGR_LBMODE (1 << 4) /* loopback mode */ 249116153Syar#define FEC_MIIGSK_CFGR_EMODE (1 << 3) /* echo mode */ 25015645Sjoerg#define FEC_MIIGSK_CFGR_IF_MODE_MASK (0x3 << 0) 251116152Syar#define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0) 252116152Syar#define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0) 25315645Sjoerg 254116152Syar#define FEC_MIIGSK_ENR 0x308 25515645Sjoerg#define FEC_MIIGSK_ENR_READY (1 << 2) 256116153Syar#define FEC_MIIGSK_ENR_EN (1 << 1) 257116153Syar 25815645Sjoerg/* 259116152Syar * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 26015645Sjoerg * layout, but the bits in the flags field have different meanings. 2611592Srgrimes */ 2621592Srgrimesstruct ffec_hwdesc 26315645Sjoerg{ 2641592Srgrimes uint32_t flags_len; 2651592Srgrimes uint32_t buf_paddr; 2661592Srgrimes}; 267116152Syar 268116153Syar#define FEC_TXDESC_READY (1 << 31) 269116153Syar#define FEC_TXDESC_T01 (1 << 30) 2701592Srgrimes#define FEC_TXDESC_WRAP (1 << 29) 2711592Srgrimes#define FEC_TXDESC_T02 (1 << 28) 2721592Srgrimes#define FEC_TXDESC_L (1 << 27) 2731592Srgrimes#define FEC_TXDESC_TC (1 << 26) 2741592Srgrimes#define FEC_TXDESC_ABC (1 << 25) 2751592Srgrimes#define FEC_TXDESC_LEN_MASK (0xffff) 2761592Srgrimes 2771592Srgrimes#define FEC_RXDESC_EMPTY (1 << 31) 278116152Syar#define FEC_RXDESC_R01 (1 << 30) 2791592Srgrimes#define FEC_RXDESC_WRAP (1 << 29) 2801592Srgrimes#define FEC_RXDESC_R02 (1 << 28) 2811592Srgrimes#define FEC_RXDESC_L (1 << 27) 282116152Syar#define FEC_RXDESC_M (1 << 24) 2831592Srgrimes#define FEC_RXDESC_BC (1 << 23) 28435665Ssteve#define FEC_RXDESC_MC (1 << 22) 285116152Syar#define FEC_RXDESC_LG (1 << 21) 286116152Syar#define FEC_RXDESC_NO (1 << 20) 2871592Srgrimes#define FEC_RXDESC_CR (1 << 18) 288116152Syar#define FEC_RXDESC_OV (1 << 17) 28915645Sjoerg#define FEC_RXDESC_TR (1 << 16) 29015645Sjoerg#define FEC_RXDESC_LEN_MASK (0xffff) 29115645Sjoerg 29215645Sjoerg#define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \ 29322208Sdavidn FEC_RXDESC_OV | FEC_RXDESC_TR) 29415645Sjoerg 29577874Syar/* 296116152Syar * The hardware imposes alignment restrictions on various objects involved in 29777874Syar * DMA transfers. These values are expressed in bytes (not bits). 298116152Syar */ 29977874Syar#define FEC_DESC_RING_ALIGN 16 30015645Sjoerg#define FEC_RXBUF_ALIGN 16 30115645Sjoerg#define FEC_TXBUF_ALIGN 16 30215645Sjoerg 30320486Smpp#endif /* IF_FFECREG_H */ 30415645Sjoerg