machfbreg.h revision 146482
1146482Smarius/*- 2146482Smarius * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina. 3146482Smarius * 4146482Smarius * Permission to use, copy, modify, distribute, and sell this software and 5146482Smarius * its documentation for any purpose is hereby granted without fee, 6146482Smarius * provided that the above copyright notice appear in all copies and that 7146482Smarius * both that copyright notice and this permission notice appear in 8146482Smarius * supporting documentation, and that the name of Kevin E. Martin not be 9146482Smarius * used in advertising or publicity pertaining to distribution of the 10146482Smarius * software without specific, written prior permission. Kevin E. Martin 11146482Smarius * makes no representations about the suitability of this software for any 12146482Smarius * purpose. It is provided "as is" without express or implied warranty. 13146482Smarius * 14146482Smarius * KEVIN E. MARTIN, RICKARD E. FAITH, AND TIAGO GONS DISCLAIM ALL 15146482Smarius * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED 16146482Smarius * WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE 17146482Smarius * AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR 18146482Smarius * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, 19146482Smarius * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, 20146482Smarius * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS 21146482Smarius * SOFTWARE. 22146482Smarius * 23146482Smarius * Modified for the Mach-8 by Rickard E. Faith (faith@cs.unc.edu) 24146482Smarius * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu) 25146482Smarius * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu) 26146482Smarius * 27146482Smarius * from: NetBSD: machfbreg.h,v 1.1 2002/10/24 18:15:57 junyoung Exp 28146482Smarius * 29146482Smarius * $FreeBSD: head/sys/dev/fb/machfbreg.h 146482 2005-05-21 20:47:38Z marius $ 30146482Smarius */ 31146482Smarius 32146482Smarius#ifndef _DEV_FB_MACHFB_H_ 33146482Smarius#define _DEV_FB_MACHFB_H_ 34146482Smarius 35146482Smarius/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ 36146482Smarius 37146482Smarius#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 00 */ 38146482Smarius#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 01 */ 39146482Smarius#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 02 */ 40146482Smarius#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 03 */ 41146482Smarius#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 04 */ 42146482Smarius#define CRTC_OFF_PITCH 0x0014 /* Dword offset 05 */ 43146482Smarius#define CRTC_INT_CNTL 0x0018 /* Dword offset 06 */ 44146482Smarius#define CRTC_GEN_CNTL 0x001C /* Dword offset 07 */ 45146482Smarius 46146482Smarius#define DSP_CONFIG 0x0020 /* Dword offset 08 */ 47146482Smarius#define DSP_ON_OFF 0x0024 /* Dword offset 09 */ 48146482Smarius 49146482Smarius#define SHARED_CNTL 0x0038 /* Dword offset 0E */ 50146482Smarius 51146482Smarius#define OVR_CLR 0x0040 /* Dword offset 10 */ 52146482Smarius#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 11 */ 53146482Smarius#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 12 */ 54146482Smarius 55146482Smarius#define CUR_CLR0 0x0060 /* Dword offset 18 */ 56146482Smarius#define CUR_CLR1 0x0064 /* Dword offset 19 */ 57146482Smarius#define CUR_OFFSET 0x0068 /* Dword offset 1A */ 58146482Smarius#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 1B */ 59146482Smarius#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 1C */ 60146482Smarius 61146482Smarius#define HW_DEBUG 0x007C /* Dword offset 1F */ 62146482Smarius 63146482Smarius#define SCRATCH_REG0 0x0080 /* Dword offset 20 */ 64146482Smarius#define SCRATCH_REG1 0x0084 /* Dword offset 21 */ 65146482Smarius 66146482Smarius#define CLOCK_CNTL 0x0090 /* Dword offset 24 */ 67146482Smarius 68146482Smarius#define BUS_CNTL 0x00A0 /* Dword offset 28 */ 69146482Smarius 70146482Smarius#define LCD_INDEX 0x00A4 /* Dword offset 29 (LTPro) */ 71146482Smarius#define LCD_DATA 0x00A8 /* Dword offset 2A (LTPro) */ 72146482Smarius 73146482Smarius#define MEM_CNTL 0x00B0 /* Dword offset 2C */ 74146482Smarius 75146482Smarius#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 2D */ 76146482Smarius#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 2E */ 77146482Smarius 78146482Smarius#define DAC_REGS 0x00C0 /* Dword offset 30 */ 79146482Smarius#define DAC_WINDEX 0x00C0 /* Dword offset 30 */ 80146482Smarius#define DAC_DATA 0x00C1 /* Dword offset 30 */ 81146482Smarius#define DAC_MASK 0x00C2 /* Dword offset 30 */ 82146482Smarius#define DAC_RINDEX 0x00C3 /* Dword offset 30 */ 83146482Smarius#define DAC_CNTL 0x00C4 /* Dword offset 31 */ 84146482Smarius 85146482Smarius#define HORZ_STRETCHING 0x00C8 /* Dword offset 32 (LT) */ 86146482Smarius#define VERT_STRETCHING 0x00CC /* Dword offset 33 (LT) */ 87146482Smarius 88146482Smarius#define GEN_TEST_CNTL 0x00D0 /* Dword offset 34 */ 89146482Smarius 90146482Smarius#define LCD_GEN_CNTL 0x00D4 /* Dword offset 35 (LT) */ 91146482Smarius#define POWER_MANAGEMENT 0x00D8 /* Dword offset 36 (LT) */ 92146482Smarius 93146482Smarius#define CONFIG_CNTL 0x00DC /* Dword offset 37 (CT, ET, VT) */ 94146482Smarius#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 38 */ 95146482Smarius#define CONFIG_STAT0 0x00E4 /* Dword offset 39 */ 96146482Smarius#define CONFIG_STAT1 0x00E8 /* Dword offset 3A */ 97146482Smarius 98146482Smarius 99146482Smarius/* GUI MEMORY MAPPED Registers */ 100146482Smarius 101146482Smarius#define DST_OFF_PITCH 0x0100 /* Dword offset 40 */ 102146482Smarius#define DST_X 0x0104 /* Dword offset 41 */ 103146482Smarius#define DST_Y 0x0108 /* Dword offset 42 */ 104146482Smarius#define DST_Y_X 0x010C /* Dword offset 43 */ 105146482Smarius#define DST_WIDTH 0x0110 /* Dword offset 44 */ 106146482Smarius#define DST_HEIGHT 0x0114 /* Dword offset 45 */ 107146482Smarius#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 46 */ 108146482Smarius#define DST_X_WIDTH 0x011C /* Dword offset 47 */ 109146482Smarius#define DST_BRES_LNTH 0x0120 /* Dword offset 48 */ 110146482Smarius#define DST_BRES_ERR 0x0124 /* Dword offset 49 */ 111146482Smarius#define DST_BRES_INC 0x0128 /* Dword offset 4A */ 112146482Smarius#define DST_BRES_DEC 0x012C /* Dword offset 4B */ 113146482Smarius#define DST_CNTL 0x0130 /* Dword offset 4C */ 114146482Smarius 115146482Smarius#define SRC_OFF_PITCH 0x0180 /* Dword offset 60 */ 116146482Smarius#define SRC_X 0x0184 /* Dword offset 61 */ 117146482Smarius#define SRC_Y 0x0188 /* Dword offset 62 */ 118146482Smarius#define SRC_Y_X 0x018C /* Dword offset 63 */ 119146482Smarius#define SRC_WIDTH1 0x0190 /* Dword offset 64 */ 120146482Smarius#define SRC_HEIGHT1 0x0194 /* Dword offset 65 */ 121146482Smarius#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 66 */ 122146482Smarius#define SRC_X_START 0x019C /* Dword offset 67 */ 123146482Smarius#define SRC_Y_START 0x01A0 /* Dword offset 68 */ 124146482Smarius#define SRC_Y_X_START 0x01A4 /* Dword offset 69 */ 125146482Smarius#define SRC_WIDTH2 0x01A8 /* Dword offset 6A */ 126146482Smarius#define SRC_HEIGHT2 0x01AC /* Dword offset 6B */ 127146482Smarius#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 6C */ 128146482Smarius#define SRC_CNTL 0x01B4 /* Dword offset 6D */ 129146482Smarius 130146482Smarius#define HOST_DATA0 0x0200 /* Dword offset 80 */ 131146482Smarius#define HOST_DATA1 0x0204 /* Dword offset 81 */ 132146482Smarius#define HOST_DATA2 0x0208 /* Dword offset 82 */ 133146482Smarius#define HOST_DATA3 0x020C /* Dword offset 83 */ 134146482Smarius#define HOST_DATA4 0x0210 /* Dword offset 84 */ 135146482Smarius#define HOST_DATA5 0x0214 /* Dword offset 85 */ 136146482Smarius#define HOST_DATA6 0x0218 /* Dword offset 86 */ 137146482Smarius#define HOST_DATA7 0x021C /* Dword offset 87 */ 138146482Smarius#define HOST_DATA8 0x0220 /* Dword offset 88 */ 139146482Smarius#define HOST_DATA9 0x0224 /* Dword offset 89 */ 140146482Smarius#define HOST_DATAA 0x0228 /* Dword offset 8A */ 141146482Smarius#define HOST_DATAB 0x022C /* Dword offset 8B */ 142146482Smarius#define HOST_DATAC 0x0230 /* Dword offset 8C */ 143146482Smarius#define HOST_DATAD 0x0234 /* Dword offset 8D */ 144146482Smarius#define HOST_DATAE 0x0238 /* Dword offset 8E */ 145146482Smarius#define HOST_DATAF 0x023C /* Dword offset 8F */ 146146482Smarius#define HOST_CNTL 0x0240 /* Dword offset 90 */ 147146482Smarius 148146482Smarius#define PAT_REG0 0x0280 /* Dword offset A0 */ 149146482Smarius#define PAT_REG1 0x0284 /* Dword offset A1 */ 150146482Smarius#define PAT_CNTL 0x0288 /* Dword offset A2 */ 151146482Smarius 152146482Smarius#define SC_LEFT 0x02A0 /* Dword offset A8 */ 153146482Smarius#define SC_RIGHT 0x02A4 /* Dword offset A9 */ 154146482Smarius#define SC_LEFT_RIGHT 0x02A8 /* Dword offset AA */ 155146482Smarius#define SC_TOP 0x02AC /* Dword offset AB */ 156146482Smarius#define SC_BOTTOM 0x02B0 /* Dword offset AC */ 157146482Smarius#define SC_TOP_BOTTOM 0x02B4 /* Dword offset AD */ 158146482Smarius 159146482Smarius#define DP_BKGD_CLR 0x02C0 /* Dword offset B0 */ 160146482Smarius#define DP_FRGD_CLR 0x02C4 /* Dword offset B1 */ 161146482Smarius#define DP_WRITE_MASK 0x02C8 /* Dword offset B2 */ 162146482Smarius#define DP_CHAIN_MASK 0x02CC /* Dword offset B3 */ 163146482Smarius#define DP_PIX_WIDTH 0x02D0 /* Dword offset B4 */ 164146482Smarius#define DP_MIX 0x02D4 /* Dword offset B5 */ 165146482Smarius#define DP_SRC 0x02D8 /* Dword offset B6 */ 166146482Smarius 167146482Smarius#define CLR_CMP_CLR 0x0300 /* Dword offset C0 */ 168146482Smarius#define CLR_CMP_MASK 0x0304 /* Dword offset C1 */ 169146482Smarius#define CLR_CMP_CNTL 0x0308 /* Dword offset C2 */ 170146482Smarius 171146482Smarius#define FIFO_STAT 0x0310 /* Dword offset C4 */ 172146482Smarius 173146482Smarius#define CONTEXT_MASK 0x0320 /* Dword offset C8 */ 174146482Smarius#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset CB */ 175146482Smarius 176146482Smarius#define GUI_TRAJ_CNTL 0x0330 /* Dword offset CC */ 177146482Smarius#define GUI_STAT 0x0338 /* Dword offset CE */ 178146482Smarius 179146482Smarius 180146482Smarius/* CRTC control values */ 181146482Smarius 182146482Smarius#define CRTC_HSYNC_NEG 0x00200000 183146482Smarius#define CRTC_VSYNC_NEG 0x00200000 184146482Smarius 185146482Smarius#define CRTC_DBL_SCAN_EN 0x00000001 186146482Smarius#define CRTC_INTERLACE_EN 0x00000002 187146482Smarius#define CRTC_HSYNC_DIS 0x00000004 188146482Smarius#define CRTC_VSYNC_DIS 0x00000008 189146482Smarius#define CRTC_CSYNC_EN 0x00000010 190146482Smarius#define CRTC_PIX_BY_2_EN 0x00000020 191146482Smarius#define CRTC_DISPLAY_DIS 0x00000040 192146482Smarius#define CRTC_VGA_XOVERSCAN 0x00000080 193146482Smarius 194146482Smarius#define CRTC_PIX_WIDTH 0x00000700 195146482Smarius#define CRTC_PIX_WIDTH_4BPP 0x00000100 196146482Smarius#define CRTC_PIX_WIDTH_8BPP 0x00000200 197146482Smarius#define CRTC_PIX_WIDTH_15BPP 0x00000300 198146482Smarius#define CRTC_PIX_WIDTH_16BPP 0x00000400 199146482Smarius#define CRTC_PIX_WIDTH_24BPP 0x00000500 200146482Smarius#define CRTC_PIX_WIDTH_32BPP 0x00000600 201146482Smarius 202146482Smarius#define CRTC_BYTE_PIX_ORDER 0x00000800 203146482Smarius#define CRTC_PIX_ORDER_MSN_LSN 0x00000000 204146482Smarius#define CRTC_PIX_ORDER_LSN_MSN 0x00000800 205146482Smarius 206146482Smarius#define CRTC_FIFO_LWM 0x000f0000 207146482Smarius#define CRTC_LOCK_REGS 0x00400000 208146482Smarius#define CRTC_EXT_DISP_EN 0x01000000 209146482Smarius#define CRTC_EN 0x02000000 210146482Smarius#define CRTC_DISP_REQ_EN 0x04000000 211146482Smarius#define CRTC_VGA_LINEAR 0x08000000 212146482Smarius#define CRTC_VSYNC_FALL_EDGE 0x10000000 213146482Smarius#define CRTC_VGA_TEXT_132 0x20000000 214146482Smarius#define CRTC_CNT_EN 0x40000000 215146482Smarius#define CRTC_CUR_B_TEST 0x80000000 216146482Smarius 217146482Smarius#define CRTC_CRNT_VLINE 0x07f00000 218146482Smarius#define CRTC_VBLANK 0x00000001 219146482Smarius 220146482Smarius/* DAC control values */ 221146482Smarius 222146482Smarius#define DAC_EXT_SEL_RS2 0x01 223146482Smarius#define DAC_EXT_SEL_RS3 0x02 224146482Smarius#define DAC_8BIT_EN 0x00000100 225146482Smarius#define DAC_PIX_DLY_MASK 0x00000600 226146482Smarius#define DAC_PIX_DLY_0NS 0x00000000 227146482Smarius#define DAC_PIX_DLY_2NS 0x00000200 228146482Smarius#define DAC_PIX_DLY_4NS 0x00000400 229146482Smarius#define DAC_BLANK_ADJ_MASK 0x00001800 230146482Smarius#define DAC_BLANK_ADJ_0 0x00000000 231146482Smarius#define DAC_BLANK_ADJ_1 0x00000800 232146482Smarius#define DAC_BLANK_ADJ_2 0x00001000 233146482Smarius 234146482Smarius 235146482Smarius/* Mix control values */ 236146482Smarius 237146482Smarius#define MIX_NOT_DST 0x0000 238146482Smarius#define MIX_0 0x0001 239146482Smarius#define MIX_1 0x0002 240146482Smarius#define MIX_DST 0x0003 241146482Smarius#define MIX_NOT_SRC 0x0004 242146482Smarius#define MIX_XOR 0x0005 243146482Smarius#define MIX_XNOR 0x0006 244146482Smarius#define MIX_SRC 0x0007 245146482Smarius#define MIX_NAND 0x0008 246146482Smarius#define MIX_NOT_SRC_OR_DST 0x0009 247146482Smarius#define MIX_SRC_OR_NOT_DST 0x000a 248146482Smarius#define MIX_OR 0x000b 249146482Smarius#define MIX_AND 0x000c 250146482Smarius#define MIX_SRC_AND_NOT_DST 0x000d 251146482Smarius#define MIX_NOT_SRC_AND_DST 0x000e 252146482Smarius#define MIX_NOR 0x000f 253146482Smarius 254146482Smarius/* Maximum engine dimensions */ 255146482Smarius#define ENGINE_MIN_X 0 256146482Smarius#define ENGINE_MIN_Y 0 257146482Smarius#define ENGINE_MAX_X 4095 258146482Smarius#define ENGINE_MAX_Y 16383 259146482Smarius 260146482Smarius/* Mach64 engine bit constants - these are typically ORed together */ 261146482Smarius 262146482Smarius/* HW_DEBUG register constants */ 263146482Smarius/* For RagePro only... */ 264146482Smarius#define AUTO_FF_DIS 0x000001000 265146482Smarius#define AUTO_BLKWRT_DIS 0x000002000 266146482Smarius 267146482Smarius/* BUS_CNTL register constants */ 268146482Smarius#define BUS_FIFO_ERR_ACK 0x00200000 269146482Smarius#define BUS_HOST_ERR_ACK 0x00800000 270146482Smarius#define BUS_APER_REG_DIS 0x00000010 271146482Smarius 272146482Smarius/* GEN_TEST_CNTL register constants */ 273146482Smarius#define GEN_OVR_OUTPUT_EN 0x20 274146482Smarius#define HWCURSOR_ENABLE 0x80 275146482Smarius#define GUI_ENGINE_ENABLE 0x100 276146482Smarius#define BLOCK_WRITE_ENABLE 0x200 277146482Smarius 278146482Smarius/* DSP_CONFIG register constants */ 279146482Smarius#define DSP_XCLKS_PER_QW 0x00003fff 280146482Smarius#define DSP_LOOP_LATENCY 0x000f0000 281146482Smarius#define DSP_PRECISION 0x00700000 282146482Smarius 283146482Smarius/* DSP_ON_OFF register constants */ 284146482Smarius#define DSP_OFF 0x000007ff 285146482Smarius#define DSP_ON 0x07ff0000 286146482Smarius 287146482Smarius/* SHARED_CNTL register constants */ 288146482Smarius#define CTD_FIFO5 0x01000000 289146482Smarius 290146482Smarius/* CLOCK_CNTL register constants */ 291146482Smarius#define CLOCK_SEL 0x0f 292146482Smarius#define CLOCK_DIV 0x30 293146482Smarius#define CLOCK_DIV1 0x00 294146482Smarius#define CLOCK_DIV2 0x10 295146482Smarius#define CLOCK_DIV4 0x20 296146482Smarius#define CLOCK_STROBE 0x40 297146482Smarius#define PLL_WR_EN 0x02 298146482Smarius 299146482Smarius/* PLL registers */ 300146482Smarius#define PLL_MACRO_CNTL 0x01 301146482Smarius#define PLL_REF_DIV 0x02 302146482Smarius#define PLL_GEN_CNTL 0x03 303146482Smarius#define MCLK_FB_DIV 0x04 304146482Smarius#define PLL_VCLK_CNTL 0x05 305146482Smarius#define VCLK_POST_DIV 0x06 306146482Smarius#define VCLK0_FB_DIV 0x07 307146482Smarius#define VCLK1_FB_DIV 0x08 308146482Smarius#define VCLK2_FB_DIV 0x09 309146482Smarius#define VCLK3_FB_DIV 0x0A 310146482Smarius#define PLL_XCLK_CNTL 0x0B 311146482Smarius#define PLL_TEST_CTRL 0x0E 312146482Smarius#define PLL_TEST_COUNT 0x0F 313146482Smarius 314146482Smarius/* Memory types for CT, ET, VT, GT */ 315146482Smarius#define DRAM 1 316146482Smarius#define EDO_DRAM 2 317146482Smarius#define PSEUDO_EDO 3 318146482Smarius#define SDRAM 4 319146482Smarius#define SGRAM 5 320146482Smarius#define SGRAM32 6 321146482Smarius 322146482Smarius#define DAC_INTERNAL 0x00 323146482Smarius#define DAC_IBMRGB514 0x01 324146482Smarius#define DAC_ATI68875 0x02 325146482Smarius#define DAC_TVP3026_A 0x72 326146482Smarius#define DAC_BT476 0x03 327146482Smarius#define DAC_BT481 0x04 328146482Smarius#define DAC_ATT20C491 0x14 329146482Smarius#define DAC_SC15026 0x24 330146482Smarius#define DAC_MU9C1880 0x34 331146482Smarius#define DAC_IMSG174 0x44 332146482Smarius#define DAC_ATI68860_B 0x05 333146482Smarius#define DAC_ATI68860_C 0x15 334146482Smarius#define DAC_TVP3026_B 0x75 335146482Smarius#define DAC_STG1700 0x06 336146482Smarius#define DAC_ATT498 0x16 337146482Smarius#define DAC_STG1702 0x07 338146482Smarius#define DAC_SC15021 0x17 339146482Smarius#define DAC_ATT21C498 0x27 340146482Smarius#define DAC_STG1703 0x37 341146482Smarius#define DAC_CH8398 0x47 342146482Smarius#define DAC_ATT20C408 0x57 343146482Smarius 344146482Smarius#define CLK_ATI18818_0 0 345146482Smarius#define CLK_ATI18818_1 1 346146482Smarius#define CLK_STG1703 2 347146482Smarius#define CLK_CH8398 3 348146482Smarius#define CLK_INTERNAL 4 349146482Smarius#define CLK_ATT20C408 5 350146482Smarius#define CLK_IBMRGB514 6 351146482Smarius 352146482Smarius/* DST_CNTL register constants */ 353146482Smarius#define DST_X_RIGHT_TO_LEFT 0 354146482Smarius#define DST_X_LEFT_TO_RIGHT 1 355146482Smarius#define DST_Y_BOTTOM_TO_TOP 0 356146482Smarius#define DST_Y_TOP_TO_BOTTOM 2 357146482Smarius#define DST_X_MAJOR 0 358146482Smarius#define DST_Y_MAJOR 4 359146482Smarius#define DST_X_TILE 8 360146482Smarius#define DST_Y_TILE 0x10 361146482Smarius#define DST_LAST_PEL 0x20 362146482Smarius#define DST_POLYGON_ENABLE 0x40 363146482Smarius#define DST_24_ROTATION_ENABLE 0x80 364146482Smarius 365146482Smarius/* SRC_CNTL register constants */ 366146482Smarius#define SRC_PATTERN_ENABLE 1 367146482Smarius#define SRC_ROTATION_ENABLE 2 368146482Smarius#define SRC_LINEAR_ENABLE 4 369146482Smarius#define SRC_BYTE_ALIGN 8 370146482Smarius#define SRC_LINE_X_RIGHT_TO_LEFT 0 371146482Smarius#define SRC_LINE_X_LEFT_TO_RIGHT 0x10 372146482Smarius 373146482Smarius/* HOST_CNTL register constants */ 374146482Smarius#define HOST_BYTE_ALIGN 1 375146482Smarius 376146482Smarius/* DP_CHAIN_MASK register constants */ 377146482Smarius#define DP_CHAIN_4BPP 0x8888 378146482Smarius#define DP_CHAIN_7BPP 0xD2D2 379146482Smarius#define DP_CHAIN_8BPP 0x8080 380146482Smarius#define DP_CHAIN_8BPP_RGB 0x9292 381146482Smarius#define DP_CHAIN_15BPP 0x4210 382146482Smarius#define DP_CHAIN_16BPP 0x8410 383146482Smarius#define DP_CHAIN_24BPP 0x8080 384146482Smarius#define DP_CHAIN_32BPP 0x8080 385146482Smarius 386146482Smarius/* DP_PIX_WIDTH register constants */ 387146482Smarius#define DST_1BPP 0 388146482Smarius#define DST_4BPP 1 389146482Smarius#define DST_8BPP 2 390146482Smarius#define DST_15BPP 3 391146482Smarius#define DST_16BPP 4 392146482Smarius#define DST_32BPP 6 393146482Smarius#define SRC_1BPP 0 394146482Smarius#define SRC_4BPP 0x100 395146482Smarius#define SRC_8BPP 0x200 396146482Smarius#define SRC_15BPP 0x300 397146482Smarius#define SRC_16BPP 0x400 398146482Smarius#define SRC_32BPP 0x600 399146482Smarius#define HOST_1BPP 0 400146482Smarius#define HOST_4BPP 0x10000 401146482Smarius#define HOST_8BPP 0x20000 402146482Smarius#define HOST_15BPP 0x30000 403146482Smarius#define HOST_16BPP 0x40000 404146482Smarius#define HOST_32BPP 0x60000 405146482Smarius#define BYTE_ORDER_MSB_TO_LSB 0 406146482Smarius#define BYTE_ORDER_LSB_TO_MSB 0x1000000 407146482Smarius 408146482Smarius/* DP_SRC register constants */ 409146482Smarius#define BKGD_SRC_BKGD_CLR 0 410146482Smarius#define BKGD_SRC_FRGD_CLR 1 411146482Smarius#define BKGD_SRC_HOST 2 412146482Smarius#define BKGD_SRC_BLIT 3 413146482Smarius#define BKGD_SRC_PATTERN 4 414146482Smarius#define FRGD_SRC_BKGD_CLR 0 415146482Smarius#define FRGD_SRC_FRGD_CLR 0x100 416146482Smarius#define FRGD_SRC_HOST 0x200 417146482Smarius#define FRGD_SRC_BLIT 0x300 418146482Smarius#define FRGD_SRC_PATTERN 0x400 419146482Smarius#define MONO_SRC_ONE 0 420146482Smarius#define MONO_SRC_PATTERN 0x10000 421146482Smarius#define MONO_SRC_HOST 0x20000 422146482Smarius#define MONO_SRC_BLIT 0x30000 423146482Smarius 424146482Smarius/* PCI IDs */ 425146482Smarius#define ATI_VENDOR 0x1002 426146482Smarius#define ATI_MACH64_CT 0x4354 /* Mach64 CT */ 427146482Smarius#define ATI_RAGE_PRO_AGP 0x4742 /* 3D Rage Pro (AGP) */ 428146482Smarius#define ATI_RAGE_PRO_AGP1X 0x4744 /* 3D Rage Pro (AGP 1x) */ 429146482Smarius#define ATI_RAGE_PRO_PCI_B 0x4749 /* 3D Rage Pro Turbo */ 430146482Smarius#define ATI_RAGE_XC_PCI66 0x474c /* Rage XC (PCI66) */ 431146482Smarius#define ATI_RAGE_XL_AGP 0x474d /* Rage XL (AGP) */ 432146482Smarius#define ATI_RAGE_XC_AGP 0x474e /* Rage XC (AGP) */ 433146482Smarius#define ATI_RAGE_XL_PCI66 0x474f /* Rage XL (PCI66) */ 434146482Smarius#define ATI_RAGE_PRO_PCI_P 0x4750 /* 3D Rage Pro */ 435146482Smarius#define ATI_RAGE_PRO_PCI_L 0x4751 /* 3D Rage Pro (limited 3D) */ 436146482Smarius#define ATI_RAGE_XL_PCI 0x4752 /* Rage XL */ 437146482Smarius#define ATI_RAGE_XC_PCI 0x4753 /* Rage XC */ 438146482Smarius#define ATI_RAGE_II 0x4754 /* 3D Rage I/II */ 439146482Smarius#define ATI_RAGE_IIP 0x4755 /* 3D Rage II+ */ 440146482Smarius#define ATI_RAGE_IIC_PCI 0x4756 /* 3D Rage IIC */ 441146482Smarius#define ATI_RAGE_IIC_AGP_B 0x4757 /* 3D Rage IIC (AGP) */ 442146482Smarius#define ATI_RAGE_IIC_AGP_P 0x475a /* 3D Rage IIC (AGP) */ 443146482Smarius#define ATI_RAGE_LT_PRO_AGP 0x4c42 /* 3D Rage LT Pro (AGP 133MHz) */ 444146482Smarius#define ATI_RAGE_MOB_M3_PCI 0x4c45 /* Rage Mobility M3 */ 445146482Smarius#define ATI_RAGE_MOB_M3_AGP 0x4c46 /* Rage Mobility M3 (AGP) */ 446146482Smarius#define ATI_RAGE_LT 0x4c47 /* 3D Rage LT */ 447146482Smarius#define ATI_RAGE_LT_PRO_PCI 0x4c49 /* 3D Rage LT Pro */ 448146482Smarius#define ATI_RAGE_MOBILITY 0x4c4d /* Rage Mobility */ 449146482Smarius#define ATI_RAGE_L_MOBILITY 0x4c4e /* Rage L Mobility */ 450146482Smarius#define ATI_RAGE_LT_PRO 0x4c50 /* 3D Rage LT Pro */ 451146482Smarius#define ATI_RAGE_LT_PRO2 0x4c51 /* 3D Rage LT Pro */ 452146482Smarius#define ATI_RAGE_MOB_M1_PCI 0x4c52 /* Rage Mobility M1 (PCI) */ 453146482Smarius#define ATI_RAGE_L_MOB_M1_PCI 0x4c53 /* Rage L Mobility (PCI) */ 454146482Smarius#define ATI_MACH64_VT 0x5654 /* Mach64 VT */ 455146482Smarius#define ATI_MACH64_VTB 0x5655 /* Mach64 VTB */ 456146482Smarius#define ATI_MACH64_VT4 0x5656 /* Mach64 VT4 */ 457146482Smarius 458146482Smarius#endif /* !_DEV_FB_MACHFB_H_ */ 459