if_et.c revision 226480
1/*- 2 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/et/if_et.c 226480 2011-10-17 19:58:34Z yongari $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/endian.h> 43#include <sys/kernel.h> 44#include <sys/bus.h> 45#include <sys/malloc.h> 46#include <sys/mbuf.h> 47#include <sys/proc.h> 48#include <sys/rman.h> 49#include <sys/module.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/ethernet.h> 55#include <net/if.h> 56#include <net/if_dl.h> 57#include <net/if_types.h> 58#include <net/bpf.h> 59#include <net/if_arp.h> 60#include <net/if_media.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <dev/et/if_etreg.h> 72#include <dev/et/if_etvar.h> 73 74#include "miibus_if.h" 75 76MODULE_DEPEND(et, pci, 1, 1, 1); 77MODULE_DEPEND(et, ether, 1, 1, 1); 78MODULE_DEPEND(et, miibus, 1, 1, 1); 79 80/* Tunables. */ 81static int msi_disable = 0; 82TUNABLE_INT("hw.et.msi_disable", &msi_disable); 83 84#define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 86static int et_probe(device_t); 87static int et_attach(device_t); 88static int et_detach(device_t); 89static int et_shutdown(device_t); 90 91static int et_miibus_readreg(device_t, int, int); 92static int et_miibus_writereg(device_t, int, int, int); 93static void et_miibus_statchg(device_t); 94 95static void et_init_locked(struct et_softc *); 96static void et_init(void *); 97static int et_ioctl(struct ifnet *, u_long, caddr_t); 98static void et_start_locked(struct ifnet *); 99static void et_start(struct ifnet *); 100static void et_watchdog(struct et_softc *); 101static int et_ifmedia_upd_locked(struct ifnet *); 102static int et_ifmedia_upd(struct ifnet *); 103static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 104 105static void et_add_sysctls(struct et_softc *); 106static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 107static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 108 109static void et_intr(void *); 110static void et_enable_intrs(struct et_softc *, uint32_t); 111static void et_disable_intrs(struct et_softc *); 112static void et_rxeof(struct et_softc *); 113static void et_txeof(struct et_softc *); 114 115static int et_dma_alloc(device_t); 116static void et_dma_free(device_t); 117static int et_dma_mem_create(device_t, bus_size_t, bus_dma_tag_t *, 118 void **, bus_addr_t *, bus_dmamap_t *); 119static void et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 120static int et_dma_mbuf_create(device_t); 121static void et_dma_mbuf_destroy(device_t, int, const int[]); 122static void et_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 123static void et_dma_buf_addr(void *, bus_dma_segment_t *, int, 124 bus_size_t, int); 125static int et_init_tx_ring(struct et_softc *); 126static int et_init_rx_ring(struct et_softc *); 127static void et_free_tx_ring(struct et_softc *); 128static void et_free_rx_ring(struct et_softc *); 129static int et_encap(struct et_softc *, struct mbuf **); 130static int et_newbuf(struct et_rxbuf_data *, int, int, int); 131static int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 132static int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 133 134static void et_stop(struct et_softc *); 135static int et_chip_init(struct et_softc *); 136static void et_chip_attach(struct et_softc *); 137static void et_init_mac(struct et_softc *); 138static void et_init_rxmac(struct et_softc *); 139static void et_init_txmac(struct et_softc *); 140static int et_init_rxdma(struct et_softc *); 141static int et_init_txdma(struct et_softc *); 142static int et_start_rxdma(struct et_softc *); 143static int et_start_txdma(struct et_softc *); 144static int et_stop_rxdma(struct et_softc *); 145static int et_stop_txdma(struct et_softc *); 146static int et_enable_txrx(struct et_softc *, int); 147static void et_reset(struct et_softc *); 148static int et_bus_config(struct et_softc *); 149static void et_get_eaddr(device_t, uint8_t[]); 150static void et_setmulti(struct et_softc *); 151static void et_tick(void *); 152static void et_setmedia(struct et_softc *); 153static void et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t); 154 155static const struct et_dev { 156 uint16_t vid; 157 uint16_t did; 158 const char *desc; 159} et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 161 "Agere ET1310 Gigabit Ethernet" }, 162 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 163 "Agere ET1310 Fast Ethernet" }, 164 { 0, 0, NULL } 165}; 166 167static device_method_t et_methods[] = { 168 DEVMETHOD(device_probe, et_probe), 169 DEVMETHOD(device_attach, et_attach), 170 DEVMETHOD(device_detach, et_detach), 171 DEVMETHOD(device_shutdown, et_shutdown), 172 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 DEVMETHOD(miibus_readreg, et_miibus_readreg), 177 DEVMETHOD(miibus_writereg, et_miibus_writereg), 178 DEVMETHOD(miibus_statchg, et_miibus_statchg), 179 180 { 0, 0 } 181}; 182 183static driver_t et_driver = { 184 "et", 185 et_methods, 186 sizeof(struct et_softc) 187}; 188 189static devclass_t et_devclass; 190 191DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 192DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 193 194static int et_rx_intr_npkts = 32; 195static int et_rx_intr_delay = 20; /* x10 usec */ 196static int et_tx_intr_nsegs = 126; 197static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 198 199TUNABLE_INT("hw.et.timer", &et_timer); 200TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 201TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 202TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 203 204struct et_bsize { 205 int bufsize; 206 et_newbuf_t newbuf; 207}; 208 209static const struct et_bsize et_bufsize_std[ET_RX_NRING] = { 210 { .bufsize = ET_RXDMA_CTRL_RING0_128, 211 .newbuf = et_newbuf_hdr }, 212 { .bufsize = ET_RXDMA_CTRL_RING1_2048, 213 .newbuf = et_newbuf_cluster }, 214}; 215 216static int 217et_probe(device_t dev) 218{ 219 const struct et_dev *d; 220 uint16_t did, vid; 221 222 vid = pci_get_vendor(dev); 223 did = pci_get_device(dev); 224 225 for (d = et_devices; d->desc != NULL; ++d) { 226 if (vid == d->vid && did == d->did) { 227 device_set_desc(dev, d->desc); 228 return (0); 229 } 230 } 231 return (ENXIO); 232} 233 234static int 235et_attach(device_t dev) 236{ 237 struct et_softc *sc; 238 struct ifnet *ifp; 239 uint8_t eaddr[ETHER_ADDR_LEN]; 240 int cap, error, msic; 241 242 sc = device_get_softc(dev); 243 sc->dev = dev; 244 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 245 MTX_DEF); 246 247 ifp = sc->ifp = if_alloc(IFT_ETHER); 248 if (ifp == NULL) { 249 device_printf(dev, "can not if_alloc()\n"); 250 error = ENOSPC; 251 goto fail; 252 } 253 254 /* 255 * Initialize tunables 256 */ 257 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 258 sc->sc_rx_intr_delay = et_rx_intr_delay; 259 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 260 sc->sc_timer = et_timer; 261 262 /* Enable bus mastering */ 263 pci_enable_busmaster(dev); 264 265 /* 266 * Allocate IO memory 267 */ 268 sc->sc_mem_rid = ET_PCIR_BAR; 269 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 270 &sc->sc_mem_rid, RF_ACTIVE); 271 if (sc->sc_mem_res == NULL) { 272 device_printf(dev, "can't allocate IO memory\n"); 273 return (ENXIO); 274 } 275 276 msic = 0; 277 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 278 sc->sc_expcap = cap; 279 sc->sc_flags |= ET_FLAG_PCIE; 280 msic = pci_msi_count(dev); 281 if (bootverbose) 282 device_printf(dev, "MSI count: %d\n", msic); 283 } 284 if (msic > 0 && msi_disable == 0) { 285 msic = 1; 286 if (pci_alloc_msi(dev, &msic) == 0) { 287 if (msic == 1) { 288 device_printf(dev, "Using %d MSI message\n", 289 msic); 290 sc->sc_flags |= ET_FLAG_MSI; 291 } else 292 pci_release_msi(dev); 293 } 294 } 295 296 /* 297 * Allocate IRQ 298 */ 299 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 300 sc->sc_irq_rid = 0; 301 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 302 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 303 } else { 304 sc->sc_irq_rid = 1; 305 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 306 &sc->sc_irq_rid, RF_ACTIVE); 307 } 308 if (sc->sc_irq_res == NULL) { 309 device_printf(dev, "can't allocate irq\n"); 310 error = ENXIO; 311 goto fail; 312 } 313 314 error = et_bus_config(sc); 315 if (error) 316 goto fail; 317 318 et_get_eaddr(dev, eaddr); 319 320 CSR_WRITE_4(sc, ET_PM, 321 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 322 323 et_reset(sc); 324 325 et_disable_intrs(sc); 326 327 error = et_dma_alloc(dev); 328 if (error) 329 goto fail; 330 331 ifp->if_softc = sc; 332 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 334 ifp->if_init = et_init; 335 ifp->if_ioctl = et_ioctl; 336 ifp->if_start = et_start; 337 ifp->if_mtu = ETHERMTU; 338 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 339 ifp->if_capenable = ifp->if_capabilities; 340 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 341 IFQ_SET_READY(&ifp->if_snd); 342 343 et_chip_attach(sc); 344 345 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 346 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 347 if (error) { 348 device_printf(dev, "attaching PHYs failed\n"); 349 goto fail; 350 } 351 352 ether_ifattach(ifp, eaddr); 353 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 354 355 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 356 NULL, et_intr, sc, &sc->sc_irq_handle); 357 if (error) { 358 ether_ifdetach(ifp); 359 device_printf(dev, "can't setup intr\n"); 360 goto fail; 361 } 362 363 et_add_sysctls(sc); 364 365 return (0); 366fail: 367 et_detach(dev); 368 return (error); 369} 370 371static int 372et_detach(device_t dev) 373{ 374 struct et_softc *sc = device_get_softc(dev); 375 376 if (device_is_attached(dev)) { 377 struct ifnet *ifp = sc->ifp; 378 379 ET_LOCK(sc); 380 et_stop(sc); 381 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 382 ET_UNLOCK(sc); 383 384 ether_ifdetach(ifp); 385 } 386 387 if (sc->sc_miibus != NULL) 388 device_delete_child(dev, sc->sc_miibus); 389 bus_generic_detach(dev); 390 391 if (sc->sc_irq_res != NULL) { 392 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 393 sc->sc_irq_res); 394 } 395 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 396 pci_release_msi(dev); 397 398 if (sc->sc_mem_res != NULL) { 399 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 400 sc->sc_mem_res); 401 } 402 403 if (sc->ifp != NULL) 404 if_free(sc->ifp); 405 406 et_dma_free(dev); 407 408 mtx_destroy(&sc->sc_mtx); 409 410 return (0); 411} 412 413static int 414et_shutdown(device_t dev) 415{ 416 struct et_softc *sc = device_get_softc(dev); 417 418 ET_LOCK(sc); 419 et_stop(sc); 420 ET_UNLOCK(sc); 421 return (0); 422} 423 424static int 425et_miibus_readreg(device_t dev, int phy, int reg) 426{ 427 struct et_softc *sc = device_get_softc(dev); 428 uint32_t val; 429 int i, ret; 430 431 /* Stop any pending operations */ 432 CSR_WRITE_4(sc, ET_MII_CMD, 0); 433 434 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 435 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 436 CSR_WRITE_4(sc, ET_MII_ADDR, val); 437 438 /* Start reading */ 439 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 440 441#define NRETRY 50 442 443 for (i = 0; i < NRETRY; ++i) { 444 val = CSR_READ_4(sc, ET_MII_IND); 445 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 446 break; 447 DELAY(50); 448 } 449 if (i == NRETRY) { 450 if_printf(sc->ifp, 451 "read phy %d, reg %d timed out\n", phy, reg); 452 ret = 0; 453 goto back; 454 } 455 456#undef NRETRY 457 458 val = CSR_READ_4(sc, ET_MII_STAT); 459 ret = val & ET_MII_STAT_VALUE_MASK; 460 461back: 462 /* Make sure that the current operation is stopped */ 463 CSR_WRITE_4(sc, ET_MII_CMD, 0); 464 return (ret); 465} 466 467static int 468et_miibus_writereg(device_t dev, int phy, int reg, int val0) 469{ 470 struct et_softc *sc = device_get_softc(dev); 471 uint32_t val; 472 int i; 473 474 /* Stop any pending operations */ 475 CSR_WRITE_4(sc, ET_MII_CMD, 0); 476 477 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 478 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 479 CSR_WRITE_4(sc, ET_MII_ADDR, val); 480 481 /* Start writing */ 482 CSR_WRITE_4(sc, ET_MII_CTRL, 483 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 484 485#define NRETRY 100 486 487 for (i = 0; i < NRETRY; ++i) { 488 val = CSR_READ_4(sc, ET_MII_IND); 489 if ((val & ET_MII_IND_BUSY) == 0) 490 break; 491 DELAY(50); 492 } 493 if (i == NRETRY) { 494 if_printf(sc->ifp, 495 "write phy %d, reg %d timed out\n", phy, reg); 496 et_miibus_readreg(dev, phy, reg); 497 } 498 499#undef NRETRY 500 501 /* Make sure that the current operation is stopped */ 502 CSR_WRITE_4(sc, ET_MII_CMD, 0); 503 return (0); 504} 505 506static void 507et_miibus_statchg(device_t dev) 508{ 509 et_setmedia(device_get_softc(dev)); 510} 511 512static int 513et_ifmedia_upd_locked(struct ifnet *ifp) 514{ 515 struct et_softc *sc = ifp->if_softc; 516 struct mii_data *mii = device_get_softc(sc->sc_miibus); 517 struct mii_softc *miisc; 518 519 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 520 PHY_RESET(miisc); 521 mii_mediachg(mii); 522 523 return (0); 524} 525 526static int 527et_ifmedia_upd(struct ifnet *ifp) 528{ 529 struct et_softc *sc = ifp->if_softc; 530 int res; 531 532 ET_LOCK(sc); 533 res = et_ifmedia_upd_locked(ifp); 534 ET_UNLOCK(sc); 535 536 return (res); 537} 538 539static void 540et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 541{ 542 struct et_softc *sc = ifp->if_softc; 543 struct mii_data *mii = device_get_softc(sc->sc_miibus); 544 545 ET_LOCK(sc); 546 mii_pollstat(mii); 547 ifmr->ifm_active = mii->mii_media_active; 548 ifmr->ifm_status = mii->mii_media_status; 549 ET_UNLOCK(sc); 550} 551 552static void 553et_stop(struct et_softc *sc) 554{ 555 struct ifnet *ifp = sc->ifp; 556 557 ET_LOCK_ASSERT(sc); 558 559 callout_stop(&sc->sc_tick); 560 561 et_stop_rxdma(sc); 562 et_stop_txdma(sc); 563 564 et_disable_intrs(sc); 565 566 et_free_tx_ring(sc); 567 et_free_rx_ring(sc); 568 569 et_reset(sc); 570 571 sc->sc_tx = 0; 572 sc->sc_tx_intr = 0; 573 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 574 575 sc->watchdog_timer = 0; 576 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 577} 578 579static int 580et_bus_config(struct et_softc *sc) 581{ 582 uint32_t val, max_plsz; 583 uint16_t ack_latency, replay_timer; 584 585 /* 586 * Test whether EEPROM is valid 587 * NOTE: Read twice to get the correct value 588 */ 589 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 590 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 591 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 592 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 593 return (ENXIO); 594 } 595 596 /* TODO: LED */ 597 598 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 599 return (0); 600 601 /* 602 * Configure ACK latency and replay timer according to 603 * max playload size 604 */ 605 val = pci_read_config(sc->dev, 606 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); 607 max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; 608 609 switch (max_plsz) { 610 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 611 ack_latency = ET_PCIV_ACK_LATENCY_128; 612 replay_timer = ET_PCIV_REPLAY_TIMER_128; 613 break; 614 615 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 616 ack_latency = ET_PCIV_ACK_LATENCY_256; 617 replay_timer = ET_PCIV_REPLAY_TIMER_256; 618 break; 619 620 default: 621 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 622 replay_timer = pci_read_config(sc->dev, 623 ET_PCIR_REPLAY_TIMER, 2); 624 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 625 ack_latency, replay_timer); 626 break; 627 } 628 if (ack_latency != 0) { 629 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 630 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 631 2); 632 } 633 634 /* 635 * Set L0s and L1 latency timer to 2us 636 */ 637 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 638 val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); 639 /* L0s exit latency : 2us */ 640 val |= 0x00005000; 641 /* L1 exit latency : 2us */ 642 val |= 0x00028000; 643 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 644 645 /* 646 * Set max read request size to 2048 bytes 647 */ 648 val = pci_read_config(sc->dev, 649 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 650 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 651 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 652 pci_write_config(sc->dev, 653 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 654 655 return (0); 656} 657 658static void 659et_get_eaddr(device_t dev, uint8_t eaddr[]) 660{ 661 uint32_t val; 662 int i; 663 664 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 665 for (i = 0; i < 4; ++i) 666 eaddr[i] = (val >> (8 * i)) & 0xff; 667 668 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 669 for (; i < ETHER_ADDR_LEN; ++i) 670 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 671} 672 673static void 674et_reset(struct et_softc *sc) 675{ 676 CSR_WRITE_4(sc, ET_MAC_CFG1, 677 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 678 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 679 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 680 681 CSR_WRITE_4(sc, ET_SWRST, 682 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 683 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 684 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 685 686 CSR_WRITE_4(sc, ET_MAC_CFG1, 687 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 688 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 689 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 690} 691 692static void 693et_disable_intrs(struct et_softc *sc) 694{ 695 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 696} 697 698static void 699et_enable_intrs(struct et_softc *sc, uint32_t intrs) 700{ 701 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 702} 703 704static int 705et_dma_alloc(device_t dev) 706{ 707 struct et_softc *sc = device_get_softc(dev); 708 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 709 struct et_txstatus_data *txsd = &sc->sc_tx_status; 710 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 711 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 712 int i, error; 713 714 /* 715 * Create top level DMA tag 716 */ 717 error = bus_dma_tag_create(NULL, 1, 0, 718 BUS_SPACE_MAXADDR_32BIT, 719 BUS_SPACE_MAXADDR, 720 NULL, NULL, 721 MAXBSIZE, 722 BUS_SPACE_UNRESTRICTED, 723 BUS_SPACE_MAXSIZE_32BIT, 724 0, NULL, NULL, &sc->sc_dtag); 725 if (error) { 726 device_printf(dev, "can't create DMA tag\n"); 727 return (error); 728 } 729 730 /* 731 * Create TX ring DMA stuffs 732 */ 733 error = et_dma_mem_create(dev, ET_TX_RING_SIZE, &tx_ring->tr_dtag, 734 (void **)&tx_ring->tr_desc, 735 &tx_ring->tr_paddr, &tx_ring->tr_dmap); 736 if (error) { 737 device_printf(dev, "can't create TX ring DMA stuffs\n"); 738 return (error); 739 } 740 741 /* 742 * Create TX status DMA stuffs 743 */ 744 error = et_dma_mem_create(dev, sizeof(uint32_t), &txsd->txsd_dtag, 745 (void **)&txsd->txsd_status, 746 &txsd->txsd_paddr, &txsd->txsd_dmap); 747 if (error) { 748 device_printf(dev, "can't create TX status DMA stuffs\n"); 749 return (error); 750 } 751 752 /* 753 * Create DMA stuffs for RX rings 754 */ 755 for (i = 0; i < ET_RX_NRING; ++i) { 756 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 757 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 758 759 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 760 761 error = et_dma_mem_create(dev, ET_RX_RING_SIZE, 762 &rx_ring->rr_dtag, 763 (void **)&rx_ring->rr_desc, 764 &rx_ring->rr_paddr, 765 &rx_ring->rr_dmap); 766 if (error) { 767 device_printf(dev, "can't create DMA stuffs for " 768 "the %d RX ring\n", i); 769 return (error); 770 } 771 rx_ring->rr_posreg = rx_ring_posreg[i]; 772 } 773 774 /* 775 * Create RX stat ring DMA stuffs 776 */ 777 error = et_dma_mem_create(dev, ET_RXSTAT_RING_SIZE, 778 &rxst_ring->rsr_dtag, 779 (void **)&rxst_ring->rsr_stat, 780 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap); 781 if (error) { 782 device_printf(dev, "can't create RX stat ring DMA stuffs\n"); 783 return (error); 784 } 785 786 /* 787 * Create RX status DMA stuffs 788 */ 789 error = et_dma_mem_create(dev, sizeof(struct et_rxstatus), 790 &rxsd->rxsd_dtag, 791 (void **)&rxsd->rxsd_status, 792 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap); 793 if (error) { 794 device_printf(dev, "can't create RX status DMA stuffs\n"); 795 return (error); 796 } 797 798 /* 799 * Create mbuf DMA stuffs 800 */ 801 error = et_dma_mbuf_create(dev); 802 if (error) 803 return (error); 804 805 return (0); 806} 807 808static void 809et_dma_free(device_t dev) 810{ 811 struct et_softc *sc = device_get_softc(dev); 812 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 813 struct et_txstatus_data *txsd = &sc->sc_tx_status; 814 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 815 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 816 int i, rx_done[ET_RX_NRING]; 817 818 /* 819 * Destroy TX ring DMA stuffs 820 */ 821 et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc, 822 tx_ring->tr_dmap); 823 824 /* 825 * Destroy TX status DMA stuffs 826 */ 827 et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status, 828 txsd->txsd_dmap); 829 830 /* 831 * Destroy DMA stuffs for RX rings 832 */ 833 for (i = 0; i < ET_RX_NRING; ++i) { 834 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 835 836 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc, 837 rx_ring->rr_dmap); 838 } 839 840 /* 841 * Destroy RX stat ring DMA stuffs 842 */ 843 et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat, 844 rxst_ring->rsr_dmap); 845 846 /* 847 * Destroy RX status DMA stuffs 848 */ 849 et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status, 850 rxsd->rxsd_dmap); 851 852 /* 853 * Destroy mbuf DMA stuffs 854 */ 855 for (i = 0; i < ET_RX_NRING; ++i) 856 rx_done[i] = ET_RX_NDESC; 857 et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done); 858 859 /* 860 * Destroy top level DMA tag 861 */ 862 if (sc->sc_dtag != NULL) 863 bus_dma_tag_destroy(sc->sc_dtag); 864} 865 866static int 867et_dma_mbuf_create(device_t dev) 868{ 869 struct et_softc *sc = device_get_softc(dev); 870 struct et_txbuf_data *tbd = &sc->sc_tx_data; 871 int i, error, rx_done[ET_RX_NRING]; 872 873 /* 874 * Create mbuf DMA tag 875 */ 876 error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 877 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 878 NULL, NULL, 879 ET_JUMBO_FRAMELEN, ET_NSEG_MAX, 880 BUS_SPACE_MAXSIZE_32BIT, 881 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_mbuf_dtag); 882 if (error) { 883 device_printf(dev, "can't create mbuf DMA tag\n"); 884 return (error); 885 } 886 887 /* 888 * Create spare DMA map for RX mbufs 889 */ 890 error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, &sc->sc_mbuf_tmp_dmap); 891 if (error) { 892 device_printf(dev, "can't create spare mbuf DMA map\n"); 893 bus_dma_tag_destroy(sc->sc_mbuf_dtag); 894 sc->sc_mbuf_dtag = NULL; 895 return (error); 896 } 897 898 /* 899 * Create DMA maps for RX mbufs 900 */ 901 bzero(rx_done, sizeof(rx_done)); 902 for (i = 0; i < ET_RX_NRING; ++i) { 903 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 904 int j; 905 906 for (j = 0; j < ET_RX_NDESC; ++j) { 907 error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, 908 &rbd->rbd_buf[j].rb_dmap); 909 if (error) { 910 device_printf(dev, "can't create %d RX mbuf " 911 "for %d RX ring\n", j, i); 912 rx_done[i] = j; 913 et_dma_mbuf_destroy(dev, 0, rx_done); 914 return (error); 915 } 916 } 917 rx_done[i] = ET_RX_NDESC; 918 919 rbd->rbd_softc = sc; 920 rbd->rbd_ring = &sc->sc_rx_ring[i]; 921 } 922 923 /* 924 * Create DMA maps for TX mbufs 925 */ 926 for (i = 0; i < ET_TX_NDESC; ++i) { 927 error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, 928 &tbd->tbd_buf[i].tb_dmap); 929 if (error) { 930 device_printf(dev, "can't create %d TX mbuf " 931 "DMA map\n", i); 932 et_dma_mbuf_destroy(dev, i, rx_done); 933 return (error); 934 } 935 } 936 937 return (0); 938} 939 940static void 941et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[]) 942{ 943 struct et_softc *sc = device_get_softc(dev); 944 struct et_txbuf_data *tbd = &sc->sc_tx_data; 945 int i; 946 947 if (sc->sc_mbuf_dtag == NULL) 948 return; 949 950 /* 951 * Destroy DMA maps for RX mbufs 952 */ 953 for (i = 0; i < ET_RX_NRING; ++i) { 954 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 955 int j; 956 957 for (j = 0; j < rx_done[i]; ++j) { 958 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 959 960 KASSERT(rb->rb_mbuf == NULL, 961 ("RX mbuf in %d RX ring is not freed yet\n", i)); 962 bus_dmamap_destroy(sc->sc_mbuf_dtag, rb->rb_dmap); 963 } 964 } 965 966 /* 967 * Destroy DMA maps for TX mbufs 968 */ 969 for (i = 0; i < tx_done; ++i) { 970 struct et_txbuf *tb = &tbd->tbd_buf[i]; 971 972 KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n")); 973 bus_dmamap_destroy(sc->sc_mbuf_dtag, tb->tb_dmap); 974 } 975 976 /* 977 * Destroy spare mbuf DMA map 978 */ 979 bus_dmamap_destroy(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap); 980 981 /* 982 * Destroy mbuf DMA tag 983 */ 984 bus_dma_tag_destroy(sc->sc_mbuf_dtag); 985 sc->sc_mbuf_dtag = NULL; 986} 987 988static int 989et_dma_mem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag, 990 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap) 991{ 992 struct et_softc *sc = device_get_softc(dev); 993 int error; 994 995 error = bus_dma_tag_create(sc->sc_dtag, ET_ALIGN, 0, 996 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 997 NULL, NULL, 998 size, 1, BUS_SPACE_MAXSIZE_32BIT, 999 0, NULL, NULL, dtag); 1000 if (error) { 1001 device_printf(dev, "can't create DMA tag\n"); 1002 return (error); 1003 } 1004 1005 error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1006 dmap); 1007 if (error) { 1008 device_printf(dev, "can't allocate DMA mem\n"); 1009 bus_dma_tag_destroy(*dtag); 1010 *dtag = NULL; 1011 return (error); 1012 } 1013 1014 error = bus_dmamap_load(*dtag, *dmap, *addr, size, 1015 et_dma_ring_addr, paddr, BUS_DMA_WAITOK); 1016 if (error) { 1017 device_printf(dev, "can't load DMA mem\n"); 1018 bus_dmamem_free(*dtag, *addr, *dmap); 1019 bus_dma_tag_destroy(*dtag); 1020 *dtag = NULL; 1021 return (error); 1022 } 1023 return (0); 1024} 1025 1026static void 1027et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 1028{ 1029 if (dtag != NULL) { 1030 bus_dmamap_unload(dtag, dmap); 1031 bus_dmamem_free(dtag, addr, dmap); 1032 bus_dma_tag_destroy(dtag); 1033 } 1034} 1035 1036static void 1037et_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1038{ 1039 KASSERT(nseg == 1, ("too many segments\n")); 1040 *((bus_addr_t *)arg) = seg->ds_addr; 1041} 1042 1043static void 1044et_chip_attach(struct et_softc *sc) 1045{ 1046 uint32_t val; 1047 1048 /* 1049 * Perform minimal initialization 1050 */ 1051 1052 /* Disable loopback */ 1053 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1054 1055 /* Reset MAC */ 1056 CSR_WRITE_4(sc, ET_MAC_CFG1, 1057 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1058 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1059 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1060 1061 /* 1062 * Setup half duplex mode 1063 */ 1064 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1065 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1066 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1067 ET_MAC_HDX_EXC_DEFER; 1068 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1069 1070 /* Clear MAC control */ 1071 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1072 1073 /* Reset MII */ 1074 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1075 1076 /* Bring MAC out of reset state */ 1077 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1078 1079 /* Enable memory controllers */ 1080 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1081} 1082 1083static void 1084et_intr(void *xsc) 1085{ 1086 struct et_softc *sc = xsc; 1087 struct ifnet *ifp; 1088 uint32_t intrs; 1089 1090 ET_LOCK(sc); 1091 ifp = sc->ifp; 1092 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1093 ET_UNLOCK(sc); 1094 return; 1095 } 1096 1097 et_disable_intrs(sc); 1098 1099 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 1100 intrs &= ET_INTRS; 1101 if (intrs == 0) /* Not interested */ 1102 goto back; 1103 1104 if (intrs & ET_INTR_RXEOF) 1105 et_rxeof(sc); 1106 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 1107 et_txeof(sc); 1108 if (intrs & ET_INTR_TIMER) 1109 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1110back: 1111 et_enable_intrs(sc, ET_INTRS); 1112 ET_UNLOCK(sc); 1113} 1114 1115static void 1116et_init_locked(struct et_softc *sc) 1117{ 1118 struct ifnet *ifp = sc->ifp; 1119 const struct et_bsize *arr; 1120 int error, i; 1121 1122 ET_LOCK_ASSERT(sc); 1123 1124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1125 return; 1126 1127 et_stop(sc); 1128 1129 arr = et_bufsize_std; 1130 for (i = 0; i < ET_RX_NRING; ++i) { 1131 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize; 1132 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf; 1133 } 1134 1135 error = et_init_tx_ring(sc); 1136 if (error) 1137 goto back; 1138 1139 error = et_init_rx_ring(sc); 1140 if (error) 1141 goto back; 1142 1143 error = et_chip_init(sc); 1144 if (error) 1145 goto back; 1146 1147 error = et_enable_txrx(sc, 1); 1148 if (error) 1149 goto back; 1150 1151 et_enable_intrs(sc, ET_INTRS); 1152 1153 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1154 1155 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1156 1157 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1159back: 1160 if (error) 1161 et_stop(sc); 1162} 1163 1164static void 1165et_init(void *xsc) 1166{ 1167 struct et_softc *sc = xsc; 1168 1169 ET_LOCK(sc); 1170 et_init_locked(sc); 1171 ET_UNLOCK(sc); 1172} 1173 1174static int 1175et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1176{ 1177 struct et_softc *sc = ifp->if_softc; 1178 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1179 struct ifreq *ifr = (struct ifreq *)data; 1180 int error = 0, mask, max_framelen; 1181 1182/* XXX LOCKSUSED */ 1183 switch (cmd) { 1184 case SIOCSIFFLAGS: 1185 ET_LOCK(sc); 1186 if (ifp->if_flags & IFF_UP) { 1187 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1188 if ((ifp->if_flags ^ sc->sc_if_flags) & 1189 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1190 et_setmulti(sc); 1191 } else { 1192 et_init_locked(sc); 1193 } 1194 } else { 1195 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1196 et_stop(sc); 1197 } 1198 sc->sc_if_flags = ifp->if_flags; 1199 ET_UNLOCK(sc); 1200 break; 1201 1202 case SIOCSIFMEDIA: 1203 case SIOCGIFMEDIA: 1204 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1205 break; 1206 1207 case SIOCADDMULTI: 1208 case SIOCDELMULTI: 1209 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1210 ET_LOCK(sc); 1211 et_setmulti(sc); 1212 ET_UNLOCK(sc); 1213 error = 0; 1214 } 1215 break; 1216 1217 case SIOCSIFMTU: 1218#if 0 1219 if (sc->sc_flags & ET_FLAG_JUMBO) 1220 max_framelen = ET_JUMBO_FRAMELEN; 1221 else 1222#endif 1223 max_framelen = MCLBYTES - 1; 1224 1225 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1226 error = EOPNOTSUPP; 1227 break; 1228 } 1229 1230 if (ifp->if_mtu != ifr->ifr_mtu) { 1231 ifp->if_mtu = ifr->ifr_mtu; 1232 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1233 et_init(sc); 1234 } 1235 break; 1236 1237 case SIOCSIFCAP: 1238 ET_LOCK(sc); 1239 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1240 if ((mask & IFCAP_TXCSUM) != 0 && 1241 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1242 ifp->if_capenable ^= IFCAP_TXCSUM; 1243 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1244 ifp->if_hwassist |= ET_CSUM_FEATURES; 1245 else 1246 ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1247 } 1248 ET_UNLOCK(sc); 1249 break; 1250 1251 default: 1252 error = ether_ioctl(ifp, cmd, data); 1253 break; 1254 } 1255 return (error); 1256} 1257 1258static void 1259et_start_locked(struct ifnet *ifp) 1260{ 1261 struct et_softc *sc = ifp->if_softc; 1262 struct et_txbuf_data *tbd; 1263 int trans; 1264 1265 ET_LOCK_ASSERT(sc); 1266 tbd = &sc->sc_tx_data; 1267 1268 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 1269 return; 1270 1271 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) 1272 return; 1273 1274 trans = 0; 1275 for (;;) { 1276 struct mbuf *m; 1277 1278 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1279 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1280 break; 1281 } 1282 1283 IFQ_DEQUEUE(&ifp->if_snd, m); 1284 if (m == NULL) 1285 break; 1286 1287 if (et_encap(sc, &m)) { 1288 ifp->if_oerrors++; 1289 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1290 break; 1291 } 1292 trans = 1; 1293 1294 BPF_MTAP(ifp, m); 1295 } 1296 1297 if (trans) 1298 sc->watchdog_timer = 5; 1299} 1300 1301static void 1302et_start(struct ifnet *ifp) 1303{ 1304 struct et_softc *sc = ifp->if_softc; 1305 1306 ET_LOCK(sc); 1307 et_start_locked(ifp); 1308 ET_UNLOCK(sc); 1309} 1310 1311static void 1312et_watchdog(struct et_softc *sc) 1313{ 1314 ET_LOCK_ASSERT(sc); 1315 1316 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1317 return; 1318 1319 if_printf(sc->ifp, "watchdog timed out\n"); 1320 1321 sc->ifp->if_oerrors++; 1322 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1323 et_init_locked(sc); 1324 et_start_locked(sc->ifp); 1325} 1326 1327static int 1328et_stop_rxdma(struct et_softc *sc) 1329{ 1330 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1331 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1332 1333 DELAY(5); 1334 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1335 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1336 return (ETIMEDOUT); 1337 } 1338 return (0); 1339} 1340 1341static int 1342et_stop_txdma(struct et_softc *sc) 1343{ 1344 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1345 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1346 return (0); 1347} 1348 1349static void 1350et_free_tx_ring(struct et_softc *sc) 1351{ 1352 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1353 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1354 int i; 1355 1356 for (i = 0; i < ET_TX_NDESC; ++i) { 1357 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1358 1359 if (tb->tb_mbuf != NULL) { 1360 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1361 m_freem(tb->tb_mbuf); 1362 tb->tb_mbuf = NULL; 1363 } 1364 } 1365 1366 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1367 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1368 BUS_DMASYNC_PREWRITE); 1369} 1370 1371static void 1372et_free_rx_ring(struct et_softc *sc) 1373{ 1374 int n; 1375 1376 for (n = 0; n < ET_RX_NRING; ++n) { 1377 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1378 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1379 int i; 1380 1381 for (i = 0; i < ET_RX_NDESC; ++i) { 1382 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1383 1384 if (rb->rb_mbuf != NULL) { 1385 bus_dmamap_unload(sc->sc_mbuf_dtag, 1386 rb->rb_dmap); 1387 m_freem(rb->rb_mbuf); 1388 rb->rb_mbuf = NULL; 1389 } 1390 } 1391 1392 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1393 bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap, 1394 BUS_DMASYNC_PREWRITE); 1395 } 1396} 1397 1398static void 1399et_setmulti(struct et_softc *sc) 1400{ 1401 struct ifnet *ifp; 1402 uint32_t hash[4] = { 0, 0, 0, 0 }; 1403 uint32_t rxmac_ctrl, pktfilt; 1404 struct ifmultiaddr *ifma; 1405 int i, count; 1406 1407 ET_LOCK_ASSERT(sc); 1408 ifp = sc->ifp; 1409 1410 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1411 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1412 1413 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1414 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1415 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1416 goto back; 1417 } 1418 1419 count = 0; 1420 if_maddr_rlock(ifp); 1421 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1422 uint32_t *hp, h; 1423 1424 if (ifma->ifma_addr->sa_family != AF_LINK) 1425 continue; 1426 1427 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1428 ifma->ifma_addr), ETHER_ADDR_LEN); 1429 h = (h & 0x3f800000) >> 23; 1430 1431 hp = &hash[0]; 1432 if (h >= 32 && h < 64) { 1433 h -= 32; 1434 hp = &hash[1]; 1435 } else if (h >= 64 && h < 96) { 1436 h -= 64; 1437 hp = &hash[2]; 1438 } else if (h >= 96) { 1439 h -= 96; 1440 hp = &hash[3]; 1441 } 1442 *hp |= (1 << h); 1443 1444 ++count; 1445 } 1446 if_maddr_runlock(ifp); 1447 1448 for (i = 0; i < 4; ++i) 1449 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1450 1451 if (count > 0) 1452 pktfilt |= ET_PKTFILT_MCAST; 1453 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1454back: 1455 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1456 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1457} 1458 1459static int 1460et_chip_init(struct et_softc *sc) 1461{ 1462 struct ifnet *ifp = sc->ifp; 1463 uint32_t rxq_end; 1464 int error, frame_len, rxmem_size; 1465 1466 /* 1467 * Split 16Kbytes internal memory between TX and RX 1468 * according to frame length. 1469 */ 1470 frame_len = ET_FRAMELEN(ifp->if_mtu); 1471 if (frame_len < 2048) { 1472 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1473 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1474 rxmem_size = ET_MEM_SIZE / 2; 1475 } else { 1476 rxmem_size = ET_MEM_SIZE - 1477 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1478 } 1479 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1480 1481 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1482 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1483 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1484 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1485 1486 /* No loopback */ 1487 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1488 1489 /* Clear MSI configure */ 1490 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1491 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1492 1493 /* Disable timer */ 1494 CSR_WRITE_4(sc, ET_TIMER, 0); 1495 1496 /* Initialize MAC */ 1497 et_init_mac(sc); 1498 1499 /* Enable memory controllers */ 1500 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1501 1502 /* Initialize RX MAC */ 1503 et_init_rxmac(sc); 1504 1505 /* Initialize TX MAC */ 1506 et_init_txmac(sc); 1507 1508 /* Initialize RX DMA engine */ 1509 error = et_init_rxdma(sc); 1510 if (error) 1511 return (error); 1512 1513 /* Initialize TX DMA engine */ 1514 error = et_init_txdma(sc); 1515 if (error) 1516 return (error); 1517 1518 return (0); 1519} 1520 1521static int 1522et_init_tx_ring(struct et_softc *sc) 1523{ 1524 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1525 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1526 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1527 1528 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1529 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1530 BUS_DMASYNC_PREWRITE); 1531 1532 tbd->tbd_start_index = 0; 1533 tbd->tbd_start_wrap = 0; 1534 tbd->tbd_used = 0; 1535 1536 bzero(txsd->txsd_status, sizeof(uint32_t)); 1537 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1538 BUS_DMASYNC_PREWRITE); 1539 return (0); 1540} 1541 1542static int 1543et_init_rx_ring(struct et_softc *sc) 1544{ 1545 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1546 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1547 int n; 1548 1549 for (n = 0; n < ET_RX_NRING; ++n) { 1550 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1551 int i, error; 1552 1553 for (i = 0; i < ET_RX_NDESC; ++i) { 1554 error = rbd->rbd_newbuf(rbd, i, 1); 1555 if (error) { 1556 if_printf(sc->ifp, "%d ring %d buf, " 1557 "newbuf failed: %d\n", n, i, error); 1558 return (error); 1559 } 1560 } 1561 } 1562 1563 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1564 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1565 BUS_DMASYNC_PREWRITE); 1566 1567 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1568 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1569 BUS_DMASYNC_PREWRITE); 1570 1571 return (0); 1572} 1573 1574static void 1575et_dma_buf_addr(void *xctx, bus_dma_segment_t *segs, int nsegs, 1576 bus_size_t mapsz __unused, int error) 1577{ 1578 struct et_dmamap_ctx *ctx = xctx; 1579 int i; 1580 1581 if (error) 1582 return; 1583 1584 if (nsegs > ctx->nsegs) { 1585 ctx->nsegs = 0; 1586 return; 1587 } 1588 1589 ctx->nsegs = nsegs; 1590 for (i = 0; i < nsegs; ++i) 1591 ctx->segs[i] = segs[i]; 1592} 1593 1594static int 1595et_init_rxdma(struct et_softc *sc) 1596{ 1597 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1598 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1599 struct et_rxdesc_ring *rx_ring; 1600 int error; 1601 1602 error = et_stop_rxdma(sc); 1603 if (error) { 1604 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1605 return (error); 1606 } 1607 1608 /* 1609 * Install RX status 1610 */ 1611 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1612 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1613 1614 /* 1615 * Install RX stat ring 1616 */ 1617 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1618 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1619 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1620 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1621 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1622 1623 /* Match ET_RXSTAT_POS */ 1624 rxst_ring->rsr_index = 0; 1625 rxst_ring->rsr_wrap = 0; 1626 1627 /* 1628 * Install the 2nd RX descriptor ring 1629 */ 1630 rx_ring = &sc->sc_rx_ring[1]; 1631 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1632 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1633 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1634 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1635 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1636 1637 /* Match ET_RX_RING1_POS */ 1638 rx_ring->rr_index = 0; 1639 rx_ring->rr_wrap = 1; 1640 1641 /* 1642 * Install the 1st RX descriptor ring 1643 */ 1644 rx_ring = &sc->sc_rx_ring[0]; 1645 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1646 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1647 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1648 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1649 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1650 1651 /* Match ET_RX_RING0_POS */ 1652 rx_ring->rr_index = 0; 1653 rx_ring->rr_wrap = 1; 1654 1655 /* 1656 * RX intr moderation 1657 */ 1658 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1659 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1660 1661 return (0); 1662} 1663 1664static int 1665et_init_txdma(struct et_softc *sc) 1666{ 1667 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1668 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1669 int error; 1670 1671 error = et_stop_txdma(sc); 1672 if (error) { 1673 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1674 return (error); 1675 } 1676 1677 /* 1678 * Install TX descriptor ring 1679 */ 1680 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1681 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1682 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1683 1684 /* 1685 * Install TX status 1686 */ 1687 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1688 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1689 1690 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1691 1692 /* Match ET_TX_READY_POS */ 1693 tx_ring->tr_ready_index = 0; 1694 tx_ring->tr_ready_wrap = 0; 1695 1696 return (0); 1697} 1698 1699static void 1700et_init_mac(struct et_softc *sc) 1701{ 1702 struct ifnet *ifp = sc->ifp; 1703 const uint8_t *eaddr = IF_LLADDR(ifp); 1704 uint32_t val; 1705 1706 /* Reset MAC */ 1707 CSR_WRITE_4(sc, ET_MAC_CFG1, 1708 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1709 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1710 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1711 1712 /* 1713 * Setup inter packet gap 1714 */ 1715 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1716 (88 << ET_IPG_NONB2B_2_SHIFT) | 1717 (80 << ET_IPG_MINIFG_SHIFT) | 1718 (96 << ET_IPG_B2B_SHIFT); 1719 CSR_WRITE_4(sc, ET_IPG, val); 1720 1721 /* 1722 * Setup half duplex mode 1723 */ 1724 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1725 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1726 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1727 ET_MAC_HDX_EXC_DEFER; 1728 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1729 1730 /* Clear MAC control */ 1731 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1732 1733 /* Reset MII */ 1734 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1735 1736 /* 1737 * Set MAC address 1738 */ 1739 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1740 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1741 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1742 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1743 1744 /* Set max frame length */ 1745 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1746 1747 /* Bring MAC out of reset state */ 1748 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1749} 1750 1751static void 1752et_init_rxmac(struct et_softc *sc) 1753{ 1754 struct ifnet *ifp = sc->ifp; 1755 const uint8_t *eaddr = IF_LLADDR(ifp); 1756 uint32_t val; 1757 int i; 1758 1759 /* Disable RX MAC and WOL */ 1760 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1761 1762 /* 1763 * Clear all WOL related registers 1764 */ 1765 for (i = 0; i < 3; ++i) 1766 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1767 for (i = 0; i < 20; ++i) 1768 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1769 1770 /* 1771 * Set WOL source address. XXX is this necessary? 1772 */ 1773 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1774 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1775 val = (eaddr[0] << 8) | eaddr[1]; 1776 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1777 1778 /* Clear packet filters */ 1779 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1780 1781 /* No ucast filtering */ 1782 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1783 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1784 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1785 1786 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1787 /* 1788 * In order to transmit jumbo packets greater than 1789 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1790 * RX MAC and RX DMA needs to be reduced in size to 1791 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1792 * order to implement this, we must use "cut through" 1793 * mode in the RX MAC, which chops packets down into 1794 * segments. In this case we selected 256 bytes, 1795 * since this is the size of the PCI-Express TLP's 1796 * that the ET1310 uses. 1797 */ 1798 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1799 ET_RXMAC_MC_SEGSZ_ENABLE; 1800 } else { 1801 val = 0; 1802 } 1803 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1804 1805 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1806 1807 /* Initialize RX MAC management register */ 1808 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1809 1810 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1811 1812 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1813 ET_RXMAC_MGT_PASS_ECRC | 1814 ET_RXMAC_MGT_PASS_ELEN | 1815 ET_RXMAC_MGT_PASS_ETRUNC | 1816 ET_RXMAC_MGT_CHECK_PKT); 1817 1818 /* 1819 * Configure runt filtering (may not work on certain chip generation) 1820 */ 1821 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1822 ET_PKTFILT_MINLEN_MASK; 1823 val |= ET_PKTFILT_FRAG; 1824 CSR_WRITE_4(sc, ET_PKTFILT, val); 1825 1826 /* Enable RX MAC but leave WOL disabled */ 1827 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1828 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1829 1830 /* 1831 * Setup multicast hash and allmulti/promisc mode 1832 */ 1833 et_setmulti(sc); 1834} 1835 1836static void 1837et_init_txmac(struct et_softc *sc) 1838{ 1839 /* Disable TX MAC and FC(?) */ 1840 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1841 1842 /* No flow control yet */ 1843 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1844 1845 /* Enable TX MAC but leave FC(?) diabled */ 1846 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1847 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1848} 1849 1850static int 1851et_start_rxdma(struct et_softc *sc) 1852{ 1853 uint32_t val = 0; 1854 1855 val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 1856 ET_RXDMA_CTRL_RING0_ENABLE; 1857 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 1858 ET_RXDMA_CTRL_RING1_ENABLE; 1859 1860 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1861 1862 DELAY(5); 1863 1864 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1865 if_printf(sc->ifp, "can't start RX DMA engine\n"); 1866 return (ETIMEDOUT); 1867 } 1868 return (0); 1869} 1870 1871static int 1872et_start_txdma(struct et_softc *sc) 1873{ 1874 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1875 return (0); 1876} 1877 1878static int 1879et_enable_txrx(struct et_softc *sc, int media_upd) 1880{ 1881 struct ifnet *ifp = sc->ifp; 1882 uint32_t val; 1883 int i, error; 1884 1885 val = CSR_READ_4(sc, ET_MAC_CFG1); 1886 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1887 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1888 ET_MAC_CFG1_LOOPBACK); 1889 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1890 1891 if (media_upd) 1892 et_ifmedia_upd_locked(ifp); 1893 else 1894 et_setmedia(sc); 1895 1896#define NRETRY 50 1897 1898 for (i = 0; i < NRETRY; ++i) { 1899 val = CSR_READ_4(sc, ET_MAC_CFG1); 1900 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1901 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1902 break; 1903 1904 DELAY(100); 1905 } 1906 if (i == NRETRY) { 1907 if_printf(ifp, "can't enable RX/TX\n"); 1908 return (0); 1909 } 1910 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 1911 1912#undef NRETRY 1913 1914 /* 1915 * Start TX/RX DMA engine 1916 */ 1917 error = et_start_rxdma(sc); 1918 if (error) 1919 return (error); 1920 1921 error = et_start_txdma(sc); 1922 if (error) 1923 return (error); 1924 1925 return (0); 1926} 1927 1928static void 1929et_rxeof(struct et_softc *sc) 1930{ 1931 struct ifnet *ifp; 1932 struct et_rxstatus_data *rxsd; 1933 struct et_rxstat_ring *rxst_ring; 1934 uint32_t rxs_stat_ring, rxst_info2; 1935 int rxst_wrap, rxst_index; 1936 1937 ET_LOCK_ASSERT(sc); 1938 ifp = sc->ifp; 1939 rxsd = &sc->sc_rx_status; 1940 rxst_ring = &sc->sc_rxstat_ring; 1941 1942 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 1943 return; 1944 1945 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1946 BUS_DMASYNC_POSTREAD); 1947 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1948 BUS_DMASYNC_POSTREAD); 1949 1950 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 1951 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1952 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 1953 ET_RXS_STATRING_INDEX_SHIFT; 1954 1955 while (rxst_index != rxst_ring->rsr_index || 1956 rxst_wrap != rxst_ring->rsr_wrap) { 1957 struct et_rxbuf_data *rbd; 1958 struct et_rxdesc_ring *rx_ring; 1959 struct et_rxstat *st; 1960 struct mbuf *m; 1961 int buflen, buf_idx, ring_idx; 1962 uint32_t rxstat_pos, rxring_pos; 1963 1964 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 1965 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1966 rxst_info2 = le32toh(st->rxst_info2); 1967 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 1968 ET_RXST_INFO2_LEN_SHIFT; 1969 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 1970 ET_RXST_INFO2_BUFIDX_SHIFT; 1971 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 1972 ET_RXST_INFO2_RINGIDX_SHIFT; 1973 1974 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1975 rxst_ring->rsr_index = 0; 1976 rxst_ring->rsr_wrap ^= 1; 1977 } 1978 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 1979 if (rxst_ring->rsr_wrap) 1980 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1981 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1982 1983 if (ring_idx >= ET_RX_NRING) { 1984 ifp->if_ierrors++; 1985 if_printf(ifp, "invalid ring index %d\n", ring_idx); 1986 continue; 1987 } 1988 if (buf_idx >= ET_RX_NDESC) { 1989 ifp->if_ierrors++; 1990 if_printf(ifp, "invalid buf index %d\n", buf_idx); 1991 continue; 1992 } 1993 1994 rbd = &sc->sc_rx_data[ring_idx]; 1995 m = rbd->rbd_buf[buf_idx].rb_mbuf; 1996 1997 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1998 if (buflen < ETHER_CRC_LEN) { 1999 m_freem(m); 2000 m = NULL; 2001 ifp->if_ierrors++; 2002 } else { 2003 m->m_pkthdr.len = m->m_len = 2004 buflen - ETHER_CRC_LEN; 2005 m->m_pkthdr.rcvif = ifp; 2006 ifp->if_ipackets++; 2007 ET_UNLOCK(sc); 2008 ifp->if_input(ifp, m); 2009 ET_LOCK(sc); 2010 } 2011 } else { 2012 ifp->if_ierrors++; 2013 } 2014 m = NULL; /* Catch invalid reference */ 2015 2016 rx_ring = &sc->sc_rx_ring[ring_idx]; 2017 2018 if (buf_idx != rx_ring->rr_index) { 2019 if_printf(ifp, "WARNING!! ring %d, " 2020 "buf_idx %d, rr_idx %d\n", 2021 ring_idx, buf_idx, rx_ring->rr_index); 2022 } 2023 2024 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2025 if (++rx_ring->rr_index == ET_RX_NDESC) { 2026 rx_ring->rr_index = 0; 2027 rx_ring->rr_wrap ^= 1; 2028 } 2029 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2030 if (rx_ring->rr_wrap) 2031 rxring_pos |= ET_RX_RING_POS_WRAP; 2032 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2033 } 2034} 2035 2036static int 2037et_encap(struct et_softc *sc, struct mbuf **m0) 2038{ 2039 struct mbuf *m = *m0; 2040 bus_dma_segment_t segs[ET_NSEG_MAX]; 2041 struct et_dmamap_ctx ctx; 2042 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 2043 struct et_txbuf_data *tbd = &sc->sc_tx_data; 2044 struct et_txdesc *td; 2045 bus_dmamap_t map; 2046 int error, maxsegs, first_idx, last_idx, i; 2047 uint32_t csum_flags, tx_ready_pos, last_td_ctrl2; 2048 2049 maxsegs = ET_TX_NDESC - tbd->tbd_used; 2050 if (maxsegs > ET_NSEG_MAX) 2051 maxsegs = ET_NSEG_MAX; 2052 KASSERT(maxsegs >= ET_NSEG_SPARE, 2053 ("not enough spare TX desc (%d)\n", maxsegs)); 2054 2055 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2056 first_idx = tx_ring->tr_ready_index; 2057 map = tbd->tbd_buf[first_idx].tb_dmap; 2058 2059 ctx.nsegs = maxsegs; 2060 ctx.segs = segs; 2061 error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m, 2062 et_dma_buf_addr, &ctx, BUS_DMA_NOWAIT); 2063 if (!error && ctx.nsegs == 0) { 2064 bus_dmamap_unload(sc->sc_mbuf_dtag, map); 2065 error = EFBIG; 2066 } 2067 if (error && error != EFBIG) { 2068 if_printf(sc->ifp, "can't load TX mbuf, error %d\n", 2069 error); 2070 goto back; 2071 } 2072 if (error) { /* error == EFBIG */ 2073 struct mbuf *m_new; 2074 2075 m_new = m_defrag(m, M_DONTWAIT); 2076 if (m_new == NULL) { 2077 if_printf(sc->ifp, "can't defrag TX mbuf\n"); 2078 error = ENOBUFS; 2079 goto back; 2080 } else { 2081 *m0 = m = m_new; 2082 } 2083 2084 ctx.nsegs = maxsegs; 2085 ctx.segs = segs; 2086 error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m, 2087 et_dma_buf_addr, &ctx, 2088 BUS_DMA_NOWAIT); 2089 if (error || ctx.nsegs == 0) { 2090 if (ctx.nsegs == 0) { 2091 bus_dmamap_unload(sc->sc_mbuf_dtag, map); 2092 error = EFBIG; 2093 } 2094 if_printf(sc->ifp, 2095 "can't load defraged TX mbuf\n"); 2096 goto back; 2097 } 2098 } 2099 2100 bus_dmamap_sync(sc->sc_mbuf_dtag, map, BUS_DMASYNC_PREWRITE); 2101 2102 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2103 sc->sc_tx += ctx.nsegs; 2104 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2105 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2106 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2107 } 2108 2109 csum_flags = 0; 2110 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2111 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2112 csum_flags |= ET_TDCTRL2_CSUM_IP; 2113 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2114 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2115 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2116 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2117 } 2118 last_idx = -1; 2119 for (i = 0; i < ctx.nsegs; ++i) { 2120 int idx; 2121 2122 idx = (first_idx + i) % ET_TX_NDESC; 2123 td = &tx_ring->tr_desc[idx]; 2124 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2125 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2126 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2127 if (i == ctx.nsegs - 1) { /* Last frag */ 2128 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2129 last_idx = idx; 2130 } else 2131 td->td_ctrl2 = htole32(csum_flags); 2132 2133 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2134 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2135 tx_ring->tr_ready_index = 0; 2136 tx_ring->tr_ready_wrap ^= 1; 2137 } 2138 } 2139 td = &tx_ring->tr_desc[first_idx]; 2140 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); /* First frag */ 2141 2142 MPASS(last_idx >= 0); 2143 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2144 tbd->tbd_buf[last_idx].tb_dmap = map; 2145 tbd->tbd_buf[last_idx].tb_mbuf = m; 2146 2147 tbd->tbd_used += ctx.nsegs; 2148 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2149 2150 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2151 BUS_DMASYNC_PREWRITE); 2152 2153 tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK; 2154 if (tx_ring->tr_ready_wrap) 2155 tx_ready_pos |= ET_TX_READY_POS_WRAP; 2156 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 2157 2158 error = 0; 2159back: 2160 if (error) { 2161 m_freem(m); 2162 *m0 = NULL; 2163 } 2164 return (error); 2165} 2166 2167static void 2168et_txeof(struct et_softc *sc) 2169{ 2170 struct ifnet *ifp; 2171 struct et_txdesc_ring *tx_ring; 2172 struct et_txbuf_data *tbd; 2173 uint32_t tx_done; 2174 int end, wrap; 2175 2176 ET_LOCK_ASSERT(sc); 2177 ifp = sc->ifp; 2178 tx_ring = &sc->sc_tx_ring; 2179 tbd = &sc->sc_tx_data; 2180 2181 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2182 return; 2183 2184 if (tbd->tbd_used == 0) 2185 return; 2186 2187 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2188 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2189 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2190 2191 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2192 struct et_txbuf *tb; 2193 2194 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2195 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2196 2197 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 2198 sizeof(struct et_txdesc)); 2199 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2200 BUS_DMASYNC_PREWRITE); 2201 2202 if (tb->tb_mbuf != NULL) { 2203 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 2204 m_freem(tb->tb_mbuf); 2205 tb->tb_mbuf = NULL; 2206 ifp->if_opackets++; 2207 } 2208 2209 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2210 tbd->tbd_start_index = 0; 2211 tbd->tbd_start_wrap ^= 1; 2212 } 2213 2214 MPASS(tbd->tbd_used > 0); 2215 tbd->tbd_used--; 2216 } 2217 2218 if (tbd->tbd_used == 0) 2219 sc->watchdog_timer = 0; 2220 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 2221 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2222 2223 et_start_locked(ifp); 2224} 2225 2226static void 2227et_tick(void *xsc) 2228{ 2229 struct et_softc *sc = xsc; 2230 struct ifnet *ifp; 2231 struct mii_data *mii; 2232 2233 ET_LOCK_ASSERT(sc); 2234 ifp = sc->ifp; 2235 mii = device_get_softc(sc->sc_miibus); 2236 2237 mii_tick(mii); 2238 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 && 2239 (mii->mii_media_status & IFM_ACTIVE) && 2240 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2241 if_printf(ifp, "Link up, enable TX/RX\n"); 2242 if (et_enable_txrx(sc, 0) == 0) 2243 et_start_locked(ifp); 2244 } 2245 et_watchdog(sc); 2246 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2247} 2248 2249static int 2250et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2251{ 2252 return (et_newbuf(rbd, buf_idx, init, MCLBYTES)); 2253} 2254 2255static int 2256et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2257{ 2258 return (et_newbuf(rbd, buf_idx, init, MHLEN)); 2259} 2260 2261static int 2262et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2263{ 2264 struct et_softc *sc = rbd->rbd_softc; 2265 struct et_rxbuf *rb; 2266 struct mbuf *m; 2267 struct et_dmamap_ctx ctx; 2268 bus_dma_segment_t seg; 2269 bus_dmamap_t dmap; 2270 int error, len; 2271 2272 MPASS(buf_idx < ET_RX_NDESC); 2273 rb = &rbd->rbd_buf[buf_idx]; 2274 2275 m = m_getl(len0, /* init ? M_WAIT :*/ M_DONTWAIT, MT_DATA, M_PKTHDR, &len); 2276 if (m == NULL) { 2277 error = ENOBUFS; 2278 2279 if (init) { 2280 if_printf(sc->ifp, 2281 "m_getl failed, size %d\n", len0); 2282 return (error); 2283 } else { 2284 goto back; 2285 } 2286 } 2287 m->m_len = m->m_pkthdr.len = len; 2288 2289 /* 2290 * Try load RX mbuf into temporary DMA tag 2291 */ 2292 ctx.nsegs = 1; 2293 ctx.segs = &seg; 2294 error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap, m, 2295 et_dma_buf_addr, &ctx, 2296 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2297 if (error || ctx.nsegs == 0) { 2298 if (!error) { 2299 bus_dmamap_unload(sc->sc_mbuf_dtag, 2300 sc->sc_mbuf_tmp_dmap); 2301 error = EFBIG; 2302 if_printf(sc->ifp, "too many segments?!\n"); 2303 } 2304 m_freem(m); 2305 m = NULL; 2306 2307 if (init) { 2308 if_printf(sc->ifp, "can't load RX mbuf\n"); 2309 return (error); 2310 } else { 2311 goto back; 2312 } 2313 } 2314 2315 if (!init) { 2316 bus_dmamap_sync(sc->sc_mbuf_dtag, rb->rb_dmap, 2317 BUS_DMASYNC_POSTREAD); 2318 bus_dmamap_unload(sc->sc_mbuf_dtag, rb->rb_dmap); 2319 } 2320 rb->rb_mbuf = m; 2321 rb->rb_paddr = seg.ds_addr; 2322 2323 /* 2324 * Swap RX buf's DMA map with the loaded temporary one 2325 */ 2326 dmap = rb->rb_dmap; 2327 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2328 sc->sc_mbuf_tmp_dmap = dmap; 2329 2330 error = 0; 2331back: 2332 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2333 return (error); 2334} 2335 2336/* 2337 * Create sysctl tree 2338 */ 2339static void 2340et_add_sysctls(struct et_softc * sc) 2341{ 2342 struct sysctl_ctx_list *ctx; 2343 struct sysctl_oid_list *children; 2344 2345 ctx = device_get_sysctl_ctx(sc->dev); 2346 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2347 2348 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2349 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 2350 "RX IM, # packets per RX interrupt"); 2351 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2352 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 2353 "RX IM, RX interrupt delay (x10 usec)"); 2354 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2355 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2356 "TX IM, # segments per TX interrupt"); 2357 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2358 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2359} 2360 2361static int 2362et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2363{ 2364 struct et_softc *sc = arg1; 2365 struct ifnet *ifp = sc->ifp; 2366 int error = 0, v; 2367 2368 v = sc->sc_rx_intr_npkts; 2369 error = sysctl_handle_int(oidp, &v, 0, req); 2370 if (error || req->newptr == NULL) 2371 goto back; 2372 if (v <= 0) { 2373 error = EINVAL; 2374 goto back; 2375 } 2376 2377 if (sc->sc_rx_intr_npkts != v) { 2378 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2379 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2380 sc->sc_rx_intr_npkts = v; 2381 } 2382back: 2383 return (error); 2384} 2385 2386static int 2387et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2388{ 2389 struct et_softc *sc = arg1; 2390 struct ifnet *ifp = sc->ifp; 2391 int error = 0, v; 2392 2393 v = sc->sc_rx_intr_delay; 2394 error = sysctl_handle_int(oidp, &v, 0, req); 2395 if (error || req->newptr == NULL) 2396 goto back; 2397 if (v <= 0) { 2398 error = EINVAL; 2399 goto back; 2400 } 2401 2402 if (sc->sc_rx_intr_delay != v) { 2403 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2404 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2405 sc->sc_rx_intr_delay = v; 2406 } 2407back: 2408 return (error); 2409} 2410 2411static void 2412et_setmedia(struct et_softc *sc) 2413{ 2414 struct mii_data *mii = device_get_softc(sc->sc_miibus); 2415 uint32_t cfg2, ctrl; 2416 2417 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 2418 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 2419 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 2420 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 2421 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 2422 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 2423 2424 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 2425 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 2426 2427 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 2428 cfg2 |= ET_MAC_CFG2_MODE_GMII; 2429 } else { 2430 cfg2 |= ET_MAC_CFG2_MODE_MII; 2431 ctrl |= ET_MAC_CTRL_MODE_MII; 2432 } 2433 2434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 2435 cfg2 |= ET_MAC_CFG2_FDX; 2436 else 2437 ctrl |= ET_MAC_CTRL_GHDX; 2438 2439 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 2440 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 2441} 2442 2443static void 2444et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr) 2445{ 2446 struct et_rxdesc_ring *rx_ring = rbd->rbd_ring; 2447 struct et_rxdesc *desc; 2448 2449 MPASS(buf_idx < ET_RX_NDESC); 2450 desc = &rx_ring->rr_desc[buf_idx]; 2451 2452 desc->rd_addr_hi = htole32(ET_ADDR_HI(paddr)); 2453 desc->rd_addr_lo = htole32(ET_ADDR_LO(paddr)); 2454 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2455 2456 bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap, 2457 BUS_DMASYNC_PREWRITE); 2458} 2459