rs690.c revision 254885
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/rs690.c 254885 2013-08-25 19:37:15Z dumbbell $"); 31 32#include <dev/drm2/drmP.h> 33#include "radeon.h" 34#include "radeon_asic.h" 35#include "atom.h" 36#include "rs690d.h" 37 38int rs690_mc_wait_for_idle(struct radeon_device *rdev) 39{ 40 unsigned i; 41 uint32_t tmp; 42 43 for (i = 0; i < rdev->usec_timeout; i++) { 44 /* read MC_STATUS */ 45 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 46 if (G_000090_MC_SYSTEM_IDLE(tmp)) 47 return 0; 48 DRM_UDELAY(1); 49 } 50 return -1; 51} 52 53static void rs690_gpu_init(struct radeon_device *rdev) 54{ 55 /* FIXME: is this correct ? */ 56 r420_pipes_init(rdev); 57 if (rs690_mc_wait_for_idle(rdev)) { 58 DRM_ERROR("Failed to wait MC idle while " 59 "programming pipes. Bad things might happen.\n"); 60 } 61} 62 63union igp_info { 64 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 65 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 66}; 67 68void rs690_pm_info(struct radeon_device *rdev) 69{ 70 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 71 union igp_info *info; 72 uint16_t data_offset; 73 uint8_t frev, crev; 74 fixed20_12 tmp; 75 76 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 77 &frev, &crev, &data_offset)) { 78 info = (union igp_info *)((uintptr_t)rdev->mode_info.atom_context->bios + data_offset); 79 80 /* Get various system informations from bios */ 81 switch (crev) { 82 case 1: 83 tmp.full = dfixed_const(100); 84 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 85 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 86 if (le16_to_cpu(info->info.usK8MemoryClock)) 87 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 88 else if (rdev->clock.default_mclk) { 89 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 90 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 91 } else 92 rdev->pm.igp_system_mclk.full = dfixed_const(400); 93 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 94 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 95 break; 96 case 2: 97 tmp.full = dfixed_const(100); 98 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 99 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 100 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 101 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 102 else if (rdev->clock.default_mclk) 103 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 104 else 105 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 106 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 107 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 108 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 109 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 110 break; 111 default: 112 /* We assume the slower possible clock ie worst case */ 113 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 114 rdev->pm.igp_system_mclk.full = dfixed_const(200); 115 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 116 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 117 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 118 break; 119 } 120 } else { 121 /* We assume the slower possible clock ie worst case */ 122 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 123 rdev->pm.igp_system_mclk.full = dfixed_const(200); 124 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 125 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 126 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 127 } 128 /* Compute various bandwidth */ 129 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 130 tmp.full = dfixed_const(4); 131 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 132 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 133 * = ht_clk * ht_width / 5 134 */ 135 tmp.full = dfixed_const(5); 136 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 137 rdev->pm.igp_ht_link_width); 138 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 139 if (tmp.full < rdev->pm.max_bandwidth.full) { 140 /* HT link is a limiting factor */ 141 rdev->pm.max_bandwidth.full = tmp.full; 142 } 143 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 144 * = (sideport_clk * 14) / 10 145 */ 146 tmp.full = dfixed_const(14); 147 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 148 tmp.full = dfixed_const(10); 149 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 150} 151 152static void rs690_mc_init(struct radeon_device *rdev) 153{ 154 u64 base; 155 156 rs400_gart_adjust_size(rdev); 157 rdev->mc.vram_is_ddr = true; 158 rdev->mc.vram_width = 128; 159 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 160 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 161 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 162 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 163 rdev->mc.visible_vram_size = rdev->mc.aper_size; 164 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 165 base = G_000100_MC_FB_START(base) << 16; 166 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 167 rs690_pm_info(rdev); 168 radeon_vram_location(rdev, &rdev->mc, base); 169 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 170 radeon_gtt_location(rdev, &rdev->mc); 171 radeon_update_bandwidth_info(rdev); 172} 173 174void rs690_line_buffer_adjust(struct radeon_device *rdev, 175 struct drm_display_mode *mode1, 176 struct drm_display_mode *mode2) 177{ 178 u32 tmp; 179 180 /* 181 * Line Buffer Setup 182 * There is a single line buffer shared by both display controllers. 183 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 184 * the display controllers. The paritioning can either be done 185 * manually or via one of four preset allocations specified in bits 1:0: 186 * 0 - line buffer is divided in half and shared between crtc 187 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 188 * 2 - D1 gets the whole buffer 189 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 190 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 191 * allocation mode. In manual allocation mode, D1 always starts at 0, 192 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 193 */ 194 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 195 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 196 /* auto */ 197 if (mode1 && mode2) { 198 if (mode1->hdisplay > mode2->hdisplay) { 199 if (mode1->hdisplay > 2560) 200 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 201 else 202 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 203 } else if (mode2->hdisplay > mode1->hdisplay) { 204 if (mode2->hdisplay > 2560) 205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 206 else 207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 208 } else 209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 210 } else if (mode1) { 211 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 212 } else if (mode2) { 213 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 214 } 215 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 216} 217 218struct rs690_watermark { 219 u32 lb_request_fifo_depth; 220 fixed20_12 num_line_pair; 221 fixed20_12 estimated_width; 222 fixed20_12 worst_case_latency; 223 fixed20_12 consumption_rate; 224 fixed20_12 active_time; 225 fixed20_12 dbpp; 226 fixed20_12 priority_mark_max; 227 fixed20_12 priority_mark; 228 fixed20_12 sclk; 229}; 230 231static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 232 struct radeon_crtc *crtc, 233 struct rs690_watermark *wm) 234{ 235 struct drm_display_mode *mode = &crtc->base.mode; 236 fixed20_12 a, b, c; 237 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 238 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 239 240 if (!crtc->base.enabled) { 241 /* FIXME: wouldn't it better to set priority mark to maximum */ 242 wm->lb_request_fifo_depth = 4; 243 return; 244 } 245 246 if (crtc->vsc.full > dfixed_const(2)) 247 wm->num_line_pair.full = dfixed_const(2); 248 else 249 wm->num_line_pair.full = dfixed_const(1); 250 251 b.full = dfixed_const(mode->crtc_hdisplay); 252 c.full = dfixed_const(256); 253 a.full = dfixed_div(b, c); 254 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 255 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 256 if (a.full < dfixed_const(4)) { 257 wm->lb_request_fifo_depth = 4; 258 } else { 259 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 260 } 261 262 /* Determine consumption rate 263 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 264 * vtaps = number of vertical taps, 265 * vsc = vertical scaling ratio, defined as source/destination 266 * hsc = horizontal scaling ration, defined as source/destination 267 */ 268 a.full = dfixed_const(mode->clock); 269 b.full = dfixed_const(1000); 270 a.full = dfixed_div(a, b); 271 pclk.full = dfixed_div(b, a); 272 if (crtc->rmx_type != RMX_OFF) { 273 b.full = dfixed_const(2); 274 if (crtc->vsc.full > b.full) 275 b.full = crtc->vsc.full; 276 b.full = dfixed_mul(b, crtc->hsc); 277 c.full = dfixed_const(2); 278 b.full = dfixed_div(b, c); 279 consumption_time.full = dfixed_div(pclk, b); 280 } else { 281 consumption_time.full = pclk.full; 282 } 283 a.full = dfixed_const(1); 284 wm->consumption_rate.full = dfixed_div(a, consumption_time); 285 286 287 /* Determine line time 288 * LineTime = total time for one line of displayhtotal 289 * LineTime = total number of horizontal pixels 290 * pclk = pixel clock period(ns) 291 */ 292 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 293 line_time.full = dfixed_mul(a, pclk); 294 295 /* Determine active time 296 * ActiveTime = time of active region of display within one line, 297 * hactive = total number of horizontal active pixels 298 * htotal = total number of horizontal pixels 299 */ 300 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 301 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 302 wm->active_time.full = dfixed_mul(line_time, b); 303 wm->active_time.full = dfixed_div(wm->active_time, a); 304 305 /* Maximun bandwidth is the minimun bandwidth of all component */ 306 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; 307 if (rdev->mc.igp_sideport_enabled) { 308 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 309 rdev->pm.sideport_bandwidth.full) 310 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; 311#ifdef DUMBBELL_WIP 312 read_delay_latency.full = dfixed_const(370 * 800 * 1000); 313#endif /* DUMBBELL_WIP */ 314 read_delay_latency.full = UINT_MAX; 315 read_delay_latency.full = dfixed_div(read_delay_latency, 316 rdev->pm.igp_sideport_mclk); 317 } else { 318 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && 319 rdev->pm.k8_bandwidth.full) 320 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; 321 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && 322 rdev->pm.ht_bandwidth.full) 323 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; 324 read_delay_latency.full = dfixed_const(5000); 325 } 326 327 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 328 a.full = dfixed_const(16); 329 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); 330 a.full = dfixed_const(1000); 331 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); 332 /* Determine chunk time 333 * ChunkTime = the time it takes the DCP to send one chunk of data 334 * to the LB which consists of pipeline delay and inter chunk gap 335 * sclk = system clock(ns) 336 */ 337 a.full = dfixed_const(256 * 13); 338 chunk_time.full = dfixed_mul(rdev->pm.sclk, a); 339 a.full = dfixed_const(10); 340 chunk_time.full = dfixed_div(chunk_time, a); 341 342 /* Determine the worst case latency 343 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 344 * WorstCaseLatency = worst case time from urgent to when the MC starts 345 * to return data 346 * READ_DELAY_IDLE_MAX = constant of 1us 347 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 348 * which consists of pipeline delay and inter chunk gap 349 */ 350 if (dfixed_trunc(wm->num_line_pair) > 1) { 351 a.full = dfixed_const(3); 352 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 353 wm->worst_case_latency.full += read_delay_latency.full; 354 } else { 355 a.full = dfixed_const(2); 356 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 357 wm->worst_case_latency.full += read_delay_latency.full; 358 } 359 360 /* Determine the tolerable latency 361 * TolerableLatency = Any given request has only 1 line time 362 * for the data to be returned 363 * LBRequestFifoDepth = Number of chunk requests the LB can 364 * put into the request FIFO for a display 365 * LineTime = total time for one line of display 366 * ChunkTime = the time it takes the DCP to send one chunk 367 * of data to the LB which consists of 368 * pipeline delay and inter chunk gap 369 */ 370 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 371 tolerable_latency.full = line_time.full; 372 } else { 373 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 374 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 375 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 376 tolerable_latency.full = line_time.full - tolerable_latency.full; 377 } 378 /* We assume worst case 32bits (4 bytes) */ 379 wm->dbpp.full = dfixed_const(4 * 8); 380 381 /* Determine the maximum priority mark 382 * width = viewport width in pixels 383 */ 384 a.full = dfixed_const(16); 385 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 386 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 387 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 388 389 /* Determine estimated width */ 390 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 391 estimated_width.full = dfixed_div(estimated_width, consumption_time); 392 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 393 wm->priority_mark.full = dfixed_const(10); 394 } else { 395 a.full = dfixed_const(16); 396 wm->priority_mark.full = dfixed_div(estimated_width, a); 397 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 398 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 399 } 400} 401 402void rs690_bandwidth_update(struct radeon_device *rdev) 403{ 404 struct drm_display_mode *mode0 = NULL; 405 struct drm_display_mode *mode1 = NULL; 406 struct rs690_watermark wm0; 407 struct rs690_watermark wm1; 408 u32 tmp; 409 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 410 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 411 fixed20_12 priority_mark02, priority_mark12, fill_rate; 412 fixed20_12 a, b; 413 414 radeon_update_display_priority(rdev); 415 416 if (rdev->mode_info.crtcs[0]->base.enabled) 417 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 418 if (rdev->mode_info.crtcs[1]->base.enabled) 419 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 420 /* 421 * Set display0/1 priority up in the memory controller for 422 * modes if the user specifies HIGH for displaypriority 423 * option. 424 */ 425 if ((rdev->disp_priority == 2) && 426 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 427 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 428 tmp &= C_000104_MC_DISP0R_INIT_LAT; 429 tmp &= C_000104_MC_DISP1R_INIT_LAT; 430 if (mode0) 431 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 432 if (mode1) 433 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 434 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 435 } 436 rs690_line_buffer_adjust(rdev, mode0, mode1); 437 438 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 439 WREG32(R_006C9C_DCP_CONTROL, 0); 440 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 441 WREG32(R_006C9C_DCP_CONTROL, 2); 442 443 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 444 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 445 446 tmp = (wm0.lb_request_fifo_depth - 1); 447 tmp |= (wm1.lb_request_fifo_depth - 1) << 16; 448 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 449 450 if (mode0 && mode1) { 451 if (dfixed_trunc(wm0.dbpp) > 64) 452 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 453 else 454 a.full = wm0.num_line_pair.full; 455 if (dfixed_trunc(wm1.dbpp) > 64) 456 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 457 else 458 b.full = wm1.num_line_pair.full; 459 a.full += b.full; 460 fill_rate.full = dfixed_div(wm0.sclk, a); 461 if (wm0.consumption_rate.full > fill_rate.full) { 462 b.full = wm0.consumption_rate.full - fill_rate.full; 463 b.full = dfixed_mul(b, wm0.active_time); 464 a.full = dfixed_mul(wm0.worst_case_latency, 465 wm0.consumption_rate); 466 a.full = a.full + b.full; 467 b.full = dfixed_const(16 * 1000); 468 priority_mark02.full = dfixed_div(a, b); 469 } else { 470 a.full = dfixed_mul(wm0.worst_case_latency, 471 wm0.consumption_rate); 472 b.full = dfixed_const(16 * 1000); 473 priority_mark02.full = dfixed_div(a, b); 474 } 475 if (wm1.consumption_rate.full > fill_rate.full) { 476 b.full = wm1.consumption_rate.full - fill_rate.full; 477 b.full = dfixed_mul(b, wm1.active_time); 478 a.full = dfixed_mul(wm1.worst_case_latency, 479 wm1.consumption_rate); 480 a.full = a.full + b.full; 481 b.full = dfixed_const(16 * 1000); 482 priority_mark12.full = dfixed_div(a, b); 483 } else { 484 a.full = dfixed_mul(wm1.worst_case_latency, 485 wm1.consumption_rate); 486 b.full = dfixed_const(16 * 1000); 487 priority_mark12.full = dfixed_div(a, b); 488 } 489 if (wm0.priority_mark.full > priority_mark02.full) 490 priority_mark02.full = wm0.priority_mark.full; 491 if (dfixed_trunc(priority_mark02) < 0) 492 priority_mark02.full = 0; 493 if (wm0.priority_mark_max.full > priority_mark02.full) 494 priority_mark02.full = wm0.priority_mark_max.full; 495 if (wm1.priority_mark.full > priority_mark12.full) 496 priority_mark12.full = wm1.priority_mark.full; 497 if (dfixed_trunc(priority_mark12) < 0) 498 priority_mark12.full = 0; 499 if (wm1.priority_mark_max.full > priority_mark12.full) 500 priority_mark12.full = wm1.priority_mark_max.full; 501 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 502 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 503 if (rdev->disp_priority == 2) { 504 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 505 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 506 } 507 } else if (mode0) { 508 if (dfixed_trunc(wm0.dbpp) > 64) 509 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 510 else 511 a.full = wm0.num_line_pair.full; 512 fill_rate.full = dfixed_div(wm0.sclk, a); 513 if (wm0.consumption_rate.full > fill_rate.full) { 514 b.full = wm0.consumption_rate.full - fill_rate.full; 515 b.full = dfixed_mul(b, wm0.active_time); 516 a.full = dfixed_mul(wm0.worst_case_latency, 517 wm0.consumption_rate); 518 a.full = a.full + b.full; 519 b.full = dfixed_const(16 * 1000); 520 priority_mark02.full = dfixed_div(a, b); 521 } else { 522 a.full = dfixed_mul(wm0.worst_case_latency, 523 wm0.consumption_rate); 524 b.full = dfixed_const(16 * 1000); 525 priority_mark02.full = dfixed_div(a, b); 526 } 527 if (wm0.priority_mark.full > priority_mark02.full) 528 priority_mark02.full = wm0.priority_mark.full; 529 if (dfixed_trunc(priority_mark02) < 0) 530 priority_mark02.full = 0; 531 if (wm0.priority_mark_max.full > priority_mark02.full) 532 priority_mark02.full = wm0.priority_mark_max.full; 533 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 534 if (rdev->disp_priority == 2) 535 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 536 } else if (mode1) { 537 if (dfixed_trunc(wm1.dbpp) > 64) 538 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 539 else 540 a.full = wm1.num_line_pair.full; 541 fill_rate.full = dfixed_div(wm1.sclk, a); 542 if (wm1.consumption_rate.full > fill_rate.full) { 543 b.full = wm1.consumption_rate.full - fill_rate.full; 544 b.full = dfixed_mul(b, wm1.active_time); 545 a.full = dfixed_mul(wm1.worst_case_latency, 546 wm1.consumption_rate); 547 a.full = a.full + b.full; 548 b.full = dfixed_const(16 * 1000); 549 priority_mark12.full = dfixed_div(a, b); 550 } else { 551 a.full = dfixed_mul(wm1.worst_case_latency, 552 wm1.consumption_rate); 553 b.full = dfixed_const(16 * 1000); 554 priority_mark12.full = dfixed_div(a, b); 555 } 556 if (wm1.priority_mark.full > priority_mark12.full) 557 priority_mark12.full = wm1.priority_mark.full; 558 if (dfixed_trunc(priority_mark12) < 0) 559 priority_mark12.full = 0; 560 if (wm1.priority_mark_max.full > priority_mark12.full) 561 priority_mark12.full = wm1.priority_mark_max.full; 562 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 563 if (rdev->disp_priority == 2) 564 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 565 } 566 567 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 568 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 569 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 570 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 571} 572 573uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 574{ 575 uint32_t r; 576 577 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 578 r = RREG32(R_00007C_MC_DATA); 579 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 580 return r; 581} 582 583void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 584{ 585 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 586 S_000078_MC_IND_WR_EN(1)); 587 WREG32(R_00007C_MC_DATA, v); 588 WREG32(R_000078_MC_INDEX, 0x7F); 589} 590 591static void rs690_mc_program(struct radeon_device *rdev) 592{ 593 struct rv515_mc_save save; 594 595 /* Stops all mc clients */ 596 rv515_mc_stop(rdev, &save); 597 598 /* Wait for mc idle */ 599 if (rs690_mc_wait_for_idle(rdev)) 600 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 601 /* Program MC, should be a 32bits limited address space */ 602 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 603 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 604 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 605 WREG32(R_000134_HDP_FB_LOCATION, 606 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 607 608 rv515_mc_resume(rdev, &save); 609} 610 611static int rs690_startup(struct radeon_device *rdev) 612{ 613 int r; 614 615 rs690_mc_program(rdev); 616 /* Resume clock */ 617 rv515_clock_startup(rdev); 618 /* Initialize GPU configuration (# pipes, ...) */ 619 rs690_gpu_init(rdev); 620 /* Initialize GART (initialize after TTM so we can allocate 621 * memory through TTM but finalize after TTM) */ 622 r = rs400_gart_enable(rdev); 623 if (r) 624 return r; 625 626 /* allocate wb buffer */ 627 r = radeon_wb_init(rdev); 628 if (r) 629 return r; 630 631 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 632 if (r) { 633 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 634 return r; 635 } 636 637 /* Enable IRQ */ 638 rs600_irq_set(rdev); 639 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 640 /* 1M ring buffer */ 641 r = r100_cp_init(rdev, 1024 * 1024); 642 if (r) { 643 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 644 return r; 645 } 646 647 r = radeon_ib_pool_init(rdev); 648 if (r) { 649 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 650 return r; 651 } 652 653 r = r600_audio_init(rdev); 654 if (r) { 655 dev_err(rdev->dev, "failed initializing audio\n"); 656 return r; 657 } 658 659 return 0; 660} 661 662int rs690_resume(struct radeon_device *rdev) 663{ 664 int r; 665 666 /* Make sur GART are not working */ 667 rs400_gart_disable(rdev); 668 /* Resume clock before doing reset */ 669 rv515_clock_startup(rdev); 670 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 671 if (radeon_asic_reset(rdev)) { 672 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 673 RREG32(R_000E40_RBBM_STATUS), 674 RREG32(R_0007C0_CP_STAT)); 675 } 676 /* post */ 677 atom_asic_init(rdev->mode_info.atom_context); 678 /* Resume clock after posting */ 679 rv515_clock_startup(rdev); 680 /* Initialize surface registers */ 681 radeon_surface_init(rdev); 682 683 rdev->accel_working = true; 684 r = rs690_startup(rdev); 685 if (r) { 686 rdev->accel_working = false; 687 } 688 return r; 689} 690 691int rs690_suspend(struct radeon_device *rdev) 692{ 693 r600_audio_fini(rdev); 694 r100_cp_disable(rdev); 695 radeon_wb_disable(rdev); 696 rs600_irq_disable(rdev); 697 rs400_gart_disable(rdev); 698 return 0; 699} 700 701void rs690_fini(struct radeon_device *rdev) 702{ 703 r600_audio_fini(rdev); 704 r100_cp_fini(rdev); 705 radeon_wb_fini(rdev); 706 radeon_ib_pool_fini(rdev); 707 radeon_gem_fini(rdev); 708 rs400_gart_fini(rdev); 709 radeon_irq_kms_fini(rdev); 710 radeon_fence_driver_fini(rdev); 711 radeon_bo_fini(rdev); 712 radeon_atombios_fini(rdev); 713 free(rdev->bios, DRM_MEM_DRIVER); 714 rdev->bios = NULL; 715} 716 717int rs690_init(struct radeon_device *rdev) 718{ 719 int r; 720 721 /* Disable VGA */ 722 rv515_vga_render_disable(rdev); 723 /* Initialize scratch registers */ 724 radeon_scratch_init(rdev); 725 /* Initialize surface registers */ 726 radeon_surface_init(rdev); 727 /* restore some register to sane defaults */ 728 r100_restore_sanity(rdev); 729 /* TODO: disable VGA need to use VGA request */ 730 /* BIOS*/ 731 if (!radeon_get_bios(rdev)) { 732 if (ASIC_IS_AVIVO(rdev)) 733 return -EINVAL; 734 } 735 if (rdev->is_atom_bios) { 736 r = radeon_atombios_init(rdev); 737 if (r) 738 return r; 739 } else { 740 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 741 return -EINVAL; 742 } 743 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 744 if (radeon_asic_reset(rdev)) { 745 dev_warn(rdev->dev, 746 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 747 RREG32(R_000E40_RBBM_STATUS), 748 RREG32(R_0007C0_CP_STAT)); 749 } 750 /* check if cards are posted or not */ 751 if (radeon_boot_test_post_card(rdev) == false) 752 return -EINVAL; 753 754 /* Initialize clocks */ 755 radeon_get_clock_info(rdev->ddev); 756 /* initialize memory controller */ 757 rs690_mc_init(rdev); 758 rv515_debugfs(rdev); 759 /* Fence driver */ 760 r = radeon_fence_driver_init(rdev); 761 if (r) 762 return r; 763 r = radeon_irq_kms_init(rdev); 764 if (r) 765 return r; 766 /* Memory manager */ 767 r = radeon_bo_init(rdev); 768 if (r) 769 return r; 770 r = rs400_gart_init(rdev); 771 if (r) 772 return r; 773 rs600_set_safe_registers(rdev); 774 775 rdev->accel_working = true; 776 r = rs690_startup(rdev); 777 if (r) { 778 /* Somethings want wront with the accel init stop accel */ 779 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 780 r100_cp_fini(rdev); 781 radeon_wb_fini(rdev); 782 radeon_ib_pool_fini(rdev); 783 rs400_gart_fini(rdev); 784 radeon_irq_kms_fini(rdev); 785 rdev->accel_working = false; 786 } 787 return 0; 788} 789