1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell#ifndef __RS600D_H__ 29254885Sdumbbell#define __RS600D_H__ 30254885Sdumbbell 31254885Sdumbbell#include <sys/cdefs.h> 32254885Sdumbbell__FBSDID("$FreeBSD: releng/10.3/sys/dev/drm2/radeon/rs600d.h 254885 2013-08-25 19:37:15Z dumbbell $"); 33254885Sdumbbell 34254885Sdumbbell/* Registers */ 35254885Sdumbbell#define R_000040_GEN_INT_CNTL 0x000040 36254885Sdumbbell#define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 37254885Sdumbbell#define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 38254885Sdumbbell#define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF 39254885Sdumbbell#define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 40254885Sdumbbell#define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 41254885Sdumbbell#define C_000040_GUI_IDLE_MASK 0xFFF7FFFF 42254885Sdumbbell#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 43254885Sdumbbell#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 44254885Sdumbbell#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 45254885Sdumbbell#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 46254885Sdumbbell#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 47254885Sdumbbell#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 48254885Sdumbbell#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 49254885Sdumbbell#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 50254885Sdumbbell#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 51254885Sdumbbell#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 52254885Sdumbbell#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 53254885Sdumbbell#define C_000040_I2C_INT_EN 0xFFFDFFFF 54254885Sdumbbell#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 55254885Sdumbbell#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 56254885Sdumbbell#define C_000040_GUI_IDLE 0xFFF7FFFF 57254885Sdumbbell#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 58254885Sdumbbell#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 59254885Sdumbbell#define C_000040_VIPH_INT_EN 0xFEFFFFFF 60254885Sdumbbell#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 61254885Sdumbbell#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 62254885Sdumbbell#define C_000040_SW_INT_EN 0xFDFFFFFF 63254885Sdumbbell#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 64254885Sdumbbell#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 65254885Sdumbbell#define C_000040_GEYSERVILLE 0xF7FFFFFF 66254885Sdumbbell#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 67254885Sdumbbell#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 68254885Sdumbbell#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 69254885Sdumbbell#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 70254885Sdumbbell#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 71254885Sdumbbell#define C_000040_DVI_I2C_INT 0xDFFFFFFF 72254885Sdumbbell#define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 73254885Sdumbbell#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 74254885Sdumbbell#define C_000040_GUIDMA 0xBFFFFFFF 75254885Sdumbbell#define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 76254885Sdumbbell#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 77254885Sdumbbell#define C_000040_VIDDMA 0x7FFFFFFF 78254885Sdumbbell#define R_000044_GEN_INT_STATUS 0x000044 79254885Sdumbbell#define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0) 80254885Sdumbbell#define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1) 81254885Sdumbbell#define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE 82254885Sdumbbell#define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1) 83254885Sdumbbell#define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1) 84254885Sdumbbell#define C_000044_VGA_INT_STAT 0xFFFFFFFD 85254885Sdumbbell#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 86254885Sdumbbell#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 87254885Sdumbbell#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 88254885Sdumbbell#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 89254885Sdumbbell#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 90254885Sdumbbell#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 91254885Sdumbbell#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 92254885Sdumbbell#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 93254885Sdumbbell#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 94254885Sdumbbell#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 95254885Sdumbbell#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 96254885Sdumbbell#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 97254885Sdumbbell#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 98254885Sdumbbell#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 99254885Sdumbbell#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 100254885Sdumbbell#define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16) 101254885Sdumbbell#define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1) 102254885Sdumbbell#define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF 103254885Sdumbbell#define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 104254885Sdumbbell#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 105254885Sdumbbell#define C_000044_I2C_INT 0xFFFDFFFF 106254885Sdumbbell#define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18) 107254885Sdumbbell#define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1) 108254885Sdumbbell#define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF 109254885Sdumbbell#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 110254885Sdumbbell#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 111254885Sdumbbell#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 112254885Sdumbbell#define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20) 113254885Sdumbbell#define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1) 114254885Sdumbbell#define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF 115254885Sdumbbell#define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21) 116254885Sdumbbell#define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1) 117254885Sdumbbell#define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF 118254885Sdumbbell#define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22) 119254885Sdumbbell#define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1) 120254885Sdumbbell#define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF 121254885Sdumbbell#define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23) 122254885Sdumbbell#define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1) 123254885Sdumbbell#define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF 124254885Sdumbbell#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 125254885Sdumbbell#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 126254885Sdumbbell#define C_000044_VIPH_INT 0xFEFFFFFF 127254885Sdumbbell#define S_000044_SW_INT(x) (((x) & 0x1) << 25) 128254885Sdumbbell#define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 129254885Sdumbbell#define C_000044_SW_INT 0xFDFFFFFF 130254885Sdumbbell#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 131254885Sdumbbell#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 132254885Sdumbbell#define C_000044_SW_INT_SET 0xFBFFFFFF 133254885Sdumbbell#define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27) 134254885Sdumbbell#define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1) 135254885Sdumbbell#define C_000044_IDCT_INT_STAT 0xF7FFFFFF 136254885Sdumbbell#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 137254885Sdumbbell#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 138254885Sdumbbell#define C_000044_GUIDMA_STAT 0xBFFFFFFF 139254885Sdumbbell#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 140254885Sdumbbell#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 141254885Sdumbbell#define C_000044_VIDDMA_STAT 0x7FFFFFFF 142254885Sdumbbell#define R_00004C_BUS_CNTL 0x00004C 143254885Sdumbbell#define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14) 144254885Sdumbbell#define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1) 145254885Sdumbbell#define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF 146254885Sdumbbell#define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20) 147254885Sdumbbell#define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1) 148254885Sdumbbell#define C_00004C_BUS_MSI_REARM 0xFFEFFFFF 149254885Sdumbbell#define R_000070_MC_IND_INDEX 0x000070 150254885Sdumbbell#define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0) 151254885Sdumbbell#define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF) 152254885Sdumbbell#define C_000070_MC_IND_ADDR 0xFFFF0000 153254885Sdumbbell#define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16) 154254885Sdumbbell#define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1) 155254885Sdumbbell#define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF 156254885Sdumbbell#define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17) 157254885Sdumbbell#define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1) 158254885Sdumbbell#define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF 159254885Sdumbbell#define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18) 160254885Sdumbbell#define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1) 161254885Sdumbbell#define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF 162254885Sdumbbell#define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19) 163254885Sdumbbell#define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1) 164254885Sdumbbell#define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF 165254885Sdumbbell#define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20) 166254885Sdumbbell#define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1) 167254885Sdumbbell#define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF 168254885Sdumbbell#define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21) 169254885Sdumbbell#define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1) 170254885Sdumbbell#define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF 171254885Sdumbbell#define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22) 172254885Sdumbbell#define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1) 173254885Sdumbbell#define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF 174254885Sdumbbell#define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23) 175254885Sdumbbell#define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1) 176254885Sdumbbell#define C_000070_MC_IND_WR_EN 0xFF7FFFFF 177254885Sdumbbell#define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24) 178254885Sdumbbell#define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1) 179254885Sdumbbell#define C_000070_MC_IND_RD_INV 0xFEFFFFFF 180254885Sdumbbell#define R_000074_MC_IND_DATA 0x000074 181254885Sdumbbell#define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) 182254885Sdumbbell#define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) 183254885Sdumbbell#define C_000074_MC_IND_DATA 0x00000000 184254885Sdumbbell#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 185254885Sdumbbell#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 186254885Sdumbbell#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 187254885Sdumbbell#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 188254885Sdumbbell#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 189254885Sdumbbell#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 190254885Sdumbbell#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 191254885Sdumbbell#define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 192254885Sdumbbell#define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 193254885Sdumbbell#define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 194254885Sdumbbell#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 195254885Sdumbbell#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 196254885Sdumbbell#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 197254885Sdumbbell#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 198254885Sdumbbell#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 199254885Sdumbbell#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 200254885Sdumbbell#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 201254885Sdumbbell#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 202254885Sdumbbell#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 203254885Sdumbbell#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 204254885Sdumbbell#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 205254885Sdumbbell#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 206254885Sdumbbell#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 207254885Sdumbbell#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 208254885Sdumbbell#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 209254885Sdumbbell#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 210254885Sdumbbell#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 211254885Sdumbbell#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 212254885Sdumbbell#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 213254885Sdumbbell#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 214254885Sdumbbell#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 215254885Sdumbbell#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 216254885Sdumbbell#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 217254885Sdumbbell#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 218254885Sdumbbell#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 219254885Sdumbbell#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 220254885Sdumbbell#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 221254885Sdumbbell#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 222254885Sdumbbell#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 223254885Sdumbbell#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 224254885Sdumbbell#define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 225254885Sdumbbell#define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 226254885Sdumbbell#define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 227254885Sdumbbell#define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 228254885Sdumbbell#define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 229254885Sdumbbell#define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 230254885Sdumbbell#define R_000134_HDP_FB_LOCATION 0x000134 231254885Sdumbbell#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 232254885Sdumbbell#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 233254885Sdumbbell#define C_000134_HDP_FB_START 0xFFFF0000 234254885Sdumbbell#define R_0007C0_CP_STAT 0x0007C0 235254885Sdumbbell#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 236254885Sdumbbell#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 237254885Sdumbbell#define C_0007C0_MRU_BUSY 0xFFFFFFFE 238254885Sdumbbell#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 239254885Sdumbbell#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 240254885Sdumbbell#define C_0007C0_MWU_BUSY 0xFFFFFFFD 241254885Sdumbbell#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 242254885Sdumbbell#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 243254885Sdumbbell#define C_0007C0_RSIU_BUSY 0xFFFFFFFB 244254885Sdumbbell#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 245254885Sdumbbell#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 246254885Sdumbbell#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 247254885Sdumbbell#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 248254885Sdumbbell#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 249254885Sdumbbell#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 250254885Sdumbbell#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 251254885Sdumbbell#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 252254885Sdumbbell#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 253254885Sdumbbell#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 254254885Sdumbbell#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 255254885Sdumbbell#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 256254885Sdumbbell#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 257254885Sdumbbell#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 258254885Sdumbbell#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 259254885Sdumbbell#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 260254885Sdumbbell#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 261254885Sdumbbell#define C_0007C0_CSI_BUSY 0xFFFFDFFF 262254885Sdumbbell#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 263254885Sdumbbell#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 264254885Sdumbbell#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 265254885Sdumbbell#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 266254885Sdumbbell#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 267254885Sdumbbell#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 268254885Sdumbbell#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 269254885Sdumbbell#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 270254885Sdumbbell#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 271254885Sdumbbell#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 272254885Sdumbbell#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 273254885Sdumbbell#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 274254885Sdumbbell#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 275254885Sdumbbell#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 276254885Sdumbbell#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 277254885Sdumbbell#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 278254885Sdumbbell#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 279254885Sdumbbell#define C_0007C0_CP_BUSY 0x7FFFFFFF 280254885Sdumbbell#define R_000E40_RBBM_STATUS 0x000E40 281254885Sdumbbell#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 282254885Sdumbbell#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 283254885Sdumbbell#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 284254885Sdumbbell#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 285254885Sdumbbell#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 286254885Sdumbbell#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 287254885Sdumbbell#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 288254885Sdumbbell#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 289254885Sdumbbell#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 290254885Sdumbbell#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 291254885Sdumbbell#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 292254885Sdumbbell#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 293254885Sdumbbell#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 294254885Sdumbbell#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 295254885Sdumbbell#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 296254885Sdumbbell#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 297254885Sdumbbell#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 298254885Sdumbbell#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 299254885Sdumbbell#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 300254885Sdumbbell#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 301254885Sdumbbell#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 302254885Sdumbbell#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 303254885Sdumbbell#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 304254885Sdumbbell#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 305254885Sdumbbell#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 306254885Sdumbbell#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 307254885Sdumbbell#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 308254885Sdumbbell#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 309254885Sdumbbell#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 310254885Sdumbbell#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 311254885Sdumbbell#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 312254885Sdumbbell#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 313254885Sdumbbell#define C_000E40_E2_BUSY 0xFFFDFFFF 314254885Sdumbbell#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 315254885Sdumbbell#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 316254885Sdumbbell#define C_000E40_RB2D_BUSY 0xFFFBFFFF 317254885Sdumbbell#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 318254885Sdumbbell#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 319254885Sdumbbell#define C_000E40_RB3D_BUSY 0xFFF7FFFF 320254885Sdumbbell#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 321254885Sdumbbell#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 322254885Sdumbbell#define C_000E40_VAP_BUSY 0xFFEFFFFF 323254885Sdumbbell#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 324254885Sdumbbell#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 325254885Sdumbbell#define C_000E40_RE_BUSY 0xFFDFFFFF 326254885Sdumbbell#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 327254885Sdumbbell#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 328254885Sdumbbell#define C_000E40_TAM_BUSY 0xFFBFFFFF 329254885Sdumbbell#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 330254885Sdumbbell#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 331254885Sdumbbell#define C_000E40_TDM_BUSY 0xFF7FFFFF 332254885Sdumbbell#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 333254885Sdumbbell#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 334254885Sdumbbell#define C_000E40_PB_BUSY 0xFEFFFFFF 335254885Sdumbbell#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 336254885Sdumbbell#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 337254885Sdumbbell#define C_000E40_TIM_BUSY 0xFDFFFFFF 338254885Sdumbbell#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 339254885Sdumbbell#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 340254885Sdumbbell#define C_000E40_GA_BUSY 0xFBFFFFFF 341254885Sdumbbell#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 342254885Sdumbbell#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 343254885Sdumbbell#define C_000E40_CBA2D_BUSY 0xF7FFFFFF 344254885Sdumbbell#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 345254885Sdumbbell#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 346254885Sdumbbell#define C_000E40_GUI_ACTIVE 0x7FFFFFFF 347254885Sdumbbell#define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4 348254885Sdumbbell#define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 349254885Sdumbbell#define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 350254885Sdumbbell#define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000 351254885Sdumbbell#define R_006534_D1MODE_VBLANK_STATUS 0x006534 352254885Sdumbbell#define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 353254885Sdumbbell#define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 354254885Sdumbbell#define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE 355254885Sdumbbell#define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 356254885Sdumbbell#define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 357254885Sdumbbell#define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF 358254885Sdumbbell#define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 359254885Sdumbbell#define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 360254885Sdumbbell#define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF 361254885Sdumbbell#define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 362254885Sdumbbell#define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 363254885Sdumbbell#define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF 364254885Sdumbbell#define R_006540_DxMODE_INT_MASK 0x006540 365254885Sdumbbell#define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0) 366254885Sdumbbell#define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1) 367254885Sdumbbell#define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE 368254885Sdumbbell#define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4) 369254885Sdumbbell#define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1) 370254885Sdumbbell#define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF 371254885Sdumbbell#define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8) 372254885Sdumbbell#define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1) 373254885Sdumbbell#define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF 374254885Sdumbbell#define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12) 375254885Sdumbbell#define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1) 376254885Sdumbbell#define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF 377254885Sdumbbell#define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30) 378254885Sdumbbell#define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1) 379254885Sdumbbell#define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF 380254885Sdumbbell#define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31) 381254885Sdumbbell#define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1) 382254885Sdumbbell#define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF 383254885Sdumbbell#define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4 384254885Sdumbbell#define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 385254885Sdumbbell#define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 386254885Sdumbbell#define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000 387254885Sdumbbell#define R_006D34_D2MODE_VBLANK_STATUS 0x006D34 388254885Sdumbbell#define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 389254885Sdumbbell#define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 390254885Sdumbbell#define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE 391254885Sdumbbell#define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 392254885Sdumbbell#define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 393254885Sdumbbell#define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF 394254885Sdumbbell#define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 395254885Sdumbbell#define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 396254885Sdumbbell#define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF 397254885Sdumbbell#define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 398254885Sdumbbell#define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 399254885Sdumbbell#define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF 400254885Sdumbbell#define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC 401254885Sdumbbell#define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4) 402254885Sdumbbell#define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1) 403254885Sdumbbell#define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF 404254885Sdumbbell#define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) 405254885Sdumbbell#define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) 406254885Sdumbbell#define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF 407254885Sdumbbell#define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16) 408254885Sdumbbell#define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1) 409254885Sdumbbell#define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF 410254885Sdumbbell#define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17) 411254885Sdumbbell#define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1) 412254885Sdumbbell#define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF 413254885Sdumbbell#define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18) 414254885Sdumbbell#define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1) 415254885Sdumbbell#define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF 416254885Sdumbbell#define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19) 417254885Sdumbbell#define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1) 418254885Sdumbbell#define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF 419254885Sdumbbell#define R_007828_DACA_AUTODETECT_CONTROL 0x007828 420254885Sdumbbell#define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 421254885Sdumbbell#define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 422254885Sdumbbell#define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC 423254885Sdumbbell#define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 424254885Sdumbbell#define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 425254885Sdumbbell#define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 426254885Sdumbbell#define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 427254885Sdumbbell#define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 428254885Sdumbbell#define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF 429254885Sdumbbell#define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838 430254885Sdumbbell#define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 431254885Sdumbbell#define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE 432254885Sdumbbell#define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 433254885Sdumbbell#define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 434254885Sdumbbell#define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF 435254885Sdumbbell#define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28 436254885Sdumbbell#define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 437254885Sdumbbell#define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 438254885Sdumbbell#define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC 439254885Sdumbbell#define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 440254885Sdumbbell#define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 441254885Sdumbbell#define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 442254885Sdumbbell#define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 443254885Sdumbbell#define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 444254885Sdumbbell#define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF 445254885Sdumbbell#define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38 446254885Sdumbbell#define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 447254885Sdumbbell#define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE 448254885Sdumbbell#define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 449254885Sdumbbell#define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 450254885Sdumbbell#define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF 451254885Sdumbbell#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00 452254885Sdumbbell#define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0) 453254885Sdumbbell#define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1) 454254885Sdumbbell#define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE 455254885Sdumbbell#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04 456254885Sdumbbell#define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0) 457254885Sdumbbell#define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1) 458254885Sdumbbell#define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE 459254885Sdumbbell#define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1) 460254885Sdumbbell#define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1) 461254885Sdumbbell#define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD 462254885Sdumbbell#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08 463254885Sdumbbell#define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0) 464254885Sdumbbell#define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE 465254885Sdumbbell#define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8) 466254885Sdumbbell#define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1) 467254885Sdumbbell#define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF 468254885Sdumbbell#define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16) 469254885Sdumbbell#define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1) 470254885Sdumbbell#define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF 471254885Sdumbbell#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10 472254885Sdumbbell#define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0) 473254885Sdumbbell#define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1) 474254885Sdumbbell#define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE 475254885Sdumbbell#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14 476254885Sdumbbell#define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0) 477254885Sdumbbell#define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1) 478254885Sdumbbell#define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE 479254885Sdumbbell#define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1) 480254885Sdumbbell#define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1) 481254885Sdumbbell#define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD 482254885Sdumbbell#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18 483254885Sdumbbell#define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0) 484254885Sdumbbell#define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE 485254885Sdumbbell#define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8) 486254885Sdumbbell#define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1) 487254885Sdumbbell#define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF 488254885Sdumbbell#define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16) 489254885Sdumbbell#define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1) 490254885Sdumbbell#define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF 491254885Sdumbbell#define R_007404_HDMI0_STATUS 0x007404 492254885Sdumbbell#define S_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) & 0x1) << 28) 493254885Sdumbbell#define G_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) >> 28) & 0x1) 494254885Sdumbbell#define C_007404_HDMI0_AZ_FORMAT_WTRIG 0xEFFFFFFF 495254885Sdumbbell#define S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) & 0x1) << 29) 496254885Sdumbbell#define G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) >> 29) & 0x1) 497254885Sdumbbell#define C_007404_HDMI0_AZ_FORMAT_WTRIG_INT 0xDFFFFFFF 498254885Sdumbbell#define R_007408_HDMI0_AUDIO_PACKET_CONTROL 0x007408 499254885Sdumbbell#define S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) & 0x1) << 28) 500254885Sdumbbell#define G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) >> 28) & 0x1) 501254885Sdumbbell#define C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK 0xEFFFFFFF 502254885Sdumbbell#define S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) & 0x1) << 29) 503254885Sdumbbell#define G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) >> 29) & 0x1) 504254885Sdumbbell#define C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK 0xDFFFFFFF 505254885Sdumbbell 506254885Sdumbbell/* MC registers */ 507254885Sdumbbell#define R_000000_MC_STATUS 0x000000 508254885Sdumbbell#define S_000000_MC_IDLE(x) (((x) & 0x1) << 0) 509254885Sdumbbell#define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1) 510254885Sdumbbell#define C_000000_MC_IDLE 0xFFFFFFFE 511254885Sdumbbell#define R_000004_MC_FB_LOCATION 0x000004 512254885Sdumbbell#define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) 513254885Sdumbbell#define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 514254885Sdumbbell#define C_000004_MC_FB_START 0xFFFF0000 515254885Sdumbbell#define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 516254885Sdumbbell#define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 517254885Sdumbbell#define C_000004_MC_FB_TOP 0x0000FFFF 518254885Sdumbbell#define R_000005_MC_AGP_LOCATION 0x000005 519254885Sdumbbell#define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 520254885Sdumbbell#define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 521254885Sdumbbell#define C_000005_MC_AGP_START 0xFFFF0000 522254885Sdumbbell#define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 523254885Sdumbbell#define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 524254885Sdumbbell#define C_000005_MC_AGP_TOP 0x0000FFFF 525254885Sdumbbell#define R_000006_AGP_BASE 0x000006 526254885Sdumbbell#define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 527254885Sdumbbell#define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 528254885Sdumbbell#define C_000006_AGP_BASE_ADDR 0x00000000 529254885Sdumbbell#define R_000007_AGP_BASE_2 0x000007 530254885Sdumbbell#define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 531254885Sdumbbell#define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 532254885Sdumbbell#define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 533254885Sdumbbell#define R_000009_MC_CNTL1 0x000009 534254885Sdumbbell#define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26) 535254885Sdumbbell#define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1) 536254885Sdumbbell#define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF 537254885Sdumbbell/* FIXME don't know the various field size need feedback from AMD */ 538254885Sdumbbell#define R_000100_MC_PT0_CNTL 0x000100 539254885Sdumbbell#define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0) 540254885Sdumbbell#define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1) 541254885Sdumbbell#define C_000100_ENABLE_PT 0xFFFFFFFE 542254885Sdumbbell#define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15) 543254885Sdumbbell#define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7) 544254885Sdumbbell#define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF 545254885Sdumbbell#define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21) 546254885Sdumbbell#define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7) 547254885Sdumbbell#define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF 548254885Sdumbbell#define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28) 549254885Sdumbbell#define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1) 550254885Sdumbbell#define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF 551254885Sdumbbell#define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29) 552254885Sdumbbell#define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1) 553254885Sdumbbell#define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF 554254885Sdumbbell#define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102 555254885Sdumbbell#define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0) 556254885Sdumbbell#define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1) 557254885Sdumbbell#define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE 558254885Sdumbbell#define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1) 559254885Sdumbbell#define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3) 560254885Sdumbbell#define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9 561254885Sdumbbell#define V_000102_PAGE_TABLE_FLAT 0 562254885Sdumbbell/* R600 documentation suggest that this should be a number of pages */ 563254885Sdumbbell#define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112 564254885Sdumbbell#define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114 565254885Sdumbbell#define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C 566254885Sdumbbell#define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C 567254885Sdumbbell#define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C 568254885Sdumbbell#define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C 569254885Sdumbbell#define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C 570254885Sdumbbell#define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0) 571254885Sdumbbell#define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1) 572254885Sdumbbell#define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE 573254885Sdumbbell#define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1) 574254885Sdumbbell#define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1) 575254885Sdumbbell#define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD 576254885Sdumbbell#define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8) 577254885Sdumbbell#define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3) 578254885Sdumbbell#define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF 579254885Sdumbbell#define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0 580254885Sdumbbell#define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1 581254885Sdumbbell#define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2 582254885Sdumbbell#define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3 583254885Sdumbbell#define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10) 584254885Sdumbbell#define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1) 585254885Sdumbbell#define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF 586254885Sdumbbell#define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0 587254885Sdumbbell#define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1 588254885Sdumbbell#define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11) 589254885Sdumbbell#define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7) 590254885Sdumbbell#define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF 591254885Sdumbbell#define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14) 592254885Sdumbbell#define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1) 593254885Sdumbbell#define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF 594254885Sdumbbell#define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15) 595254885Sdumbbell#define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7) 596254885Sdumbbell#define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF 597254885Sdumbbell#define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20) 598254885Sdumbbell#define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) 599254885Sdumbbell#define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF 600254885Sdumbbell 601254885Sdumbbell#define R_006548_D1MODE_PRIORITY_A_CNT 0x006548 602254885Sdumbbell#define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 603254885Sdumbbell#define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 604254885Sdumbbell#define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000 605254885Sdumbbell#define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 606254885Sdumbbell#define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 607254885Sdumbbell#define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF 608254885Sdumbbell#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 609254885Sdumbbell#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 610254885Sdumbbell#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 611254885Sdumbbell#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 612254885Sdumbbell#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 613254885Sdumbbell#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 614254885Sdumbbell#define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C 615254885Sdumbbell#define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 616254885Sdumbbell#define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 617254885Sdumbbell#define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000 618254885Sdumbbell#define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 619254885Sdumbbell#define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 620254885Sdumbbell#define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF 621254885Sdumbbell#define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 622254885Sdumbbell#define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 623254885Sdumbbell#define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 624254885Sdumbbell#define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 625254885Sdumbbell#define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 626254885Sdumbbell#define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 627254885Sdumbbell#define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48 628254885Sdumbbell#define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 629254885Sdumbbell#define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 630254885Sdumbbell#define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000 631254885Sdumbbell#define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 632254885Sdumbbell#define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 633254885Sdumbbell#define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF 634254885Sdumbbell#define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 635254885Sdumbbell#define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 636254885Sdumbbell#define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 637254885Sdumbbell#define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 638254885Sdumbbell#define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 639254885Sdumbbell#define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 640254885Sdumbbell#define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C 641254885Sdumbbell#define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 642254885Sdumbbell#define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 643254885Sdumbbell#define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000 644254885Sdumbbell#define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 645254885Sdumbbell#define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 646254885Sdumbbell#define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF 647254885Sdumbbell#define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 648254885Sdumbbell#define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 649254885Sdumbbell#define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 650254885Sdumbbell#define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 651254885Sdumbbell#define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 652254885Sdumbbell#define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 653254885Sdumbbell 654254885Sdumbbell/* PLL regs */ 655254885Sdumbbell#define GENERAL_PWRMGT 0x8 656254885Sdumbbell#define GLOBAL_PWRMGT_EN (1 << 0) 657254885Sdumbbell#define MOBILE_SU (1 << 2) 658254885Sdumbbell#define DYN_PWRMGT_SCLK_LENGTH 0xc 659254885Sdumbbell#define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) 660254885Sdumbbell#define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) 661254885Sdumbbell#define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) 662254885Sdumbbell#define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) 663254885Sdumbbell#define POWER_D1_SCLK_HILEN(x) ((x) << 16) 664254885Sdumbbell#define POWER_D1_SCLK_LOLEN(x) ((x) << 20) 665254885Sdumbbell#define STATIC_SCREEN_HILEN(x) ((x) << 24) 666254885Sdumbbell#define STATIC_SCREEN_LOLEN(x) ((x) << 28) 667254885Sdumbbell#define DYN_SCLK_VOL_CNTL 0xe 668254885Sdumbbell#define IO_CG_VOLTAGE_DROP (1 << 0) 669254885Sdumbbell#define VOLTAGE_DROP_SYNC (1 << 2) 670254885Sdumbbell#define VOLTAGE_DELAY_SEL(x) ((x) << 3) 671254885Sdumbbell#define HDP_DYN_CNTL 0x10 672254885Sdumbbell#define HDP_FORCEON (1 << 0) 673254885Sdumbbell#define MC_HOST_DYN_CNTL 0x1e 674254885Sdumbbell#define MC_HOST_FORCEON (1 << 0) 675254885Sdumbbell#define DYN_BACKBIAS_CNTL 0x29 676254885Sdumbbell#define IO_CG_BACKBIAS_EN (1 << 0) 677254885Sdumbbell 678254885Sdumbbell/* mmreg */ 679254885Sdumbbell#define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0 680254885Sdumbbell#define PWRDN_WAIT_BUSY_OFF (1 << 0) 681254885Sdumbbell#define PWRDN_WAIT_PWRSEQ_OFF (1 << 4) 682254885Sdumbbell#define PWRDN_WAIT_PPLL_OFF (1 << 8) 683254885Sdumbbell#define PWRUP_WAIT_PPLL_ON (1 << 12) 684254885Sdumbbell#define PWRUP_WAIT_MEM_INIT_DONE (1 << 16) 685254885Sdumbbell#define PM_ASSERT_RESET (1 << 20) 686254885Sdumbbell#define PM_PWRDN_PPLL (1 << 24) 687254885Sdumbbell 688254885Sdumbbell#endif 689