1254885Sdumbbell/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2254885Sdumbbell * 3254885Sdumbbell * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4254885Sdumbbell * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5254885Sdumbbell * All rights reserved. 6254885Sdumbbell * 7254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 8254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 9254885Sdumbbell * to deal in the Software without restriction, including without limitation 10254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 12254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 13254885Sdumbbell * 14254885Sdumbbell * The above copyright notice and this permission notice (including the next 15254885Sdumbbell * paragraph) shall be included in all copies or substantial portions of the 16254885Sdumbbell * Software. 17254885Sdumbbell * 18254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21254885Sdumbbell * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24254885Sdumbbell * DEALINGS IN THE SOFTWARE. 25254885Sdumbbell * 26254885Sdumbbell * Authors: 27254885Sdumbbell * Kevin E. Martin <martin@valinux.com> 28254885Sdumbbell * Gareth Hughes <gareth@valinux.com> 29254885Sdumbbell */ 30254885Sdumbbell 31254885Sdumbbell#include <sys/cdefs.h> 32254885Sdumbbell__FBSDID("$FreeBSD: releng/10.3/sys/dev/drm2/radeon/radeon_drv.h 282199 2015-04-28 19:35:05Z dumbbell $"); 33254885Sdumbbell 34254885Sdumbbell#ifndef __RADEON_DRV_H__ 35254885Sdumbbell#define __RADEON_DRV_H__ 36254885Sdumbbell 37254885Sdumbbell#include "radeon_family.h" 38254885Sdumbbell 39254885Sdumbbell/* General customization: 40254885Sdumbbell */ 41254885Sdumbbell 42254885Sdumbbell#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 43254885Sdumbbell 44254885Sdumbbell#define DRIVER_NAME "radeon" 45254885Sdumbbell#define DRIVER_DESC "ATI Radeon" 46254885Sdumbbell#define DRIVER_DATE "20080528" 47254885Sdumbbell 48254885Sdumbbell/* Interface history: 49254885Sdumbbell * 50254885Sdumbbell * 1.1 - ?? 51254885Sdumbbell * 1.2 - Add vertex2 ioctl (keith) 52254885Sdumbbell * - Add stencil capability to clear ioctl (gareth, keith) 53254885Sdumbbell * - Increase MAX_TEXTURE_LEVELS (brian) 54254885Sdumbbell * 1.3 - Add cmdbuf ioctl (keith) 55254885Sdumbbell * - Add support for new radeon packets (keith) 56254885Sdumbbell * - Add getparam ioctl (keith) 57254885Sdumbbell * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 58254885Sdumbbell * 1.4 - Add scratch registers to get_param ioctl. 59254885Sdumbbell * 1.5 - Add r200 packets to cmdbuf ioctl 60254885Sdumbbell * - Add r200 function to init ioctl 61254885Sdumbbell * - Add 'scalar2' instruction to cmdbuf 62254885Sdumbbell * 1.6 - Add static GART memory manager 63254885Sdumbbell * Add irq handler (won't be turned on unless X server knows to) 64254885Sdumbbell * Add irq ioctls and irq_active getparam. 65254885Sdumbbell * Add wait command for cmdbuf ioctl 66254885Sdumbbell * Add GART offset query for getparam 67254885Sdumbbell * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 68254885Sdumbbell * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 69254885Sdumbbell * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 70254885Sdumbbell * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 71254885Sdumbbell * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 72254885Sdumbbell * Add 'GET' queries for starting additional clients on different VT's. 73254885Sdumbbell * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 74254885Sdumbbell * Add texture rectangle support for r100. 75254885Sdumbbell * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 76254885Sdumbbell * clients use to tell the DRM where they think the framebuffer is 77254885Sdumbbell * located in the card's address space 78254885Sdumbbell * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 79254885Sdumbbell * and GL_EXT_blend_[func|equation]_separate on r200 80254885Sdumbbell * 1.12- Add R300 CP microcode support - this just loads the CP on r300 81254885Sdumbbell * (No 3D support yet - just microcode loading). 82254885Sdumbbell * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 83254885Sdumbbell * - Add hyperz support, add hyperz flags to clear ioctl. 84254885Sdumbbell * 1.14- Add support for color tiling 85254885Sdumbbell * - Add R100/R200 surface allocation/free support 86254885Sdumbbell * 1.15- Add support for texture micro tiling 87254885Sdumbbell * - Add support for r100 cube maps 88254885Sdumbbell * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 89254885Sdumbbell * texture filtering on r200 90254885Sdumbbell * 1.17- Add initial support for R300 (3D). 91254885Sdumbbell * 1.18- Add support for GL_ATI_fragment_shader, new packets 92254885Sdumbbell * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 93254885Sdumbbell * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 94254885Sdumbbell * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 95254885Sdumbbell * 1.19- Add support for gart table in FB memory and PCIE r300 96254885Sdumbbell * 1.20- Add support for r300 texrect 97254885Sdumbbell * 1.21- Add support for card type getparam 98254885Sdumbbell * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 99254885Sdumbbell * 1.23- Add new radeon memory map work from benh 100254885Sdumbbell * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 101254885Sdumbbell * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 102254885Sdumbbell * new packet type) 103254885Sdumbbell * 1.26- Add support for variable size PCI(E) gart aperture 104254885Sdumbbell * 1.27- Add support for IGP GART 105254885Sdumbbell * 1.28- Add support for VBL on CRTC2 106254885Sdumbbell * 1.29- R500 3D cmd buffer support 107254885Sdumbbell * 1.30- Add support for occlusion queries 108254885Sdumbbell * 1.31- Add support for num Z pipes from GET_PARAM 109254885Sdumbbell * 1.32- fixes for rv740 setup 110254885Sdumbbell * 1.33- Add r6xx/r7xx const buffer support 111254885Sdumbbell */ 112254885Sdumbbell#define DRIVER_MAJOR 1 113254885Sdumbbell#define DRIVER_MINOR 33 114254885Sdumbbell#define DRIVER_PATCHLEVEL 0 115254885Sdumbbell 116254885Sdumbbellenum radeon_cp_microcode_version { 117254885Sdumbbell UCODE_R100, 118254885Sdumbbell UCODE_R200, 119254885Sdumbbell UCODE_R300, 120254885Sdumbbell}; 121254885Sdumbbell 122254885Sdumbbelltypedef struct drm_radeon_freelist { 123254885Sdumbbell unsigned int age; 124254885Sdumbbell struct drm_buf *buf; 125254885Sdumbbell struct drm_radeon_freelist *next; 126254885Sdumbbell struct drm_radeon_freelist *prev; 127254885Sdumbbell} drm_radeon_freelist_t; 128254885Sdumbbell 129254885Sdumbbelltypedef struct drm_radeon_ring_buffer { 130254885Sdumbbell u32 *start; 131254885Sdumbbell u32 *end; 132254885Sdumbbell int size; 133254885Sdumbbell int size_l2qw; 134254885Sdumbbell 135254885Sdumbbell int rptr_update; /* Double Words */ 136254885Sdumbbell int rptr_update_l2qw; /* log2 Quad Words */ 137254885Sdumbbell 138254885Sdumbbell int fetch_size; /* Double Words */ 139254885Sdumbbell int fetch_size_l2ow; /* log2 Oct Words */ 140254885Sdumbbell 141254885Sdumbbell u32 tail; 142254885Sdumbbell u32 tail_mask; 143254885Sdumbbell int space; 144254885Sdumbbell 145254885Sdumbbell int high_mark; 146254885Sdumbbell} drm_radeon_ring_buffer_t; 147254885Sdumbbell 148254885Sdumbbelltypedef struct drm_radeon_depth_clear_t { 149254885Sdumbbell u32 rb3d_cntl; 150254885Sdumbbell u32 rb3d_zstencilcntl; 151254885Sdumbbell u32 se_cntl; 152254885Sdumbbell} drm_radeon_depth_clear_t; 153254885Sdumbbell 154254885Sdumbbellstruct drm_radeon_driver_file_fields { 155254885Sdumbbell int64_t radeon_fb_delta; 156254885Sdumbbell}; 157254885Sdumbbell 158254885Sdumbbellstruct mem_block { 159254885Sdumbbell struct mem_block *next; 160254885Sdumbbell struct mem_block *prev; 161254885Sdumbbell int start; 162254885Sdumbbell int size; 163254885Sdumbbell struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 164254885Sdumbbell}; 165254885Sdumbbell 166254885Sdumbbellstruct radeon_surface { 167254885Sdumbbell int refcount; 168254885Sdumbbell u32 lower; 169254885Sdumbbell u32 upper; 170254885Sdumbbell u32 flags; 171254885Sdumbbell}; 172254885Sdumbbell 173254885Sdumbbellstruct radeon_virt_surface { 174254885Sdumbbell int surface_index; 175254885Sdumbbell u32 lower; 176254885Sdumbbell u32 upper; 177254885Sdumbbell u32 flags; 178254885Sdumbbell struct drm_file *file_priv; 179254885Sdumbbell#define PCIGART_FILE_PRIV ((void *) -1L) 180254885Sdumbbell}; 181254885Sdumbbell 182254885Sdumbbell#define RADEON_FLUSH_EMITED (1 << 0) 183254885Sdumbbell#define RADEON_PURGE_EMITED (1 << 1) 184254885Sdumbbell 185254885Sdumbbellstruct drm_radeon_master_private { 186254885Sdumbbell drm_local_map_t *sarea; 187254885Sdumbbell drm_radeon_sarea_t *sarea_priv; 188254885Sdumbbell}; 189254885Sdumbbell 190254885Sdumbbelltypedef struct drm_radeon_private { 191254885Sdumbbell drm_radeon_ring_buffer_t ring; 192254885Sdumbbell 193254885Sdumbbell u32 fb_location; 194254885Sdumbbell u32 fb_size; 195254885Sdumbbell int new_memmap; 196254885Sdumbbell 197254885Sdumbbell int gart_size; 198254885Sdumbbell u32 gart_vm_start; 199254885Sdumbbell unsigned long gart_buffers_offset; 200254885Sdumbbell 201254885Sdumbbell int cp_mode; 202254885Sdumbbell int cp_running; 203254885Sdumbbell 204254885Sdumbbell drm_radeon_freelist_t *head; 205254885Sdumbbell drm_radeon_freelist_t *tail; 206254885Sdumbbell int last_buf; 207254885Sdumbbell int writeback_works; 208254885Sdumbbell 209254885Sdumbbell int usec_timeout; 210254885Sdumbbell 211254885Sdumbbell int microcode_version; 212254885Sdumbbell 213254885Sdumbbell struct { 214254885Sdumbbell u32 boxes; 215254885Sdumbbell int freelist_timeouts; 216254885Sdumbbell int freelist_loops; 217254885Sdumbbell int requested_bufs; 218254885Sdumbbell int last_frame_reads; 219254885Sdumbbell int last_clear_reads; 220254885Sdumbbell int clears; 221254885Sdumbbell int texture_uploads; 222254885Sdumbbell } stats; 223254885Sdumbbell 224254885Sdumbbell int do_boxes; 225254885Sdumbbell int page_flipping; 226254885Sdumbbell 227254885Sdumbbell u32 color_fmt; 228254885Sdumbbell unsigned int front_offset; 229254885Sdumbbell unsigned int front_pitch; 230254885Sdumbbell unsigned int back_offset; 231254885Sdumbbell unsigned int back_pitch; 232254885Sdumbbell 233254885Sdumbbell u32 depth_fmt; 234254885Sdumbbell unsigned int depth_offset; 235254885Sdumbbell unsigned int depth_pitch; 236254885Sdumbbell 237254885Sdumbbell u32 front_pitch_offset; 238254885Sdumbbell u32 back_pitch_offset; 239254885Sdumbbell u32 depth_pitch_offset; 240254885Sdumbbell 241254885Sdumbbell drm_radeon_depth_clear_t depth_clear; 242254885Sdumbbell 243254885Sdumbbell unsigned long ring_offset; 244254885Sdumbbell unsigned long ring_rptr_offset; 245254885Sdumbbell unsigned long buffers_offset; 246254885Sdumbbell unsigned long gart_textures_offset; 247254885Sdumbbell 248254885Sdumbbell drm_local_map_t *sarea; 249254885Sdumbbell drm_local_map_t *cp_ring; 250254885Sdumbbell drm_local_map_t *ring_rptr; 251254885Sdumbbell drm_local_map_t *gart_textures; 252254885Sdumbbell 253254885Sdumbbell struct mem_block *gart_heap; 254254885Sdumbbell struct mem_block *fb_heap; 255254885Sdumbbell 256254885Sdumbbell /* SW interrupt */ 257254885Sdumbbell wait_queue_head_t swi_queue; 258254885Sdumbbell atomic_t swi_emitted; 259254885Sdumbbell int vblank_crtc; 260254885Sdumbbell uint32_t irq_enable_reg; 261254885Sdumbbell uint32_t r500_disp_irq_reg; 262254885Sdumbbell 263254885Sdumbbell struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 264254885Sdumbbell struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 265254885Sdumbbell 266254885Sdumbbell unsigned long pcigart_offset; 267254885Sdumbbell unsigned int pcigart_offset_set; 268254885Sdumbbell struct drm_ati_pcigart_info gart_info; 269254885Sdumbbell 270254885Sdumbbell u32 scratch_ages[5]; 271254885Sdumbbell 272254885Sdumbbell int have_z_offset; 273254885Sdumbbell 274254885Sdumbbell /* starting from here on, data is preserved across an open */ 275254885Sdumbbell uint32_t flags; /* see radeon_chip_flags */ 276254885Sdumbbell resource_size_t fb_aper_offset; 277254885Sdumbbell 278254885Sdumbbell int num_gb_pipes; 279254885Sdumbbell int num_z_pipes; 280254885Sdumbbell int track_flush; 281254885Sdumbbell drm_local_map_t *mmio; 282254885Sdumbbell 283254885Sdumbbell /* r6xx/r7xx pipe/shader config */ 284254885Sdumbbell int r600_max_pipes; 285254885Sdumbbell int r600_max_tile_pipes; 286254885Sdumbbell int r600_max_simds; 287254885Sdumbbell int r600_max_backends; 288254885Sdumbbell int r600_max_gprs; 289254885Sdumbbell int r600_max_threads; 290254885Sdumbbell int r600_max_stack_entries; 291254885Sdumbbell int r600_max_hw_contexts; 292254885Sdumbbell int r600_max_gs_threads; 293254885Sdumbbell int r600_sx_max_export_size; 294254885Sdumbbell int r600_sx_max_export_pos_size; 295254885Sdumbbell int r600_sx_max_export_smx_size; 296254885Sdumbbell int r600_sq_num_cf_insts; 297254885Sdumbbell int r700_sx_num_of_sets; 298254885Sdumbbell int r700_sc_prim_fifo_size; 299254885Sdumbbell int r700_sc_hiz_tile_fifo_size; 300254885Sdumbbell int r700_sc_earlyz_tile_fifo_fize; 301254885Sdumbbell int r600_group_size; 302254885Sdumbbell int r600_npipes; 303254885Sdumbbell int r600_nbanks; 304254885Sdumbbell 305254885Sdumbbell struct sx cs_mutex; 306254885Sdumbbell u32 cs_id_scnt; 307254885Sdumbbell u32 cs_id_wcnt; 308254885Sdumbbell /* r6xx/r7xx drm blit vertex buffer */ 309254885Sdumbbell struct drm_buf *blit_vb; 310254885Sdumbbell 311254885Sdumbbell /* firmware */ 312254885Sdumbbell const struct firmware *me_fw, *pfp_fw; 313254885Sdumbbell} drm_radeon_private_t; 314254885Sdumbbell 315254885Sdumbbelltypedef struct drm_radeon_buf_priv { 316254885Sdumbbell u32 age; 317254885Sdumbbell} drm_radeon_buf_priv_t; 318254885Sdumbbell 319254885Sdumbbellstruct drm_buffer; 320254885Sdumbbell 321254885Sdumbbelltypedef struct drm_radeon_kcmd_buffer { 322254885Sdumbbell int bufsz; 323254885Sdumbbell struct drm_buffer *buffer; 324254885Sdumbbell int nbox; 325254885Sdumbbell struct drm_clip_rect __user *boxes; 326254885Sdumbbell} drm_radeon_kcmd_buffer_t; 327254885Sdumbbell 328254885Sdumbbellextern int radeon_no_wb; 329254885Sdumbbellextern struct drm_ioctl_desc radeon_ioctls[]; 330254885Sdumbbellextern int radeon_max_ioctl; 331282199Sdumbbell#ifdef COMPAT_FREEBSD32 332282199Sdumbbellextern struct drm_ioctl_desc radeon_compat_ioctls[]; 333282199Sdumbbellextern int radeon_num_compat_ioctls; 334282199Sdumbbell#endif 335254885Sdumbbell 336254885Sdumbbellextern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 337254885Sdumbbellextern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 338254885Sdumbbell 339254885Sdumbbell#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 340254885Sdumbbell#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 341254885Sdumbbell 342254885Sdumbbell/* Check whether the given hardware address is inside the framebuffer or the 343254885Sdumbbell * GART area. 344254885Sdumbbell */ 345254885Sdumbbellstatic __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 346254885Sdumbbell u64 off) 347254885Sdumbbell{ 348254885Sdumbbell u32 fb_start = dev_priv->fb_location; 349254885Sdumbbell u32 fb_end = fb_start + dev_priv->fb_size - 1; 350254885Sdumbbell u32 gart_start = dev_priv->gart_vm_start; 351254885Sdumbbell u32 gart_end = gart_start + dev_priv->gart_size - 1; 352254885Sdumbbell 353254885Sdumbbell return ((off >= fb_start && off <= fb_end) || 354254885Sdumbbell (off >= gart_start && off <= gart_end)); 355254885Sdumbbell} 356254885Sdumbbell 357254885Sdumbbell/* radeon_state.c */ 358254885Sdumbbellextern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); 359254885Sdumbbell 360254885Sdumbbell /* radeon_cp.c */ 361254885Sdumbbellextern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 362254885Sdumbbellextern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 363254885Sdumbbellextern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 364254885Sdumbbellextern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 365254885Sdumbbellextern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 366254885Sdumbbellextern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 367254885Sdumbbellextern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 368254885Sdumbbellextern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 369254885Sdumbbellextern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 370254885Sdumbbellextern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 371254885Sdumbbellextern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 372254885Sdumbbellextern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 373254885Sdumbbell 374254885Sdumbbellextern void radeon_freelist_reset(struct drm_device * dev); 375254885Sdumbbellextern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 376254885Sdumbbell 377254885Sdumbbellextern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 378254885Sdumbbell 379254885Sdumbbellextern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 380254885Sdumbbell 381254885Sdumbbellextern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 382254885Sdumbbellextern int radeon_presetup(struct drm_device *dev); 383254885Sdumbbellextern int radeon_driver_postcleanup(struct drm_device *dev); 384254885Sdumbbell 385254885Sdumbbellextern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 386254885Sdumbbellextern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 387254885Sdumbbellextern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 388254885Sdumbbellextern void radeon_mem_takedown(struct mem_block **heap); 389254885Sdumbbellextern void radeon_mem_release(struct drm_file *file_priv, 390254885Sdumbbell struct mem_block *heap); 391254885Sdumbbell 392254885Sdumbbellextern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 393254885Sdumbbellextern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 394254885Sdumbbellextern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 395254885Sdumbbell 396254885Sdumbbell /* radeon_irq.c */ 397254885Sdumbbellextern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 398254885Sdumbbellextern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 399254885Sdumbbellextern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 400254885Sdumbbell 401254885Sdumbbellextern void radeon_do_release(struct drm_device * dev); 402254885Sdumbbellextern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 403254885Sdumbbellextern int radeon_enable_vblank(struct drm_device *dev, int crtc); 404254885Sdumbbellextern void radeon_disable_vblank(struct drm_device *dev, int crtc); 405254885Sdumbbellextern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 406254885Sdumbbellextern void radeon_driver_irq_preinstall(struct drm_device * dev); 407254885Sdumbbellextern int radeon_driver_irq_postinstall(struct drm_device *dev); 408254885Sdumbbellextern void radeon_driver_irq_uninstall(struct drm_device * dev); 409254885Sdumbbellextern void radeon_enable_interrupt(struct drm_device *dev); 410254885Sdumbbellextern int radeon_vblank_crtc_get(struct drm_device *dev); 411254885Sdumbbellextern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 412254885Sdumbbell 413254885Sdumbbellextern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 414254885Sdumbbellextern int radeon_driver_unload(struct drm_device *dev); 415254885Sdumbbellextern int radeon_driver_firstopen(struct drm_device *dev); 416254885Sdumbbellextern void radeon_driver_preclose(struct drm_device *dev, 417254885Sdumbbell struct drm_file *file_priv); 418254885Sdumbbellextern void radeon_driver_postclose(struct drm_device *dev, 419254885Sdumbbell struct drm_file *file_priv); 420254885Sdumbbellextern void radeon_driver_lastclose(struct drm_device * dev); 421254885Sdumbbellextern int radeon_driver_open(struct drm_device *dev, 422254885Sdumbbell struct drm_file *file_priv); 423254885Sdumbbellextern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 424254885Sdumbbell unsigned long arg); 425254885Sdumbbellextern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 426254885Sdumbbell unsigned long arg); 427254885Sdumbbell 428254885Sdumbbellextern int radeon_master_create(struct drm_device *dev, struct drm_master *master); 429254885Sdumbbellextern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); 430254885Sdumbbellextern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master); 431254885Sdumbbell/* r300_cmdbuf.c */ 432254885Sdumbbellextern void r300_init_reg_flags(struct drm_device *dev); 433254885Sdumbbell 434254885Sdumbbellextern int r300_do_cp_cmdbuf(struct drm_device *dev, 435254885Sdumbbell struct drm_file *file_priv, 436254885Sdumbbell drm_radeon_kcmd_buffer_t *cmdbuf); 437254885Sdumbbell 438254885Sdumbbell/* r600_cp.c */ 439254885Sdumbbellextern int r600_do_engine_reset(struct drm_device *dev); 440254885Sdumbbellextern int r600_do_cleanup_cp(struct drm_device *dev); 441254885Sdumbbellextern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 442254885Sdumbbell struct drm_file *file_priv); 443254885Sdumbbellextern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 444254885Sdumbbellextern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 445254885Sdumbbellextern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 446254885Sdumbbellextern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 447254885Sdumbbellextern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 448254885Sdumbbellextern int r600_cp_dispatch_indirect(struct drm_device *dev, 449254885Sdumbbell struct drm_buf *buf, int start, int end); 450254885Sdumbbellextern int r600_page_table_init(struct drm_device *dev); 451254885Sdumbbellextern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 452254885Sdumbbellextern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 453254885Sdumbbellextern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); 454254885Sdumbbellextern int r600_cp_dispatch_texture(struct drm_device *dev, 455254885Sdumbbell struct drm_file *file_priv, 456254885Sdumbbell drm_radeon_texture_t *tex, 457254885Sdumbbell drm_radeon_tex_image_t *image); 458254885Sdumbbell/* r600_blit.c */ 459254885Sdumbbellextern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); 460254885Sdumbbellextern void r600_done_blit_copy(struct drm_device *dev); 461254885Sdumbbellextern void r600_blit_copy(struct drm_device *dev, 462254885Sdumbbell uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 463254885Sdumbbell int size_bytes); 464254885Sdumbbellextern void r600_blit_swap(struct drm_device *dev, 465254885Sdumbbell uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 466254885Sdumbbell int sx, int sy, int dx, int dy, 467254885Sdumbbell int w, int h, int src_pitch, int dst_pitch, int cpp); 468254885Sdumbbell 469254885Sdumbbell/* atpx handler */ 470282199Sdumbbell#if defined(CONFIG_VGA_SWITCHEROO) 471254885Sdumbbellvoid radeon_register_atpx_handler(void); 472254885Sdumbbellvoid radeon_unregister_atpx_handler(void); 473282199Sdumbbell#else 474282199Sdumbbellstatic inline void radeon_register_atpx_handler(void) {} 475282199Sdumbbellstatic inline void radeon_unregister_atpx_handler(void) {} 476282199Sdumbbell#endif 477254885Sdumbbell 478254885Sdumbbell/* Flags for stats.boxes 479254885Sdumbbell */ 480254885Sdumbbell#define RADEON_BOX_DMA_IDLE 0x1 481254885Sdumbbell#define RADEON_BOX_RING_FULL 0x2 482254885Sdumbbell#define RADEON_BOX_FLIP 0x4 483254885Sdumbbell#define RADEON_BOX_WAIT_IDLE 0x8 484254885Sdumbbell#define RADEON_BOX_TEXTURE_LOAD 0x10 485254885Sdumbbell 486254885Sdumbbell/* Register definitions, register access macros and drmAddMap constants 487254885Sdumbbell * for Radeon kernel driver. 488254885Sdumbbell */ 489254885Sdumbbell#define RADEON_MM_INDEX 0x0000 490254885Sdumbbell#define RADEON_MM_DATA 0x0004 491254885Sdumbbell 492254885Sdumbbell#define RADEON_AGP_COMMAND 0x0f60 493254885Sdumbbell#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 494254885Sdumbbell# define RADEON_AGP_ENABLE (1<<8) 495254885Sdumbbell#define RADEON_AUX_SCISSOR_CNTL 0x26f0 496254885Sdumbbell# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 497254885Sdumbbell# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 498254885Sdumbbell# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 499254885Sdumbbell# define RADEON_SCISSOR_0_ENABLE (1 << 28) 500254885Sdumbbell# define RADEON_SCISSOR_1_ENABLE (1 << 29) 501254885Sdumbbell# define RADEON_SCISSOR_2_ENABLE (1 << 30) 502254885Sdumbbell 503254885Sdumbbell/* 504254885Sdumbbell * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 505254885Sdumbbell * don't have an explicit bus mastering disable bit. It's handled 506254885Sdumbbell * by the PCI D-states. PMI_BM_DIS disables D-state bus master 507254885Sdumbbell * handling, not bus mastering itself. 508254885Sdumbbell */ 509254885Sdumbbell#define RADEON_BUS_CNTL 0x0030 510254885Sdumbbell/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 511254885Sdumbbell# define RADEON_BUS_MASTER_DIS (1 << 6) 512254885Sdumbbell/* rs600/rs690/rs740 */ 513254885Sdumbbell# define RS600_BUS_MASTER_DIS (1 << 14) 514254885Sdumbbell# define RS600_MSI_REARM (1 << 20) 515254885Sdumbbell/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 516254885Sdumbbell 517254885Sdumbbell#define RADEON_BUS_CNTL1 0x0034 518254885Sdumbbell# define RADEON_PMI_BM_DIS (1 << 2) 519254885Sdumbbell# define RADEON_PMI_INT_DIS (1 << 3) 520254885Sdumbbell 521254885Sdumbbell#define RV370_BUS_CNTL 0x004c 522254885Sdumbbell# define RV370_PMI_BM_DIS (1 << 5) 523254885Sdumbbell# define RV370_PMI_INT_DIS (1 << 6) 524254885Sdumbbell 525254885Sdumbbell#define RADEON_MSI_REARM_EN 0x0160 526254885Sdumbbell/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 527254885Sdumbbell# define RV370_MSI_REARM_EN (1 << 0) 528254885Sdumbbell 529254885Sdumbbell#define RADEON_CLOCK_CNTL_DATA 0x000c 530254885Sdumbbell# define RADEON_PLL_WR_EN (1 << 7) 531254885Sdumbbell#define RADEON_CLOCK_CNTL_INDEX 0x0008 532254885Sdumbbell#define RADEON_CONFIG_APER_SIZE 0x0108 533254885Sdumbbell#define RADEON_CONFIG_MEMSIZE 0x00f8 534254885Sdumbbell#define RADEON_CRTC_OFFSET 0x0224 535254885Sdumbbell#define RADEON_CRTC_OFFSET_CNTL 0x0228 536254885Sdumbbell# define RADEON_CRTC_TILE_EN (1 << 15) 537254885Sdumbbell# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 538254885Sdumbbell#define RADEON_CRTC2_OFFSET 0x0324 539254885Sdumbbell#define RADEON_CRTC2_OFFSET_CNTL 0x0328 540254885Sdumbbell 541254885Sdumbbell#define RADEON_PCIE_INDEX 0x0030 542254885Sdumbbell#define RADEON_PCIE_DATA 0x0034 543254885Sdumbbell#define RADEON_PCIE_TX_GART_CNTL 0x10 544254885Sdumbbell# define RADEON_PCIE_TX_GART_EN (1 << 0) 545254885Sdumbbell# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 546254885Sdumbbell# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 547254885Sdumbbell# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 548254885Sdumbbell# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 549254885Sdumbbell# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 550254885Sdumbbell# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 551254885Sdumbbell# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 552254885Sdumbbell#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 553254885Sdumbbell#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 554254885Sdumbbell#define RADEON_PCIE_TX_GART_BASE 0x13 555254885Sdumbbell#define RADEON_PCIE_TX_GART_START_LO 0x14 556254885Sdumbbell#define RADEON_PCIE_TX_GART_START_HI 0x15 557254885Sdumbbell#define RADEON_PCIE_TX_GART_END_LO 0x16 558254885Sdumbbell#define RADEON_PCIE_TX_GART_END_HI 0x17 559254885Sdumbbell 560254885Sdumbbell#define RS480_NB_MC_INDEX 0x168 561254885Sdumbbell# define RS480_NB_MC_IND_WR_EN (1 << 8) 562254885Sdumbbell#define RS480_NB_MC_DATA 0x16c 563254885Sdumbbell 564254885Sdumbbell#define RS690_MC_INDEX 0x78 565254885Sdumbbell# define RS690_MC_INDEX_MASK 0x1ff 566254885Sdumbbell# define RS690_MC_INDEX_WR_EN (1 << 9) 567254885Sdumbbell# define RS690_MC_INDEX_WR_ACK 0x7f 568254885Sdumbbell#define RS690_MC_DATA 0x7c 569254885Sdumbbell 570254885Sdumbbell/* MC indirect registers */ 571254885Sdumbbell#define RS480_MC_MISC_CNTL 0x18 572254885Sdumbbell# define RS480_DISABLE_GTW (1 << 1) 573254885Sdumbbell/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 574254885Sdumbbell# define RS480_GART_INDEX_REG_EN (1 << 12) 575254885Sdumbbell# define RS690_BLOCK_GFX_D3_EN (1 << 14) 576254885Sdumbbell#define RS480_K8_FB_LOCATION 0x1e 577254885Sdumbbell#define RS480_GART_FEATURE_ID 0x2b 578254885Sdumbbell# define RS480_HANG_EN (1 << 11) 579254885Sdumbbell# define RS480_TLB_ENABLE (1 << 18) 580254885Sdumbbell# define RS480_P2P_ENABLE (1 << 19) 581254885Sdumbbell# define RS480_GTW_LAC_EN (1 << 25) 582254885Sdumbbell# define RS480_2LEVEL_GART (0 << 30) 583254885Sdumbbell# define RS480_1LEVEL_GART (1 << 30) 584261455Seadler# define RS480_PDC_EN (1U << 31) 585254885Sdumbbell#define RS480_GART_BASE 0x2c 586254885Sdumbbell#define RS480_GART_CACHE_CNTRL 0x2e 587254885Sdumbbell# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 588254885Sdumbbell#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 589254885Sdumbbell# define RS480_GART_EN (1 << 0) 590254885Sdumbbell# define RS480_VA_SIZE_32MB (0 << 1) 591254885Sdumbbell# define RS480_VA_SIZE_64MB (1 << 1) 592254885Sdumbbell# define RS480_VA_SIZE_128MB (2 << 1) 593254885Sdumbbell# define RS480_VA_SIZE_256MB (3 << 1) 594254885Sdumbbell# define RS480_VA_SIZE_512MB (4 << 1) 595254885Sdumbbell# define RS480_VA_SIZE_1GB (5 << 1) 596254885Sdumbbell# define RS480_VA_SIZE_2GB (6 << 1) 597254885Sdumbbell#define RS480_AGP_MODE_CNTL 0x39 598254885Sdumbbell# define RS480_POST_GART_Q_SIZE (1 << 18) 599254885Sdumbbell# define RS480_NONGART_SNOOP (1 << 19) 600254885Sdumbbell# define RS480_AGP_RD_BUF_SIZE (1 << 20) 601254885Sdumbbell# define RS480_REQ_TYPE_SNOOP_SHIFT 22 602254885Sdumbbell# define RS480_REQ_TYPE_SNOOP_MASK 0x3 603254885Sdumbbell# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 604254885Sdumbbell#define RS480_MC_MISC_UMA_CNTL 0x5f 605254885Sdumbbell#define RS480_MC_MCLK_CNTL 0x7a 606254885Sdumbbell#define RS480_MC_UMA_DUALCH_CNTL 0x86 607254885Sdumbbell 608254885Sdumbbell#define RS690_MC_FB_LOCATION 0x100 609254885Sdumbbell#define RS690_MC_AGP_LOCATION 0x101 610254885Sdumbbell#define RS690_MC_AGP_BASE 0x102 611254885Sdumbbell#define RS690_MC_AGP_BASE_2 0x103 612254885Sdumbbell 613254885Sdumbbell#define RS600_MC_INDEX 0x70 614254885Sdumbbell# define RS600_MC_ADDR_MASK 0xffff 615254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 616254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 617254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 618254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 619254885Sdumbbell# define RS600_MC_IND_AIC_RBS (1 << 20) 620254885Sdumbbell# define RS600_MC_IND_CITF_ARB0 (1 << 21) 621254885Sdumbbell# define RS600_MC_IND_CITF_ARB1 (1 << 22) 622254885Sdumbbell# define RS600_MC_IND_WR_EN (1 << 23) 623254885Sdumbbell#define RS600_MC_DATA 0x74 624254885Sdumbbell 625254885Sdumbbell#define RS600_MC_STATUS 0x0 626254885Sdumbbell# define RS600_MC_IDLE (1 << 1) 627254885Sdumbbell#define RS600_MC_FB_LOCATION 0x4 628254885Sdumbbell#define RS600_MC_AGP_LOCATION 0x5 629254885Sdumbbell#define RS600_AGP_BASE 0x6 630254885Sdumbbell#define RS600_AGP_BASE_2 0x7 631254885Sdumbbell#define RS600_MC_CNTL1 0x9 632254885Sdumbbell# define RS600_ENABLE_PAGE_TABLES (1 << 26) 633254885Sdumbbell#define RS600_MC_PT0_CNTL 0x100 634254885Sdumbbell# define RS600_ENABLE_PT (1 << 0) 635254885Sdumbbell# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 636254885Sdumbbell# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 637254885Sdumbbell# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 638254885Sdumbbell# define RS600_INVALIDATE_L2_CACHE (1 << 29) 639254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 640254885Sdumbbell# define RS600_ENABLE_PAGE_TABLE (1 << 0) 641254885Sdumbbell# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 642254885Sdumbbell#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 643254885Sdumbbell#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 644254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 645254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 646254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 647254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 648254885Sdumbbell#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 649254885Sdumbbell# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 650254885Sdumbbell# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 651254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 652254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 653254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 654254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 655254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 656254885Sdumbbell# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 657254885Sdumbbell# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 658254885Sdumbbell# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 659254885Sdumbbell# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 660254885Sdumbbell# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 661254885Sdumbbell# define RS600_INVALIDATE_L1_TLB (1 << 20) 662254885Sdumbbell 663254885Sdumbbell#define R520_MC_IND_INDEX 0x70 664254885Sdumbbell#define R520_MC_IND_WR_EN (1 << 24) 665254885Sdumbbell#define R520_MC_IND_DATA 0x74 666254885Sdumbbell 667254885Sdumbbell#define RV515_MC_FB_LOCATION 0x01 668254885Sdumbbell#define RV515_MC_AGP_LOCATION 0x02 669254885Sdumbbell#define RV515_MC_AGP_BASE 0x03 670254885Sdumbbell#define RV515_MC_AGP_BASE_2 0x04 671254885Sdumbbell 672254885Sdumbbell#define R520_MC_FB_LOCATION 0x04 673254885Sdumbbell#define R520_MC_AGP_LOCATION 0x05 674254885Sdumbbell#define R520_MC_AGP_BASE 0x06 675254885Sdumbbell#define R520_MC_AGP_BASE_2 0x07 676254885Sdumbbell 677254885Sdumbbell#define RADEON_MPP_TB_CONFIG 0x01c0 678254885Sdumbbell#define RADEON_MEM_CNTL 0x0140 679254885Sdumbbell#define RADEON_MEM_SDRAM_MODE_REG 0x0158 680254885Sdumbbell#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 681254885Sdumbbell#define RS480_AGP_BASE_2 0x0164 682254885Sdumbbell#define RADEON_AGP_BASE 0x0170 683254885Sdumbbell 684254885Sdumbbell/* pipe config regs */ 685254885Sdumbbell#define R400_GB_PIPE_SELECT 0x402c 686254885Sdumbbell#define RV530_GB_PIPE_SELECT2 0x4124 687254885Sdumbbell#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 688254885Sdumbbell#define R300_GB_TILE_CONFIG 0x4018 689254885Sdumbbell# define R300_ENABLE_TILING (1 << 0) 690254885Sdumbbell# define R300_PIPE_COUNT_RV350 (0 << 1) 691254885Sdumbbell# define R300_PIPE_COUNT_R300 (3 << 1) 692254885Sdumbbell# define R300_PIPE_COUNT_R420_3P (6 << 1) 693254885Sdumbbell# define R300_PIPE_COUNT_R420 (7 << 1) 694254885Sdumbbell# define R300_TILE_SIZE_8 (0 << 4) 695254885Sdumbbell# define R300_TILE_SIZE_16 (1 << 4) 696254885Sdumbbell# define R300_TILE_SIZE_32 (2 << 4) 697254885Sdumbbell# define R300_SUBPIXEL_1_12 (0 << 16) 698254885Sdumbbell# define R300_SUBPIXEL_1_16 (1 << 16) 699254885Sdumbbell#define R300_DST_PIPE_CONFIG 0x170c 700261455Seadler# define R300_PIPE_AUTO_CONFIG (1U << 31) 701254885Sdumbbell#define R300_RB2D_DSTCACHE_MODE 0x3428 702254885Sdumbbell# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 703254885Sdumbbell# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 704254885Sdumbbell 705254885Sdumbbell#define RADEON_RB3D_COLOROFFSET 0x1c40 706254885Sdumbbell#define RADEON_RB3D_COLORPITCH 0x1c48 707254885Sdumbbell 708254885Sdumbbell#define RADEON_SRC_X_Y 0x1590 709254885Sdumbbell 710254885Sdumbbell#define RADEON_DP_GUI_MASTER_CNTL 0x146c 711254885Sdumbbell# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 712254885Sdumbbell# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 713254885Sdumbbell# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 714254885Sdumbbell# define RADEON_GMC_BRUSH_NONE (15 << 4) 715254885Sdumbbell# define RADEON_GMC_DST_16BPP (4 << 8) 716254885Sdumbbell# define RADEON_GMC_DST_24BPP (5 << 8) 717254885Sdumbbell# define RADEON_GMC_DST_32BPP (6 << 8) 718254885Sdumbbell# define RADEON_GMC_DST_DATATYPE_SHIFT 8 719254885Sdumbbell# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 720254885Sdumbbell# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 721254885Sdumbbell# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 722254885Sdumbbell# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 723254885Sdumbbell# define RADEON_GMC_WR_MSK_DIS (1 << 30) 724254885Sdumbbell# define RADEON_ROP3_S 0x00cc0000 725254885Sdumbbell# define RADEON_ROP3_P 0x00f00000 726254885Sdumbbell#define RADEON_DP_WRITE_MASK 0x16cc 727254885Sdumbbell#define RADEON_SRC_PITCH_OFFSET 0x1428 728254885Sdumbbell#define RADEON_DST_PITCH_OFFSET 0x142c 729254885Sdumbbell#define RADEON_DST_PITCH_OFFSET_C 0x1c80 730254885Sdumbbell# define RADEON_DST_TILE_LINEAR (0 << 30) 731254885Sdumbbell# define RADEON_DST_TILE_MACRO (1 << 30) 732261455Seadler# define RADEON_DST_TILE_MICRO (2U << 30) 733261455Seadler# define RADEON_DST_TILE_BOTH (3U << 30) 734254885Sdumbbell 735254885Sdumbbell#define RADEON_SCRATCH_REG0 0x15e0 736254885Sdumbbell#define RADEON_SCRATCH_REG1 0x15e4 737254885Sdumbbell#define RADEON_SCRATCH_REG2 0x15e8 738254885Sdumbbell#define RADEON_SCRATCH_REG3 0x15ec 739254885Sdumbbell#define RADEON_SCRATCH_REG4 0x15f0 740254885Sdumbbell#define RADEON_SCRATCH_REG5 0x15f4 741254885Sdumbbell#define RADEON_SCRATCH_UMSK 0x0770 742254885Sdumbbell#define RADEON_SCRATCH_ADDR 0x0774 743254885Sdumbbell 744254885Sdumbbell#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 745254885Sdumbbell 746254885Sdumbbellextern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 747254885Sdumbbell 748254885Sdumbbell#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 749254885Sdumbbell 750254885Sdumbbell#define R600_SCRATCH_REG0 0x8500 751254885Sdumbbell#define R600_SCRATCH_REG1 0x8504 752254885Sdumbbell#define R600_SCRATCH_REG2 0x8508 753254885Sdumbbell#define R600_SCRATCH_REG3 0x850c 754254885Sdumbbell#define R600_SCRATCH_REG4 0x8510 755254885Sdumbbell#define R600_SCRATCH_REG5 0x8514 756254885Sdumbbell#define R600_SCRATCH_REG6 0x8518 757254885Sdumbbell#define R600_SCRATCH_REG7 0x851c 758254885Sdumbbell#define R600_SCRATCH_UMSK 0x8540 759254885Sdumbbell#define R600_SCRATCH_ADDR 0x8544 760254885Sdumbbell 761254885Sdumbbell#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 762254885Sdumbbell 763254885Sdumbbell#define RADEON_GEN_INT_CNTL 0x0040 764254885Sdumbbell# define RADEON_CRTC_VBLANK_MASK (1 << 0) 765254885Sdumbbell# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 766254885Sdumbbell# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 767254885Sdumbbell# define RADEON_SW_INT_ENABLE (1 << 25) 768254885Sdumbbell 769254885Sdumbbell#define RADEON_GEN_INT_STATUS 0x0044 770254885Sdumbbell# define RADEON_CRTC_VBLANK_STAT (1 << 0) 771254885Sdumbbell# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 772254885Sdumbbell# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 773254885Sdumbbell# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 774254885Sdumbbell# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 775254885Sdumbbell# define RADEON_SW_INT_TEST (1 << 25) 776254885Sdumbbell# define RADEON_SW_INT_TEST_ACK (1 << 25) 777254885Sdumbbell# define RADEON_SW_INT_FIRE (1 << 26) 778254885Sdumbbell# define R500_DISPLAY_INT_STATUS (1 << 0) 779254885Sdumbbell 780254885Sdumbbell#define RADEON_HOST_PATH_CNTL 0x0130 781254885Sdumbbell# define RADEON_HDP_SOFT_RESET (1 << 26) 782254885Sdumbbell# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 783254885Sdumbbell# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 784254885Sdumbbell 785254885Sdumbbell#define RADEON_ISYNC_CNTL 0x1724 786254885Sdumbbell# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 787254885Sdumbbell# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 788254885Sdumbbell# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 789254885Sdumbbell# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 790254885Sdumbbell# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 791254885Sdumbbell# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 792254885Sdumbbell 793254885Sdumbbell#define RADEON_RBBM_GUICNTL 0x172c 794254885Sdumbbell# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 795254885Sdumbbell# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 796254885Sdumbbell# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 797254885Sdumbbell# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 798254885Sdumbbell 799254885Sdumbbell#define RADEON_MC_AGP_LOCATION 0x014c 800254885Sdumbbell#define RADEON_MC_FB_LOCATION 0x0148 801254885Sdumbbell#define RADEON_MCLK_CNTL 0x0012 802254885Sdumbbell# define RADEON_FORCEON_MCLKA (1 << 16) 803254885Sdumbbell# define RADEON_FORCEON_MCLKB (1 << 17) 804254885Sdumbbell# define RADEON_FORCEON_YCLKA (1 << 18) 805254885Sdumbbell# define RADEON_FORCEON_YCLKB (1 << 19) 806254885Sdumbbell# define RADEON_FORCEON_MC (1 << 20) 807254885Sdumbbell# define RADEON_FORCEON_AIC (1 << 21) 808254885Sdumbbell 809254885Sdumbbell#define RADEON_PP_BORDER_COLOR_0 0x1d40 810254885Sdumbbell#define RADEON_PP_BORDER_COLOR_1 0x1d44 811254885Sdumbbell#define RADEON_PP_BORDER_COLOR_2 0x1d48 812254885Sdumbbell#define RADEON_PP_CNTL 0x1c38 813254885Sdumbbell# define RADEON_SCISSOR_ENABLE (1 << 1) 814254885Sdumbbell#define RADEON_PP_LUM_MATRIX 0x1d00 815254885Sdumbbell#define RADEON_PP_MISC 0x1c14 816254885Sdumbbell#define RADEON_PP_ROT_MATRIX_0 0x1d58 817254885Sdumbbell#define RADEON_PP_TXFILTER_0 0x1c54 818254885Sdumbbell#define RADEON_PP_TXOFFSET_0 0x1c5c 819254885Sdumbbell#define RADEON_PP_TXFILTER_1 0x1c6c 820254885Sdumbbell#define RADEON_PP_TXFILTER_2 0x1c84 821254885Sdumbbell 822254885Sdumbbell#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 823254885Sdumbbell#define R300_DSTCACHE_CTLSTAT 0x1714 824254885Sdumbbell# define R300_RB2D_DC_FLUSH (3 << 0) 825254885Sdumbbell# define R300_RB2D_DC_FREE (3 << 2) 826254885Sdumbbell# define R300_RB2D_DC_FLUSH_ALL 0xf 827261455Seadler# define R300_RB2D_DC_BUSY (1U << 31) 828254885Sdumbbell#define RADEON_RB3D_CNTL 0x1c3c 829254885Sdumbbell# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 830254885Sdumbbell# define RADEON_PLANE_MASK_ENABLE (1 << 1) 831254885Sdumbbell# define RADEON_DITHER_ENABLE (1 << 2) 832254885Sdumbbell# define RADEON_ROUND_ENABLE (1 << 3) 833254885Sdumbbell# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 834254885Sdumbbell# define RADEON_DITHER_INIT (1 << 5) 835254885Sdumbbell# define RADEON_ROP_ENABLE (1 << 6) 836254885Sdumbbell# define RADEON_STENCIL_ENABLE (1 << 7) 837254885Sdumbbell# define RADEON_Z_ENABLE (1 << 8) 838254885Sdumbbell# define RADEON_ZBLOCK16 (1 << 15) 839254885Sdumbbell#define RADEON_RB3D_DEPTHOFFSET 0x1c24 840254885Sdumbbell#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 841254885Sdumbbell#define RADEON_RB3D_DEPTHPITCH 0x1c28 842254885Sdumbbell#define RADEON_RB3D_PLANEMASK 0x1d84 843254885Sdumbbell#define RADEON_RB3D_STENCILREFMASK 0x1d7c 844254885Sdumbbell#define RADEON_RB3D_ZCACHE_MODE 0x3250 845254885Sdumbbell#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 846254885Sdumbbell# define RADEON_RB3D_ZC_FLUSH (1 << 0) 847254885Sdumbbell# define RADEON_RB3D_ZC_FREE (1 << 2) 848254885Sdumbbell# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 849261455Seadler# define RADEON_RB3D_ZC_BUSY (1U << 31) 850254885Sdumbbell#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 851254885Sdumbbell# define R300_ZC_FLUSH (1 << 0) 852254885Sdumbbell# define R300_ZC_FREE (1 << 1) 853261455Seadler# define R300_ZC_BUSY (1U << 31) 854254885Sdumbbell#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 855254885Sdumbbell# define RADEON_RB3D_DC_FLUSH (3 << 0) 856254885Sdumbbell# define RADEON_RB3D_DC_FREE (3 << 2) 857254885Sdumbbell# define RADEON_RB3D_DC_FLUSH_ALL 0xf 858261455Seadler# define RADEON_RB3D_DC_BUSY (1U << 31) 859254885Sdumbbell#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 860254885Sdumbbell# define R300_RB3D_DC_FLUSH (2 << 0) 861254885Sdumbbell# define R300_RB3D_DC_FREE (2 << 2) 862254885Sdumbbell# define R300_RB3D_DC_FINISH (1 << 4) 863254885Sdumbbell#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 864254885Sdumbbell# define RADEON_Z_TEST_MASK (7 << 4) 865254885Sdumbbell# define RADEON_Z_TEST_ALWAYS (7 << 4) 866254885Sdumbbell# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 867254885Sdumbbell# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 868254885Sdumbbell# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 869254885Sdumbbell# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 870254885Sdumbbell# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 871254885Sdumbbell# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 872254885Sdumbbell# define RADEON_FORCE_Z_DIRTY (1 << 29) 873254885Sdumbbell# define RADEON_Z_WRITE_ENABLE (1 << 30) 874261455Seadler# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31) 875254885Sdumbbell#define RADEON_RBBM_SOFT_RESET 0x00f0 876254885Sdumbbell# define RADEON_SOFT_RESET_CP (1 << 0) 877254885Sdumbbell# define RADEON_SOFT_RESET_HI (1 << 1) 878254885Sdumbbell# define RADEON_SOFT_RESET_SE (1 << 2) 879254885Sdumbbell# define RADEON_SOFT_RESET_RE (1 << 3) 880254885Sdumbbell# define RADEON_SOFT_RESET_PP (1 << 4) 881254885Sdumbbell# define RADEON_SOFT_RESET_E2 (1 << 5) 882254885Sdumbbell# define RADEON_SOFT_RESET_RB (1 << 6) 883254885Sdumbbell# define RADEON_SOFT_RESET_HDP (1 << 7) 884254885Sdumbbell/* 885254885Sdumbbell * 6:0 Available slots in the FIFO 886254885Sdumbbell * 8 Host Interface active 887254885Sdumbbell * 9 CP request active 888254885Sdumbbell * 10 FIFO request active 889254885Sdumbbell * 11 Host Interface retry active 890254885Sdumbbell * 12 CP retry active 891254885Sdumbbell * 13 FIFO retry active 892254885Sdumbbell * 14 FIFO pipeline busy 893254885Sdumbbell * 15 Event engine busy 894254885Sdumbbell * 16 CP command stream busy 895254885Sdumbbell * 17 2D engine busy 896254885Sdumbbell * 18 2D portion of render backend busy 897254885Sdumbbell * 20 3D setup engine busy 898254885Sdumbbell * 26 GA engine busy 899254885Sdumbbell * 27 CBA 2D engine busy 900254885Sdumbbell * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 901254885Sdumbbell * command stream queue not empty or Ring Buffer not empty 902254885Sdumbbell */ 903254885Sdumbbell#define RADEON_RBBM_STATUS 0x0e40 904254885Sdumbbell/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 905254885Sdumbbell/* #define RADEON_RBBM_STATUS 0x1740 */ 906254885Sdumbbell/* bits 6:0 are dword slots available in the cmd fifo */ 907254885Sdumbbell# define RADEON_RBBM_FIFOCNT_MASK 0x007f 908254885Sdumbbell# define RADEON_HIRQ_ON_RBB (1 << 8) 909254885Sdumbbell# define RADEON_CPRQ_ON_RBB (1 << 9) 910254885Sdumbbell# define RADEON_CFRQ_ON_RBB (1 << 10) 911254885Sdumbbell# define RADEON_HIRQ_IN_RTBUF (1 << 11) 912254885Sdumbbell# define RADEON_CPRQ_IN_RTBUF (1 << 12) 913254885Sdumbbell# define RADEON_CFRQ_IN_RTBUF (1 << 13) 914254885Sdumbbell# define RADEON_PIPE_BUSY (1 << 14) 915254885Sdumbbell# define RADEON_ENG_EV_BUSY (1 << 15) 916254885Sdumbbell# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 917254885Sdumbbell# define RADEON_E2_BUSY (1 << 17) 918254885Sdumbbell# define RADEON_RB2D_BUSY (1 << 18) 919254885Sdumbbell# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 920254885Sdumbbell# define RADEON_VAP_BUSY (1 << 20) 921254885Sdumbbell# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 922254885Sdumbbell# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 923254885Sdumbbell# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 924254885Sdumbbell# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 925254885Sdumbbell# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 926254885Sdumbbell# define RADEON_GA_BUSY (1 << 26) 927254885Sdumbbell# define RADEON_CBA2D_BUSY (1 << 27) 928261455Seadler# define RADEON_RBBM_ACTIVE (1U << 31) 929254885Sdumbbell#define RADEON_RE_LINE_PATTERN 0x1cd0 930254885Sdumbbell#define RADEON_RE_MISC 0x26c4 931254885Sdumbbell#define RADEON_RE_TOP_LEFT 0x26c0 932254885Sdumbbell#define RADEON_RE_WIDTH_HEIGHT 0x1c44 933254885Sdumbbell#define RADEON_RE_STIPPLE_ADDR 0x1cc8 934254885Sdumbbell#define RADEON_RE_STIPPLE_DATA 0x1ccc 935254885Sdumbbell 936254885Sdumbbell#define RADEON_SCISSOR_TL_0 0x1cd8 937254885Sdumbbell#define RADEON_SCISSOR_BR_0 0x1cdc 938254885Sdumbbell#define RADEON_SCISSOR_TL_1 0x1ce0 939254885Sdumbbell#define RADEON_SCISSOR_BR_1 0x1ce4 940254885Sdumbbell#define RADEON_SCISSOR_TL_2 0x1ce8 941254885Sdumbbell#define RADEON_SCISSOR_BR_2 0x1cec 942254885Sdumbbell#define RADEON_SE_COORD_FMT 0x1c50 943254885Sdumbbell#define RADEON_SE_CNTL 0x1c4c 944254885Sdumbbell# define RADEON_FFACE_CULL_CW (0 << 0) 945254885Sdumbbell# define RADEON_BFACE_SOLID (3 << 1) 946254885Sdumbbell# define RADEON_FFACE_SOLID (3 << 3) 947254885Sdumbbell# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 948254885Sdumbbell# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 949254885Sdumbbell# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 950254885Sdumbbell# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 951254885Sdumbbell# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 952254885Sdumbbell# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 953254885Sdumbbell# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 954254885Sdumbbell# define RADEON_FOG_SHADE_FLAT (1 << 14) 955254885Sdumbbell# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 956254885Sdumbbell# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 957254885Sdumbbell# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 958254885Sdumbbell# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 959254885Sdumbbell# define RADEON_ROUND_MODE_TRUNC (0 << 28) 960254885Sdumbbell# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 961254885Sdumbbell#define RADEON_SE_CNTL_STATUS 0x2140 962254885Sdumbbell#define RADEON_SE_LINE_WIDTH 0x1db8 963254885Sdumbbell#define RADEON_SE_VPORT_XSCALE 0x1d98 964254885Sdumbbell#define RADEON_SE_ZBIAS_FACTOR 0x1db0 965254885Sdumbbell#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 966254885Sdumbbell#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 967254885Sdumbbell#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 968254885Sdumbbell# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 969254885Sdumbbell# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 970254885Sdumbbell#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 971254885Sdumbbell#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 972254885Sdumbbell# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 973254885Sdumbbell#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 974254885Sdumbbell#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 975254885Sdumbbell#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 976254885Sdumbbell#define RADEON_SURFACE_CNTL 0x0b00 977254885Sdumbbell# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 978254885Sdumbbell# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 979254885Sdumbbell# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 980254885Sdumbbell# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 981254885Sdumbbell# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 982254885Sdumbbell# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 983254885Sdumbbell# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 984254885Sdumbbell# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 985254885Sdumbbell# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 986254885Sdumbbell#define RADEON_SURFACE0_INFO 0x0b0c 987254885Sdumbbell# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 988254885Sdumbbell# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 989254885Sdumbbell# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 990254885Sdumbbell# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 991254885Sdumbbell# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 992254885Sdumbbell# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 993254885Sdumbbell#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 994254885Sdumbbell#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 995254885Sdumbbell# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 996254885Sdumbbell#define RADEON_SURFACE1_INFO 0x0b1c 997254885Sdumbbell#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 998254885Sdumbbell#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 999254885Sdumbbell#define RADEON_SURFACE2_INFO 0x0b2c 1000254885Sdumbbell#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1001254885Sdumbbell#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1002254885Sdumbbell#define RADEON_SURFACE3_INFO 0x0b3c 1003254885Sdumbbell#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1004254885Sdumbbell#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1005254885Sdumbbell#define RADEON_SURFACE4_INFO 0x0b4c 1006254885Sdumbbell#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1007254885Sdumbbell#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1008254885Sdumbbell#define RADEON_SURFACE5_INFO 0x0b5c 1009254885Sdumbbell#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1010254885Sdumbbell#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1011254885Sdumbbell#define RADEON_SURFACE6_INFO 0x0b6c 1012254885Sdumbbell#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1013254885Sdumbbell#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1014254885Sdumbbell#define RADEON_SURFACE7_INFO 0x0b7c 1015254885Sdumbbell#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1016254885Sdumbbell#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1017254885Sdumbbell#define RADEON_SW_SEMAPHORE 0x013c 1018254885Sdumbbell 1019254885Sdumbbell#define RADEON_WAIT_UNTIL 0x1720 1020254885Sdumbbell# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1021254885Sdumbbell# define RADEON_WAIT_2D_IDLE (1 << 14) 1022254885Sdumbbell# define RADEON_WAIT_3D_IDLE (1 << 15) 1023254885Sdumbbell# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1024254885Sdumbbell# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1025254885Sdumbbell# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1026254885Sdumbbell 1027254885Sdumbbell#define RADEON_RB3D_ZMASKOFFSET 0x3234 1028254885Sdumbbell#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1029254885Sdumbbell# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1030254885Sdumbbell# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1031254885Sdumbbell 1032254885Sdumbbell/* CP registers */ 1033254885Sdumbbell#define RADEON_CP_ME_RAM_ADDR 0x07d4 1034254885Sdumbbell#define RADEON_CP_ME_RAM_RADDR 0x07d8 1035254885Sdumbbell#define RADEON_CP_ME_RAM_DATAH 0x07dc 1036254885Sdumbbell#define RADEON_CP_ME_RAM_DATAL 0x07e0 1037254885Sdumbbell 1038254885Sdumbbell#define RADEON_CP_RB_BASE 0x0700 1039254885Sdumbbell#define RADEON_CP_RB_CNTL 0x0704 1040254885Sdumbbell# define RADEON_BUF_SWAP_32BIT (2 << 16) 1041254885Sdumbbell# define RADEON_RB_NO_UPDATE (1 << 27) 1042261455Seadler# define RADEON_RB_RPTR_WR_ENA (1U << 31) 1043254885Sdumbbell#define RADEON_CP_RB_RPTR_ADDR 0x070c 1044254885Sdumbbell#define RADEON_CP_RB_RPTR 0x0710 1045254885Sdumbbell#define RADEON_CP_RB_WPTR 0x0714 1046254885Sdumbbell 1047254885Sdumbbell#define RADEON_CP_RB_WPTR_DELAY 0x0718 1048254885Sdumbbell# define RADEON_PRE_WRITE_TIMER_SHIFT 0 1049254885Sdumbbell# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1050254885Sdumbbell 1051254885Sdumbbell#define RADEON_CP_IB_BASE 0x0738 1052254885Sdumbbell 1053254885Sdumbbell#define RADEON_CP_CSQ_CNTL 0x0740 1054254885Sdumbbell# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1055254885Sdumbbell# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1056254885Sdumbbell# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1057254885Sdumbbell# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1058254885Sdumbbell# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1059254885Sdumbbell# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1060254885Sdumbbell# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1061254885Sdumbbell 1062254885Sdumbbell#define R300_CP_RESYNC_ADDR 0x0778 1063254885Sdumbbell#define R300_CP_RESYNC_DATA 0x077c 1064254885Sdumbbell 1065254885Sdumbbell#define RADEON_AIC_CNTL 0x01d0 1066254885Sdumbbell# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1067254885Sdumbbell# define RS400_MSI_REARM (1 << 3) 1068254885Sdumbbell#define RADEON_AIC_STAT 0x01d4 1069254885Sdumbbell#define RADEON_AIC_PT_BASE 0x01d8 1070254885Sdumbbell#define RADEON_AIC_LO_ADDR 0x01dc 1071254885Sdumbbell#define RADEON_AIC_HI_ADDR 0x01e0 1072254885Sdumbbell#define RADEON_AIC_TLB_ADDR 0x01e4 1073254885Sdumbbell#define RADEON_AIC_TLB_DATA 0x01e8 1074254885Sdumbbell 1075254885Sdumbbell/* CP command packets */ 1076254885Sdumbbell#define RADEON_CP_PACKET0 0x00000000 1077254885Sdumbbell# define RADEON_ONE_REG_WR (1 << 15) 1078254885Sdumbbell#define RADEON_CP_PACKET1 0x40000000 1079254885Sdumbbell#define RADEON_CP_PACKET2 0x80000000 1080254885Sdumbbell#define RADEON_CP_PACKET3 0xC0000000 1081254885Sdumbbell# define RADEON_CP_NOP 0x00001000 1082254885Sdumbbell# define RADEON_CP_NEXT_CHAR 0x00001900 1083254885Sdumbbell# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1084254885Sdumbbell# define RADEON_CP_SET_SCISSORS 0x00001E00 1085254885Sdumbbell /* GEN_INDX_PRIM is unsupported starting with R300 */ 1086254885Sdumbbell# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1087254885Sdumbbell# define RADEON_WAIT_FOR_IDLE 0x00002600 1088254885Sdumbbell# define RADEON_3D_DRAW_VBUF 0x00002800 1089254885Sdumbbell# define RADEON_3D_DRAW_IMMD 0x00002900 1090254885Sdumbbell# define RADEON_3D_DRAW_INDX 0x00002A00 1091254885Sdumbbell# define RADEON_CP_LOAD_PALETTE 0x00002C00 1092254885Sdumbbell# define RADEON_3D_LOAD_VBPNTR 0x00002F00 1093254885Sdumbbell# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1094254885Sdumbbell# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1095254885Sdumbbell# define RADEON_3D_CLEAR_ZMASK 0x00003200 1096254885Sdumbbell# define RADEON_CP_INDX_BUFFER 0x00003300 1097254885Sdumbbell# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1098254885Sdumbbell# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1099254885Sdumbbell# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1100254885Sdumbbell# define RADEON_3D_CLEAR_HIZ 0x00003700 1101254885Sdumbbell# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1102254885Sdumbbell# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1103254885Sdumbbell# define RADEON_CNTL_PAINT_MULTI 0x00009A00 1104254885Sdumbbell# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1105254885Sdumbbell# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1106254885Sdumbbell 1107254885Sdumbbell# define R600_IT_INDIRECT_BUFFER_END 0x00001700 1108254885Sdumbbell# define R600_IT_SET_PREDICATION 0x00002000 1109254885Sdumbbell# define R600_IT_REG_RMW 0x00002100 1110254885Sdumbbell# define R600_IT_COND_EXEC 0x00002200 1111254885Sdumbbell# define R600_IT_PRED_EXEC 0x00002300 1112254885Sdumbbell# define R600_IT_START_3D_CMDBUF 0x00002400 1113254885Sdumbbell# define R600_IT_DRAW_INDEX_2 0x00002700 1114254885Sdumbbell# define R600_IT_CONTEXT_CONTROL 0x00002800 1115254885Sdumbbell# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 1116254885Sdumbbell# define R600_IT_INDEX_TYPE 0x00002A00 1117254885Sdumbbell# define R600_IT_DRAW_INDEX 0x00002B00 1118254885Sdumbbell# define R600_IT_DRAW_INDEX_AUTO 0x00002D00 1119254885Sdumbbell# define R600_IT_DRAW_INDEX_IMMD 0x00002E00 1120254885Sdumbbell# define R600_IT_NUM_INSTANCES 0x00002F00 1121254885Sdumbbell# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 1122254885Sdumbbell# define R600_IT_INDIRECT_BUFFER_MP 0x00003800 1123254885Sdumbbell# define R600_IT_MEM_SEMAPHORE 0x00003900 1124254885Sdumbbell# define R600_IT_MPEG_INDEX 0x00003A00 1125254885Sdumbbell# define R600_IT_WAIT_REG_MEM 0x00003C00 1126254885Sdumbbell# define R600_IT_MEM_WRITE 0x00003D00 1127254885Sdumbbell# define R600_IT_INDIRECT_BUFFER 0x00003200 1128254885Sdumbbell# define R600_IT_SURFACE_SYNC 0x00004300 1129254885Sdumbbell# define R600_CB0_DEST_BASE_ENA (1 << 6) 1130254885Sdumbbell# define R600_TC_ACTION_ENA (1 << 23) 1131254885Sdumbbell# define R600_VC_ACTION_ENA (1 << 24) 1132254885Sdumbbell# define R600_CB_ACTION_ENA (1 << 25) 1133254885Sdumbbell# define R600_DB_ACTION_ENA (1 << 26) 1134254885Sdumbbell# define R600_SH_ACTION_ENA (1 << 27) 1135254885Sdumbbell# define R600_SMX_ACTION_ENA (1 << 28) 1136254885Sdumbbell# define R600_IT_ME_INITIALIZE 0x00004400 1137254885Sdumbbell# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1138254885Sdumbbell# define R600_IT_COND_WRITE 0x00004500 1139254885Sdumbbell# define R600_IT_EVENT_WRITE 0x00004600 1140254885Sdumbbell# define R600_IT_EVENT_WRITE_EOP 0x00004700 1141254885Sdumbbell# define R600_IT_ONE_REG_WRITE 0x00005700 1142254885Sdumbbell# define R600_IT_SET_CONFIG_REG 0x00006800 1143254885Sdumbbell# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1144254885Sdumbbell# define R600_SET_CONFIG_REG_END 0x0000ac00 1145254885Sdumbbell# define R600_IT_SET_CONTEXT_REG 0x00006900 1146254885Sdumbbell# define R600_SET_CONTEXT_REG_OFFSET 0x00028000 1147254885Sdumbbell# define R600_SET_CONTEXT_REG_END 0x00029000 1148254885Sdumbbell# define R600_IT_SET_ALU_CONST 0x00006A00 1149254885Sdumbbell# define R600_SET_ALU_CONST_OFFSET 0x00030000 1150254885Sdumbbell# define R600_SET_ALU_CONST_END 0x00032000 1151254885Sdumbbell# define R600_IT_SET_BOOL_CONST 0x00006B00 1152254885Sdumbbell# define R600_SET_BOOL_CONST_OFFSET 0x0003e380 1153254885Sdumbbell# define R600_SET_BOOL_CONST_END 0x00040000 1154254885Sdumbbell# define R600_IT_SET_LOOP_CONST 0x00006C00 1155254885Sdumbbell# define R600_SET_LOOP_CONST_OFFSET 0x0003e200 1156254885Sdumbbell# define R600_SET_LOOP_CONST_END 0x0003e380 1157254885Sdumbbell# define R600_IT_SET_RESOURCE 0x00006D00 1158254885Sdumbbell# define R600_SET_RESOURCE_OFFSET 0x00038000 1159254885Sdumbbell# define R600_SET_RESOURCE_END 0x0003c000 1160254885Sdumbbell# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 1161254885Sdumbbell# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 1162254885Sdumbbell# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 1163254885Sdumbbell# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 1164254885Sdumbbell# define R600_IT_SET_SAMPLER 0x00006E00 1165254885Sdumbbell# define R600_SET_SAMPLER_OFFSET 0x0003c000 1166254885Sdumbbell# define R600_SET_SAMPLER_END 0x0003cff0 1167254885Sdumbbell# define R600_IT_SET_CTL_CONST 0x00006F00 1168254885Sdumbbell# define R600_SET_CTL_CONST_OFFSET 0x0003cff0 1169254885Sdumbbell# define R600_SET_CTL_CONST_END 0x0003e200 1170254885Sdumbbell# define R600_IT_SURFACE_BASE_UPDATE 0x00007300 1171254885Sdumbbell 1172254885Sdumbbell#define RADEON_CP_PACKET_MASK 0xC0000000 1173254885Sdumbbell#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1174254885Sdumbbell#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1175254885Sdumbbell#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1176254885Sdumbbell#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1177254885Sdumbbell 1178261455Seadler#define RADEON_VTX_Z_PRESENT (1U << 31) 1179254885Sdumbbell#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1180254885Sdumbbell 1181254885Sdumbbell#define RADEON_PRIM_TYPE_NONE (0 << 0) 1182254885Sdumbbell#define RADEON_PRIM_TYPE_POINT (1 << 0) 1183254885Sdumbbell#define RADEON_PRIM_TYPE_LINE (2 << 0) 1184254885Sdumbbell#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1185254885Sdumbbell#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1186254885Sdumbbell#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1187254885Sdumbbell#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1188254885Sdumbbell#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1189254885Sdumbbell#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1190254885Sdumbbell#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1191254885Sdumbbell#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1192254885Sdumbbell#define RADEON_PRIM_TYPE_MASK 0xf 1193254885Sdumbbell#define RADEON_PRIM_WALK_IND (1 << 4) 1194254885Sdumbbell#define RADEON_PRIM_WALK_LIST (2 << 4) 1195254885Sdumbbell#define RADEON_PRIM_WALK_RING (3 << 4) 1196254885Sdumbbell#define RADEON_COLOR_ORDER_BGRA (0 << 6) 1197254885Sdumbbell#define RADEON_COLOR_ORDER_RGBA (1 << 6) 1198254885Sdumbbell#define RADEON_MAOS_ENABLE (1 << 7) 1199254885Sdumbbell#define RADEON_VTX_FMT_R128_MODE (0 << 8) 1200254885Sdumbbell#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1201254885Sdumbbell#define RADEON_NUM_VERTICES_SHIFT 16 1202254885Sdumbbell 1203254885Sdumbbell#define RADEON_COLOR_FORMAT_CI8 2 1204254885Sdumbbell#define RADEON_COLOR_FORMAT_ARGB1555 3 1205254885Sdumbbell#define RADEON_COLOR_FORMAT_RGB565 4 1206254885Sdumbbell#define RADEON_COLOR_FORMAT_ARGB8888 6 1207254885Sdumbbell#define RADEON_COLOR_FORMAT_RGB332 7 1208254885Sdumbbell#define RADEON_COLOR_FORMAT_RGB8 9 1209254885Sdumbbell#define RADEON_COLOR_FORMAT_ARGB4444 15 1210254885Sdumbbell 1211254885Sdumbbell#define RADEON_TXFORMAT_I8 0 1212254885Sdumbbell#define RADEON_TXFORMAT_AI88 1 1213254885Sdumbbell#define RADEON_TXFORMAT_RGB332 2 1214254885Sdumbbell#define RADEON_TXFORMAT_ARGB1555 3 1215254885Sdumbbell#define RADEON_TXFORMAT_RGB565 4 1216254885Sdumbbell#define RADEON_TXFORMAT_ARGB4444 5 1217254885Sdumbbell#define RADEON_TXFORMAT_ARGB8888 6 1218254885Sdumbbell#define RADEON_TXFORMAT_RGBA8888 7 1219254885Sdumbbell#define RADEON_TXFORMAT_Y8 8 1220254885Sdumbbell#define RADEON_TXFORMAT_VYUY422 10 1221254885Sdumbbell#define RADEON_TXFORMAT_YVYU422 11 1222254885Sdumbbell#define RADEON_TXFORMAT_DXT1 12 1223254885Sdumbbell#define RADEON_TXFORMAT_DXT23 14 1224254885Sdumbbell#define RADEON_TXFORMAT_DXT45 15 1225254885Sdumbbell 1226254885Sdumbbell#define R200_PP_TXCBLEND_0 0x2f00 1227254885Sdumbbell#define R200_PP_TXCBLEND_1 0x2f10 1228254885Sdumbbell#define R200_PP_TXCBLEND_2 0x2f20 1229254885Sdumbbell#define R200_PP_TXCBLEND_3 0x2f30 1230254885Sdumbbell#define R200_PP_TXCBLEND_4 0x2f40 1231254885Sdumbbell#define R200_PP_TXCBLEND_5 0x2f50 1232254885Sdumbbell#define R200_PP_TXCBLEND_6 0x2f60 1233254885Sdumbbell#define R200_PP_TXCBLEND_7 0x2f70 1234254885Sdumbbell#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1235254885Sdumbbell#define R200_PP_TFACTOR_0 0x2ee0 1236254885Sdumbbell#define R200_SE_VTX_FMT_0 0x2088 1237254885Sdumbbell#define R200_SE_VAP_CNTL 0x2080 1238254885Sdumbbell#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1239254885Sdumbbell#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1240254885Sdumbbell#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1241254885Sdumbbell#define R200_PP_TXFILTER_5 0x2ca0 1242254885Sdumbbell#define R200_PP_TXFILTER_4 0x2c80 1243254885Sdumbbell#define R200_PP_TXFILTER_3 0x2c60 1244254885Sdumbbell#define R200_PP_TXFILTER_2 0x2c40 1245254885Sdumbbell#define R200_PP_TXFILTER_1 0x2c20 1246254885Sdumbbell#define R200_PP_TXFILTER_0 0x2c00 1247254885Sdumbbell#define R200_PP_TXOFFSET_5 0x2d78 1248254885Sdumbbell#define R200_PP_TXOFFSET_4 0x2d60 1249254885Sdumbbell#define R200_PP_TXOFFSET_3 0x2d48 1250254885Sdumbbell#define R200_PP_TXOFFSET_2 0x2d30 1251254885Sdumbbell#define R200_PP_TXOFFSET_1 0x2d18 1252254885Sdumbbell#define R200_PP_TXOFFSET_0 0x2d00 1253254885Sdumbbell 1254254885Sdumbbell#define R200_PP_CUBIC_FACES_0 0x2c18 1255254885Sdumbbell#define R200_PP_CUBIC_FACES_1 0x2c38 1256254885Sdumbbell#define R200_PP_CUBIC_FACES_2 0x2c58 1257254885Sdumbbell#define R200_PP_CUBIC_FACES_3 0x2c78 1258254885Sdumbbell#define R200_PP_CUBIC_FACES_4 0x2c98 1259254885Sdumbbell#define R200_PP_CUBIC_FACES_5 0x2cb8 1260254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1261254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1262254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1263254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1264254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1265254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1266254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1267254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1268254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1269254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1270254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1271254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1272254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1273254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1274254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1275254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1276254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1277254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1278254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1279254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1280254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1281254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1282254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1283254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1284254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1285254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1286254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1287254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1288254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1289254885Sdumbbell#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1290254885Sdumbbell 1291254885Sdumbbell#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1292254885Sdumbbell#define R200_SE_VTE_CNTL 0x20b0 1293254885Sdumbbell#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1294254885Sdumbbell#define R200_PP_TAM_DEBUG3 0x2d9c 1295254885Sdumbbell#define R200_PP_CNTL_X 0x2cc4 1296254885Sdumbbell#define R200_SE_VAP_CNTL_STATUS 0x2140 1297254885Sdumbbell#define R200_RE_SCISSOR_TL_0 0x1cd8 1298254885Sdumbbell#define R200_RE_SCISSOR_TL_1 0x1ce0 1299254885Sdumbbell#define R200_RE_SCISSOR_TL_2 0x1ce8 1300254885Sdumbbell#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1301254885Sdumbbell#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1302254885Sdumbbell#define R200_SE_VTX_STATE_CNTL 0x2180 1303254885Sdumbbell#define R200_RE_POINTSIZE 0x2648 1304254885Sdumbbell#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1305254885Sdumbbell 1306254885Sdumbbell#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1307254885Sdumbbell#define RADEON_PP_TEX_SIZE_1 0x1d0c 1308254885Sdumbbell#define RADEON_PP_TEX_SIZE_2 0x1d14 1309254885Sdumbbell 1310254885Sdumbbell#define RADEON_PP_CUBIC_FACES_0 0x1d24 1311254885Sdumbbell#define RADEON_PP_CUBIC_FACES_1 0x1d28 1312254885Sdumbbell#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1313254885Sdumbbell#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1314254885Sdumbbell#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1315254885Sdumbbell#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1316254885Sdumbbell 1317254885Sdumbbell#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1318254885Sdumbbell 1319254885Sdumbbell#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1320254885Sdumbbell#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1321254885Sdumbbell#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1322254885Sdumbbell#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1323254885Sdumbbell#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1324254885Sdumbbell#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1325254885Sdumbbell#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1326254885Sdumbbell#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1327254885Sdumbbell#define R200_3D_DRAW_IMMD_2 0xC0003500 1328254885Sdumbbell#define R200_SE_VTX_FMT_1 0x208c 1329254885Sdumbbell#define R200_RE_CNTL 0x1c50 1330254885Sdumbbell 1331254885Sdumbbell#define R200_RB3D_BLENDCOLOR 0x3218 1332254885Sdumbbell 1333254885Sdumbbell#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1334254885Sdumbbell 1335254885Sdumbbell#define R200_PP_TRI_PERF 0x2cf8 1336254885Sdumbbell 1337254885Sdumbbell#define R200_PP_AFS_0 0x2f80 1338254885Sdumbbell#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1339254885Sdumbbell 1340254885Sdumbbell#define R200_VAP_PVS_CNTL_1 0x22D0 1341254885Sdumbbell 1342254885Sdumbbell#define RADEON_CRTC_CRNT_FRAME 0x0214 1343254885Sdumbbell#define RADEON_CRTC2_CRNT_FRAME 0x0314 1344254885Sdumbbell 1345254885Sdumbbell#define R500_D1CRTC_STATUS 0x609c 1346254885Sdumbbell#define R500_D2CRTC_STATUS 0x689c 1347254885Sdumbbell#define R500_CRTC_V_BLANK (1<<0) 1348254885Sdumbbell 1349254885Sdumbbell#define R500_D1CRTC_FRAME_COUNT 0x60a4 1350254885Sdumbbell#define R500_D2CRTC_FRAME_COUNT 0x68a4 1351254885Sdumbbell 1352254885Sdumbbell#define R500_D1MODE_V_COUNTER 0x6530 1353254885Sdumbbell#define R500_D2MODE_V_COUNTER 0x6d30 1354254885Sdumbbell 1355254885Sdumbbell#define R500_D1MODE_VBLANK_STATUS 0x6534 1356254885Sdumbbell#define R500_D2MODE_VBLANK_STATUS 0x6d34 1357254885Sdumbbell#define R500_VBLANK_OCCURED (1<<0) 1358254885Sdumbbell#define R500_VBLANK_ACK (1<<4) 1359254885Sdumbbell#define R500_VBLANK_STAT (1<<12) 1360254885Sdumbbell#define R500_VBLANK_INT (1<<16) 1361254885Sdumbbell 1362254885Sdumbbell#define R500_DxMODE_INT_MASK 0x6540 1363254885Sdumbbell#define R500_D1MODE_INT_MASK (1<<0) 1364254885Sdumbbell#define R500_D2MODE_INT_MASK (1<<8) 1365254885Sdumbbell 1366254885Sdumbbell#define R500_DISP_INTERRUPT_STATUS 0x7edc 1367254885Sdumbbell#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1368254885Sdumbbell#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1369254885Sdumbbell 1370254885Sdumbbell/* R6xx/R7xx registers */ 1371254885Sdumbbell#define R600_MC_VM_FB_LOCATION 0x2180 1372254885Sdumbbell#define R600_MC_VM_AGP_TOP 0x2184 1373254885Sdumbbell#define R600_MC_VM_AGP_BOT 0x2188 1374254885Sdumbbell#define R600_MC_VM_AGP_BASE 0x218c 1375254885Sdumbbell#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1376254885Sdumbbell#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1377254885Sdumbbell#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1378254885Sdumbbell 1379254885Sdumbbell#define R700_MC_VM_FB_LOCATION 0x2024 1380254885Sdumbbell#define R700_MC_VM_AGP_TOP 0x2028 1381254885Sdumbbell#define R700_MC_VM_AGP_BOT 0x202c 1382254885Sdumbbell#define R700_MC_VM_AGP_BASE 0x2030 1383254885Sdumbbell#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1384254885Sdumbbell#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1385254885Sdumbbell#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1386254885Sdumbbell 1387254885Sdumbbell#define R600_MCD_RD_A_CNTL 0x219c 1388254885Sdumbbell#define R600_MCD_RD_B_CNTL 0x21a0 1389254885Sdumbbell 1390254885Sdumbbell#define R600_MCD_WR_A_CNTL 0x21a4 1391254885Sdumbbell#define R600_MCD_WR_B_CNTL 0x21a8 1392254885Sdumbbell 1393254885Sdumbbell#define R600_MCD_RD_SYS_CNTL 0x2200 1394254885Sdumbbell#define R600_MCD_WR_SYS_CNTL 0x2214 1395254885Sdumbbell 1396254885Sdumbbell#define R600_MCD_RD_GFX_CNTL 0x21fc 1397254885Sdumbbell#define R600_MCD_RD_HDP_CNTL 0x2204 1398254885Sdumbbell#define R600_MCD_RD_PDMA_CNTL 0x2208 1399254885Sdumbbell#define R600_MCD_RD_SEM_CNTL 0x220c 1400254885Sdumbbell#define R600_MCD_WR_GFX_CNTL 0x2210 1401254885Sdumbbell#define R600_MCD_WR_HDP_CNTL 0x2218 1402254885Sdumbbell#define R600_MCD_WR_PDMA_CNTL 0x221c 1403254885Sdumbbell#define R600_MCD_WR_SEM_CNTL 0x2220 1404254885Sdumbbell 1405254885Sdumbbell# define R600_MCD_L1_TLB (1 << 0) 1406254885Sdumbbell# define R600_MCD_L1_FRAG_PROC (1 << 1) 1407254885Sdumbbell# define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1408254885Sdumbbell 1409254885Sdumbbell# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1410254885Sdumbbell# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1411254885Sdumbbell# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1412254885Sdumbbell# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1413254885Sdumbbell# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1414254885Sdumbbell 1415254885Sdumbbell# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1416254885Sdumbbell# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1417254885Sdumbbell 1418254885Sdumbbell# define R600_MCD_SEMAPHORE_MODE (1 << 10) 1419254885Sdumbbell# define R600_MCD_WAIT_L2_QUERY (1 << 11) 1420254885Sdumbbell# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1421254885Sdumbbell# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1422254885Sdumbbell 1423254885Sdumbbell#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1424254885Sdumbbell#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1425254885Sdumbbell#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1426254885Sdumbbell 1427254885Sdumbbell#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1428254885Sdumbbell#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1429254885Sdumbbell#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1430254885Sdumbbell#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1431254885Sdumbbell 1432254885Sdumbbell# define R700_ENABLE_L1_TLB (1 << 0) 1433254885Sdumbbell# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1434254885Sdumbbell# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1435254885Sdumbbell# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1436254885Sdumbbell# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1437254885Sdumbbell# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1438254885Sdumbbell 1439254885Sdumbbell#define R700_MC_ARB_RAMCFG 0x2760 1440254885Sdumbbell# define R700_NOOFBANK_SHIFT 0 1441254885Sdumbbell# define R700_NOOFBANK_MASK 0x3 1442254885Sdumbbell# define R700_NOOFRANK_SHIFT 2 1443254885Sdumbbell# define R700_NOOFRANK_MASK 0x1 1444254885Sdumbbell# define R700_NOOFROWS_SHIFT 3 1445254885Sdumbbell# define R700_NOOFROWS_MASK 0x7 1446254885Sdumbbell# define R700_NOOFCOLS_SHIFT 6 1447254885Sdumbbell# define R700_NOOFCOLS_MASK 0x3 1448254885Sdumbbell# define R700_CHANSIZE_SHIFT 8 1449254885Sdumbbell# define R700_CHANSIZE_MASK 0x1 1450254885Sdumbbell# define R700_BURSTLENGTH_SHIFT 9 1451254885Sdumbbell# define R700_BURSTLENGTH_MASK 0x1 1452254885Sdumbbell#define R600_RAMCFG 0x2408 1453254885Sdumbbell# define R600_NOOFBANK_SHIFT 0 1454254885Sdumbbell# define R600_NOOFBANK_MASK 0x1 1455254885Sdumbbell# define R600_NOOFRANK_SHIFT 1 1456254885Sdumbbell# define R600_NOOFRANK_MASK 0x1 1457254885Sdumbbell# define R600_NOOFROWS_SHIFT 2 1458254885Sdumbbell# define R600_NOOFROWS_MASK 0x7 1459254885Sdumbbell# define R600_NOOFCOLS_SHIFT 5 1460254885Sdumbbell# define R600_NOOFCOLS_MASK 0x3 1461254885Sdumbbell# define R600_CHANSIZE_SHIFT 7 1462254885Sdumbbell# define R600_CHANSIZE_MASK 0x1 1463254885Sdumbbell# define R600_BURSTLENGTH_SHIFT 8 1464254885Sdumbbell# define R600_BURSTLENGTH_MASK 0x1 1465254885Sdumbbell 1466254885Sdumbbell#define R600_VM_L2_CNTL 0x1400 1467254885Sdumbbell# define R600_VM_L2_CACHE_EN (1 << 0) 1468254885Sdumbbell# define R600_VM_L2_FRAG_PROC (1 << 1) 1469254885Sdumbbell# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1470254885Sdumbbell# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1471254885Sdumbbell# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1472254885Sdumbbell 1473254885Sdumbbell#define R600_VM_L2_CNTL2 0x1404 1474254885Sdumbbell# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1475254885Sdumbbell# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1476254885Sdumbbell#define R600_VM_L2_CNTL3 0x1408 1477254885Sdumbbell# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1478254885Sdumbbell# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1479254885Sdumbbell# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1480254885Sdumbbell# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1481254885Sdumbbell# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1482254885Sdumbbell 1483254885Sdumbbell#define R600_VM_L2_STATUS 0x140c 1484254885Sdumbbell 1485254885Sdumbbell#define R600_VM_CONTEXT0_CNTL 0x1410 1486254885Sdumbbell# define R600_VM_ENABLE_CONTEXT (1 << 0) 1487254885Sdumbbell# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1488254885Sdumbbell 1489254885Sdumbbell#define R600_VM_CONTEXT0_CNTL2 0x1430 1490254885Sdumbbell#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1491254885Sdumbbell#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1492254885Sdumbbell#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1493254885Sdumbbell#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1494254885Sdumbbell#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1495254885Sdumbbell#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1496254885Sdumbbell 1497254885Sdumbbell#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1498254885Sdumbbell#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1499254885Sdumbbell#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1500254885Sdumbbell 1501254885Sdumbbell#define R600_HDP_HOST_PATH_CNTL 0x2c00 1502254885Sdumbbell 1503254885Sdumbbell#define R600_GRBM_CNTL 0x8000 1504254885Sdumbbell# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1505254885Sdumbbell 1506254885Sdumbbell#define R600_GRBM_STATUS 0x8010 1507254885Sdumbbell# define R600_CMDFIFO_AVAIL_MASK 0x1f 1508254885Sdumbbell# define R700_CMDFIFO_AVAIL_MASK 0xf 1509261455Seadler# define R600_GUI_ACTIVE (1U << 31) 1510254885Sdumbbell#define R600_GRBM_STATUS2 0x8014 1511254885Sdumbbell#define R600_GRBM_SOFT_RESET 0x8020 1512254885Sdumbbell# define R600_SOFT_RESET_CP (1 << 0) 1513254885Sdumbbell#define R600_WAIT_UNTIL 0x8040 1514254885Sdumbbell 1515254885Sdumbbell#define R600_CP_SEM_WAIT_TIMER 0x85bc 1516254885Sdumbbell#define R600_CP_ME_CNTL 0x86d8 1517254885Sdumbbell# define R600_CP_ME_HALT (1 << 28) 1518254885Sdumbbell#define R600_CP_QUEUE_THRESHOLDS 0x8760 1519254885Sdumbbell# define R600_ROQ_IB1_START(x) ((x) << 0) 1520254885Sdumbbell# define R600_ROQ_IB2_START(x) ((x) << 8) 1521254885Sdumbbell#define R600_CP_MEQ_THRESHOLDS 0x8764 1522254885Sdumbbell# define R700_STQ_SPLIT(x) ((x) << 0) 1523254885Sdumbbell# define R600_MEQ_END(x) ((x) << 16) 1524254885Sdumbbell# define R600_ROQ_END(x) ((x) << 24) 1525254885Sdumbbell#define R600_CP_PERFMON_CNTL 0x87fc 1526254885Sdumbbell#define R600_CP_RB_BASE 0xc100 1527254885Sdumbbell#define R600_CP_RB_CNTL 0xc104 1528254885Sdumbbell# define R600_RB_BUFSZ(x) ((x) << 0) 1529254885Sdumbbell# define R600_RB_BLKSZ(x) ((x) << 8) 1530254885Sdumbbell# define R600_BUF_SWAP_32BIT (2 << 16) 1531254885Sdumbbell# define R600_RB_NO_UPDATE (1 << 27) 1532261455Seadler# define R600_RB_RPTR_WR_ENA (1U << 31) 1533254885Sdumbbell#define R600_CP_RB_RPTR_WR 0xc108 1534254885Sdumbbell#define R600_CP_RB_RPTR_ADDR 0xc10c 1535254885Sdumbbell#define R600_CP_RB_RPTR_ADDR_HI 0xc110 1536254885Sdumbbell#define R600_CP_RB_WPTR 0xc114 1537254885Sdumbbell#define R600_CP_RB_WPTR_ADDR 0xc118 1538254885Sdumbbell#define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1539254885Sdumbbell#define R600_CP_RB_RPTR 0x8700 1540254885Sdumbbell#define R600_CP_RB_WPTR_DELAY 0x8704 1541254885Sdumbbell#define R600_CP_PFP_UCODE_ADDR 0xc150 1542254885Sdumbbell#define R600_CP_PFP_UCODE_DATA 0xc154 1543254885Sdumbbell#define R600_CP_ME_RAM_RADDR 0xc158 1544254885Sdumbbell#define R600_CP_ME_RAM_WADDR 0xc15c 1545254885Sdumbbell#define R600_CP_ME_RAM_DATA 0xc160 1546254885Sdumbbell#define R600_CP_DEBUG 0xc1fc 1547254885Sdumbbell 1548254885Sdumbbell#define R600_PA_CL_ENHANCE 0x8a14 1549254885Sdumbbell# define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1550254885Sdumbbell# define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1551254885Sdumbbell#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1552254885Sdumbbell#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1553254885Sdumbbell#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1554254885Sdumbbell# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1555254885Sdumbbell# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1556254885Sdumbbell#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1557254885Sdumbbell#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1558254885Sdumbbell#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1559254885Sdumbbell#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1560254885Sdumbbell# define R600_S0_X(x) ((x) << 0) 1561254885Sdumbbell# define R600_S0_Y(x) ((x) << 4) 1562254885Sdumbbell# define R600_S1_X(x) ((x) << 8) 1563254885Sdumbbell# define R600_S1_Y(x) ((x) << 12) 1564254885Sdumbbell# define R600_S2_X(x) ((x) << 16) 1565254885Sdumbbell# define R600_S2_Y(x) ((x) << 20) 1566254885Sdumbbell# define R600_S3_X(x) ((x) << 24) 1567254885Sdumbbell# define R600_S3_Y(x) ((x) << 28) 1568254885Sdumbbell# define R600_S4_X(x) ((x) << 0) 1569254885Sdumbbell# define R600_S4_Y(x) ((x) << 4) 1570254885Sdumbbell# define R600_S5_X(x) ((x) << 8) 1571254885Sdumbbell# define R600_S5_Y(x) ((x) << 12) 1572254885Sdumbbell# define R600_S6_X(x) ((x) << 16) 1573254885Sdumbbell# define R600_S6_Y(x) ((x) << 20) 1574254885Sdumbbell# define R600_S7_X(x) ((x) << 24) 1575254885Sdumbbell# define R600_S7_Y(x) ((x) << 28) 1576254885Sdumbbell#define R600_PA_SC_FIFO_SIZE 0x8bd0 1577254885Sdumbbell# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1578254885Sdumbbell# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1579254885Sdumbbell# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1580254885Sdumbbell#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1581254885Sdumbbell# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1582254885Sdumbbell# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1583254885Sdumbbell# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1584254885Sdumbbell#define R600_PA_SC_ENHANCE 0x8bf0 1585254885Sdumbbell# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1586254885Sdumbbell# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1587254885Sdumbbell#define R600_PA_SC_CLIPRECT_RULE 0x2820c 1588254885Sdumbbell#define R700_PA_SC_EDGERULE 0x28230 1589254885Sdumbbell#define R600_PA_SC_LINE_STIPPLE 0x28a0c 1590254885Sdumbbell#define R600_PA_SC_MODE_CNTL 0x28a4c 1591254885Sdumbbell#define R600_PA_SC_AA_CONFIG 0x28c04 1592254885Sdumbbell 1593254885Sdumbbell#define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1594254885Sdumbbell# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1595254885Sdumbbell# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1596254885Sdumbbell# define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1597254885Sdumbbell#define R600_SX_DEBUG_1 0x9054 1598254885Sdumbbell# define R600_SMX_EVENT_RELEASE (1 << 0) 1599254885Sdumbbell# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1600254885Sdumbbell#define R700_SX_DEBUG_1 0x9058 1601254885Sdumbbell# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1602254885Sdumbbell#define R600_SX_MISC 0x28350 1603254885Sdumbbell 1604254885Sdumbbell#define R600_DB_DEBUG 0x9830 1605261455Seadler# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) 1606254885Sdumbbell#define R600_DB_WATERMARKS 0x9838 1607254885Sdumbbell# define R600_DEPTH_FREE(x) ((x) << 0) 1608254885Sdumbbell# define R600_DEPTH_FLUSH(x) ((x) << 5) 1609254885Sdumbbell# define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1610254885Sdumbbell# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1611254885Sdumbbell#define R700_DB_DEBUG3 0x98b0 1612254885Sdumbbell# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1613254885Sdumbbell#define RV700_DB_DEBUG4 0x9b8c 1614254885Sdumbbell# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1615254885Sdumbbell 1616254885Sdumbbell#define R600_VGT_CACHE_INVALIDATION 0x88c4 1617254885Sdumbbell# define R600_CACHE_INVALIDATION(x) ((x) << 0) 1618254885Sdumbbell# define R600_VC_ONLY 0 1619254885Sdumbbell# define R600_TC_ONLY 1 1620254885Sdumbbell# define R600_VC_AND_TC 2 1621254885Sdumbbell# define R700_AUTO_INVLD_EN(x) ((x) << 6) 1622254885Sdumbbell# define R700_NO_AUTO 0 1623254885Sdumbbell# define R700_ES_AUTO 1 1624254885Sdumbbell# define R700_GS_AUTO 2 1625254885Sdumbbell# define R700_ES_AND_GS_AUTO 3 1626254885Sdumbbell#define R600_VGT_GS_PER_ES 0x88c8 1627254885Sdumbbell#define R600_VGT_ES_PER_GS 0x88cc 1628254885Sdumbbell#define R600_VGT_GS_PER_VS 0x88e8 1629254885Sdumbbell#define R600_VGT_GS_VERTEX_REUSE 0x88d4 1630254885Sdumbbell#define R600_VGT_NUM_INSTANCES 0x8974 1631254885Sdumbbell#define R600_VGT_STRMOUT_EN 0x28ab0 1632254885Sdumbbell#define R600_VGT_EVENT_INITIATOR 0x28a90 1633254885Sdumbbell# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1634254885Sdumbbell#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1635254885Sdumbbell# define R600_VTX_REUSE_DEPTH_MASK 0xff 1636254885Sdumbbell#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1637254885Sdumbbell# define R600_DEALLOC_DIST_MASK 0x7f 1638254885Sdumbbell 1639254885Sdumbbell#define R600_CB_COLOR0_BASE 0x28040 1640254885Sdumbbell#define R600_CB_COLOR1_BASE 0x28044 1641254885Sdumbbell#define R600_CB_COLOR2_BASE 0x28048 1642254885Sdumbbell#define R600_CB_COLOR3_BASE 0x2804c 1643254885Sdumbbell#define R600_CB_COLOR4_BASE 0x28050 1644254885Sdumbbell#define R600_CB_COLOR5_BASE 0x28054 1645254885Sdumbbell#define R600_CB_COLOR6_BASE 0x28058 1646254885Sdumbbell#define R600_CB_COLOR7_BASE 0x2805c 1647254885Sdumbbell#define R600_CB_COLOR7_FRAG 0x280fc 1648254885Sdumbbell 1649254885Sdumbbell#define R600_CB_COLOR0_SIZE 0x28060 1650254885Sdumbbell#define R600_CB_COLOR0_VIEW 0x28080 1651254885Sdumbbell#define R600_CB_COLOR0_INFO 0x280a0 1652254885Sdumbbell#define R600_CB_COLOR0_TILE 0x280c0 1653254885Sdumbbell#define R600_CB_COLOR0_FRAG 0x280e0 1654254885Sdumbbell#define R600_CB_COLOR0_MASK 0x28100 1655254885Sdumbbell 1656254885Sdumbbell#define AVIVO_D1MODE_VLINE_START_END 0x6538 1657254885Sdumbbell#define AVIVO_D2MODE_VLINE_START_END 0x6d38 1658254885Sdumbbell#define R600_CP_COHER_BASE 0x85f8 1659254885Sdumbbell#define R600_DB_DEPTH_BASE 0x2800c 1660254885Sdumbbell#define R600_SQ_PGM_START_FS 0x28894 1661254885Sdumbbell#define R600_SQ_PGM_START_ES 0x28880 1662254885Sdumbbell#define R600_SQ_PGM_START_VS 0x28858 1663254885Sdumbbell#define R600_SQ_PGM_RESOURCES_VS 0x28868 1664254885Sdumbbell#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 1665254885Sdumbbell#define R600_SQ_PGM_START_GS 0x2886c 1666254885Sdumbbell#define R600_SQ_PGM_START_PS 0x28840 1667254885Sdumbbell#define R600_SQ_PGM_RESOURCES_PS 0x28850 1668254885Sdumbbell#define R600_SQ_PGM_EXPORTS_PS 0x28854 1669254885Sdumbbell#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc 1670254885Sdumbbell#define R600_VGT_DMA_BASE 0x287e8 1671254885Sdumbbell#define R600_VGT_DMA_BASE_HI 0x287e4 1672254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 1673254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 1674254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 1675254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c 1676254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 1677254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 1678254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c 1679254885Sdumbbell#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 1680254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 1681254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 1682254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 1683254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 1684254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc 1685254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec 1686254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc 1687254885Sdumbbell#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c 1688254885Sdumbbell 1689254885Sdumbbell#define R600_VGT_PRIMITIVE_TYPE 0x8958 1690254885Sdumbbell 1691254885Sdumbbell#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 1692254885Sdumbbell#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 1693254885Sdumbbell#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 1694254885Sdumbbell 1695254885Sdumbbell#define R600_TC_CNTL 0x9608 1696254885Sdumbbell# define R600_TC_L2_SIZE(x) ((x) << 5) 1697254885Sdumbbell# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1698254885Sdumbbell 1699254885Sdumbbell#define R600_ARB_POP 0x2418 1700254885Sdumbbell# define R600_ENABLE_TC128 (1 << 30) 1701254885Sdumbbell#define R600_ARB_GDEC_RD_CNTL 0x246c 1702254885Sdumbbell 1703254885Sdumbbell#define R600_TA_CNTL_AUX 0x9508 1704254885Sdumbbell# define R600_DISABLE_CUBE_WRAP (1 << 0) 1705254885Sdumbbell# define R600_DISABLE_CUBE_ANISO (1 << 1) 1706254885Sdumbbell# define R700_GETLOD_SELECT(x) ((x) << 2) 1707254885Sdumbbell# define R600_SYNC_GRADIENT (1 << 24) 1708254885Sdumbbell# define R600_SYNC_WALKER (1 << 25) 1709254885Sdumbbell# define R600_SYNC_ALIGNER (1 << 26) 1710254885Sdumbbell# define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1711261455Seadler# define R600_BILINEAR_PRECISION_8_BIT (1U << 31) 1712254885Sdumbbell 1713254885Sdumbbell#define R700_TCP_CNTL 0x9610 1714254885Sdumbbell 1715254885Sdumbbell#define R600_SMX_DC_CTL0 0xa020 1716254885Sdumbbell# define R700_USE_HASH_FUNCTION (1 << 0) 1717254885Sdumbbell# define R700_CACHE_DEPTH(x) ((x) << 1) 1718254885Sdumbbell# define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1719254885Sdumbbell# define R700_STALL_ON_EVENT (1 << 11) 1720254885Sdumbbell#define R700_SMX_EVENT_CTL 0xa02c 1721254885Sdumbbell# define R700_ES_FLUSH_CTL(x) ((x) << 0) 1722254885Sdumbbell# define R700_GS_FLUSH_CTL(x) ((x) << 3) 1723254885Sdumbbell# define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1724254885Sdumbbell# define R700_SYNC_FLUSH_CTL (1 << 8) 1725254885Sdumbbell 1726254885Sdumbbell#define R600_SQ_CONFIG 0x8c00 1727254885Sdumbbell# define R600_VC_ENABLE (1 << 0) 1728254885Sdumbbell# define R600_EXPORT_SRC_C (1 << 1) 1729254885Sdumbbell# define R600_DX9_CONSTS (1 << 2) 1730254885Sdumbbell# define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1731254885Sdumbbell# define R600_DX10_CLAMP (1 << 4) 1732254885Sdumbbell# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1733254885Sdumbbell# define R600_PS_PRIO(x) ((x) << 24) 1734254885Sdumbbell# define R600_VS_PRIO(x) ((x) << 26) 1735254885Sdumbbell# define R600_GS_PRIO(x) ((x) << 28) 1736254885Sdumbbell# define R600_ES_PRIO(x) ((x) << 30) 1737254885Sdumbbell#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1738254885Sdumbbell# define R600_NUM_PS_GPRS(x) ((x) << 0) 1739254885Sdumbbell# define R600_NUM_VS_GPRS(x) ((x) << 16) 1740254885Sdumbbell# define R700_DYN_GPR_ENABLE (1 << 27) 1741254885Sdumbbell# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1742254885Sdumbbell#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1743254885Sdumbbell# define R600_NUM_GS_GPRS(x) ((x) << 0) 1744254885Sdumbbell# define R600_NUM_ES_GPRS(x) ((x) << 16) 1745254885Sdumbbell#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1746254885Sdumbbell# define R600_NUM_PS_THREADS(x) ((x) << 0) 1747254885Sdumbbell# define R600_NUM_VS_THREADS(x) ((x) << 8) 1748254885Sdumbbell# define R600_NUM_GS_THREADS(x) ((x) << 16) 1749254885Sdumbbell# define R600_NUM_ES_THREADS(x) ((x) << 24) 1750254885Sdumbbell#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1751254885Sdumbbell# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1752254885Sdumbbell# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1753254885Sdumbbell#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1754254885Sdumbbell# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1755254885Sdumbbell# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1756254885Sdumbbell#define R600_SQ_MS_FIFO_SIZES 0x8cf0 1757254885Sdumbbell# define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1758254885Sdumbbell# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1759254885Sdumbbell# define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1760254885Sdumbbell# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1761254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1762254885Sdumbbell# define R700_SIMDA_RING0(x) ((x) << 0) 1763254885Sdumbbell# define R700_SIMDA_RING1(x) ((x) << 8) 1764254885Sdumbbell# define R700_SIMDB_RING0(x) ((x) << 16) 1765254885Sdumbbell# define R700_SIMDB_RING1(x) ((x) << 24) 1766254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1767254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1768254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1769254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1770254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1771254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1772254885Sdumbbell#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1773254885Sdumbbell 1774254885Sdumbbell#define R600_SPI_PS_IN_CONTROL_0 0x286cc 1775254885Sdumbbell# define R600_NUM_INTERP(x) ((x) << 0) 1776254885Sdumbbell# define R600_POSITION_ENA (1 << 8) 1777254885Sdumbbell# define R600_POSITION_CENTROID (1 << 9) 1778254885Sdumbbell# define R600_POSITION_ADDR(x) ((x) << 10) 1779254885Sdumbbell# define R600_PARAM_GEN(x) ((x) << 15) 1780254885Sdumbbell# define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1781254885Sdumbbell# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1782254885Sdumbbell# define R600_PERSP_GRADIENT_ENA (1 << 28) 1783254885Sdumbbell# define R600_LINEAR_GRADIENT_ENA (1 << 29) 1784254885Sdumbbell# define R600_POSITION_SAMPLE (1 << 30) 1785261455Seadler# define R600_BARYC_AT_SAMPLE_ENA (1U << 31) 1786254885Sdumbbell#define R600_SPI_PS_IN_CONTROL_1 0x286d0 1787254885Sdumbbell# define R600_GEN_INDEX_PIX (1 << 0) 1788254885Sdumbbell# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1789254885Sdumbbell# define R600_FRONT_FACE_ENA (1 << 8) 1790254885Sdumbbell# define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1791254885Sdumbbell# define R600_FRONT_FACE_ALL_BITS (1 << 11) 1792254885Sdumbbell# define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1793254885Sdumbbell# define R600_FOG_ADDR(x) ((x) << 17) 1794254885Sdumbbell# define R600_FIXED_PT_POSITION_ENA (1 << 24) 1795254885Sdumbbell# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1796254885Sdumbbell# define R700_POSITION_ULC (1 << 30) 1797254885Sdumbbell#define R600_SPI_INPUT_Z 0x286d8 1798254885Sdumbbell 1799254885Sdumbbell#define R600_SPI_CONFIG_CNTL 0x9100 1800254885Sdumbbell# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1801254885Sdumbbell# define R600_DISABLE_INTERP_1 (1 << 5) 1802254885Sdumbbell#define R600_SPI_CONFIG_CNTL_1 0x913c 1803254885Sdumbbell# define R600_VTX_DONE_DELAY(x) ((x) << 0) 1804254885Sdumbbell# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1805254885Sdumbbell 1806254885Sdumbbell#define R600_GB_TILING_CONFIG 0x98f0 1807254885Sdumbbell# define R600_PIPE_TILING(x) ((x) << 1) 1808254885Sdumbbell# define R600_BANK_TILING(x) ((x) << 4) 1809254885Sdumbbell# define R600_GROUP_SIZE(x) ((x) << 6) 1810254885Sdumbbell# define R600_ROW_TILING(x) ((x) << 8) 1811254885Sdumbbell# define R600_BANK_SWAPS(x) ((x) << 11) 1812254885Sdumbbell# define R600_SAMPLE_SPLIT(x) ((x) << 14) 1813254885Sdumbbell# define R600_BACKEND_MAP(x) ((x) << 16) 1814254885Sdumbbell#define R600_DCP_TILING_CONFIG 0x6ca0 1815254885Sdumbbell#define R600_HDP_TILING_CONFIG 0x2f3c 1816254885Sdumbbell 1817254885Sdumbbell#define R600_CC_RB_BACKEND_DISABLE 0x98f4 1818254885Sdumbbell#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1819254885Sdumbbell# define R600_BACKEND_DISABLE(x) ((x) << 16) 1820254885Sdumbbell 1821254885Sdumbbell#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1822254885Sdumbbell#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1823254885Sdumbbell# define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1824254885Sdumbbell# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1825254885Sdumbbell# define R600_INACTIVE_SIMDS(x) ((x) << 16) 1826254885Sdumbbell# define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1827254885Sdumbbell 1828254885Sdumbbell#define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1829254885Sdumbbell#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1830254885Sdumbbell#define R700_CGTS_TCC_DISABLE 0x9148 1831254885Sdumbbell#define R700_CGTS_USER_TCC_DISABLE 0x914c 1832254885Sdumbbell 1833254885Sdumbbell/* Constants */ 1834254885Sdumbbell#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1835254885Sdumbbell 1836254885Sdumbbell#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1837254885Sdumbbell#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1838254885Sdumbbell#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1839254885Sdumbbell#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1840254885Sdumbbell#define RADEON_LAST_DISPATCH 1 1841254885Sdumbbell 1842254885Sdumbbell#define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1843254885Sdumbbell#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1844254885Sdumbbell#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1845254885Sdumbbell#define R600_LAST_SWI_REG R600_SCRATCH_REG3 1846254885Sdumbbell 1847254885Sdumbbell#define RADEON_MAX_VB_AGE 0x7fffffff 1848254885Sdumbbell#define RADEON_MAX_VB_VERTS (0xffff) 1849254885Sdumbbell 1850254885Sdumbbell#define RADEON_RING_HIGH_MARK 128 1851254885Sdumbbell 1852254885Sdumbbell#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1853254885Sdumbbell 1854254885Sdumbbell#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1855254885Sdumbbell#define RADEON_WRITE(reg, val) \ 1856254885Sdumbbelldo { \ 1857254885Sdumbbell if (reg < 0x10000) { \ 1858254885Sdumbbell DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1859254885Sdumbbell } else { \ 1860254885Sdumbbell DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1861254885Sdumbbell DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1862254885Sdumbbell } \ 1863254885Sdumbbell} while (0) 1864254885Sdumbbell#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1865254885Sdumbbell#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1866254885Sdumbbell 1867254885Sdumbbell#define RADEON_WRITE_PLL(addr, val) \ 1868254885Sdumbbelldo { \ 1869254885Sdumbbell RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1870254885Sdumbbell ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1871254885Sdumbbell RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1872254885Sdumbbell} while (0) 1873254885Sdumbbell 1874254885Sdumbbell#define RADEON_WRITE_PCIE(addr, val) \ 1875254885Sdumbbelldo { \ 1876254885Sdumbbell RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1877254885Sdumbbell ((addr) & 0xff)); \ 1878254885Sdumbbell RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1879254885Sdumbbell} while (0) 1880254885Sdumbbell 1881254885Sdumbbell#define R500_WRITE_MCIND(addr, val) \ 1882254885Sdumbbelldo { \ 1883254885Sdumbbell RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1884254885Sdumbbell RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1885254885Sdumbbell RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1886254885Sdumbbell} while (0) 1887254885Sdumbbell 1888254885Sdumbbell#define RS480_WRITE_MCIND(addr, val) \ 1889254885Sdumbbelldo { \ 1890254885Sdumbbell RADEON_WRITE(RS480_NB_MC_INDEX, \ 1891254885Sdumbbell ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1892254885Sdumbbell RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1893254885Sdumbbell RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1894254885Sdumbbell} while (0) 1895254885Sdumbbell 1896254885Sdumbbell#define RS690_WRITE_MCIND(addr, val) \ 1897254885Sdumbbelldo { \ 1898254885Sdumbbell RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1899254885Sdumbbell RADEON_WRITE(RS690_MC_DATA, val); \ 1900254885Sdumbbell RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1901254885Sdumbbell} while (0) 1902254885Sdumbbell 1903254885Sdumbbell#define RS600_WRITE_MCIND(addr, val) \ 1904254885Sdumbbelldo { \ 1905254885Sdumbbell RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1906254885Sdumbbell RADEON_WRITE(RS600_MC_DATA, val); \ 1907254885Sdumbbell} while (0) 1908254885Sdumbbell 1909254885Sdumbbell#define IGP_WRITE_MCIND(addr, val) \ 1910254885Sdumbbelldo { \ 1911254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1912254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1913254885Sdumbbell RS690_WRITE_MCIND(addr, val); \ 1914254885Sdumbbell else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1915254885Sdumbbell RS600_WRITE_MCIND(addr, val); \ 1916254885Sdumbbell else \ 1917254885Sdumbbell RS480_WRITE_MCIND(addr, val); \ 1918254885Sdumbbell} while (0) 1919254885Sdumbbell 1920254885Sdumbbell#define CP_PACKET0( reg, n ) \ 1921254885Sdumbbell (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1922254885Sdumbbell#define CP_PACKET0_TABLE( reg, n ) \ 1923254885Sdumbbell (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1924254885Sdumbbell#define CP_PACKET1( reg0, reg1 ) \ 1925254885Sdumbbell (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1926254885Sdumbbell#define CP_PACKET2() \ 1927254885Sdumbbell (RADEON_CP_PACKET2) 1928254885Sdumbbell#define CP_PACKET3( pkt, n ) \ 1929254885Sdumbbell (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1930254885Sdumbbell 1931254885Sdumbbell/* ================================================================ 1932254885Sdumbbell * Engine control helper macros 1933254885Sdumbbell */ 1934254885Sdumbbell 1935254885Sdumbbell#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1936254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1937254885Sdumbbell OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1938254885Sdumbbell RADEON_WAIT_HOST_IDLECLEAN) ); \ 1939254885Sdumbbell} while (0) 1940254885Sdumbbell 1941254885Sdumbbell#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1942254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1943254885Sdumbbell OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1944254885Sdumbbell RADEON_WAIT_HOST_IDLECLEAN) ); \ 1945254885Sdumbbell} while (0) 1946254885Sdumbbell 1947254885Sdumbbell#define RADEON_WAIT_UNTIL_IDLE() do { \ 1948254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1949254885Sdumbbell OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1950254885Sdumbbell RADEON_WAIT_3D_IDLECLEAN | \ 1951254885Sdumbbell RADEON_WAIT_HOST_IDLECLEAN) ); \ 1952254885Sdumbbell} while (0) 1953254885Sdumbbell 1954254885Sdumbbell#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1955254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1956254885Sdumbbell OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1957254885Sdumbbell} while (0) 1958254885Sdumbbell 1959254885Sdumbbell#define RADEON_FLUSH_CACHE() do { \ 1960254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1961254885Sdumbbell OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1962254885Sdumbbell OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1963254885Sdumbbell } else { \ 1964254885Sdumbbell OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1965254885Sdumbbell OUT_RING(R300_RB3D_DC_FLUSH); \ 1966254885Sdumbbell } \ 1967254885Sdumbbell} while (0) 1968254885Sdumbbell 1969254885Sdumbbell#define RADEON_PURGE_CACHE() do { \ 1970254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1971254885Sdumbbell OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1972254885Sdumbbell OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1973254885Sdumbbell } else { \ 1974254885Sdumbbell OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1975254885Sdumbbell OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1976254885Sdumbbell } \ 1977254885Sdumbbell} while (0) 1978254885Sdumbbell 1979254885Sdumbbell#define RADEON_FLUSH_ZCACHE() do { \ 1980254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1981254885Sdumbbell OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1982254885Sdumbbell OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1983254885Sdumbbell } else { \ 1984254885Sdumbbell OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1985254885Sdumbbell OUT_RING(R300_ZC_FLUSH); \ 1986254885Sdumbbell } \ 1987254885Sdumbbell} while (0) 1988254885Sdumbbell 1989254885Sdumbbell#define RADEON_PURGE_ZCACHE() do { \ 1990254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1991254885Sdumbbell OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1992254885Sdumbbell OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1993254885Sdumbbell } else { \ 1994254885Sdumbbell OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1995254885Sdumbbell OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1996254885Sdumbbell } \ 1997254885Sdumbbell} while (0) 1998254885Sdumbbell 1999254885Sdumbbell/* ================================================================ 2000254885Sdumbbell * Misc helper macros 2001254885Sdumbbell */ 2002254885Sdumbbell 2003254885Sdumbbell/* Perfbox functionality only. 2004254885Sdumbbell */ 2005254885Sdumbbell#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 2006254885Sdumbbelldo { \ 2007254885Sdumbbell if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 2008254885Sdumbbell u32 head = GET_RING_HEAD( dev_priv ); \ 2009254885Sdumbbell if (head == dev_priv->ring.tail) \ 2010254885Sdumbbell dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 2011254885Sdumbbell } \ 2012254885Sdumbbell} while (0) 2013254885Sdumbbell 2014254885Sdumbbell#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 2015254885Sdumbbelldo { \ 2016282199Sdumbbell struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \ 2017254885Sdumbbell drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \ 2018254885Sdumbbell if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2019254885Sdumbbell int __ret; \ 2020254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 2021254885Sdumbbell __ret = r600_do_cp_idle(dev_priv); \ 2022254885Sdumbbell else \ 2023254885Sdumbbell __ret = radeon_do_cp_idle(dev_priv); \ 2024254885Sdumbbell if ( __ret ) return __ret; \ 2025254885Sdumbbell sarea_priv->last_dispatch = 0; \ 2026254885Sdumbbell radeon_freelist_reset( dev ); \ 2027254885Sdumbbell } \ 2028254885Sdumbbell} while (0) 2029254885Sdumbbell 2030254885Sdumbbell#define RADEON_DISPATCH_AGE( age ) do { \ 2031254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2032254885Sdumbbell OUT_RING( age ); \ 2033254885Sdumbbell} while (0) 2034254885Sdumbbell 2035254885Sdumbbell#define RADEON_FRAME_AGE( age ) do { \ 2036254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2037254885Sdumbbell OUT_RING( age ); \ 2038254885Sdumbbell} while (0) 2039254885Sdumbbell 2040254885Sdumbbell#define RADEON_CLEAR_AGE( age ) do { \ 2041254885Sdumbbell OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2042254885Sdumbbell OUT_RING( age ); \ 2043254885Sdumbbell} while (0) 2044254885Sdumbbell 2045254885Sdumbbell#define R600_DISPATCH_AGE(age) do { \ 2046254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2047254885Sdumbbell OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2048254885Sdumbbell OUT_RING(age); \ 2049254885Sdumbbell} while (0) 2050254885Sdumbbell 2051254885Sdumbbell#define R600_FRAME_AGE(age) do { \ 2052254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2053254885Sdumbbell OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2054254885Sdumbbell OUT_RING(age); \ 2055254885Sdumbbell} while (0) 2056254885Sdumbbell 2057254885Sdumbbell#define R600_CLEAR_AGE(age) do { \ 2058254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2059254885Sdumbbell OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2060254885Sdumbbell OUT_RING(age); \ 2061254885Sdumbbell} while (0) 2062254885Sdumbbell 2063254885Sdumbbell/* ================================================================ 2064254885Sdumbbell * Ring control 2065254885Sdumbbell */ 2066254885Sdumbbell 2067254885Sdumbbell#define RADEON_VERBOSE 0 2068254885Sdumbbell 2069254885Sdumbbell#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2070254885Sdumbbell 2071254885Sdumbbell#define RADEON_RING_ALIGN 16 2072254885Sdumbbell 2073254885Sdumbbell#define BEGIN_RING( n ) do { \ 2074254885Sdumbbell if ( RADEON_VERBOSE ) { \ 2075254885Sdumbbell DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2076254885Sdumbbell } \ 2077254885Sdumbbell _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \ 2078254885Sdumbbell _align_nr += n; \ 2079254885Sdumbbell if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ 2080254885Sdumbbell COMMIT_RING(); \ 2081254885Sdumbbell radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ 2082254885Sdumbbell } \ 2083254885Sdumbbell _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2084254885Sdumbbell ring = dev_priv->ring.start; \ 2085254885Sdumbbell write = dev_priv->ring.tail; \ 2086254885Sdumbbell mask = dev_priv->ring.tail_mask; \ 2087254885Sdumbbell} while (0) 2088254885Sdumbbell 2089254885Sdumbbell#define ADVANCE_RING() do { \ 2090254885Sdumbbell if ( RADEON_VERBOSE ) { \ 2091254885Sdumbbell DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2092254885Sdumbbell write, dev_priv->ring.tail ); \ 2093254885Sdumbbell } \ 2094254885Sdumbbell if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2095254885Sdumbbell DRM_ERROR( \ 2096254885Sdumbbell "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2097254885Sdumbbell ((dev_priv->ring.tail + _nr) & mask), \ 2098254885Sdumbbell write, __LINE__); \ 2099254885Sdumbbell } else \ 2100254885Sdumbbell dev_priv->ring.tail = write; \ 2101254885Sdumbbell} while (0) 2102254885Sdumbbell 2103254885Sdumbbellextern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2104254885Sdumbbell 2105254885Sdumbbell#define COMMIT_RING() do { \ 2106254885Sdumbbell radeon_commit_ring(dev_priv); \ 2107254885Sdumbbell } while(0) 2108254885Sdumbbell 2109254885Sdumbbell#define OUT_RING( x ) do { \ 2110254885Sdumbbell if ( RADEON_VERBOSE ) { \ 2111254885Sdumbbell DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2112254885Sdumbbell (unsigned int)(x), write ); \ 2113254885Sdumbbell } \ 2114254885Sdumbbell ring[write++] = (x); \ 2115254885Sdumbbell write &= mask; \ 2116254885Sdumbbell} while (0) 2117254885Sdumbbell 2118254885Sdumbbell#define OUT_RING_REG( reg, val ) do { \ 2119254885Sdumbbell OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2120254885Sdumbbell OUT_RING( val ); \ 2121254885Sdumbbell} while (0) 2122254885Sdumbbell 2123254885Sdumbbell#define OUT_RING_TABLE( tab, sz ) do { \ 2124254885Sdumbbell int _size = (sz); \ 2125254885Sdumbbell int *_tab = (int *)(tab); \ 2126254885Sdumbbell \ 2127254885Sdumbbell if (write + _size > mask) { \ 2128254885Sdumbbell int _i = (mask+1) - write; \ 2129254885Sdumbbell _size -= _i; \ 2130254885Sdumbbell while (_i > 0 ) { \ 2131254885Sdumbbell *(int *)(ring + write) = *_tab++; \ 2132254885Sdumbbell write++; \ 2133254885Sdumbbell _i--; \ 2134254885Sdumbbell } \ 2135254885Sdumbbell write = 0; \ 2136254885Sdumbbell _tab += _i; \ 2137254885Sdumbbell } \ 2138254885Sdumbbell while (_size > 0) { \ 2139254885Sdumbbell *(ring + write) = *_tab++; \ 2140254885Sdumbbell write++; \ 2141254885Sdumbbell _size--; \ 2142254885Sdumbbell } \ 2143254885Sdumbbell write &= mask; \ 2144254885Sdumbbell} while (0) 2145254885Sdumbbell 2146254885Sdumbbell/** 2147254885Sdumbbell * Copy given number of dwords from drm buffer to the ring buffer. 2148254885Sdumbbell */ 2149254885Sdumbbell#define OUT_RING_DRM_BUFFER(buf, sz) do { \ 2150254885Sdumbbell int _size = (sz) * 4; \ 2151254885Sdumbbell struct drm_buffer *_buf = (buf); \ 2152254885Sdumbbell int _part_size; \ 2153254885Sdumbbell while (_size > 0) { \ 2154254885Sdumbbell _part_size = _size; \ 2155254885Sdumbbell \ 2156254885Sdumbbell if (write + _part_size/4 > mask) \ 2157254885Sdumbbell _part_size = ((mask + 1) - write)*4; \ 2158254885Sdumbbell \ 2159254885Sdumbbell if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \ 2160254885Sdumbbell _part_size = PAGE_SIZE - drm_buffer_index(_buf);\ 2161254885Sdumbbell \ 2162254885Sdumbbell \ 2163254885Sdumbbell \ 2164254885Sdumbbell memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \ 2165254885Sdumbbell [drm_buffer_index(_buf)], _part_size); \ 2166254885Sdumbbell \ 2167254885Sdumbbell _size -= _part_size; \ 2168254885Sdumbbell write = (write + _part_size/4) & mask; \ 2169254885Sdumbbell drm_buffer_advance(_buf, _part_size); \ 2170254885Sdumbbell } \ 2171254885Sdumbbell} while (0) 2172254885Sdumbbell 2173254885Sdumbbell 2174254885Sdumbbell#endif /* __RADEON_DRV_H__ */ 2175